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integrated circuit systems, inc. ics9342 third party brands and names are the property of their respective owners. 9342 rev e 9/06/00 pin configuration 48-pin 300mil ssop recommended application: power pc system clock output features: ? 12- cpus @ 3.3v, up to 146mhz 1- pciref @ 3.3v, up to 73mhz 1 - out 3.3v, 64mhz 1 - out/2 3.3v, out/2mhz 2 - ref @ 3.3v, 14.318mhz features: up to 146mhz frequency support support power management: cpu, pci stop and power down mode. spread spectrum for emi control (0 to -0.5%, 0.25%). uses external 14.318mhz crystal fs pins for frequency select support for industrial temperature range (-40c to 85c) key specifications: cpu output skew: <200ps cpu - pci output skew: <500ps cpu output jitter: <150ps pci output jitter: <500ps 133mhz clock generator and integrated buffer for powerpc? vddref ref1 ref0 gndref x1 x2 *pd# *cpu-stop# vdd gnd *pci_stop# *ss_en# vddpci pciref gndpci *fs0 *fs1 *fs2 vddfp gndfp *test#/out *boost#/out_div2 *pdfp# vdda outsel1* vddcpu gndcpu cpu0 cpu1 cpu2 vddcpu gndcpu cpu3 cpu4 cpu5 vddcpu gndcpu cpu6 cpu7 cpu8 vddcpu gndcpu cpu9 cpu10 cpu11 vddcpu gndcpu outsel0* ics9342 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

functionality block diagram ss_en# outsel (1:0) pll2 pll1 spread spectrum out out/div2 cpuclk (11:0) 12 2 pciref x1 x2 xtal osc cpu divder pci divder stop stop fs (2:0) pd# pdfp# test# boost# control logic config. reg. / 2 ref (1:0) t s e t2 s f1 s f0 s f u p c z h m i c p z h m f e r z h m 1111 3 3 . 3 3 13 3 . 3 38 1 3 . 4 1 1110 0 0 . 0 0 13 3 . 3 38 1 3 . 4 1 1101 3 3 . 3 83 3 . 3 38 1 3 . 4 1 1100 6 6 . 6 63 3 . 3 38 1 3 . 4 1 1011 3 3 . 3 3 16 6 . 6 68 1 3 . 4 1 1010 0 0 . 0 0 16 6 . 6 68 1 3 . 4 1 1001 3 3 . 3 86 6 . 6 68 1 3 . 4 1 1000 6 6 . 6 66 6 . 6 68 1 3 . 4 1 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ics9342 third party brands and names are the property of their respective owners. pin configuration general description the ics9342 generates all clocks required for high speed powerpc risc microprocessor systems. with a zero delay buffer chip such as the ics9112-17 multiple pci clock outputs can be generated in phase with pciref. spread spectrum may be enabled by driving the ss_en# pin low. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9342 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. pin number pin name type description 1 vddref pwr ref(1:0), xtal power supply, nominal 3.3v 2,3 ref[1:0] out 14.318 mhz reference clocks 4 gndref pwr ground pin for the ref outputs 5 x1 in crystal input,nominally 14.318m hz. 6 x2 out crystal output, nominally 14.318mhz. 7 pd# in powers down chip, active low. 8 cpu_stop# in stops all cpuclks [11:0] at logic 0 level, when input low 9 vdd pwr 3.3v power for the digital core. 10 gnd pwr ground pin for the digital core. 11 pci_sto p# in drives pciref to logic 0 level, when input low 12 ss_en# in spread spectrum is turned on by driving this input low and turned off by drivin g it hi g h. 13 vddpci pwr power supply for pciref, nominal 3.3v. 14 pciref out reference clock for pci zero delay buffer. 15 gndpci pwr ground pin for pciref. 18, 17, 16 fs (2:0) in frequency select pins. 19 vddfp pwr 3.3v power for the fixed pll core. 20 gndfp per ground pin for the fixed pll core. out out 3.3v out reference clock. test# in logic input to select over clocking or under clocking frequencies. (latched in p ut) out_div2 out 3.3v 1/2 frequency out reference clock. boost# in logic input to select normal or test mode frequencies. (latched input) 23 pdfp# in powers down fixed pll. when driven to low, out and out_div2 clocks will be sto pp ed 24 vdda pwr 3.3v power for the pll core 48, 25 outsel(1:0) in frequency select pins for out and out_div2 clocks. 26, 31, 36, 41, 46 gndcpu pwr ground pin for cpu clocks. 27, 32, 37, 42, 47 vddcpu pwr 3.3v power supply for cpu clocks. 21 22
ics9342 third party brands and names are the property of their respective owners. frequency selection 1 l e s _ t u o0 l e s _ t u o t u o ) z h m ( 2 v i d _ t u o ) z h m ( f e r ) z h m ( 118 44 28 1 3 . 4 1 10 0 40 28 1 3 . 4 1 014 62 38 1 3 . 4 1 008 4# 8 48 1 3 . 4 1 # t s o o b# t s e t2 s f1 s f0 s f u p c z h m i c p z h m f e r z h m e u l a v / e p y t s s d e l b a n e s s f i x 1 111 3 3 . 3 3 13 3 . 3 38 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 x1110 0 0 . 0 0 13 3 . 3 38 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 x1101 3 3 . 3 83 3 . 3 38 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 x1100 6 6 . 6 63 3 . 3 38 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 x1011 3 3 . 3 3 16 6 . 6 68 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 x1010 0 0 . 0 0 16 6 . 6 68 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 x1001 3 3 . 3 86 6 . 6 68 1 3 . 4 1d a e r p s n w o d % 5 . - o t 0 x 1 000 6 6 . 6 66 6 . 6 68 1 3 . 4 1d a e r p s n w o d % 5 . 0 - o t 0 1 0 111 2 6 . 6 4 16 . 6 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 10110 9 9 . 9 0 16 . 6 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 10101 8 5 . 1 96 . 6 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 10100 1 3 . 3 76 . 6 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 10011 2 6 . 6 4 13 . 3 78 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 10010 9 9 . 9 0 13 . 3 78 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 10001 8 5 . 1 93 . 3 78 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 1 0 000 1 3 . 3 73 . 3 78 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 0 0 111 8 9 . 9 1 10 0 . 0 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 00110 0 0 . 0 90 0 . 0 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 00101 3 9 . 4 70 0 . 0 38 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 00100 8 / f e r = i c p , 4 / f e r = u p c , e d o m t s e t 00011 8 9 . 9 1 10 0 . 0 68 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 00010 0 0 . 0 90 0 . 0 68 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 00001 3 9 . 4 70 0 . 0 68 1 3 . 4 1d a e r p s r e t n e c % 5 2 . 0 + 0 0 000 s t u p t u o l l a , e t a t s i r t
ics9342 third party brands and names are the property of their respective owners. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . -40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70 o c; su p ply voltag e v dd = 3.3 v +/-5% (unles s otherwis e s tated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 a i dd3.3 op6 6 select @ 66mhz; max discrete cap loads 134 175 operating i dd3.3 op8 3 select @ 83mhz; max discrete cap loads 165 200 supply current i dd3 .3op1 0 0 select @ 100mhz; max discrete cap loads 198 225 i dd3 .3op1 3 3 select @ 133mhz; max discrete cap loads 254 300 power down supply current input frequency f i v dd = 3.3 v 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 13.5 18 22.5 pf transition time 1 t tran s to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 1 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-pci v t = 1.5 v 190 500 ps input capacitance 1 ma pd# = 0 i dd3.3pd 313 400 a
ics9342 third party brands and names are the property of their respective owners. electrical characteristics - pci t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l =30 pf parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 21 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 21.2 55 ? output high voltage v oh1 i oh = -11 ma 2.4 output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -60 -22 ma output low current i ol1 v ol = 0.8 v 25 47 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.9 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 170 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 20 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 29 45 ? output high voltage v oh2b i oh = -8.0 ma 2 2.4 v output low voltage v ol2 b i ol = 12 ma 0.32 0.4 v output high current i oh2b v oh =1.7 v -37 -16 ma output low current i ol2b v ol = 0.7 v 19 26 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.4 v 1.13 2 ns fall time t f2b 1 v oh = 2.4 v, v ol = 0.4 v 1.27 2 ns vt = 1.5 v; cpu@ 66m, 83m, 100m 45 52 56 vt = 1.5 v; cpu@133m & 146.6m 51 56 60 skew t sk2b 1 vt = 1.5 v 187 200 ps vt = 1.5 v; normal 95 150 vt = 1.5 v; spread, cpu = 91.58mhz 143 200 vt = 1.5 v; spread, cpu remaining freq. 143 175 1 guaranteed by design, not 100% tested in production. duty cycle d t2b 1 % jitter, cycle-to-cycle tj cyc-cyc2b 1 ps
ics9342 third party brands and names are the property of their respective owners. electrical characteristics - ref, out, out/2 t a = 0 - 70 o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) symbol conditions min typ max units r dsp5 1 v o = v dd *(0.5) 20 34 60 ? r dsn5 1 v o = v dd *(0.5) 20 31 60 ? v oh5 i oh = -12 ma 2.4 2.9 v v ol5 i ol = 10 ma 0.33 0.4 v i oh5 v oh = 2.0 v -30 -20 ma i ol5 v ol = 0.8 v 16 23 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v; out 1.5 1.8 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v; out 1.5 2 4 ns duty cycle 1 d t5 v t = 1.5 v; out 45 52 55 % ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v; out/2 1.5 2.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v; out/2 1.5 2.1 4 ns duty cycle 1 d t5 v t = 1.5 v; out/2 45 50 55 % ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v; ref 1.5 2.7 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v; ref 1.5 2.8 4 ns duty cycle 1 d t5 v t = 1.5 v; ref 45 50 55 % t jcyc-cyc5 v t = 1.5 v; out, out/2 280 500 ps t jcyc-cyc5 v t = 1.5 v; ref 450 1000 ps 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle1 jitter, cycle-to-cycle 1 parameter output low voltage output high current output high voltage output impedance ref out out/2 output low current
ics9342 third party brands and names are the property of their respective owners. fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9342 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
ics9342 third party brands and names are the property of their respective owners. # d p# p f d p2 v i d _ t u o , 1 t u of e r , i c p , u p c 11 g n i n n u rg n i n n u r 10 d e p p o t sg n i n n u r 01 d e p p o t sd e p p o t s 00 d e p p o t sd e p p o t s power management pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. the ref and out clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpu (defined as inside the ics9342 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpu pciref vco crystal pd#
ics9342 third party brands and names are the property of their respective owners. pci_stop# timing diagram pci_stop# is an input to the clock synthesizer. it is used to turn off the pciref clock for low power operation. pciref clock is required to be stopped in a low state and started such that a full high pulse width is guaranteed. notes: 1. all timing is referenced to cpuclk. 2. internal means inside the chip. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high state. cpuclk (internal) (internal) (externall) pciclk pci_stop# cpu_stop# pd# pciref cpu_stop# timing diagram cpu_stop# is an asynchronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is asserted asynchronously by the external clock control logic with the rising edge of free running pci clock (and hence cpu clock) and must be internally synchronized to the external output. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. notes: 1. all timing is referenced to the internal cpuclk. 2. the internal label means inside the chip and is a reference only. this in fact may not be the way that the control is design ed. 3. pd# and pci_stop# are shown in a high state. cpuclk (internal) (internal) (externall) pciclk pci_stop# cpu_stop# pd# cpuclk

ics9342 third party brands and names are the property of their respective owners. ordering information ics9342 y f-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min ma x min ma x a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min ma x min ma x 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 64 20.828 21.082 .820 .830 symbol see variations see variations in millimeters common dimensions in inc hes common dimensions see variations n d mm. d (inch) see variations ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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