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this is information on a product in full production. november 2014 docid16553 rev 3 1/115 stm32f101xf stm32f101xg xl-density access line, arm ? -based 32-bit mcu with 768 kb to 1 mb flash, 15 timers, 1 adc and 10 communication interfaces datasheet ? production data features ? core ? : arm 32-bit cortex ? -m3 cpu with mpu ? 36 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance ? single-cycle multiplic ation and hardware division ? memories ? 768 kbytes to 1 mbyte of flash memory (dual bank with read-w hile-write capability) ? 80 kbytes of sram ? flexible static memo ry controller with 4 chip select. supports compact flash, sram, psram, no r and nand memories ? lcd parallel interface, 8080/6800 modes ? clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr, and programmable voltage detector (pvd) ? 4-to-16 mhz cr ystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc with calibration capability ? 32 khz oscillator for rtc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers ? 1 x 12-bit, 1 s a/d converters (up to 16 channels) ? conversion range: 0 to 3.6 v ? temperature sensor ? 2 12-bit d/a converters ? dma ? 12-channel dma controller ? peripherals supported: timers, adc, dac, spis, i 2 cs and usarts ? up to 112 fast i/o ports ? 51/80/112 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant ? debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m3 embedded trace macrocell? ? up to 15 timers ? up to ten 16-bit timers, with up to 4 ic/oc/pwm or pulse counters ? 2 watchdog timers (independent and window) ? systick timer: a 24-bit downcounter ? 2 16-bit basic timers to drive the dac ? up to 10 communica tion interfaces ? up to 2 x i 2 c interfaces (smstm32f101xf, stm32f101xg7816 interface, lin, irda capability, modem control) ? up to 3 spis (18 mbit/s) ? crc calculation unit, 96-bit unique id ? ecopack ? packages table 1. device summary reference part number stm32f101xf stm32f101rf stm32f101vf stm32f101zf stm32f101xg STM32F101RG stm32f101vg stm32f101zg lqfp144 20 20 mm l qfp64 10 10 mm lqfp100 14 14 mm www.st.com
contents stm32f101xf, stm32f101xg 2/115 docid16553 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 arm ? cortex?-m3 core with embedded flash and sram . . . . . . . . . 15 2.3.2 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.6 fsmc (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 lcd parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 rtc (real-time clock) and backup register s . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.20 universal synchronous/asynchronous receiver transmitters (usarts) . 21 2.3.21 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 adc (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid16553 rev 3 3/115 stm32f101xf, stm32f101xg contents 4 3 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 39 5.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 40 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.10 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.3.12 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 77 5.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.16 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.18 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.20 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
contents stm32f101xf, stm32f101xg 4/115 docid16553 rev 3 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.1.1 lqfp144, 20 x 20 mm, 144-pin thin qu ad flat package . . . . . . . . . . . 100 6.1.2 lqfp100, 14 x 14 mm, 100-pin low-profile quad fl at package . . . . . . 104 6.1.3 lqfp64, 10 x 10 mm, 64 pin low-profile quad flat package . . . . . . . . 107 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.2.2 evaluating the maximum junction temperature for an application . . . . 111 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
docid16553 rev 3 5/115 stm32f101xf, stm32f101xg list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f101xf and stm32f101xg features and peri pheral counts . . . . . . . . . . . . . . . . . 11 table 3. stm32f101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. stm32f101xf and stm32f101xg timer feature comp arison . . . . . . . . . . . . . . . . . . . . . . 19 table 5. stm32f101xf/stm32f101xg pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 14. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 44 table 17. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 44 table 18. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 47 table 20. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 23. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 table 24. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 26. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 27. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 28. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 29. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 30. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 31. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . . 57 table 32. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . . 58 table 33. asynchronous multiplexed nor/ psram read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 34. asynchronous multiplexed nor/ psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. synchronous multiplexed nor/ps ram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 36. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 37. synchronous non-multiplexed nor/psram read timi ngs . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 38. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 39. switching characteristics for pc card/cf read and write cycles in attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 40. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . . 73 table 41. switching characteristics for nand flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 42. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 43. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 44. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
list of tables stm32f101xf, stm32f101xg 6/115 docid16553 rev 3 table 45. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 46. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 47. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 48. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 49. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 50. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 51. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 52. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 53. scl frequency (f pclk1 = 36 mhz, v dd = v dd_i2c = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 54. stm32f10xxx spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 55. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 56. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 57. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 58. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 59. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 60. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 61. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 62. lqfp144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . 101 table 63. lqpf100 ? 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . 104 table 64. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 107 table 65. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 66. stm32f101xf and stm32f101xg ordering informa tion scheme . . . . . . . . . . . . . . . . . . 112 table 67. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
docid16553 rev 3 7/115 stm32f101xf, stm32f101xg list of figures 8 list of figures figure 1. stm32f101xf and stm32f101xg access line bloc k diagram . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, perip herals enabled. . . . . . . . . . . . . . . . . . 43 figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, perip herals disabled . . . . . . . . . . . . . . . . . 43 figure 13. typical current consumption on v bat with rtc on vs. temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14. typical current consumption in standby mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 16. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19. asynchronous non-multip lexed sram/psram/nor re ad waveforms . . . . . . . . . . . . . . . 57 figure 20. asynchronous non-multiple xed sram/psram/nor write waveform s . . . . . . . . . . . . . . . 58 figure 21. asynchronous multiplexed nor/psram read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 22. asynchronous multiplexed nor/psram write wave forms . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 24. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 25. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 27. pc card/compactflash controller waveforms for common me mory read access . . . . . . . 69 figure 28. pc card/compactflash co ntroller waveforms for common memo ry write access . . . . . . . 69 figure 29. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 30. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 31. pc card/compactflash cont roller waveforms for i/o space read access . . . . . . . . . . . . . 71 figure 32. pc card/compactflash cont roller waveforms for i/o space write access . . . . . . . . . . . . . 72 figure 33. nand controller waveforms for re ad access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 34. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 35. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 74 figure 36. nand controller waveforms for common memory wr ite access. . . . . . . . . . . . . . . . . . . . . 75 figure 37. standard i/o input characterist ics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 38. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 figure 39. 5 v tolerant i/o inpu t characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 40. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 41. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 42. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
list of figures stm32f101xf, stm32f101xg 8/115 docid16553 rev 3 figure 43. i 2 c bus ac waveforms and measurement circuit (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 44. spi timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 45. spi timing diagram - slave mode and cpha=1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 46. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 47. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 48. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 49. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 96 figure 50. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . . 97 figure 51. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 52. lqfp144, 20 x 20 mm, 144-pin thin quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 53. recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 54. lqfp144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 55. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 104 figure 56. recommended footprintt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 57. lqfp100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 58. tlqfp64 ? 10 x 10 mm, 64 pin low-profile q uad flat package outline . . . . . . . . . . . . . . . 107 figure 59. recommended footprintt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 60. lqfp64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 61. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
docid16553 rev 3 9/115 stm32f101xf, stm32f101xg introduction 114 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f101xf and stm32f101xg xl-densit y access line microcontrollers. for more details on the whole stmicroelectronics stm32f101xx family, please refer to section 2.2: full compatibility thro ughout the family . the xl-density stm32f101xx datasheet should be read in conjunction with the stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com. for information on the cortex ? -m3 core please refer to the cortex ? -m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/inde x.jsp?topic=/com.arm.doc.ddi0337e/.
description stm32f101xf, stm32f101xg 10/115 docid16553 rev 3 2 description the stm32f101xf and stm32f101xg access line family incorporates the high- performance arm ? cortex ? -m3 32-bit risc core operating at a 36 mhz frequency, high- speed embedded memories (flash memory up to 1 mbyte and sram of 80 kbytes), and an extensive range of enhanced i/os and peripherals connected to two apb buses. all devices offer one 12-bit adc, ten general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two i 2 cs, three spis and five usarts. the stm32f101xx xl-density access line family operates in the ?40 to +85 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. these features make the stm32f101xx xl-den sity access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, pc peripherals and gaming, gps platforms, indust rial applications, plc, printers, scanners alarm systems , power meters, and video intercom.
docid16553 rev 3 11/115 stm32f101xf, stm32f101xg description 114 2.1 device overview the stm32f101xx xl-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. figure 1 shows the general block diagram of the device family. table 2. stm32f101xf and stm32f101xg features and peripheral counts peripherals stm32f101rx stm32f101vx stm32f101zx flash memory 768 kb 1 mb 768 kb 1 mb 768 kb 1 mb sram in kbytes 80 80 80 fsmc no yes yes timers general-purpose 10 basic 2 communication interfaces spi 3 i 2 c2 usart 5 gpios 51 80 112 12-bit adc number of channels 1 16 12-bit dac number of channels yes 2 cpu frequency 36 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperature: ?40 to +85 c (see table 10 ) junction temperature: ?40 to +105 c (see ta ble 1 0 ) package lqfp64 lqfp100 (1) 1. for the lqfp100 package, only fsmc bank1 and b ank2 are available. b ank1 can only support a multiplexed nor/psram memory using the ne1 chip select. bank2 can only s upport a 16- or 8-bit nand flash memory using the nce2 chip select. the interr upt line cannot be used since port g is not available in this package. lqfp144
description stm32f101xf, stm32f101xg 12/115 docid16553 rev 3 figure 1. stm32f101xf and stm32f101xg access line block diagram 1. t a = ?40 c to +85 c (junction temperature up to 105 c). 2. af = alternate function on i/o port pin. 0!;= %84)4 !& !(" 7+50 & max -(z 6 33 )# '0$-! 4)- 4)- 84!, k(z &lash+byte 6 $$ "ack upinterfac e 4)- "us matrix bit 24# 2#-(z #ortex -#05 $bus obl &lash interface 53!24 30) "ackup reg )# 2848#43243 53!24 2#k(z 3tan dby )7$' 6 "!4 0/2 0$2 6 $$! 6 "!4 6to 6 #+as!& 2848#43243 #+as!& .6)# 30) interfac e 6 $$! 06$ )nt !(" !0" !75 30) 5!24 28 48as!& 5!24 2848as!& 4)- 0,, 6 $$! &3-# $!#?/54as!& $!#?/54as!& 32!- +byte '0$-! 4)- 4)- .*4234 *4$) *4#+37#,+ *4-337$)/ *4$/ as!& !;= $;= #,+ ./% .7% .%;= .",;= .7!)4 ., as!& channels channels '0)/port! '0)/port" '0)/port# '0)/port$ '0)/port% '0)/port& '0)/port' 53!24 4empsensor bit!$# )& 0";= 0#;= 0$;= 0%;= 0&;= 0';= !$#?).;= 6 $$! !0"&max-(z !0" 4race controller 0bus )bus 3ystem 2eset clock control 0#,+ 0#,+ (#,+ &#,+ 0ower 6oltreg 6to6 3upply supervision 6 $$ 0/2 2eset .234 6 $$! 6 33! /3#?). /3#?/54 6 $$ 84!,/3# -(z /3#?). /3#?/54 4!-0%2 24# !,!2-3%#/.$/54 channelsas!& channelsas!& channelsas!& channelsas!& -/3)-)3/ 3#+.33as!& -/3)-)3/ 3#+.33as!& 3#,3$!3-"!as!& 3#,3$!3-"!as!& 77$' ai !0"& max -(z 42!#%#,+ 42!#%$;= as!3 37*4!' 40)5 %4- 4racetrig 6 2%& 6 2%&n 6 2%& -/3)-)3/3#+ .33as!& 2848#43243 as!& bit$!# )& )& )& bit$!# 4)- 4)- 4)- channelsas!& channelas!& channelas!& 4)- 4)- 4)- channelsas!& channelas!& channelas!& -05 &lash+byte bit obl &lash interface
docid16553 rev 3 13/115 stm32f101xf, stm32f101xg description 114 figure 2. clock tree 1. when the hsi is used as a pll clock input, the maxi mum system clock frequency t hat can be achieved is 36 mhz. 2. to have an adc conversion time of 1 s, apb2 must be at 14 mhz or 28 mhz. (3%/3# -(z /3#?). /3#?/54 /3#?). /3#?/54 ,3%/3# k(z -(z (3)2# ,3)2# k(z toindependentwatchdog)7$' 0,, xxx 0,,-5, (3%(ighspeedexternalclocksignal ig ,3% ,3) (3) ,egend -#/ #lock/utput -ain 0,,8402% x !(" 0rescaler 0,,#,+ (3) (3% !0" 0rescaler !$# 0rescaler !$##,+ 0#,+ (#,+ 0,,#,+ to!("buscore memoryand$-! to!$# ,3% ,3) (3) (3) (3% peripherals to!0" 0eripheral#lock %nable %nable 0eripheral#lock !0" 0rescaler 0#,+ to!0"peripherals 0eripheral#lock %nable -(zmax -(z -(zmax -(zmax to24# 0,,32# 37 -#/ #33 to#ortex3ystemtimer #lock %nable 393#,+ max 24##,+ 24#3%,;= 4)-x#,+ )7$'#,+ 393#,+ &#,+#ortex freerunningclock 4)- to4)- and to&3-# &3-##,+ 0eripheralclock enable ai )f!0"prescaler x elsex (ighspeedinternalclocksignal ,owspeedexternalclocksignal ,owspeedinternalclocksignal 0eripheral#lock %nable 4)-x#,+ 4)- to4)-4)- and4)- )f!0"prescaler x elsex &,)4&#,+ to&lashprogramming interface
description stm32f101xf, stm32f101xg 14/115 docid16553 rev 3 2.2 full compatibility throughout the family the stm32f101xx is a complete family whose members are fully pin-to-pin, software and feature compatible.in the reference manual, the stm32f101x4 and stm32f101x6 are identified as low-density devices, the stm32f 101x8 and stm32f101xb are referred to as medium-density devices, the stm32f10 1xc, stm32f101xd and stm32f101xe are referred to as high-density devices, and the stm32f101xf and stm32f101xg are referred to as xl-density devices. low-, high-density and xl-density devices are an extension of the stm32f101x8/b medium-density devices, they are specifie d in the stm32f101x4/6, stm32f101xc/d/e and stm32f101xf/g datasheets, respectively. low-density devices feature lower flash memory and ram capacities, less timers and peripherals. high-density devices have highe r flash memory and ram densities, and additional peripherals like fsmc and dac. xl-density devices bring greater flash and ram capacities, and more features, namely an mpu, a higher number of timers and a dual bank flash memory, while remaining fully compatible with the other members of the family. the stm32f101x4, stm32f101x6, stm32f101xc, stm32f101xd, stm32f101xe, stm32f101xf and stm32f101xg are a drop-in replacement for the stm32f101x8/b devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. moreover, the stm32f101xx access line family is fully compatible with all existing stm32f103xx performance line and stm32f102xx usb access line devices. table 3. stm32f101xx family pinout memory size low-density devices medium-density devices high-density devices xl-density devices 16 kb flash 32 kb flash (1) 64 kb flash 128 kb flash 256 kb flash 384 kb flash 512 kb flash 768 kb flash 1 mb flash 4 kb ram 6 kb ram 10 kb ram 16 kb ram 32 kb ram 48 kb ram 48 kb ram 80 kb ram 80 kb ram 144 5 usarts 4 16-bit timers, 2 basic timers 3 spis, 2 i 2 cs, 1 adc, 1 dac fsmc (100 and 144 pins) 5 usarts 10 16-bit timers, 2 basic timers 3 spis, 2 i 2 cs, 1 adc, 1 dac fsmc (100 and 144 pins), cortex-m3 with mpu, dual bank flash memory 100 3 usarts 3 16-bit timers 2 spis, 2 i2cs, 1 adc 64 2 usarts 2 16-bit timers 1 spi, 1 i 2 c 1 adc 48 36 1. for orderable part numbers that do not show the a internal code after the temperature range code (6), the reference datasheet for electrical characte ristics is that of the stm32f 101x8/b medium-density devices.
docid16553 rev 3 15/115 stm32f101xf, stm32f101xg description 114 2.3 overview 2.3.1 arm ? cortex?-m3 core with embedded flash and sram the arm ? cortex ? -m3 processor is the latest generation of arm ? processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm ? cortex ? -m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm ? core in the memory size usually associated with 8- and 16-bit devices. the stm32f101xf and stm32f101xg access line family having an embedded arm ? core, is therefore compatible with all arm ? tools and software. figure 1 shows the general block diagram of the device family. 2.3.2 memory protection unit the memory protection unit (mpu) is used to se parate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially help ful for applications w here some critical or certified code has to be protected against th e misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rt os can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 2.3.3 embedded flash memory 768 kbytes to 1 mbyte of embedded flash are available for storing programs and data. the flash memory is organized as two banks. the first bank has a size of 512 kbytes. the second bank is either 256 or 512 kbytes depe nding on the device. this gives the device the capability of writing to one ban k while executing code from th e other bank (r ead-while-write capability). 2.3.4 crc (cyclic redundan cy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location.
description stm32f101xf, stm32f101xg 16/115 docid16553 rev 3 2.3.5 embedded sram 80 kbytes of embedded sram accessed (read/wr ite) at cpu clock speed with 0 wait states. 2.3.6 fsmc (flexible static memory controller) the fsmc is embedded in the stm32f101xf and stm32f101xg access line family. it has four chip select outputs su pporting the following modes: pc card/compact flash, sram, psram, nor and nand. functionality overview: ? the three fsmc interrupt lines are ored in order to be connected to the nvic ? write fifo ? code execution from external memory except for nand flash and pc card ? the targeted frequency is hclk/2, so exte rnal access is at 18 mhz when hclk is at 36 mhz 2.3.7 lcd parallel interface the fsmc can be configured to interface seam lessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high- performance solutions using external controllers with dedicated acceleration. 2.3.8 nested vectored interrupt controller (nvic) the stm32f101xf and stm32f101xg access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of cortex ? -m3) and 16 priority levels. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.9 external interrupt /event controller (exti) the external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 112 gpios can be connected to the 16 external interrupt lines.
docid16553 rev 3 17/115 stm32f101xf, stm32f101xg description 114 2.3.10 clocks and startup system clock selection is perf ormed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-16 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers are used to configure th e ahb frequency, the high-speed apb (apb2) domain and the low-speed apb (apb1) domain. the maximum frequency of the ahb and apb domains is 36 mhz. see figure 2 for details on the clock tree. 2.3.11 boot modes at startup, boot pins are used to select one of three boot options: ? boot from user flash: you have an option to boot from any of two memory banks. by default, boot from flash memory bank 1 is se lected. you can choose to boot from flash memory bank 2 by setting a bit in the option bytes. ? boot from system memory ? boot from embedded sram the bootloader is located in system memory. it is used to reprogram the flash memory by using usart1. 2.3.12 power supply schemes ? v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc or dac is used). v dda and v ssa must be connected to v dd and v ss , respectively. ? v bat = 1.8 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 9: power supply scheme . 2.3.13 power supply supervisor the device has an integrated power-on reset (por)/power-down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to table 12: embedded reset and power control block characteristics for the values of v por/pdr and v pvd .
description stm32f101xf, stm32f101xg 18/115 docid16553 rev 3 2.3.14 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. ? mr is used in the nominal regulation mode (run) ? lpr is used in the stop modes. ? power down is used in standby mode: the re gulator output is in high impedance: the kernel circuitry is powered do wn, inducing zero consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode. 2.3.15 low-power modes the stm32f101xf and stm32f101xg access line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output or the rtc alarm. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 2.3.16 dma the flexible 12-channel general-purpose dmas (7 channels for dma1 and 5 channels for dma2) are able to manage memory-to-memory , peripheral-to-memory and memory-to- peripheral transfers. the two dma controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardw are dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose and basic timers timx, dac and adc.
docid16553 rev 3 19/115 stm32f101xf, stm32f101xg description 114 2.3.17 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when v dd power is not present. they are not reset by a system or power re set, and they are not reset when the device wakes up from the standby mode. the real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillato r or the high spee d external clock di vided by 128. the internal low-speed rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare register to generate an alarm. a 20-bit prescaler is us ed for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. 2.3.18 timers and watchdogs the xl-density stm32f101xx access line devices include up to ten general-purpose timers, two basic timers, two watchdog timers and a systick timer. table 4: stm32f101xf and stm32f101xg timer feature comparison compares the features of the general-purpose and basic timers. general-purpose timers (timx) there are 10 synchronizable general-purpose timers embedded in the stm32f101xf and stm32f101xg xl-density access line devices (see table 4 for differences). ? tim2, tim3, tim4, tim5 there are up to 4 synchronizable general-purpose timers (tim2, tim3, tim4 and tim5) embedded in the stm32f101xf and stm32f101xg access line devices. these timers are based on a 16-bit auto -reload up/down counter, a 16-bit prescaler and feature 4 independent channels each fo r input capture/output compare, pwm or table 4. stm32f101xf and stm32f101xg timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2, tim3, tim4, tim5 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim9, tim12 16-bit up any integer between 1 and 65536 no 2 no tim10, tim11, tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no
description stm32f101xf, stm32f101xg 20/115 docid16553 rev 3 one-pulse mode output. this gives up to 16 input captures / output compares / pwms on the largest packages. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. they all have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. ? tim10, tim11 and tim9 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10 and tim11 feature one independent channel, whereas tim9 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with t he tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. ? tim13, tim14 and tim12 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim13 and tim14 feature one independ ent channel, whereas tim12 has two independent channels for input capture/output compare, pwm or one-pulse mode output. they can be synchronized with t he tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. basic timers tim6 and tim7 these timers are mainly used for dac trigge r generation. they can also be used as a generic 16-bit time base. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source
docid16553 rev 3 21/115 stm32f101xf, stm32f101xg description 114 2.3.19 i2c bus up to two i2c bus interfaces can operate in multi-master and slave modes. they support standard and fast modes. they support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.3.20 universal synchr onous/asynchronous receiver transmitters (usarts) the stm32f101xf and stm32f101xg access line embeds three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3) and two universal asynchronous receiver transmitters (uart4 and uart5). these five interfaces provide asynchronou s communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the five inte rfaces are able to commu nicate at speeds of up to 2.25 mbit/s. usart1, usart2 and usart3 also provide hardware management of the cts and rts signals, smart card mode (i so 7816 compliant) and spi-like communication capability. all interfaces can be served by the dma controller except for uart5. 2.3.21 serial peripheral interface (spi) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification support s basic sd card/mmc modes. all spis can be served by the dma controller. 2.3.22 gpios (general- purpose inputs/outputs) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current- capable. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 2.3.23 adc (analog to digital converter) a 12-bit analog-to-digital converter is embedded into stm32f101xf and stm32f101xg access line devices. it has up to 16 external channels, performi ng conversions in single-shot or scan modes. in scan mode, automatic conv ersion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds.
description stm32f101xf, stm32f101xg 22/115 docid16553 rev 3 the events generated by the general-purpose timers (timx) can be internally connected to the adc start trigger and injection trigger, respectively, to allo w the application to synchronize a/d conversion and timers. 2.3.24 dac (digital-to-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ seven dac trigger inputs are used in the stm32f101xf and stm32f101xg access line family. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. 2.3.25 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel wh ich is used to convert the sensor output voltage into a digital value. 2.3.26 serial wire jtag debug port (swj-dp) the arm ? swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. 2.3.27 embedded trace macrocell? the arm ? embedded trace macrocell provides a gr eater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f10xxx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common develop ment tool vendors. it operates with third party debugger software tools.
docid16553 rev 3 23/115 stm32f101xf, stm32f101xg pinouts and pin descriptions 114 3 pinouts and pin descriptions figure 3. lqfp144 pinout 1. the above figure shows the package top view. 6 $$? 6 33? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$? 6 33? 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$? 6 33? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 0% 6 $$? 0% 6 33? 0% .# 0% 0! 0% 0! 6"!4 0! 0# 4!-0%2 24# 0! 0# /3#?). 0! 0# /3#?/54 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$? 0& 6 33? 6 33? 0' 6 $$? 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' /3#?). 0$ /3#?/54 0$ .234 6 $$? 0# 6 33? 0# 0$ 0# 0$ 0# 0$ 6 33! 0$ 6 2%& 0$ 6 2%& 0$ 6 $$! 0" 0! 7 + 5 0 0" 0! 0" 0! 0" 0! 6 33? 6 $$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633? 6 $$? 0& 0& 0& 0' 0' 0% 0% 0% 6 33? 6 $$? 0% 0% 0% 0% 0% 0% 0" 0" 6 33? 6 $$? ,1&0 ai
pinouts and pin descriptions stm32f101xf, stm32f101xg 24/115 docid16553 rev 3 figure 4. lqfp100 pinout 1. the above figure shows the package top view. ai 6$$? 633? .# 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$? 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 0% 0% 0% 0% 0% 6"!4 0# 4!-0%2 24# 0# /3#?). 0# /3#?/54 633? 6$$? /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0! 7 + 5 0 0! 0! ,1&0
docid16553 rev 3 25/115 stm32f101xf, stm32f101xg pinouts and pin descriptions 114 figure 5. lqfp64 pinout 1. the above figure shows the package top view. 6 "!4 0# 4!-0%2 24# 0# /3#?). 0# /3#?/54 0$ /3#?). 0$ /3#?/54 .234 0# 0# 0# 0# 6 33! 6 $$! 0! 7 + 5 0 0! 0! 6 $$? 6 33? 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! 6 $$? 6 33? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 6 33? 6 $$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 6 33? 6 $$? ,1&0 ai table 5. stm32f101xf/stm3 2f101xg pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap 1 - 1 pe2 i/o ft pe2 traceclk / fsmc_a23 2 - 2 pe3 i/o ft pe3 traced0 / fsmc_a19 3 - 3 pe4 i/o ft pe4 traced1 / fsmc_a20 4 - 4 pe5 i/o ft pe5 traced2 / fsmc_a21 tim9_ch1 5 - 5 pe6 i/o ft pe6 traced3 / fsmc_a22 tim9_ch2 616 v bat sv bat 7 2 7 pc13-tamper-rtc (5) i/o pc13 (6) tamper-rtc
pinouts and pin descriptions stm32f101xf, stm32f101xg 26/115 docid16553 rev 3 8 3 8 pc14-osc32_in (5) i/o pc14 (6) osc32_in 9 4 9 pc15-osc32_out (5) i/o pc15 (6) osc32_out 10 - - pf0 i/o ft pf0 fsmc_a0 11 - - pf1 i/o ft pf1 fsmc_a1 12 - - pf2 i/o ft pf2 fsmc_a2 13 - - pf3 i/o ft pf3 fsmc_a3 14 - - pf4 i/o ft pf4 fsmc_a4 15 - - pf5 i/o ft pf5 fsmc_a5 16 - 10 v ss_5 sv ss_5 17 - 11 v dd_5 sv dd_5 18 - - pf6 i/o pf6 fsmc_niord tim10_ch1 19 - - pf7 i/o pf7 fsmc_nreg tim11_ch1 20 - - pf8 i/o pf8 fsmc_niowr tim13_ch1 21 - - pf9 i/o pf9 fsmc_cd tim14_ch1 22 - - pf10 i/o pf10 fsmc_intr 23 5 12 osc_in i osc_in pd0 (7) 24 6 13 osc_out o osc_out pd1 (7) 25 7 14 nrst i/o nrst 26 8 15 pc0 i/o pc0 adc_in10 27 9 16 pc1 i/o pc1 adc_in11 28 10 17 pc2 i/o pc2 adc_in12 29 11 18 pc3 i/o pc3 adc_in13 30 12 19 v ssa sv ssa 31 - 20 v ref- sv ref- 32 - 21 v ref+ sv ref+ 33 13 22 v dda sv dda 34 14 23 pa0-wkup i/o pa0 wkup/ usart2_cts (8) / adc_in0 / tim5_ch1/ tim2_ch1_etr (8) table 5. stm32f101xf/stm32f101xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap
docid16553 rev 3 27/115 stm32f101xf, stm32f101xg pinouts and pin descriptions 114 35 15 24 pa1 i/o pa1 usart2_rts (8) / adc_in1 / tim5_ch2 tim2_ch2 (8) 36 16 25 pa2 i/o pa2 usart2_tx (8) / tim5_ch3 / adc_in2/ tim2_ch3 (8) / tim9_ch1 37 17 26 pa3 i/o pa3 usart2_rx (8) / tim5_ch4/ adc_in3 / tim2_ch4 (8) / tim9_ch2 38 18 27 v ss_4 sv ss_4 39 19 28 v dd_4 sv dd_4 40 20 29 pa4 i/o pa4 spi1_nss/ dac_out1 / adc_in4 / usart2_ck (8) 41 21 30 pa5 i/o pa5 spi1_sck / dac_out2 / adc_in5 42 22 31 pa6 i/o pa6 spi1_miso / adc_in6 / tim3_ch1 (8) / tim13_ch1 43 23 32 pa7 i/o pa7 spi1_mosi / adc_in7 / tim3_ch2 (8) / tim14_ch1 44 24 33 pc4 i/o pc4 adc_in14 45 25 34 pc5 i/o pc5 adc_in15 46 26 35 pb0 i/o pb0 adc_in8 / tim3_ch3 (8) 47 27 36 pb1 i/o pb1 adc_in9 / tim3_ch4 (8) 48 28 37 pb2 i/o ft pb2/boot1 49 - - pf11 i/o ft pf11 fsmc_nios16 50 - - pf12 i/o ft pf12 fsmc_a6 51 - - v ss_6 sv ss_6 52 - - v dd_6 sv dd_6 53 - - pf13 i/o ft pf13 fsmc_a7 54 - - pf14 i/o ft pf14 fsmc_a8 55 - - pf15 i/o ft pf15 fsmc_a9 56 - - pg0 i/o ft pg0 fsmc_a10 57 - - pg1 i/o ft pg1 fsmc_a11 table 5. stm32f101xf/stm32f101xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap
pinouts and pin descriptions stm32f101xf, stm32f101xg 28/115 docid16553 rev 3 58 - 38 pe7 i/o ft pe7 fsmc_d4 59 - 39 pe8 i/o ft pe8 fsmc_d5 60 - 40 pe9 i/o ft pe9 fsmc_d6 61 - - v ss_7 sv ss_7 62 - - v dd_7 sv dd_7 63 - 41 pe10 i/o ft pe10 fsmc_d7 64 - 42 pe11 i/o ft pe11 fsmc_d8 65 - 43 pe12 i/o ft pe12 fsmc_d9 66 - 44 pe13 i/o ft pe13 fsmc_d10 67 - 45 pe14 i/o ft pe14 fsmc_d11 68 - 46 pe15 i/o ft pe15 fsmc_d12 69 29 47 pb10 i/o ft pb10 i2c2_scl / usart3_tx (8) tim2_ch3 70 30 48 pb11 i/o ft pb11 i2c2_sda / usart3_rx (8) tim2_ch4 71 31 49 v ss_1 sv ss_1 72 32 50 v dd_1 sv dd_1 73 33 51 pb12 i/o ft pb12 spi2_nss (8) / i2c2_smba / usart3_ck (8) 74 34 52 pb13 i/o ft pb13 spi2_sck (8) / usart3_cts (8) 75 35 53 pb14 i/o ft pb14 spi2_miso (8) / usart3_rts (8) / tim12_ch1 76 36 54 pb15 i/o ft pb15 spi2_mosi (8) / tim12_ch2 77 - 55 pd8 i/o ft pd8 fsmc_d13 usart3_tx 78 - 56 pd9 i/o ft pd9 fsmc_d14 usart3_rx 79 - 57 pd10 i/o ft pd10 fsmc_d15 usart3_ck 80 - 58 pd11 i/o ft pd11 fsmc_a16 usart3_cts 81 - 59 pd12 i/o ft pd12 fsmc_a17 tim4_ch1 / usart3_rts 82 - 60 pd13 i/o ft pd13 fsmc_a18 tim4_ch2 83 - - v ss_8 sv ss_8 table 5. stm32f101xf/stm32f101xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap
docid16553 rev 3 29/115 stm32f101xf, stm32f101xg pinouts and pin descriptions 114 84 - - v dd_8 sv dd_8 85 - 61 pd14 i/o ft pd14 fsmc_d0 tim4_ch3 86 - 62 pd15 i/o ft pd15 fsmc_d1 tim4_ch4 87 - - pg2 i/o ft pg2 fsmc_a12 88 - - pg3 i/o ft pg3 fsmc_a13 89 - - pg4 i/o ft pg4 fsmc_a14 90 - - pg5 i/o ft pg5 fsmc_a15 91 - - pg6 i/o ft pg6 fsmc_int2 92 - - pg7 i/o ft pg7 fsmc_int3 93 - - pg8 i/o ft pg8 94 - - v ss_9 sv ss_9 95 - - v dd_9 sv dd_9 96 37 63 pc6 i/o ft pc6 tim3_ch1 97 38 64 pc7 i/o ft pc7 tim3_ch2 98 39 65 pc8 i/o ft pc8 tim3_ch3 99 40 66 pc9 i/o ft pc9 tim3_ch4 100 41 67 pa8 i/o ft pa8 usart1_ck / mco 101 42 68 pa9 i/o ft pa9 usart1_tx (8) 102 43 69 pa10 i/o ft pa10 usart1_rx (8) 103 44 70 pa11 i/o ft pa11 usart1_cts 104 45 71 pa12 i/o ft pa12 usart1_rts 105 46 72 pa13 i/o ft jtms-swdio pa13 106 - 73 not connected 107 47 74 v ss_2 sv ss_2 108 48 75 v dd_2 sv dd_2 109 49 76 pa14 i/o ft jtck- swclk pa14 110 50 77 pa15 i/o ft jtdi spi3_nss tim2_ch1_etr/ pa15 / spi1_nss 111 51 78 pc10 i/o ft pc10 uart4_tx usart3_tx table 5. stm32f101xf/stm32f101xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap
pinouts and pin descriptions stm32f101xf, stm32f101xg 30/115 docid16553 rev 3 112 52 79 pc11 i/o ft pc11 uart4_rx usart3_rx 113 53 80 pc12 i/o ft pc12 uart5_tx usart3_ck 114 - 81 pd0 i/o ft fsmc_d2 (9) 115 - 82 pd1 i/o ft fsmc_d3 (9) 116 54 83 pd2 i/o ft pd2 tim3_etr / uart5_rx 117 - 84 pd3 i/o ft pd3 fsmc_clk usart2_cts 118 - 85 pd4 i/o ft pd4 fsmc_noe usart2_rts 119 - 86 pd5 i/o ft pd5 fsmc_nwe usart2_tx 120 - - v ss_10 sv ss_10 121 - - v dd_10 sv dd_10 122 - 87 pd6 i/o ft pd6 fsmc_nwait usart2_rx 123 - 88 pd7 i/o ft pd7 fsmc_ne1 / fsmc_nce2 usart2_ck 124 - - pg9 i/o ft pg9 fsmc_ne2 / fsmc_nce3 125 - - pg10 i/o ft pg10 fsmc_ne3 / fsmc_nce4_1 126 - - pg11 i/o ft pg11 fsmc_nce4_2 127 - - pg12 i/o ft pg12 fsmc_ne4 128 - - pg13 i/o ft pg13 fsmc_a24 129 - - pg14 i/o ft pg14 fsmc_a25 130 - - v ss_11 sv ss_11 131 - - v dd_11 sv dd_11 132 - - pg15 i/o ft pg15 133 55 89 pb3 i/o ft jtdo spi3_sck tim2_ch2 /pb3 traceswo spi1_sck 134 56 90 pb4 i/o ft njtrst spi3_miso pb4 / tim3_ch1 spi1_miso 135 57 91 pb5 i/o pb5 i2c1_smba/ spi3_mosi tim3_ch2 / spi1_mosi 136 58 92 pb6 i/o ft pb6 i2c1_scl / tim4_ch1 (8) usart1_tx table 5. stm32f101xf/stm32f101xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap
docid16553 rev 3 31/115 stm32f101xf, stm32f101xg pinouts and pin descriptions 114 137 59 93 pb7 i/o ft pb7 i2c1_sda / fsmc_nadv / tim4_ch2 (8) usart1_rx 138 60 94 boot0 i boot0 139 61 95 pb8 i/o ft pb8 tim4_ch3 (8) / tim10_ch1 i2c1_scl 140 62 96 pb9 i/o ft pb9 tim4_ch4 (8) / tim10_ch1 i2c1_sda 141 - 97 pe0 i/o ft pe0 tim4_etr (8) / fsmc_nbl0 142 - 98 pe1 i/o ft pe1 fsmc_nbl1 143 63 99 v ss_3 sv ss_3 144 64 100 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. 3. function availability depends on the chosen device. 4. if several peripherals share the same i/o pin, to avoid conf lict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register description sections in the stm32f10xxx reference manual, available from the stmicroelectronics website: www.st.com. 7. for the lqfp64 package, the pins number 5 and 6 are co nfigured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by software on these pins. for the lqfp100 and lqfp144 packages, pd0 and pd1 are available by default, so there is no need for rem apping. for more details, refer to alternate function i/o and debug configuration section in the stm32f10xxx reference manual 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug conf iguration section in the stm32f10xxx reference manual, available from the stmicroelec tronics website: www.st.com. 9. for devices delivered in lqfp64 packages , the fsmc function is not available. table 5. stm32f101xf/stm32f101xg pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp144 lqfp64 lqfp100 default remap
pinouts and pin descriptions stm32f101xf, stm32f101xg 32/115 docid16553 rev 3 table 6. fsmc pin definition pins fsmc lqfp100 (1) cf cf/ide nor/psram/ sram nor/psram mux nand 16 bit pe2 a23 a23 yes pe3 a19 a19 yes pe4 a20 a20 yes pe5 a21 a21 yes pe6 a22 a22 yes pf0 a0 a0 a0 - pf1 a1 a1 a1 - pf2 a2 a2 a2 - pf3 a3 a3 - pf4 a4 a4 - pf5 a5 a5 - pf6 niord niord - pf7 nreg nreg - pf8 niowr niowr - pf9 cd cd - pf10 intr intr - pf11 nios16 nios16 - pf12 a6 a6 - pf13 a7 a7 - pf14 a8 a8 - pf15 a9 a9 - pg0 a10 a10 - pg1 a11 - pe7 d4 d4 d4 da4 d4 yes pe8 d5 d5 d5 da5 d5 yes pe9 d6 d6 d6 da6 d6 yes pe10 d7 d7 d7 da7 d7 yes pe11 d8 d8 d8 da8 d8 yes pe12 d9 d9 d9 da9 d9 yes pe13 d10 d10 d10 da10 d10 yes pe14 d11 d11 d11 da11 d11 yes pe15 d12 d12 d12 da12 d12 yes pd8 d13 d13 d13 da13 d13 yes
docid16553 rev 3 33/115 stm32f101xf, stm32f101xg pinouts and pin descriptions 114 pd9 d14 d14 d14 da14 d14 yes pd10 d15 d15 d15 da15 d15 yes pd11 a16 a16 cle yes pd12 a17 a17 ale yes pd13 a18 a18 yes pd14 d0 d0 d0 da0 d0 yes pd15 d1 d1 d1 da1 d1 yes pg2 a12 - pg3 a13 - pg4 a14 - pg5 a15 - pg6 int2 - pg7 int3 - pd0 d2 d2 d2 da2 d2 yes pd1 d3 d3 d3 da3 d3 yes pd3 clk clk yes pd4 noe noe noe noe noe yes pd5 nwe nwe nwe nwe nwe yes pd6 nwait nwait nwait nwait nwait yes pd7 ne1 ne1 nce2 yes pg9 ne2 ne2 nce3 - pg10 nce4_1 nce4_1 ne3 ne3 - pg11 nce4_2 nce4_2 - pg12 ne4 ne4 - pg13 a24 a24 - pg14 a25 a25 - pb7 nadv nadv yes pe0 nbl0 nbl0 yes pe1 nbl1 nbl1 yes 1. ports f and g are not available in devices delivered in 100-pin packages. table 6. fsmc pin definition (continued) pins fsmc lqfp100 (1) cf cf/ide nor/psram/ sram nor/psram mux nand 16 bit
memory mapping stm32f101xf, stm32f101xg 34/115 docid16553 rev 3 4 memory mapping the memory map is shown in figure 6 . figure 6. memory map 0e\wh eorfn &ruwh[0
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docid16553 rev 3 35/115 stm32f101xf, stm32f101xg electrical characteristics 114 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ). 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 7 .
electrical characteristics stm32f101xf, stm32f101xg 36/115 docid16553 rev 3 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 8 . 5.1.6 power supply scheme figure 9. power supply scheme caution: in figure 9 , the 4.7 f capacitor must be connected to v dd3 . figure 7. pin loading conditi ons figure 8. pin input voltage dl & s) 670)3,1 dl 670)3,1 9 ,1 ai 6 $$ !n alo g 2#s0,, 0o werswi tch 6 "!4 '0)/s /54 ). +ernellogic #05 $igital -emories "ackupcircuitry /3#+24# "ackupregisters 7ake uplogic n& ?& 6 2egulator 6 33 6 $$! 6 2%& 6 2%& 6 33! !$# $!# ,evelshifter )/ ,ogic 6 $$ n& ?& 6 2%& n& ?& 6 $$
docid16553 rev 3 37/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.1.7 current consumption measurement figure 10. current consum ption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 7: voltage characteristics , table 8: current characteristics , and table 9: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional ope ration of the device at these conditions is not im plied. exposure to maximum rating conditions for extended periods may affect device reliability. ai 6 "!4 6 $$ 6 $$! ) $$ ?6 "!4 ) $$ table 7. voltage characteristics symbol ratings min max unit v dd ? v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 8: current characteristics for the maximum allowed injected current values. input voltage on five volt tolerant pin v ss ? 0.3 v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins 50 mv |v ssx ? v ss | variations between all the different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.12: absolute maximum ratings (electrical sensitivity)
electrical characteristics stm32f101xf, stm32f101xg 38/115 docid16553 rev 3 table 8. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2) 2. negative injection disturbs the analog per formance of the device. see note 3 below table 59 on page 95 . injected current on five volt tolerant pins (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative injection is induced by v in docid16553 rev 3 39/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.3 operating conditions 5.3.1 general operating conditions 5.3.2 operating conditions at power-up / power-down the parameters given in table 11 are derived from tests performed under the ambient temperature condition summarized in table 10 . table 10. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 36 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 36 v dd standard operating voltage 2 3.6 v v dda (1) 1. when the adc is used, refer to table 56: adc characteristics . analog operating voltage (adc not used) must be the same potential as v dd (2) 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 23.6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.8 3.6 v p d power dissipation at t a = 85 c (3) 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 110 ). lqfp144 666 mw lqfp100 434 lqfp64 444 t a ambient temperature maximum power dissipation ?40 85 c low-power dissipation (4) 4. in low-power dissipation state, t a can be extended to this range as long as t j does not exceed t j max (see table 6.2: thermal characteristics on page 110 ). ?40 105 c t j junction temperature range ?40 105 c table 11. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 s/v v dd fall time rate 20
electrical characteristics stm32f101xf, stm32f101xg 40/115 docid16553 rev 3 5.3.3 embedded reset and power control block characteristics the parameters given in table 12 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . . table 12. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1.5 2.5 3.5 ms
docid16553 rev 3 41/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.3.4 embedded reference voltage the parameters given in table 13 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 10: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled except if it is explicitly mentioned ? the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 36 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk1 = f hclk/2 , f pclk2 = f hclk the parameters given in table 14 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . table 13. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/ c
electrical characteristics stm32f101xf, stm32f101xg 42/115 docid16553 rev 3 table 14. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. guaranteed by characterization results, not tested in production. unit t a = 85 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 41 ma 24 mhz 29 16 mhz 22 8 mhz 12.5 external clock (2) , all peripherals disabled 36 mhz 24 24 mhz 17.5 16 mhz 14 8 mhz 8.5 table 15. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. guaranteed by characterization results, tested in production at v dd max, f hclk max. unit t a = 85 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 37 ma 24 mhz 26.5 16 mhz 19 8 mhz 11.5 external clock (2) all peripherals disabled 36 mhz 20.5 24 mhz 15 16 mhz 11 8 mhz 7.5
docid16553 rev 3 43/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 11. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled figure 12. typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled 0 5 10 15 20 25 30 35 -45257085 temperature (c) consumption (ma) 8 mhz 16 mhz 24 mhz 36 mhz 0 2 4 6 8 10 12 14 16 18 -45 25 70 85 temperature (c) consumption (ma) 8 mhz 16 mhz 24 mhz 36 mhz
electrical characteristics stm32f101xf, stm32f101xg 44/115 docid16553 rev 3 table 16. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) 1. guaranteed by characterization results, tested in production at v dd max, f hclk max with peripherals enabled. unit t a = 85 c i dd supply current in sleep mode external clock (2) all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 27.5 ma 24 mhz 20 16 mhz 15 8 mhz 9 external clock (2) , all peripherals disabled 36 mhz 6.9 24 mhz 5.9 16 mhz 5.4 8 mhz 4.7 table 17. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd / v bat = 2.0 v v dd / v bat = 2.4 v v dd /v ba t = 3.3 v t a = 85 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 34.5 35 379 a regulator in low-power mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 24.5 25 365 supply current in standby mode low-speed internal rc oscillator and independent watchdog on 33.8 low-speed internal rc oscillator on, independent watchdog off 2.8 3.6 low-speed internal rc oscillator and independent watchdog off, low-speed oscillator and rtc off 1.9 2.1 5 (2) i dd_vbat backup domain supply current low-speed oscillator and rtc on 1.05 1.1 1.4 2 (2) 1. typical values are measured at t a = 25 c. 2. guaranteed by characterization results, not tested in production.
docid16553 rev 3 45/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 13. typical current consumption on v bat with rtc on vs. temperature at different v bat values figure 14. typical current consumption in standby mode versus temperature at different v dd values 7hpshudwxuh?& &rqvxpswlrq?$ 9 9 9 9 9 dl 0 0.5 1 1.5 2 2.5 3 3.5 -45257085 temperature (c) consumption (a) 2.4v 2.7v 3.0v 3.3v 3.6v
electrical characteristics stm32f101xf, stm32f101xg 46/115 docid16553 rev 3 typical current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled except if it is explicitly mentioned ? the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 36 mhz) ? prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk1 = f hclk/4 , f pclk2 = f hclk/2 , f adcclk = f pclk2 /4 ? when the peripherals are enabled f pclk1 = f hclk , f pclk2 = f hclk , f adcclk = f pclk2 /2 the parameters given in table 18 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . table 18. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 28.5 18.7 ma 24 mhz 24.1 12.8 16 mhz 14 9.2 8 mhz 7.7 5.4 4 mhz 4.6 3.4 2 mhz 3 2.3 1 mhz 2.2 1.8 500 khz 1.7 1.5 125 khz 1.4 1.3 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 27.5 17.5 24 mhz 18.9 11.6 16 mhz 12.2 8.2 8 mhz 7.2 4.8 4 mhz 4 2.7 2 mhz 2.3 1.7 1 mhz 1.5 1.2 500 khz 1.1 0.9 125 khz 0.75 0.7
docid16553 rev 3 47/115 stm32f101xf, stm32f101xg electrical characteristics 114 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 20 . the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature and v dd supply voltage conditions summarized in table 7 . table 19. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 36 mhz 17.7 4 ma 24 mhz 12.2 3.1 16 mhz 8.4 2.3 8 mhz 4.6 1.5 4 mhz 3 1.3 2 mhz 2.15 1.25 1 mhz 1.7 1.2 500 khz 1.5 1.15 125 khz 1.35 1.15 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 17 3.35 24 mhz 11.6 2.3 16 mhz 7.7 1.6 8 mhz 3.9 0.8 4 mhz 2.3 0.7 2 mhz 1.5 0.6 1 mhz 1.1 0.5 500 khz 0.9 0.5 125 khz 0.7 0.5
electrical characteristics stm32f101xf, stm32f101xg 48/115 docid16553 rev 3 table 20. peripheral current consumption peripheral typical consumption at 25 c (1) 1. f hclk = 36 mhz, f apb1 = f hclk/2 , f apb2 = f hclk , default prescaler value for each peripheral. unit apb1 tim2 0.8 ma tim3 0.8 tim4 0.8 tim5 0.75 tim6 0.3 tim7 0.3 tim12 0.5 tim13 0.4 tim14 0.4 spi2 0.3 spi3 0.3 usart2 0.35 usart3 0.35 usart4 0.35 usart5 0.35 i2c1 0.3 i2c2 0.3 dac (2) 2. specific conditions for dac: en1, en2 bits in th e dac_cr register are set to 1 and the converted value set to 0x800. 1.05 apb2 gpioa 0.35 ma gpiob 0.4 gpioc 0.4 gpiod 0.4 gpioe 0.4 gpiof 0.4 gpiog 0.4 tim1 1 tim8 1 tim9 0.5 tim10 0.4 tim11 0.4 adc1 (3) 1.4 spi1 0.3 usart1 0.6
docid16553 rev 3 49/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.3.6 external clock source characteristics high-speed external user clock generated from an external source the characteristics given in table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 10 . low-speed external user clock generated from an external source the characteristics given in table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 10 . 3. specific conditions for adc: f hclk = 28 mhz, f apb1 = f hclk/2 , f apb2 = f hclk , f adcclk = f apb2 /2, adon bit in the adc_cr2 register is set to 1. table 21. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production 1825mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 5 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5pf ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss v in v dd 1 a table 22. low-speed user external clock characteristics symbol parameter condi tions min typ max unit f lse_ext user external clock source frequency (1) 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50
electrical characteristics stm32f101xf, stm32f101xg 50/115 docid16553 rev 3 figure 15. high-speed external clock source ac timing diagram figure 16. low-speed external clock source ac timing diagram c in(lse) osc32_in input capacitance (1) 5pf ducy (lse) duty cycle 30 70 % i l osc32_in input leakage current v ss v in v dd 1 a 1. guaranteed by design, not tested in production. table 22. low-speed user external clock characteristics symbol parameter condi tions min typ max unit dle 26 & b, 1 ([whuqdo forfnvrxufh 670)[[[ 9 +6(+ w :+6( , / 7 +6( w w u+6( w :+6( i +6(bh[w 9 +6(/ dlf 26&b,1 ([whuqdo forfnvrxufh 670)[[[ 9 /6(+ w i/6( w :/6( , / 7 /6( w w u/6( w :/6( i /6(bh[w 9 /6(/
docid16553 rev 3 51/115 stm32f101xf, stm32f101xg electrical characteristics 114 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 23 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 17 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 23. hse 4-16 mhz oscillator characteristics (1)(2) 1. resonator characteristics given by t he crystal/ceramic resonator manufacturer. 2. guaranteed by characterization results, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor 200 k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 30 pf i 2 hse driving current v dd = 3.3 v v in = v ss with 30 pf load 1ma g m oscillator transconductance startup 25 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms
electrical characteristics stm32f101xf, stm32f101xg 52/115 docid16553 rev 3 figure 17. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 24 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). dle 26&b28 7 26&b,1 i +6( & / 5 ) 670)[[[ 0+ ] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq 5 (;7 & / table 24. lse oscillator characteristics (f lse = 32.768 khz) (1) (2) symbol parameter conditions min typ max unit r f feedback resistor 5 m c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) r s = 30 k 15 pf i 2 lse driving current v dd = 3.3 v v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (3) startup time v dd is stabilized t a = 50 c 1.5 s t a = 25 c 2.5 t a = 10 c 4 t a = 0 c 6 t a = -10 c 10 t a = -20 c 17 t a = -30 c 32 t a = -40 c 60 1. guaranteed by characterization results, not tested in production. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. t su(lse) is the startup time measured from the moment it is e nabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
docid16553 rev 3 53/115 stm32f101xf, stm32f101xg electrical characteristics 114 note: for c l1 and c l2 , it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator. c l1 and c l2, are usually the same size. the crystal manufacture r typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 18. typical applicati on with a 32.768 khz crystal 5.3.7 internal clock source characteristics the parameters given in table 25 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . high-speed internal (hsi) rc oscillator dle 26&b28 7 26&b,1 i /6( & / 5 ) 670)[[[ .+ ] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq & / table 25. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 85 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz ducy (hsi) duty cycle 45 55 % acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 1 (3) % factory- calibrated (4) t a = ?40 to 105 c ?2 2.5 % t a = ?10 to 85 c ?1.5 2.2 % t a = 0 to 70 c ?1.3 2 % t a = 25 c ?1.1 1.8 % t su(hsi) (4) hsi oscillator startup time 12s i dd(hsi) (4) hsi oscillator power consumption 80 100 a
electrical characteristics stm32f101xf, stm32f101xg 54/115 docid16553 rev 3 low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in table 27 are measured on a wakeup phase with an 8-mhz hsi rc oscillator. the clock source used to wake up the device depends from the current operating mode: ? stop or standby mode: the clo ck source is the rc oscillator ? sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibration? available from the st website www.st.com. 3. guaranteed by design, not tested in production. 4. guaranteed by characterization results, not tested in production. table 26. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 85 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization results, not tested in production. frequency 30 40 60 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (3) lsi oscillator power consumption 0.65 1.2 a table 27. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low-power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s
docid16553 rev 3 55/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.3.8 pll characteristics the parameters given in table 28 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . 5.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 85 c unless otherwise specified. table 28. pll characteristics symbol parameter value unit min (1) typ max (1) 1. guaranteed by characterization results, not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.025mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 36 mhz t lock pll lock time 200 s jitter cycle-to-cycle jitter 300 ps table 29. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +85 c 40 52.5 70 s t erase page (2 kb) erase time t a = ?40 to +85 c 20 40 ms t me mass erase time t a = ?40 to +85 c 20 40 ms i dd supply current read mode f hclk = 36 mhz with 1 wait state, v dd = 3.3 v 28 ma write mode f hclk = 36 mhz, v dd = 3.3 v 7ma erase mode f hclk = 36 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v
electrical characteristics stm32f101xf, stm32f101xg 56/115 docid16553 rev 3 5.3.10 fsmc characteristics asynchronous waveforms and timings figure 19 through figure 22 represent asynchronous waveforms and table 31 through table 34 provide the corresponding ti mings. the results shown in these tables are obtained with the following fsmc configuration: ? addresssetuptime = 0 ? addressholdtime = 1 ? datasetuptime = 1 table 30. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization re sults, not tested in production. n end endurance t a = ?40 c to 85 c 10 kcycles t ret data retention t a = 85 c, 1 kcycle (2) 2. cycling performed over the whole temperature range. 30 years t a = 55 c, 10 kcycle (2) 20
docid16553 rev 3 57/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 19. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. note: fsmc_busturnaroundduration = 0. 'dwd )60&b1( )60&b1%/>@ )60&b'>@ w y%/b1( w k'dwdb1( )60&b12( $gguhvv )60&b$>@ w y$b1( )60&b1:( w vx'dwdb1( w z1( 069 z12( w w y12(b1( w k1(b12( w k'dwdb12( w k$b12( w k%/b12( w vx'dwdb12( )60&b1$'9 w y1$'9b1( w z1$'9 table 31. asynchronous non-multiplexed sram/psram/nor read timings (1) (2) symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk + 0.5 5t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 1.5 ns t w(noe) fsmc_noe low time 5t hclk ? 1 5t hclk + 1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 3 ns t h(a_noe) address hold time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0.5 - ns t su(data_ne) data to fsmc_nex high setup time 2t hclk - 1 - ns t su(data_noe) data to fsmc_noex high setup time 2t hclk - 1 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns
electrical characteristics stm32f101xf, stm32f101xg 58/115 docid16553 rev 3 figure 20. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. t h(data_ne) data hold time after fsmc_nex high 0 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 0 ns t w(nadv) fsmc_nadv low time - t hclk + 2 ns 1. c l = 15 pf. 2. guaranteed by characterization results, not tested in production. table 32. asynchronous non-multipl exed sram/psram/nor write timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk + 0.5 3t hclk + 1.5 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk + 0.5 t hclk + 1.5 ns t w(nwe) fsmc_nwe low time t hclk ? 0.5 t hclk + 1 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ? 0.5 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t h(a_nwe) address hold time after fsmc_nwe high t hclk -ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1.5 - ns t v(data_ne) fsmc_nex low to data valid - t hclk ns table 31. asynchronous non-multipl exed sram/psram/nor read timings (1) (2) symbol parameter min max unit 1%/ 'dwd )60&b1([ )60&b1%/>@ )60&b'>@ w y%/b1( w k'dwdb1:( )60&b12( $gguhvv )60&b$>@ w y$b1( w z1:( )60&b1:( w y1:(b1( w k1(b1:( w k$b1:( w k%/b1:( w y'dwdb1( w z1( dl )60&b1$'9 w y1$'9b1( w z1$'9
docid16553 rev 3 59/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 21. asynchronous multiplexed nor/psram read waveforms t h(data_nwe) data hold time after fsmc_nwe high t hclk -ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 0 ns t w(nadv) fsmc_nadv low time - t hclk + 1.5 ns 1. c l = 15 pf. 2. guaranteed by characterization results, not tested in production. table 33. asynchronous multip lexed nor/psram read timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 7t hclk + 0.5 7t hclk + 2 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 3t hclk + 0.5 3t hclk + 1.5 ns t w(noe) fsmc_noe low time 4t hclk ? 1 4t hclk + 1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0.5 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 0 1 ns t w(nadv) fsmc_nadv low time t hclk + 0.5 t hclk + 2 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk - ns table 32. asynchronous non-multiple xed sram/psram/nor write timings (1)(2) symbol parameter min max unit .", $ata &3-#?.",;= &3-#? !$;= t v",?.% t h$ata?.% !ddress &3-#?!;= t v!?.% &3-#?.7% t v!?.% aib !ddress &3-#?.!$6 t v.!$6?.% t w.!$6 t su$ata?.% t h!$?.!$6 &3-#?.% &3-#?./% t w.% t w./% t v./%?.% t h.%?./% t h!?./% t h",?./% t su$ata?./% t h$ata?./%
electrical characteristics stm32f101xf, stm32f101xg 60/115 docid16553 rev 3 t h(a_noe) address hold time after fsmc_noe high t hclk -2 - ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0.5 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0 ns t su(data_ne) data to fsmc_nex high setup time 4t hclk - 0.5 - ns t su(data_noe) data to fsmc_noe high setup time 4t hclk - 1 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns 1. c l = 15 pf. 2. guaranteed by characterization results, not tested in production table 33. asynchronous multip lexed nor/psram read timings (1)(2) (continued) symbol parameter min max unit
docid16553 rev 3 61/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 22. asynchronous multip lexed nor/psram write waveforms table 34. asynchrono us multiplexed nor/ psram write timings (1)(2) 1. c l = 15 pf. 2. guaranteed by characterization re sults, not tested in production.. symbol parameter min max unit t w(ne) fsmc_ne low time 5t hclk + 0.5 5t hclk + 2 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk + 1 t hclk + 1.5 ns t w(nwe) fsmc_nwe low time 3t hclk ? 1 3t hclk + 2 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk - 0.5 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 3.5 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 0 1 ns t w(nadv) fsmc_nadv low time t hclk + 0.5 t hclk + 1.5 ns t h(ad_nadv) fsmc_ad (address) valid hold time after fsmc_nadv high t hclk ? 0.5 - ns t h(a_nwe) address hold time after fsmc_nwe high 4t hclk ? 2 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 0.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1.5 - ns t v(data_nadv) fsmc_nadv high to data valid - t hclk + 6 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ? 0.5 - ns 1%/ 'dwd )60&b1([ )60&b1%/>@ )60&b$'>@ w y%/b1( w k'dwdb1:( )60&b12( $gguhvv )60&b$>@ w y$b1( w z1:( )60&b1:( w y1:(b1( w k1(b1:( w k$b1:( w k%/b1:( w y$b1( w z1( dl% $gguhvv )60&b1$'9 w y1$'9b1( w z1$'9 w y'dwdb1$'9 w k$'b1$'9
electrical characteristics stm32f101xf, stm32f101xg 62/115 docid16553 rev 3 synchronous waveforms and timings figure 23 through figure 26 represent synchronous waveforms and table 36 through table 38 provide the corresponding ti mings. the results shown in these tables are obtained with the following fsmc configuration: ? burstaccessmode = fsmc_burstaccessmode_enable; ? memorytype = fsmc_memorytype_cram; ? writeburst = fsmc_writeburst_enable; ? clkdivision = 1; (0 is not supported, see the stm32f10xxx reference manual) ? datalatency = 1 for nor flash; datalatency = 0 for psram figure 23. synchronous multiplexed nor/psram read timings )60&b&/. )60&b1([ )60&b1$'9 )60&b$>@ )60&b12( )60&b$'>@ $'>@ ' ' )60&b1:$,7 :$,7&)* e:$,732/e )60&b1:$,7 :$,7&)* e:$,732/e w z&/. w z&/. 'dwdodwhqf\ %867851 w g&/./1([/ w g&/./1([+ w g&/./1$'9/ w g&/./$9 w g&/./1$'9+ w g&/./$,9 w g&/.+12(/ w g&/./12(+ w g&/./$'9 w g&/./$',9 w vx$'9&/.+ w k&/.+$'9 w vx$'9&/.+ w k&/.+$'9 w vx1:$,79&/.+ w k&/.+1:$,79 w vx1:$,79&/.+ w k&/.+1:$,79 w vx1:$,79&/.+ w k&/.+1:$,79 dlk
docid16553 rev 3 63/115 stm32f101xf, stm32f101xg electrical characteristics 114 table 35. synchronous multiplexed nor/psram read timings (1)(2) 1. c l = 15 pf. 2. guaranteed by characterization results, not tested in production.. symbol parameter min max unit t w(clk) fsmc_clk period 55.5 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 0.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 0.5 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 1.5 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - 14 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 11 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0.5 - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 2- ns t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 - ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 8 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns
electrical characteristics stm32f101xf, stm32f101xg 64/115 docid16553 rev 3 figure 24. synchronous multiplexed psram write timings &3-#?#,+ &3-#?.%x &3-#?.!$6 &3-#?!;= &3-#?.7% &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+, !)6 t d#,+, .7%( t d#,+, .7%, t d#,+, .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 aig t d#,+, $ata &3-#?.",
docid16553 rev 3 65/115 stm32f101xf, stm32f101xg electrical characteristics 114 table 36. synchronous multiplexed psram write timings (1)(2) 1. c l = 15 pf. 2. guaranteed by characterization results, not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 27.5 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 1 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 1 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1.5 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 10 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 1 - ns t d(clkl-data) fsmc_a/d[15:0] valid after fsmc_clk low - 6 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 1 - ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns
electrical characteristics stm32f101xf, stm32f101xg 66/115 docid16553 rev 3 figure 25. synchronous non-multiplexed nor/psram read timings table 37. synchronous non-multipl exed nor/psram read timings (1)(2) 1. c l = 15 pf. symbol parameter min max unit t w(clk) fsmc_clk period 27.6 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 1.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 2 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 0.5 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 1 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 0...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 0...25) 2 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - t hclk + 1 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 - ns t su(dv-clkh) fsmc_d[15:0] valid data before fsmc_clk high 3.5 - ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 0 - ns t su(nwaitv-clkh) fsmc_nwait valid before fsmc_smclk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns &3-#?#,+ &3-#?.%x &3-#?!;= &3-#?./% &3-#?$;= $ $ &3-#?.7!)4 7!)4#&'b7!)40/,b &3-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+, .%x( t d#,+, !6 t d#,+, !)6 t d#,+( ./%, t d#,+, ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 aig &3-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( $
docid16553 rev 3 67/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 26. synchronous non-multi plexed psram write timings 2. guaranteed by characterization re sults, not tested in production. table 38. synchronous non-multiplexed psram write timings (1)(2) symbol parameter min max unit t w(clk) fsmc_clk period 27.6 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x = 0...2) - 0.5 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x = 0...2) 1.5 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 1 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 0.5 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x = 16...25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x = 16...25) 1.5 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 1.5 - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - 2.5 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 0.5 - ns )60&b&/. )60&b1([ )60&b1$'9 )60&b$>@ )60&b12( )60&b$'>@ $'>@ ' ' )60&b1:$,7 :$,7&)* e:$,732/e )60&b1:$,7 :$,7&)* e:$,732/e w z&/. w z&/. 'dwdodwhqf\ %867851 w g&/./1([/ w g&/./1([+ w g&/./1$'9/ w g&/./$9 w g&/./1$'9+ w g&/./$,9 w g&/.+12(/ w g&/./12(+ w g&/./$'9 w g&/./$',9 w vx$'9&/.+ w k&/.+$'9 w vx$'9&/.+ w k&/.+$'9 w vx1:$,79&/.+ w k&/.+1:$,79 w vx1:$,79&/.+ w k&/.+1:$,79 w vx1:$,79&/.+ w k&/.+1:$,79 dlk
electrical characteristics stm32f101xf, stm32f101xg 68/115 docid16553 rev 3 pc card/compactflash controller waveforms and timings figure 27 through figure 32 represent synchronous waveforms and table 40 and table 41 provide the corresponding timings. the result s shown in this table are obtained with the following fsmc configuration: ? com.fsmc_setuptime = 0x04; ? com.fsmc_waitsetuptime = 0x07; ? com.fsmc_holdsetuptime = 0x04; ? com.fsmc_hizsetuptime = 0x00; ? att.fsmc_setuptime = 0x04; ? att.fsmc_waitsetuptime = 0x07; ? att.fsmc_holdsetuptime = 0x04; ? att.fsmc_hizsetuptime = 0x00; ? io.fsmc_setuptime = 0x04; ? io.fsmc_waitsetuptime = 0x07; ? io.fsmc_holdsetuptime = 0x04; ? io.fsmc_hizsetu ptime = 0x00; ? tclrsetuptime = 0; ? tarsetuptime = 0; t su(nwaitv-clkh) fsmc_nwait valid before fsmc_clk high 7 ns t h(clkh-nwaitv) fsmc_nwait valid after fsmc_clk high 2 ns 1. c l = 15 pf. 2. guaranteed by characterization results, not tested in production. table 38. synchronous non-multiplexed psram write timings (1)(2) (continued) symbol parameter min max unit
docid16553 rev 3 69/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 27. pc card/compactflash controll er waveforms for common memory read access 1. fsmc_nce4_2 remains high (inac tive during 8-bit access. figure 28. pc card/compactflash contro ller waveforms for co mmon memory write access )60&b1:( w z12( )60&b1 2( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g1&(b12( w vx'12( w k12(' w y1&([$ w g15(*1&([ w g1,25'1&([ w k1&([$, w k1&([15(* w k1&([1,25' w k1&([ 1,2:5 dle w g1&(b1:( w z1:( w k1:(' w y1&(b$ w g15(*1&(b w g1,25'1&(b w k1&(b$, 0(0[+,= w y1:(' w k1&(b15(* w k1&(b1,25' w k1&(b1,2:5 dle )60&b1:( )60&b1 2( )60&b'>@ )60&b$>@ )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g1:(1&(b w g'1:( )60&b1&(b +ljk
electrical characteristics stm32f101xf, stm32f101xg 70/115 docid16553 rev 3 figure 29. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). w g1&(b12( w z12( w vx'12( w k12(' w y1&(b$ w k1&(b$, w g15(*1&(b w k1&(b15(* dle )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g12(1&(b +ljk
docid16553 rev 3 71/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 30. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are dr iven (bits 8...15 remains hiz). figure 31. pc card/compactflash controll er waveforms for i/o space read access w z1:( w y1&(b$ w g15(*1&(b w k1&(b$, w k1&(b15(* w y1:(' dle )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25' w g1:(1&(b +ljk w g1&(b1:( w g1,25'1&(b w z1,25' w vx'1,25' w g1,25'' w y1&([$ w k1&(b$, dl% )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1&(b )60&b1&(b )60&b15(* )60&b1,2:5 )60&b1,25'
electrical characteristics stm32f101xf, stm32f101xg 72/115 docid16553 rev 3 figure 32. pc card/compactflash controller waveforms for i/o space write access w g1&(b1,2:5 w z1,2:5 w y1&([$ w k1&(b$, w k1,2:5' $77[+,= w y1,2:5' dle )60&b1:( )60&b12( )60&b'>@ )60&b$>@ )60&b1,2:5 )60&b15(* )60&b1,2:5 )60&b1,25' table 39. switching characteristics for pc card/cf read and write cycles in attribute/common space symbol parameter min max unit t v(ncex-a) fsmc_ncex low to fsmc_ay valid - 0 ns t h(ncex-ai) fsmc_ncex high to fsmc_ax invalid 0 - t d(nreg-ncex) fsmc_ncex low to fsmc_nreg valid - 2 t h(ncex-nreg) fsmc_ncex high to fsmc_nreg invalid t hclk + 4 - t d(ncex_nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 t d(ncex_noe) fsmc_ncex low to fsmc_noe low - 5t hclk + 1 t w(noe) fsmc_noe low width 8t hclk - 0.5 8t hclk + 1 t d(noe-ncex fsmc_noe high to fsmc_ncex high 5t hclk - 0.5 - t su(d-noe) fsmc_d[15:0] valid data before fsmc_noe high 32 - t h(noe-d) fsmc_noe high to fsmc_d[15:0] invalid t hclk - t w(nwe) fsmc_nwe low width 8t hclk ? 1 8t hclk + 4 t d(nwe_ncex) fsmc_nwe high to fsmc_ncex high 5t hclk + 1.5 - t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 t h(nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 11t hclk - t d(d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk + 2.5 -
docid16553 rev 3 73/115 stm32f101xf, stm32f101xg electrical characteristics 114 nand controller waveforms and timings figure 33 through figure 36 represent synchronous waveforms and table 40 and table 41 provide the corresponding timings. the result s shown in this table are obtained with the following fsmc configuration: ? com.fsmc_setuptime = 0x00; ? com.fsmc_waitsetuptime = 0x02; ? com.fsmc_holdsetuptime = 0x02; ? com.fsmc_hizsetuptime = 0x00; ? att.fsmc_setuptime = 0x01; ? att.fsmc_waitsetuptime = 0x02; ? att.fsmc_holdsetuptime = 0x01; ? att.fsmc_hizsetuptime = 0x00; ? bank = fsmc_bank_nand; ? memorydatawidth = fsmc_memorydatawidth_16b; ? ecc = fsmc_ecc_enable; ? eccpagesize = fsmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0; table 40. switching characteristics for pc card/cf read and write cycles in i/o space symbol parameter min max unit tw (niowr) fsmc_niowr low width 8 thclk - ns tv (niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - 5 thclk - 4 ns th (niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 11thclk - 7 -ns td (nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - 5thclk + 1 ns th (ncex-niowr) fsmc_ncex high to fsmc_niowr invalid 5thclk - 2.5 -ns td (niord-ncex) fsmc_ncex low to fsmc_niord valid - 5thclk - 0.5 ns th (ncex-niord) fsmc_ncex high to fsmc_niord) valid 5 thclk - 0.5 -ns tw (niord) fsmc_niord low width 8thclk - ns tsu (d-niord) fsmc_d[15:0] valid before fsmc_niord high 28 ns td (niord-d) fsmc_d[15:0] valid after fsmc_niord high 3 ns
electrical characteristics stm32f101xf, stm32f101xg 74/115 docid16553 rev 3 figure 33. nand controller waveforms for read access figure 34. nand controller waveforms for write access figure 35. nand controller waveforms for common memory read access )60&b1:( )60&b12(15( )60&b'>@ w vx'12( w k12(' dle $/()60&b$ &/()60&b$ )60&b1&([ /rz w g$/(12( w k12($/( w k1:(' w y1:(' dle )60&b1:( )60&b12(15( )60&b'>@ $/()60&b$ &/()60&b$ )60&b1&([ /rz w g$/(1:( w k1:($/( )60&b1:( )60&b1 2( )60&b'>@ w z12( w vx'12( w k12(' dle $/()60&b$ &/()60&b$ )60&b1&([ /rz w g$/(12( w k12($/(
docid16553 rev 3 75/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 36. nand controller wavefo rms for common memory write access 5.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. table 41. switching characteris tics for nand flash write cycles (1) 1. c l = 15 pf. symbol parameter min max unit t w(nwe) fsmc_nwe low width 3t hclk 3t hclk ns t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 2t hclk + 2 - ns t d(ale-nwe) fsmc_ale valid before fsmc_nwe low - 3t hclk + 1.5 ns t h(nwe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk + 8 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 2t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 2t hclk - ns w z1:( w k1:(' w y1:(' dle )60&b1:( )60&b1 2( )60&b'>@ w g'1:( $/()60&b$ &/()60&b$ )60&b1&([ /rz w g$/(1:( w k1:($/(
electrical characteristics stm32f101xf, stm32f101xg 76/115 docid16553 rev 3 the test results are given in table 42 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and pre qualification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be app lied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 42. ems characteristics symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 36 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp144, t a = +25 c, f hclk = 36 mhz conforms to iec 61000-4-4 4a table 43. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/36 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp144 package compliant with iec 61967-2 0.1 mhz to 30 mhz 8 dbv 30 mhz to 130 mhz 27 130 mhz to 1 ghz 26 sae emi level 4 -
docid16553 rev 3 77/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.3.12 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/ ansi/esd stm5.3.1 standard. static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78 ic latch-up standard. 5.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the de vice, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adja cent pins or other functional failure (for example reset, oscillator frequency deviation). table 44. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 ii 500 table 45. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +85 c conforming to jesd78a ii level a
electrical characteristics stm32f101xf, stm32f101xg 78/115 docid16553 rev 3 the test results are given in table 46 table 46. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on osc_in32, osc_out32, pa4, pa5, pc13 -0 +0 ma injected current on all ft pins -5 +0 injected current on any other pin -5 +5
docid16553 rev 3 79/115 stm32f101xf, stm32f101xg electrical characteristics 114 5.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 47 are derived from tests performed under the conditions summarized in table 10 . all i/os are cmos and ttl compliant. all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 37 and figure 38 for standard i/os, and in figure 39 and figure 40 for 5 v tolerant i/os. table 47. i/o static characteristics symbol parameter conditions min typ max unit v il standard io input low level voltage ?0.3 0.28*(v dd -2 v)+0.8 v v io ft (1) input low level voltage ?0.3 0.32*(v dd -2v)+0.75 v v v ih standard io input high level voltage 0.41*(v dd -2 v)+1.3 v v dd +0.3 v io ft (1) input high level voltage v dd > 2 v 0.42*(v dd -2 v)+1 v 5.5 v v dd 2 v 5.2 v hys standard io schmitt trigger voltage hysteresis (2) 200 mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) mv i lkg input leakage current (4) v ss v in v dd standard i/os 1 a v in = 5 v i/o ft 3 r pu weak pull-up equivalent resistor (5) v in = v ss 30 40 50 k r pd weak pull-down equivalent resistor (5) v in = v dd 30 40 50 k c io i/o pin capacitance 5 pf 1. ft = five-volt tolerant. in order to sustain a voltage higher than v dd +0.3 the internal pull-up/pull-down resistors must be disabled. 2. hysteresis voltage between schmitt trigger switching levels . guaranteed by characterization results, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negative current is injected on adjacent pins. 5. pull-up and pull-down resistors are designed with a true re sistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order) .
electrical characteristics stm32f101xf, stm32f101xg 80/115 docid16553 rev 3 figure 37. standard i/o input characteristics - cmos port figure 38. standard i/o input characteristics - ttl port aib 6 $$ 6 )nputrange notguaranteed 6 )( 6 $$ #-/3standardrequirement6 )( 6 $$ 6 )( 6 ), 6 #-/3standardrequirement6 ), 6 $$ 7 ),max 7 )(min 6 $$ 6 ), ai )nputrange notguaranteed 6 )( 6 ), 6 44,requirements 6 )( 6 6 )( 6 $$ 6 ), 6 $$ 44,requirements 6 ), 6 6 $$ 6 7 ),max 7 )(min
docid16553 rev 3 81/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 39. 5 v tolerant i/o inpu t characteristics - cmos port figure 40. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can si nk or source up to 8 ma, and sink or source up to 20 ma (with a relaxedv ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3 ma. when using th e gpios pc13 to pc15 in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 5.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 8 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 8 ). 6$$ #-/3standardrequirements6 )( 6 $$ #-/3standardrequirment6 ), 6 $$ 6 )( 6 ), 6 6 $$ 6 )nputrange notguaranteed aib 6 )( 6 $$ 6 ), 6 $$ notguaranteed )nputrange 44,requirement6 )( 6 6 )(
6 $$ 6 ),
6 $$ 44,requirements6 ), 6 6 )( 6 ), 6 6 $$ 6 7 ),max 7 )(min ai 6 )(
6 $$ 6 ),
6 $$ "asedondesignsimulations "asedondesignsimulations
electrical characteristics stm32f101xf, stm32f101xg 82/115 docid16553 rev 3 output voltage levels unless otherwise specified, the parameters given in table 48 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . all i/os are cmos and ttl compliant. table 48. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at the same time cmos port (2) , i io = +8 ma, 2.7 v < v dd < 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 8 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time 2.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +20 ma (4) 2.7 v < v dd < 3.6 v 4. guaranteed by characterization results, not tested in production. 1.3 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?1.3 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +6 ma (4) 2 v < v dd < 2.7 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4
docid16553 rev 3 83/115 stm32f101xf, stm32f101xg electrical characteristics 114 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 41 and table 49 , respectively. unless otherwise specified, the parameters given in table 49 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . table 49. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bits. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex [1:0] bit value (1) symbol parameter conditions max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 41 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to hi gh level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to hi gh level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to hi gh level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns
electrical characteristics stm32f101xf, stm32f101xg 84/115 docid16553 rev 3 figure 41. i/o ac charac teristics definition 5.3.15 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 47 ). unless otherwise specified, the parameters given in table 50 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 10 . dlg w u,2rxw 287387 (;7(51$/ 21&/ 0d[lpxpiuhtxhqf\lvdfklhyhgliw u w i ?7dqgliwkhgxw\f\fohlv zkhqordghge\& / vshflilhglqwkhwdeoh3 ,2$&fkdudfwhulvwlfv 7 w i,2rxw table 50. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 ns
docid16553 rev 3 85/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 42. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 50 . otherwise the reset will not be taken into account by the device. dlf 670) 5 38 1567 9 '' )lowhu ,qwhuqdo5hvhw ?) ([whuqdo uhvhwflufxlw
electrical characteristics stm32f101xf, stm32f101xg 86/115 docid16553 rev 3 5.3.16 tim time r characteristics the parameters given in table 51 are guaranteed by design. refer to section 5.3.13: i/o current injection char acteristics for details on the input/output alternate function characteristics (output comp are, input capture, external clock, pwm output). 5.3.17 communications interfaces i 2 c interface characteristics the stm32f101xf and stm32f101xg access line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: t he i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 52 . refer also to section 5.3.13: i/o current injection characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 51. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 36 mhz 27.8 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 36 mhz 018mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 36 mhz 0.0278 1820 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 36 mhz 119.2 s
docid16553 rev 3 87/115 stm32f101xf, stm32f101xg electrical characteristics 114 table 52. i 2 c characteristics symbol parameter standard mode i 2 c (1)(2) 1. guaranteed by design, not tested in production. 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve the fast mode i 2 c frequencies and it must be a multiple of 10 mhz in order to reach the i2c fast mode maximum clock speed of 400 khz. fast mode i 2 c (1)(2) unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time - 3450 (3) 3. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. - 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 - 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf t sp pulse width of the spikes that are suppressed by the analog filter for standard and fast mode 050 (4) 4. the minimum width of the spikes filtered by the analog filter is above t sp (max). 050 (4) s
electrical characteristics stm32f101xf, stm32f101xg 88/115 docid16553 rev 3 figure 43. i 2 c bus ac waveforms and measurement circuit (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . 1. r s = series protection resistor. 2. r p = external pull-up resistor. 3. v dd_i2c is the i2c bus power supply. table 53. scl frequency (f pclk1 = 36 mhz, v dd = v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tolerance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384 ]e?? ^dzd ^ z w /?? s z/? ^dd?? ^ ^> ? (~^ ? ?~^ ^> ? z~^d ? ~^>, ? ~^>> ? ?~^ ? ?~^> ? (~^> ? z~^ ^ d z dzwd ^dzd ? ?~^d ? ?~^dk ^dkw ? ~^dkw^d s z/? z w z ^ z ^
docid16553 rev 3 89/115 stm32f101xf, stm32f101xg electrical characteristics 114 spi interface characteristics unless otherwise specified, the parameters given in table 54table 55 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 10 . refer to section 5.3.13: i/o current injection char acteristics for more details on the input/output alternate function char acteristics (nss, sck, mosi, miso). table 54. stm32f10xxx spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 10 mhz slave mode 10 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns t su(nss) (1) 1. guaranteed by characterization re sults, not tested in production. nss setup time slave mode 4t pclk t h(nss) (1) nss hold time slave mode 73 t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (1) t su(si) (1) data input setup time master mode - spi1 3 master mode - spi2 5 slave mode 4 t h(mi) (1) data input hold time master mode - spi1 4 master mode - spi2 6 t h(si) (1) slave mode 5 t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 36 mhz, presc = 4 055 slave mode, f pclk = 20 mhz 4t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the out put and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 10 t v(so) (1) data output valid time slave mode (after enable edge) 25 t v(mo) (1) data output valid time master mode (after enable edge) 6 t h(so) (1) data output hold time slave mode (after enable edge) 25 t h(mo) (1) master mode (after enable edge) 6
electrical characteristics stm32f101xf, stm32f101xg 90/115 docid16553 rev 3 table 55. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 18 mhz slave mode 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) nss setup time slave mode 4t pclk ns t h(nss) (1) nss hold time slave mode 2t pclk t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 5 t h(mi) (1) data input hold time master mode 5 t h(si) (1) slave mode 4 t a(so) (1)(2) data output access time slave mode, f pclk = 20 mhz 0 3t pclk t dis(so) (1)(3) data output disable time slave mode 2 10 t v(so) (1)(1) data output valid time slave mode (after enable edge) 25 t v(mo) (1)(1) data output valid time master mode (after enable edge) 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 t h(mo) (1) master mode (after enable edge) 2 1. guaranteed by characterization results not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z
docid16553 rev 3 91/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 44. spi timing diagram - slave mode and cpha=0 figure 45. spi timing diagra m - slave mode and cpha=1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . dlf ^</v?? w,a dk^/ / ewhd d/^k khd whd w,a d^ k hd d^ /e /d khd >^ /e >^ khd wk>a wk>a /d /e e^^]v?? ?^h~e^^ ?~^< ?z~e^^ ?~^k ?~^<,?~^<> ?~^k ?z~^k ??~^<?(~^< ?]?~^k ??~^/ ?z~^/ dl ^</v?? w,a dk^ / /ewhd d/^ k khd w hd w,a d^ k h d d^ /e / d khd >^ /e >^ khd wk>a wk>a /d /e ? ^h~e^^ ? ~^< ? z~e^^ ? ~^k ? ~^>, ? ~^>> ? ~^k ? z~^k ? ?~^> ? (~^> ? ]?~^k ? ?~^/ ? z~^/ e^^]v??
electrical characteristics stm32f101xf, stm32f101xg 92/115 docid16553 rev 3 figure 46. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . 5.3.18 12-bit adc characteristics unless otherwise specified, the parameters given in table 56 are preliminary values derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in table 10 . note: it is recommended to perform a calibration after each power-up. ai6 3#+/utput #0(! -/3) /54054 -)3/ ).0 54 #0(! -3 "). - 3"/54 ") 4). ,3"/54 ,3"). #0/, #0/, " ) 4/54 .33input t c3#+ t w3#+( t w3#+, t r3#+ t f3#+ t h-) (igh 3#+/utput #0(! #0(! #0/, #0/, t su-) t v-/ t h-/
docid16553 rev 3 93/115 stm32f101xf, stm32f101xg electrical characteristics 114 equation 1: r ain max formula: table 56. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 220 (1) 1. guaranteed by characterization results, not tested in production. a f adc adc clock frequency 0.6 14 mhz f s (2) 2. guaranteed by design, not tested in production. sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain conversion voltage range (3) 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 3: pinouts and pin descriptions for further details. 0 (v ssa or v ref- tied to ground) v ref+ v r ain (2) external input impedance see equation 1 and table 57 for details 50 k r adc (2) sampling switch resistance 1 k c adc (2) internal sample and hold capacitor 8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t lat (2) injection trigger conversion latency f adc = 14 mhz 0.214 s 3 (4) 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 56 . 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (4) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc r ain t s f adc c adc 2 n2 + () ln ------------------------------------------------------------- - r adc ? <
electrical characteristics stm32f101xf, stm32f101xg 94/115 docid16553 rev 3 the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 57. r ain max for f adc = 14 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 58. adc accuracy - limited test conditions (1)(2) 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: inje cting negative current on any of the standard analog input pins should be avoided as this significantly reduc es the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.13 does not affect the adc accuracy. symbol parameter test conditions typ max (3) 3. guaranteed by characterization results, not tested in production. unit et total unadjusted error f pclk2 = 28 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 3 v to 3.6 v, t a = 25 c measurements made after adc calibration v ref+ = v dda 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5
docid16553 rev 3 95/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 47. adc accuracy characteristics table 59. adc accuracy (1) (2)(3) 1. adc dc accuracy values are measured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency, v ref and temperature ranges. 3. adc accuracy vs. negative injection current: injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.13 does not affect the adc accuracy. symbol parameter test conditions typ max (4) 4. preliminary values. unit et total unadjusted error f pclk2 = 28 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 ( 2 ( * / 6% ,'($/ ([dpsohridqdfwxdowudqvihufxuyh 7khlghdowudqvihufxuyh (qgsrlqwfruuhodwlrqolqh (7 7rwdo xqdmxvwhghuurupd[lpxpghyldwlrq ehwzhhqwkhdfwxdodqgwkhlghdowudqihufxuyhv (2 2iivhwhuurughyldwlrqehwzhhqwkhiluvwdfwxdo wudqvlvlwrqdqgwkhiluvwlghdorqh (* *dlqhurughyldwlrqehwzhhqwkhodvwlghdo wudqvlwlrqdqgwkhodvwdfwxdorqh (' 'liihuhqwldo olqhdulw\ huuru pd[lpxp ghyldwlrq ehwzhhqdfwxdovwhsvdqglghdorqh (/ ,qwhjudoolqhdulw\huurupd[lpxpghyldwlrq ehwzhhqdq\dfwxdowudqvlwlrqdqgwkhhqgsrlqw fruuhodwlrqrqh ( 7 ( ' ( / 9''$ 966$ dle 9 5() rughshqglqjrqsdfndjh@ 9 ''$ >/6% ,'($/
electrical characteristics stm32f101xf, stm32f101xg 96/115 docid16553 rev 3 figure 48. typical connecti on diagram using the adc 1. refer to table 56 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 49 or figure 50 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 49. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. dlg 670)[[[ 9 '' $,1[ , / ??$ 9 9 7 5 $,1 & sdudvlwlf 9 $,1 9 9 7 5 $'& & $'& elw frqyhuwhu 6dpsohdqgkrog$'& frqyhuwhu 9 5() 670)[[[ 9 ''$ 9 66$ 9 5() ?)q) ?)q) dlf 6hhqrwh 6hhqrwh
docid16553 rev 3 97/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 50. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref- inputs are available only on 100-pin packages. 5.3.19 dac electri cal specifications 6 2%& 6 $$! 34-&xxx ?&n& 6 2%&n 6 33! aic 3eenote 3eenote table 60. dac characteristics symbol parameter min typ max (1) unit comments v dda analog supply voltage 2.4 3.6 v v ref+ reference supply voltage 2.4 3.6 v v ref+ must always be below v dda v ssa ground 0 0 v r load (2) resistive load with buffer on 5 k r o (2) impedance output with buffer off 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x155) and (0xeab) at v ref+ = 2.4 v. dac_out max (2) higher dac_out voltage with buffer on v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off 0.5 mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off v ref+ ? 1lsb v
electrical characteristics stm32f101xf, stm32f101xg 98/115 docid16553 rev 3 i ddvref+ dac dc current consumption in quiescent mode (standby mode) 220 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs. i dda dac dc current consumption in quiescent mode (3) 380 a with no load, middle code (0x800) on the inputs. 480 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs. dnl (1) differential non linearity difference between two consecutive code-1lsb) 0.5 lsb given for the dac in 10-bit configuration. 2 lsb given for the dac in 12-bit configuration. inl (1) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) 1 lsb given for the dac in 10-bit configuration. 4 lsb given for the dac in 12-bit configuration. offset (1) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) 10 mv 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v. 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v. gain error (1) gain error 0.5 % given for the dac in 12bit configuration. t settling (1) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb 34 sc load 50 pf, r load 5k update rate (1) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) 1ms/sc load 50 pf, r load 5k t wakeup (1) wakeup time from off state (setting the enx bit in the dac control register) 6.5 10 s c load 50 pf, r load 5k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement ?67 ?40 db no r load , c load = 50 pf 1. preliminary values. 2. guaranteed by design, not tested in production. 3. quiescent mode refers to the state of the dac when a steady value is kept on the output so that no dynamic consumption is involved. table 60. dac characteristics (continued) symbol parameter min typ max (1) unit comments
docid16553 rev 3 99/115 stm32f101xf, stm32f101xg electrical characteristics 114 figure 51. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 5.3.20 temperature sensor characteristics 5 / & / '$&b287[ %xiihu elw gljlwdowr dqdorj frqyhuwhu ai6 table 61. ts characteristics symbol parameter min typ max unit t l (1) 1. preliminary values. v sense linearity with temperature 1 2 c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 (1) voltage at 25c 1.34 1.43 1.52 v t start (2) 2. guaranteed by design, not tested in production. startup time 4 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s
package characteristics stm32f101xf, stm32f101xg 100/115 docid16553 rev 3 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 6.1.1 lqfp144, 20 x 20 mm, 1 44-pin thin quad flat package figure 52. lqfp144, 20 x 20 mm, 144-pin thin quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # !?-%?6 ! ! ! , , c b !
docid16553 rev 3 101/115 stm32f101xf, stm32f101xg package characteristics 114 table 62. lqfp144, 20 x 20 mm, 144-pin thin quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.050 0.15 0.0020 0.0059 a2 1.350 1.400 1.45 0.0531 0.0551 0.0571 b 0.170 0.220 0.27 0.0067 0.0087 0.0106 c 0.090 0.20 0.0035 0.0079 d 21.800 22.000 22.20 0.8583 0.8661 0.874 d1 19.800 20.000 20.20 0.7795 0.7874 0.7953 d3 17.500 0.689 e 21.800 22.000 22.20 0.8583 0.8661 0.874 e1 19.800 20.000 20.20 0.7795 0.7874 0.7953 e3 17.500 0.689 e 0.500 0.0197 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f101xf, stm32f101xg 102/115 docid16553 rev 3 figure 53. recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. aic
docid16553 rev 3 103/115 stm32f101xf, stm32f101xg package characteristics 114 device marking figure 54. lqfp144 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 'dwhfrgh 3lqlghqwlilhu 670)=)7 $ 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh <:: 2swlrqdojdwhpdun
package characteristics stm32f101xf, stm32f101xg 104/115 docid16553 rev 3 6.1.2 lqfp100, 14 x 14 mm, 100-pi n low-profile quad flat package figure 55. lqfp100 ? 14 x 14 mm, 100-pin low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).'0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b ! table 63. lqpf100 ? 14 x 14 mm, 100-pin low- profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.622 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.000 0.4724 e 15.800 16.000 16.200 0.622 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.000 0.4724
docid16553 rev 3 105/115 stm32f101xf, stm32f101xg package characteristics 114 figure 56. recommended footprintt 1. drawing is not to scale. 2. dimensions are in millimeters. e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 63. lqpf100 ? 14 x 14 mm, 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max aic
package characteristics stm32f101xf, stm32f101xg 106/115 docid16553 rev 3 device marking figure 57. lqfp100 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 'dwhfrgh 3lq lqghqwlilhu 670) 9*7$ < :: 2swlrqdojdwhpdun
docid16553 rev 3 107/115 stm32f101xf, stm32f101xg package characteristics 114 6.1.3 lqfp64, 10 x 10 mm, 64 pin low-prof ile quad flat package figure 58. tlqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline 1. drawing is not to scale. :b0(b9 $ $ $ 6($7,1*3/$1( fff & e & f $ / / . ,'(17,),&$7,21 3,1 ' ' ' h ( ( ( *$8*(3/$1( pp table 64. lqfp64 ? 10 x 10 mm, 64 pin low- profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d. 7.500 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197
package characteristics stm32f101xf, stm32f101xg 108/115 docid16553 rev 3 figure 59. recommended footprintt 1. drawing is not to scale. 2. dimensions are in millimeters. k 03.57 03.57 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. table 64. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aic
docid16553 rev 3 109/115 stm32f101xf, stm32f101xg package characteristics 114 device marking figure 60. lqfp64 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 'dwhfrgh 3lq lqghqwlilhu 670) 5)7 < :: $
package characteristics stm32f101xf, stm32f101xg 110/115 docid16553 rev 3 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 10: general operating conditions on page 39 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 65. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp144 - 20 x 20 mm / 0.5 mm pitch 30 c/w thermal resistance junction-ambient lqfp100 - 14 x 14 mm / 0.5 mm pitch 46 thermal resistance junction-ambient lqfp64 - 10 x 10 mm / 0.5 mm pitch 45
docid16553 rev 3 111/115 stm32f101xf, stm32f101xg package characteristics 114 6.2.2 evaluating the maximum juncti on temperature for an application when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 66: stm32f101xf and stm32f101xg ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific ma ximum junction temperature. here, only temperature range 6 is available (?40 to 85 c). the following example shows how to calculate the temperature range needed for a given application, making it possible to check wh ether the required temperature range is compatible with the stm32f10xxx junction temperature range. example: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output mode at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in table 66 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.1 c = 102.1 c this is within the junction temperature range of the stm32f10xxx (?40 < t j < 105 c). figure 61. lqfp64 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 t a (c) p d (mw) suffix 6
part numbering stm32f101xf, stm32f101xg 112/115 docid16553 rev 3 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 66. stm32f101xf and stm32f101xg ordering information scheme example: stm32 f 101 r f t 6 xxx device family stm32 = arm ? -based 32-bit microcontroller product type f = general-purpose device subfamily 101 = access line pin count r = 64 pins v = 100 pins z = 144 pins flash memory size f = 768 kbytes of flash memory g = 1 mbyte of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c. options xxx = programmed parts tr = tape and real
docid16553 rev 3 113/115 stm32f101xf, stm32f101xg revision history 114 8 revision history table 67. document revision history date revision changes 27-oct-2009 1 initial release. 15-nov-2010 2 lqfp64 package mechanical data updated: see figure 58: tlqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline and table 64: lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . internal code removed from table 66: stm32f101xf and stm32f101xg ordering information scheme . updated note 2 below table 52: i2c characteristics updated figure 43: i2c bus ac waveforms and measurement circuit(1) updated figure 42: recommended nrst pin protection updated note 1 below table 47: i/o static characteristics updated table 20: peripheral current consumption updated table 14: maximum current consumption in run mode, code with data processing running from flash updated table 15: maximum current consumption in run mode, code with data processing running from ram updated table 16: maximum current consumption in sleep mode, code running from flash or ram updated table 17: typical and maximum current consumptions in stop and standby modes updated table 18: typical current consum ption in run mode, code with data processing running from flash updated table 19: typical current consumption in sleep mode, code running from flash or ram updated table 24: lse oscillator characteristics (flse = 32.768 khz) updated figure 19: asynchronous non-multiplexed sram/psram/nor read waveforms on page 57 added section 5.3.13: i/o current inject ion characteristics on page 99.
revision history stm32f101xf, stm32f101xg 114/115 docid16553 rev 3 25-nov-2014 3 updated number of adcs in table 2: stm32f101xf and stm32f101xg features and peripheral counts . modified section 2.3.22: gpios (general -purpose inputs/outputs) on page 21 . added note below figure 3: lqfp144 pinout , figure 4: lqfp100 pinout , and figure 5: lqfp64 pinout . modified osc_in, osc_out, pd0, pd1, pb8, pb9 and pf8 in table 5: stm32f101xf/stm32f101xg pin definitions on page 25 / updated notes related to parameters not tested in production in the whole document. modified notes in table 7: voltage characteristics on page 37 and table 8: current characteristics on page 38 . removed adc2/3 and can from table 20: peripheral current consumption on page 48 . modified t w(hse) value in table 21: high-speed external user clock characteristics on page 49 . updated table 24: lse oscillator characteristics (flse = 32.768 khz) on page 52 . changed jesd22-c101 to ansi/esd stm5.3.1 in section : electrostatic discharge (esd) . updated section 5.3.10: fsmc characteristics on page 56 . updated figure 41: i/o ac char acteristics definition . updated conditions related to section : i2c interface characteristics on page 86 . modified table 52: i2c characteristics on page 87 , updated figure 43: i2c bus ac waveforms and measurement circuit(1) and v dd /v dd_i2c conditions in table 53: scl frequency (fpclk1= 36 mhz, vdd = vdd_i2c = 3.3 v) on page 88 . modified section : output driving current on page 81 . modified table 52: i2c characteristics on page 87 and updated figure 43: i2c bus ac waveforms and measurement circuit(1) . modified figure 46: spi timing diagram - master mode(1) on page 92 . modified notes in table 56: adc characteristics on page 93 and table 59: adc accuracy on page 95 . updated i dda definition in table 60: dac characteristics on page 97 and removed comment re lated to the offset parameter for 10 mv. added device marking information for all packages. table 67. document revision history (continued) date revision changes
docid16553 rev 3 115/115 stm32f101xf, stm32f101xg 115 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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