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1 of 82 GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 GS2962 3g/hd/sd-sdi serializer with complete smpte video support www.gennum.com key features ? operation at 2.970gb/s, 2.970/1.001gb/s, 1.485gb/s, 1.485/1.001gb/s and 270mb/s ? supports smpte 425m (level a and level b), smpte 424m, smpte 292, smpte 259m-c and dvb-asi ? integrated cable driver ? integrated, low noise vco ? integrated narrow-bandwidth pll ? ancillary data insertion ? optional conversion from smpte 425m level a to level b for 1080p 50/60 4:2:2 10-bit ? parallel data bus selectable as either 20-bit or 10-bit ? smpte video processing including trs calculation and insertion, line number calculation and insertion, line based crc calculation and insertion, illegal code re-mapping, smpte 352m payload identifier generation and insertion ?gspi host interface ? 1.2v digital core power supply, 1.2v and 3.3v analog power supplies, and selectable 1.8v or 3.3v i/o power supply ? -20oc to +85oc operating temperature range ? low power operation (typically at 400mw, including cable driver) ? small 11mm x 11mm 100-ball bga package ? pb-free and rohs compliant applications description the GS2962 is a complete sdi transmitter, generating a smpte 424m, smpte 292, smpte 259m-c or dvb-asi compliant serial digital output signal. the integrated narrow-bw pll allows the device to accept parallel clocks with high input jitter, and still provide a smpte compliant serial digital output. the device can operate in four basic user selectable modes: smpte mode, dvb-asi mode, data-through mode, or standby mode. in smpte mode, the GS2962 performs all smpte processing features. both smpte 425m level a and level b formats are supported with optional conversion from level a to level b for 1080p 50/60 4:2:2 10-bit. in dvb-asi mode, the device will perform 8b/10b encoding prior to transmission. in data-through mode, all smpte and dvb-asi processing is disabled. the device can be used as a simple parallel to serial converter. the device can also operate in a lower power standby mode. in this mode, no signal is generated at the output. the GS2962 integrates a fully smpte-compliant cable driver for smpte 259m-c, smpte 292 and smpte 424m interfaces. it features automatic dual slew-rate selection, depending on 3gb/s or hd or sd operational requirements. hd-sdi application: single link (3g-sdi) to dual link (hd-sdi) converter GS2962 link a link b hv f/pclk 10-bit 3g-sdi gs2960 eq gs2974 GS2962 10-bit hv f/pclk hd-sdi appli c ation: dual link (hd-sdi) to single link (3g-sdi) converter hd-sdi deserializer (gs1559 or gs2970) link a fifo wr deserializer link b fifo wr GS2962 gs4910 10-bit 3g-sdi hvf xtal hv f/pclk hv f/pclk hv f/pclk (gs1559 or gs2970) 10-bit 10-bit 10-bit hd-sdi hd-sdi hd-sdi eq eq gs2974b gs2974b
2 of 82 GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 functional block diagram figure a: GS2962 functional block diagram revision history input mux/ demux din[19:0] smpte 352m generation and insertion anc data insertion trs , line number and crc insertion edh packet insertion dvb-asi 8b/10b encoder f/de v/vsync h/hsync tim_861 parallel to serial converter mux smpte cable driver sdo sdo rset sdo_en/dis pclk gspi host interface hanc/ vanc blanking pll with low noise vco clockcleaner? locked cs_tms sclk_tclk sdin_tdi sdout_tdo dvb_asi nrz/nrzi smpte scrambler lf vbg rate_sel[1:0] cd_vdd cd_gnd jtag controller tms tdi tdo jtag/host tck dedicated jtag pins shared jtag and gspi pins (for drop-in compatibility with gs1572/82) core_vdd core_gnd io_vdd io_gnd reset standby 20bit/10bit anc_blank pll_vdd pll_vdd avdd agnd vco_gnd vco_gnd ioproc_en/dis smpte_bypass smpte 425m 1080p 50/60 4:2:2 10-bit level a level b version ecr pcn date changes and/or modifications 7 155080 5 6 059 o c to b er 2010 revise d power ratin g in stan db y mo d e. do c umente d cs um b ehaviour in s e c tion 4.7 , s e c tion 4.8.4 an d c onfi g uration an d s tatus re g isters . 6 153717 ? mar c h 2010 up d ates throu g hout entire d o c ument. a dd e d fi g ure 4-2 , fi g ure 4-3 an d fi g ure 4-4 . c orre c tion to re g isters 040h to 13fh in ta b le 4-1 6 : c onfi g uration an d s tatus re g isters . 5 152224 ? j uly 2009 up d ate d devi c e laten c y num b ers in 2.4 a c ele c tri c al c hara c teristi c s . up d ates to 4.7 an c data insertion . repla c e d 7.3 markin g dia g ram . 4 151319 ? j anuary 2009 c orre c tion to timin g values in ta b le 4-1: gs 29 6 2 di g ital input a c ele c tri c al c hara c teristi c s . 3 150802 ? de c em b er 2008 c onversion to data s heet. 2 150720 ? o c to b er 2008 c onversion to preliminary data s heet. 1 148587 ? s eptem b er 2008 new do c ument.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 3 of 82 contents key features................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 functional block diagram ....................................................................................................... .......................2 revision history ............................................................................................................... ..................................2 1. pin out..................................................................................................................... ..........................................7 1.1 pin assignment ............................................................................................................ ......................7 1.2 pin descriptions .......................................................................................................... ......................8 2. electrical characteristics .................................................................................................. ....................... 15 2.1 absolute maximum ratings .................................................................................................. ..... 15 2.2 recommended operating conditions .................................................................................... 15 2.3 dc electrical characteristics ............................................................................................. ........ 16 2.4 ac electrical characteristics ............................................................................................. ........ 18 3. input/output circuits ....................................................................................................... ........................ 21 4. detailed description........................................................................................................ .......................... 26 4.1 functional overview ....................................................................................................... ............. 26 4.2 parallel data inputs ...................................................................................................... ................. 27 4.2.1 parallel input in smpte mode....................................................................................... 28 4.2.2 parallel input in dvb-asi mode................................................................................... 29 4.2.3 parallel input in data-through mode......................................................................... 29 4.2.4 parallel input clock (pclk) ............................................................................................ 30 4.3 smpte mode ................................................................................................................ ................... 31 4.3.1 h:v:f timing ............................................................................................................. .......... 31 4.3.2 cea 861 timing........................................................................................................... ....... 33 4.4 dvb-asi mode .............................................................................................................. ................. 40 4.5 data-through mode ......................................................................................................... ............ 41 4.6 standby mode .............................................................................................................. ................... 41 4.7 anc data insertion ........................................................................................................ ............... 41 4.7.1 anc insertion operating modes .................................................................................. 42 4.7.2 3g anc insertion......................................................................................................... ...... 43 4.7.3 hd anc insertion......................................................................................................... ..... 45 4.7.4 sd anc insertion......................................................................................................... ...... 46 4.8 additional processing functions ........................................................................................... ... 47 4.8.1 video format detection .................................................................................................. 4 7 4.8.2 3g format detection ...................................................................................................... .. 50 4.8.3 anc data blanking ........................................................................................................ ... 52 4.8.4 anc data checksum calculation and insertion..................................................... 53 4.8.5 trs generation and insertion ....................................................................................... 53 4.8.6 hd and 3g line number calculation and insertion.............................................. 54 4.8.7 illegal code re-mapping................................................................................................. 5 4 4.8.8 smpte 352m payload identifier packet insertion.................................................. 54 4.8.9 line based crc generation and insertion (hd/3g) .............................................. 55
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 4 of 82 4.8.10 edh generation and insertion ................................................................................... 55 4.8.11 smpte 372m conversion ............................................................................................. 56 4.8.12 processing feature disable.......................................................................................... 56 4.9 serial digital output ..................................................................................................... ................ 57 4.9.1 output signal interface levels...................................................................................... 58 4.9.2 overshoot/undershoot.................................................................................................... 5 8 4.9.3 slew rate selection...................................................................................................... ..... 59 4.9.4 serial digital output mute.............................................................................................. 5 9 4.10 serial clock pll ......................................................................................................... .................. 59 4.10.1 pll bandwidth........................................................................................................... ...... 60 4.10.2 lock detect............................................................................................................. ........... 61 4.11 gspi host interface ...................................................................................................... ............... 61 4.11.1 command word description ...................................................................................... 62 4.11.2 data read or write access........................................................................................... 63 4.11.3 gspi timing............................................................................................................. .......... 64 4.12 host interface register maps ............................................................................................. ..... 66 4.13 jtag id codeword ......................................................................................................... ............ 76 4.14 jtag test operation ...................................................................................................... ............ 76 4.15 device power-up .......................................................................................................... .............. 76 4.16 device reset ............................................................................................................. ..................... 76 5. application reference design ................................................................................................ ............... 77 5.1 typical application circuit ............................................................................................... ......... 77 6. references & relevant standards ............................................................................................. ............ 78 7. package & ordering information .............................................................................................. ............ 79 7.1 package dimensions ........................................................................................................ ............. 79 7.2 packaging data ............................................................................................................ ................... 80 7.3 marking diagram ........................................................................................................... ................ 80 7.4 solder reflow profiles .................................................................................................... .............. 81 7.5 ordering information ...................................................................................................... ............. 81
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 5 of 82 list of figures figure 3-1: differential output stage.......................................................................................... ............. 21 figure 3-2: digital input pin .................................................................................................. ...................... 21 figure 3-3: digital input pin with schmitt tri gger............................................................................. .. 22 figure 3-4: digital input pin with weak pull-down............................................................................. 2 2 figure 3-5: digital input pin with weak pull-up................................................................................ ... 23 figure 3-6: bidirectional digital input/output pin with programmable drive strength......... 23 figure 3-7: bidirectional digital input/output pin with programmable drive strength ........ 24 figure 3-8: vbg ............................................................................................................... ............................... 24 figure 3-9: loop filter ....................................................................................................... ........................... 25 figure 4-1: GS2962 video host interface timing diagrams ............................................................ 27 figure 4-2: h:v:f output timing - 3g level a and hdtv 20-bit mode ...................................... 32 figure 4-3: h:v:f output timing - 3g level a and hdtv 10-bit mode 3g level b 20-bit mode, each 10-bit stream .................................................................................... ..... 32 figure 4-4: h:v:f output timing - 3g level b 10-bit mode ............................................................. 32 figure 4-5: h:v:f input timing - hd 20-bit input mode ................................................................... 32 figure 4-6: h:v:f input timing - hd 10-bit input mode ................................................................... 33 figure 4-7: h:v:f input timing - sd 20-bit mode ............................................................................... 33 figure 4-8: h:v:f input timing - sd 10-bit mode ............................................................................... 33 figure 4-9: h:v:de input timing 1280 x 720p @ 59.94/60 (format 4) ........................................ 35 figure 4-10: h:v:de input timing 1920 x 1080i @ 59.94/60 (format 5) ..................................... 35 figure 4-11: h:v:de input timing 720 (1440) x 480i @ 59.94/60 (format 6&7) ....................... 36 figure 4-12: h:v:de input timing 1280 x 720p @ 50 (format 19) ................................................ 36 figure 4-13: h:v:de input timing 1920 x 1080i @ 50 (format 20) ............................................... 37 figure 4-14: h:v:de input timing 720 (1440) x 576 @ 50 (format 21&22) ................................ 38 figure 4-15: h:v:de input timing 1920 x 1080p @ 59.94/60 (format 16) ................................. 38 figure 4-16: h:v:de input timing 1920 x 1080p @ 50 (format 31) .............................................. 39 figure 4-17: h:v:de input timing 1920 x 1080p @ 23.94/24 (format 32) ................................. 39 figure 4-18: h:v:de input timing 1920 x 1080p @ 25 (format 33) .............................................. 40 figure 4-19: h:v:de input timing 1920 x 1080p @ 29.97/30 (format 34) ................................. 40 figure 4-20: orl matching network, bnc and coaxial cable connection ............................... 58 figure 4-21: gspi application interface connection ........................................................................ 62 figure 4-22: command word format .............................................................................................. ....... 62 figure 4-23: data word format ................................................................................................. ............... 63 figure 4-24: write mode ....................................................................................................... ....................... 64 figure 4-25: read mode ........................................................................................................ ....................... 64 figure 4-26: gspi time delay .................................................................................................. .................. 64 figure 4-27: reset pulse ...................................................................................................... ......................... 76 figure 7-1: pb-free solder reflow profile ..................................................................................... ......... 81
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 6 of 82 list of tables table 1-1: pin descriptions .................................................................................................... ........................ 8 table 2-1: absolute maximum ratings............................................................................................ ....... 15 table 2-2: recommended operating conditions................................................................................ 15 table 2-3: dc electrical characteristics ....................................................................................... .......... 16 table 2-4: ac electrical characteristics ....................................................................................... .......... 18 table 4-1: GS2962 digital input ac electrical ch aracteristics ....................................................... 27 table 4-2: GS2962 input video data format selections................................................................... 27 table 4-3: GS2962 pclk input rates............................................................................................. .......... 30 table 4-4: cea861 timing formats ............................................................................................... .......... 34 table 4-5: supported video standards........................................................................................... ........ 48 table 4-6: smpte 352m packet data.............................................................................................. ......... 52 table 4-7: ioproc register bits................................................................................................ ................ 57 table 4-7: serial digital output - serial output data rate............................................................... 57 table 4-8: r set resistor value vs. output swing................................................................................. 58 table 4-9: serial digital output - overshoot/undershoot ............................................................... 59 table 4-10: serial digital output - rise/fall time............................................................................. .. 59 table 4-11: pclk and serial digital clock rates ................................................................................ . 60 table 4-12: GS2962 pll bandwidth............................................................................................... .......... 60 table 4-13: GS2962 lock detect indication ...................................................................................... .... 61 table 4-14: gspi time delay.................................................................................................... .................. 64 table 4-15: gspi ac characteristics............................................................................................ ............ 65 table 4-16: configuration and status registers................................................................................. .. 66 table 7-1: packaging data...................................................................................................... ..................... 80
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 7 of 82 1. pin out 1.1 pin assignment 1 3 2 45 6 7 8 9 10 a b c d e f g h j k vbg dvb_asi 20bit/ 10bit din18 sdo locked jtag/ host reset core _gnd sdo din17 sdo_ en/dis f/de h/hsync vco_ gnd pll_ vdd a_gnd detect _trs core _vdd core _gnd core _gnd core _gnd vco_ vdd core _vdd core _vdd standby rsv a_vdd lf tdi a_gnd core _gnd io_gnd io_vdd cd_vdd cd_gnd pll_ gnd pll_ gnd v/vsync sdout_ tdo cs_ tms sdin_ tdi sclk_ tck smpte_ bypass io_gnd io_vdd anc_ blank pclk tim_861 tck din15 din16 din19 din13 din14 din12 din11 din10 pll_ gnd din9 din8 din7 din6 din5 din4 din3 din1 din0 din2 core _gnd core _gnd core _gnd core _vdd core _gnd cd_gnd cd_gnd cd_gnd rset tdo tms pll_ vdd core _gnd rsv rsv rsv core _gnd rate_ sel0 rate_ sel1 rsv rsv rsv rsv rsv rsv rsv rsv rsv core _gnd core _gnd ioproc _en/dis
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 8 of 82 1.2 pin descriptions table 1-1: pin descriptions pin number name timing ty p e description a1, a2, b1, b2, b3, c 1, c 2, c 3, d1, d2 din[19:10] input parallel data bu s s i g nal levels are lv c mo s / lvttl c ompati b le. 20- b it mo d e 20bit/10bit = hi g h data s tream 1/luma d ata input in s mpte mo d e ( s mpte_bypa ss = hi g h) data input in d ata throu g h mo d e ( s mpte_bypa ss = low) 10- b it mo d e 20bit/10bit = low multiplexe d data s tream 1/luma an d data s tream 2/ c hroma d ata input in s mpte mo d e ( s mpte_bypa ss = hi g h) data input in d ata throu g h mo d e ( s mpte_bypa ss = low) dvb-a s i d ata input in dvb-a s i mo d e ( s mpte_bypa ss = low) (dvb_a s i = hi g h) a3 f/de s yn c h- ronous with p c lk input parallel data timin g . s i g nal levels are lv c mo s / lvttl c ompati b le. tim_8 6 1 = low: use d to in d i c ate the odd / even fiel d of the vi d eo si g nal when dete c t_tr s is set low. the d evi c e will set the f b it in all out g oin g tr s si g nals for the entire perio d that the f input si g nal is hi g h (iopro c _en/di s must also b e hi g h). the f si g nal shoul d b e set hi g h for the entire perio d of fiel d 2 an d shoul d b e set low for all lines in fiel d 1 an d for all lines in pro g ressive s c an systems. the f si g nal is i g nore d when dete c t_tr s = hi g h. tim_8 6 1 = hi g h: the de si g nal is use d to in d i c ate the a c tive vi d eo perio d when dete c t_tr s is set low. de is hi g h for a c tive d ata an d low for b lankin g . s ee s e c tion 4.3 an d s e c tion 4.3.2 for timin g d etails. the de si g nal is i g nore d when dete c t_tr s = hi g h.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 9 of 82 a4 h/h s yn cs yn c h- ronous with p c lk input parallel data timin g . s i g nal levels are lv c mo s / lvttl c ompati b le. tim_8 6 1 is low: the h si g nal is use d to in d i c ate the portion of the vi d eo line c ontainin g a c tive vi d eo d ata, when dete c t_tr s is set low. a c tive line blankin g the h si g nal shoul d b e low for the a c tive portion of the vi d eo line. the si g nal g oes low at the first a c tive pixel of the line, an d then g oes hi g h after the last a c tive pixel of the line. the h si g nal shoul d b e set hi g h for the entire horizontal b lankin g perio d , in c lu d in g b oth eav an d s av tr s wor d s, an d low otherwise. tr s base d blankin g (h_ c onfi g = 1 h ) the h si g nal shoul d b e set hi g h for the entire horizontal b lankin g perio d as in d i c ate d b y the h b it in the re c eive d tr s id wor d s, an d low otherwise. tim_8 6 1 = hi g h: the h s yn c si g nal in d i c ates horizontal timin g . s ee s e c tion 4.3 . when dete c t_tr s is hi g h, this pin is i g nore d at all times. if dete c t_tr s is set hi g h an d tim_8 6 1 is set hi g h, the dete c t_tr s feature will take priority. a5, e1, g 10, k8 c ore_vdd input power power supply c onne c tion for d i g ital c ore lo g i c . c onne c t to 1.2v d c d i g ital. a 6 , b 6 pll_vdd input power power supply pin for pll. c onne c t to 1.2v d c analo g . a7 lf analo g output loop filter c omponent c onne c tion. a8 vb g output ban dg ap volta g e filter c onne c tion. a9, d 6 , d7, d8, h7, j 4, j 5, j6 , j 7, k4, k5, k 6 , k7 r s v ? these pins are reserve d an d shoul d b e left un c onne c te d . a10 a_vdd input power vdd for sensitive analo g c ir c uitry. c onne c t to 3.3vd c analo g . b4 p c lk input parallel data bu s c lo c k. s i g nal levels are lv c mo s / lvttl c ompati b le. 3 g 20- b it mo d ep c lk @ 148.5mhz 3 g 10- b it mo d e ddr p c lk @ 148.5mhz hd 20- b it mo d ep c lk @ 74.25mhz hd 10- b it mo d ep c lk @ 148.5mhz s d 20- b it mo d ep c lk @ 13.5mhz s d 10- b it mo d ep c lk @ 27mhz dvb-a s i mo d ep c lk @ 27mhz table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 10 of 82 b5, c 5, d5, e2, e5, e 6 , f4, f5, f 6 , f7, g 9, h5, h 6 c ore_ g nd input power reserve d . c onne c t to c ore_ g nd. b7 v c o_vdd input powe r power pin for v c o. c onne c t to 1.2v d c analo g followe d b y an r c filter (see typi c al appli c ation c ir c uit on pa g e 77 ). v c o_vdd is nominally 0.7v. b8 v c o_ g nd input power g roun d c onne c tion for v c o. c onne c t to analo g g nd. b9, b10 a_ g nd input power g nd pins for sensitive analo g c ir c uitry. c onne c t to analo g g nd. c 4v/v s yn cs yn c h- ronous with p c lk input parallel data timin g . s i g nal levels are lv c mo s / lvttl c ompati b le. tim_8 6 1 = low: the v si g nal is use d to in d i c ate the portion of the vi d eo fiel d /frame that is use d for verti c al b lankin g , when dete c t_tr s is set low. the v si g nal shoul d b e set hi g h for the entire verti c al b lankin g perio d an d shoul d b e set low for all lines outsi d e of the verti c al b lankin g interval. the v si g nal is i g nore d when dete c t_tr s = hi g h. tim_8 6 1 = hi g h: the v s yn c si g nal in d i c ates verti c al timin g . s ee s e c tion 4.3 for timin g d etails. the v s yn c si g nal is i g nore d when dete c t_tr s = hi g h. c6 , c 7, c 8pll_ g nd input power g roun d c onne c tion for pll. c onne c t to analo g g nd. c 9, d9, e9, f9 c d_ g nd input power g roun d c onne c tion for the serial d i g ital c a b le d river. c onne c t to analo g g nd. c 10, d10 s do, s do output s erial data output s i g nal. s erial d i g ital output si g nal operatin g at 2.97 gb /s, 2.97/1.001 gb s, 1.485 gb /s, 1.485 /1.001 gb /s or 270m b /s. the slew rate of the output is automati c ally c ontrolle d to meet s mpte 424m, s mpte 292 an d 259m spe c ifi c ations a cc or d in g to the settin g of the rate_ s el0 an d rate_ s el1 pins. d3 s tandby input s tan db y input. hi g h to pla c e the d evi c e in s tan db y mo d e. d4 s do_en/di s input c ontrol s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. use d to ena b le or d isa b le the serial d i g ital output sta g e. when s do_en/di s is low, the serial d i g ital output si g nals s do an d s do are d isa b le d an d b e c ome hi g h impe d an c e. when s do_en/di s is hi g h, the serial d i g ital output si g nals s do an d s do are ena b le d . table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 11 of 82 e3, e4 rate_ s el0, rate_ s el1 input c ontrol s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. use d to c onfi g ure the operatin g d ata rate. e7 tdi input c ommuni c ation s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. de d i c ate d j ta g pin. test d ata in. this pin is use d to shift j ta g test d ata into the d evi c e when the j ta g /ho s t pin is low. e8 tm s input c ommuni c ation s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. de d i c ate d j ta g pin. test mo d e start. this pin is j ta g test mo d e s tart, use d to c ontrol the operation of the j ta g test when the j ta g /ho s t pin is low. e10 c d_vdd input power power for the serial d i g ital c a b le d river. c onne c t to 3.3v d c analo g . f1, f2, h1, h2, j 1, j 2, j 3, k1, k2, k3 din[9:0] input parallel data bu s . s i g nal levels are lv c mo s / lvttl c ompati b le. in 10- b it mo d e, these pins are not use d . 20- b it mo d e 20bit/10bit = hi g h data s tream 2/ c hroma d ata input in s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low data input in d ata throu g h mo d e s mpte_bypa ss = low dvb_a s i = low not use d in dvb-a s i mo d e s mpte_bypa ss = low dvb_a s i = hi g h 10- b it mo d e 20bit/10bit = low not use d . f3 dete c t_tr s input c ontrol s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. use d to sele c t external hvf timin g mo d e or tr s extra c tion timin g mo d e. when dete c t_tr s is low, the d evi c e extra c ts all internal timin g from the supplie d h:v:f or c ea-8 6 1 timin g si g nals, d epen d ent on the status of the tim8 6 1 pin. when dete c t_tr s is hi g h, the d evi c e extra c ts all internal timin g from tr s si g nals em b e dd e d in the supplie d vi d eo stream. table 1-1: pin descriptions (continued) pin number name timing ty p e description rate_ s el0 data rate 0 0 1 0 1 x 1.485 or 1.485/1.001 gb /s 2.97 or 2.97/1.001 gb /s 270m b /s rate_ s el1
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 12 of 82 f8 tdo output c ommuni c ation s i g nal output. s i g nal levels are lv c mo s /lvttl c ompati b le. de d i c ate d j ta g pin. j ta g test data output. this pin is use d to shift results from the d evi c e when the j ta g /ho s t pin is low. f10 r s et input an external 1% resistor c onne c te d to this input is use d to set the s do/ s do output si g nal amplitu d e. g 1, h10 io_vdd input power power c onne c tion for d i g ital i/o. c onne c t to 3.3v or 1.8v d c d i g ital. g 2, h9 io_ g nd input power g roun d c onne c tion for d i g ital i/o. c onne c t to d i g ital g nd. g 3tim_8 6 1 input c ontrol s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. use d to sele c t external c ea-8 6 1 timin g mo d e. when dete c t_tr s is low an d tim-8 6 1 is low, the d evi c e extra c ts all internal timin g from the supplie d h:v:f timin g si g nals. when dete c t_tr s is low an d tim-8 6 1 is hi g h, the d evi c e extra c ts all internal timin g from the supplie d h s yn c , v s yn c , de timin g si g nals. when dete c t_tr s is hi g h, the d evi c e extra c ts all internal timin g from tr s si g nals em b e dd e d in the supplie d vi d eo stream. g 420 b it/10 b it input c ontrol s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. use d to sele c t the input b us wi d th. g 5dvb_a s i input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to ena b le/ d isa b le the dvb-a s i d ata transmission. when dvb_a s i is set hi g h an d s mpte_bypa ss is set low, then the d evi c e will c arry out dvb-a s i wor d ali g nment, i/o pro c essin g an d transmission. when s mpte_bypa ss an d dvb_a s i are b oth set low, the d evi c e operates in d ata-throu g h mo d e. g6 s mpte_bypa ss input c ontrol s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. use d to ena b le / d isa b le all forms of en c o d in g / d e c o d in g , s c ram b lin g an d edh insertion. when set low, the d evi c e operates in d ata throu g h mo d e (dvb_a s i= low), or in dvb-a s i mo d e (dvb_a s i = hi g h). no s mpte s c ram b lin g takes pla c e an d none of the i/o pro c essin g features of the d evi c e are availa b le when s mpte_bypa ss is set low. when set hi g h, the d evi c e c arries out s mpte s c ram b lin g an d i/o pro c essin g . table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 13 of 82 g 7iopro c _en/di s input c ontrol s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. use d to ena b le or d isa b le the i/o pro c essin g features. when iopro c _en/di s is hi g h, the i/o pro c essin g features of the d evi c e are ena b le d . when iopro c _en/di s is low, the i/o pro c essin g features of the d evi c e are d isa b le d . only appli c a b le in s mpte mo d e. g 8re s et input c ontrol s i g nal input s i g nal levels are lv c mo s /lvttl c ompati b le. use d to reset the internal operatin g c on d itions to d efault settin g s an d to reset the j ta g sequen c e. normal mo d e ( j ta g /ho s t = low). when low, all fun c tional b lo c ks will b e set to d efault c on d itions an d all input an d output si g nals b e c ome hi g h impe d an c e. when hi g h, normal operation of the d evi c e resumes. j ta g test mo d e ( j ta g /ho s t = hi g h). when low, all fun c tional b lo c ks will b e set to d efault an d the j ta g test sequen c e will b e reset. when hi g h, normal operation of the j ta g test sequen c e resumes. h3 an c _blank input c ontrol s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. when an c _blank is low, the luma an d c hroma input d ata is set to the appropriate b lankin g levels d urin g the h an d v b lankin g intervals. when an c _blank is hi g h, the b lankin g fun c tion is d isa b le d . only appli c a b le in s mpte mo d e. h4 lo c ked output s tatu s s i g nal output. s i g nal levels are lv c mo s / lvttl c ompati b le. pll lo c k in d i c ation. hi g h in d i c ates pll is lo c ke d . low in d i c ates pll is not lo c ke d . h8 j ta g /ho s t input c ontrol s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. use d to sele c t j ta g test mo d e or host interfa c e mo d e. when j ta g /ho s t is hi g h, the host interfa c e port is c onfi g ure d for j ta g test. when j ta g /ho s t is low, normal operation of the host interfa c e port resumes an d the separate j ta g pins b e c ome the j ta g port. j 8t c k input c ommuni c ation s i g nal input. s i g nal levels are lv c mo s /lvttl c ompati b le. j ta g s erial data c lo c k s i g nal. this pin is the j ta g c lo c k when the j ta g /ho s t pin is low. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 14 of 82 j 9 s dout_tdo output c ommuni c ation s i g nal output. s i g nal levels are lv c mo s / lvttl c ompati b le. s hare d j ta g /ho s t pin. provi d e d for c ompati b ility with the gs 1582. s erial data output/test data output. host mo d e ( j ta g /ho s t = low) this pin operates as the host interfa c e serial output, use d to rea d status an d c onfi g uration information from the internal re g isters of the d evi c e. j ta g test mo d e ( j ta g /ho s t = hi g h) this pin is use d to shift test results an d operates as the j ta g test d ata output, tdo (for new d esi g ns, use the d e d i c ate d j ta g port). note: if the host interfa c e is not b ein g use d leave this pin un c onne c te d . io_vdd = 3.3v drive s tren g th = 12ma io_vdd = 1.8v drive s tren g th = 4ma j 10 sc lk_t c k input c ommuni c ation s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. s hare d j ta g /ho s t pin. provi d e d for pin c ompati b ility with gs 1582. s erial d ata c lo c k si g nal. host mo d e ( j ta g /ho s t = low) sc lk_t c k operates as the host interfa c e b urst c lo c k, sc lk. c omman d an d d ata rea d /write wor d s are c lo c ke d into the d evi c e syn c hronously with this c lo c k. j ta g test mo d e ( j ta g /ho s t = hi g h) this pin is the te s t mode s tart pin, use d to c ontrol the operation of the j ta g test c lo c k, t c k (for new d esi g ns, use the d e d i c ate d j ta g port). note: if the host interfa c e is not b ein g use d , tie this pin hi g h. k9 cs _tm s input c ommuni c ation s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. c hip sele c t / test mo d e start. j ta g test mo d e ( j ta g /ho s t = hi g h) cs _tm s operates as the j ta g test mo d e start, tm s , use d to c ontrol the operation of the j ta g test, an d is a c tive hi g h (for new d esi g ns, use the d e d i c ate d j ta g port). host mo d e ( j ta g /ho s t = low), cs _tm s operates as the host interfa c e c hip s ele c t, cs , an d is a c tive low. k10 s din_tdi input c ommuni c ation s i g nal input. s i g nal levels are lv c mo s / lvttl c ompati b le. s hare d j ta g /ho s t pin. provi d e d for pin c ompati b ility with gs 1582. s erial d ata in/test d ata in. in j ta g mo d e, this pin is use d to shift test d ata into the d evi c e (for new d esi g ns, use the d e d i c ate d j ta g port). in host interfa c e mo d e, this pin is use d to write a dd ress an d c onfi g uration d ata wor d s into the d evi c e. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 15 of 82 2. electrical characteristics 2.1 absolute maximum ratings 2.2 recommended operating conditions table 2-1: absolute maximum ratings parameter value/units s upply volta g e, di g ital c ore ( c ore_vdd) -0.3v to +1.5v s upply volta g e, di g ital i/o (io_vdd) -0.3v to +3. 6 v s upply volta g e, analo g 1.2v (pll_vdd, v c o_vdd) -0.3v to +1.5v s upply volta g e, analo g 3.3v ( c d_vdd, a_vdd) -0.3v to +3. 6 v input volta g e ran g e (r s et) -0.3v to ( c d_vdd + 0.3)v input volta g e ran g e (vb g ) -0.3v to (a_vdd + 0.3)v input volta g e ran g e (lf) -0.3v to (pll_vdd + 0.3)v input volta g e ran g e ( d i g ital inputs) -2.0v to +5.25v operatin g temperature ran g e -20 c to +85 c fun c tional temperature ran g e -40 c to +85 c s tora g e temperature ran g e -40 c to +125 c peak reflow temperature ( j ede c j - s td-020 c )2 6 0 c e s d s ensitivity, hbm ( j e s d22-a114) 2kv note s : a b solute maximum ratin g s are those values b eyon d whi c h d ama g e may o cc ur. fun c tional operation un d er these c on d itions or at any other c on d ition b eyon d those in d i c ate d in the a c /d c ele c tri c al c hara c teristi c s se c tions is not implie d . table 2-2: recommended operating conditions parameter symbol conditions min typ max units notes operatin g temperature ran g e, am b ient t a ?-20 ? 85 c ? s upply volta g e, di g ital c ore c ore_vdd ? 1.14 1.2 1.2 6 v ? s upply volta g e, di g ital i/o io_vdd 1.8v mo d e 1.71 1.8 1.89 v ? 3.3v mo d e 3.13 3.3 3.47 v ? s upply volta g e, pll pll_vdd ? 1.14 1.2 1.2 6 v? s upply volta g e, v c ov c o_vdd ? ? 0.7 ? v1
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 16 of 82 2.3 dc electrical characteristics s upply volta g e, analo g a_vdd ? 3.13 3.3 3.47 v ? s upply volta g e, c d c d_vdd ? 3.13 3.3 3.47 v ? notes: 1. this is 0.7v rather than 1.2v because there is a voltage drop across an external 105 resistor. see typical application circuit on page 77 . table 2-2: recommended operating conditions parameter symbol conditions min typ max units notes table 2-3: dc electrical characteristics v cc = 3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units notes system +1.2v s upply c urrent i 1v2 10 b it 3 g ? 110 170 ma ? 20 b it 3 g ? 110 170 ma ? 10/20 b it hd ? 90 150 ma ? 10/20 b it s d ? 75 120 ma ? dvb_a s i ? 75 120 ma ? +1.8v s upply c urrent i 1v8 10 b it 3 g ? 10 15 ma ? 20 b it 3 g ? 10 15 ma ? 10/20 b it hd ? 10 25 ma ? 10/20 b it s d ? 310ma ? dvb_a s i ? 310ma ? +3.3v s upply c urrent i 3v3 10 b it 3 g ? 80 100 ma ? 20 b it 3 g ? 80 100 ma ? 10/20 b it hd ? 80 100 ma ? 10/20 b it s d ? 70 90 ma ? dvb_a s i ? 70 90 ma ? total devi c e power (io_vdd = 1.8v) p 1d8 10 b it 3 g ? 350 510 mw ? 20 b it 3 g ? 350 510 mw ? 10/20 b it hd ? 330 490 mw ? 10/20 b it s d ? 300 450 mw ? dvb_a s i ? 300 410 mw ? reset ? 200 ? mw ? s tan db y ? 100 180 mw 1
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 17 of 82 total devi c e power (io_vdd = 3.3v) p 3d3 10 b it 3 g ? 370 510 mw ? 20 b it 3 g ? 380 520 mw ? 10/20 b it hd ? 370 500 mw ? 10/20 b it s d ? 320 450 mw ? dvb_a s i ? 320 450 mw ? reset ? 230 ? mw ? s tan db y ? 110 180 mw 1 digital i/o input lo g i c low v il 3.3v or 1.8v operation io_v ss -0.3 ? 0.3 x io_vdd v ? input lo g i c hi g hv ih 3.3v or 1.8v operation 0.7 x io_vdd ? io_vdd+0.3 v ? output lo g i c low v ol iol=5ma, 1.8v operation ?? 0.2 v ? iol=8ma, 3.3v operation ?? 0.4 v ? output lo g i c hi g h v oh ioh=-5ma, 1.8v operation 1.4 ? ?v ? ioh=-8ma, 3.3v operation 2.4 ? ?v ? serial output s erial output c ommon mo d e volta g e v c mout 75 loa d , r s et = 750 s d an d hd mo d e 2.5 s di_vdd - (0.75/2) s di_vdd - (0.55/2) v ? notes: 1. devices manufactured prior to april 1, 2011 consume 150mw of power in standby mode. table 2-3: dc electrical characteristics (continued) v cc = 3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min ty p max units notes
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 18 of 82 2.4 ac electrical characteristics table 2-4: ac electrical characteristics v cc = 3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min typ max units notes system devi c e laten c y?3 g b ypass (p c lk = 148.5mhz) ?54?p c lk ? ?3 g s mpte (p c lk = 148.5mhz) ?95?p c lk ? ?3 g iopro c d isa b le d 20- b it mo d e (p c lk = 148.5mhz) ?94?p c lk ? ? hd b ypass (p c lk = 74.25mhz) ?54?p c lk ? ?hd s mpte (p c lk = 74.25mhz) ?95?p c lk ? ? hd iopro c d isa b le d 10- b it mo d e (p c lk = 74.25mhz) 98 ? s d b ypass (p c lk = 27mhz) ?54?p c lk ? ? s d s mpte (p c lk = 27mhz) ? 112 ? p c lk ? ? s d iopro c d isa b le d 10- b it mo d e (p c lk = 27mhz) ?94?p c lk ? ?dvb-a s i?52?p c lk ? reset pulse wi d th t reset ?1??ms? parallel input parallel c lo c k frequen c yf p c lk ? 13.5 ? 148.5 mhz ? parallel c lo c k duty c y c le d c p c lk ?40? 6 0% ? input data s etup time t su 50% levels; 3.3v or 1.8v operation 1.2 ? ? ns 1 input data hol d time t ih 0.8 ? ? ns 1 serial digital output s erial output data rate dr s do ? ? 2.97 ? gb /s ? ? ? 2.97/1.001 ? gb /s ? ? ? 1.485 ? gb /s ? ? ? 1.485/1.001 ? gb /s ? ? ? 270 ? m b /s ?
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 19 of 82 s erial output s win g v sdd r s et = 750 75 loa d 750 800 850 mvp-p ? s erial output rise/fall time 20% ~ 80% trf s do 3 g /hd mo d e ? 120 135 ps ? trf s do s d mo d e 400 66 0 800 ps ? mismat c h in rise/fall time t r , t f ???35ps? duty c y c le distortion ? ? ? ? 5 % 2 overshoot ?3 g /hd mo d e? 510%2 ? s d mo d e? 38%2 output return loss orl 1.485 g hz - 2.97 g hz ?-12? d b3 5 mhz - 1.485 g hz ?-18? d b3 s erial output intrinsi c j itter t o j pseu d oran d om an d s mpte c olour bars 3 g si g nal ?40 6 8ps4, 6 t o j pseu d oran d om an d s mpte c olour bars hd si g nal ?5095ps4, 6 t o j pseu d oran d om an d s mpte c olour bars s d si g nal ? 200 400 ps 5 gspi gs pi input c lo c k frequen c yf sc lk 50% levels 3.3v or 1.8v operation ??80mhz? gs pi input c lo c k duty c y c le d c sc lk 40 50 6 0% ? gs pi input data s etup time ? 1.5 ? ? ns ? gs pi input data hol d time ? 1.5 ? ? ns ? gs pi output data hol d time ? 15pf loa d 1.5 ? ? ns ? cs low b efore sc lk risin g e dg e t 0 50% levels 3.3v or 1.8v operation 1.5 ? ? ns ? time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g d ata wor d - write c y c le t 4 50% levels 3.3v or 1.8v operation p c lk (mhz) ns ? ? ns ? unlo c ke d 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6 .7 table 2-4: ac electrical characteristics (continued) v cc = 3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min typ max units notes
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 20 of 82 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g d ata wor d - rea d c y c le t 5 50% levels 3.3v or 1.8v operation p c lk (mhz) ns ? ? ns ? unlo c ke d 1187 13.5 297 27.0 148.4 74.25 53.9 148.5 27 cs hi g h after sc lk fallin g e dg e t 7 50% levels 3.3v or 1.8v operation p c lk (mhz) ns ? ? ns ? unlo c ke d 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6 .7 notes: 1. input setup and hold time is dependent on the rise and fall time on the parallel input . parallel clock and data with rise tim e or fall time greater than 500ps require larger setup and hold times. 2. single ended into 75 external load. 3. orl depends on board design. 4. alignment jitter = measured from 100khz to serial data rate/10. 5. alignment jitter = measured from 1khz to 27mhz. 6. this is the maximum jitter for a ber of 10-12. th e equivalent jitter value as per rp184 is 40ps max. table 2-4: ac electrical characteristics (continued) v cc = 3.3v 5%, t a = -20 c to +85 c , unless otherwise shown parameter symbol conditions min typ max units notes
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 21 of 82 3. input/output circuits fi g ure 3-1: differential output s ta g e ( s do/ s do ) fi g ure 3-2: di g ital input pin (20 b it/ 10 b it , an c _blank , dete c t_tr s , dvb_a s i, rate_ s el0, s mpte_bypa ss , rate_ s el1, tim_8 6 1, f/de, h/h s yn c , p c lk, v/v s yn c ) i ref c d_vdd s do s do io_vdd 200 input pin
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 22 of 82 fi g ure 3-3: di g ital input pin with sc hmitt tri gg er ( re s et ) fi g ure 3-4: di g ital input pin with weak pull- d own - maximum pull- d own c urrent <110ma ( j ta g / ho s t , s tandby, sc lk_t c k, s din_tdi, t c k, tdi) io_vdd 200 input pin io_vdd 200 input pin
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 23 of 82 fi g ure 3-5: di g ital input pin with weak pull-up - maximum pull-up c urrent <110ma ( cs _tm s , s do_en/ di s , tm s ) fi g ure 3- 6 : bi d ire c tional di g ital input/output pin with pro g ramma b le d rive stren g th. these pins are c onfi g ure d to input at all times ex c ept in test mo d e. (din0, din2, din3, din4, din5, din 6 , din7, din8, din9, din10, din11, din12, din13, din14, din15, din1 6 , din17, din18, din19, din1) 200 input pin io_vdd io_vdd io_vdd 200 output pin
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 24 of 82 fi g ure 3-7: bi d ire c tional di g ital input/output pin with pro g ramma b le d rive stren g th. these pins are c onfi g ure d to output at all times ex c ept in reset mo d e. (lo c ked, s dout_tdo, tdo) fi g ure 3-8: vb g io_vdd 200 output pin vb g 50 2k a_vdd
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 25 of 82 fi g ure 3-9: loop filter 30 pll_vdd lf 30
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 26 of 82 4. detailed description 4.1 functional overview the GS2962 is a multi-rate transmitter with integrated smpte digital video processing and an integrated cable driver. it provides a complete transmit solution at 2.970gb/s, 2.970/1.001gb/s, 1.485gb/s, 1.485/1.001gb/s or 270mb/s. the device has four basic modes of operation that must be set through external device pins: smpte mode, dvb-asi mode, data-through mode and standby mode. in smpte mode, the device will accept 10-b it multiplexed or 20-bit demultiplexed smpte compliant data. by default, the device's additional processing features will be enabled in this mode. in dvb-asi mode, the GS2962 will accept an 8-bit parallel dvb-asi compliant transport stream on din[17:10]. the serial output data stream will be 8b/10b encoded with stuffing characters added as per the standard. data-through mode allows for the serializing of data not conforming to smpte or dvb-asi streams. no additional processing will be done in this mode. in addition, the device may be put into standby, to reduce power consumption. the serial digital output features a high-impedance mode and adjustable signal swing. the output slew rate is automatically set by the rate_sel0 and rate_sel1 pin setting. the GS2962 provides several data proce ssing functions; including generic anc insertion, smpte 352m and edh data packet generation and insertion, automatic video standards detection, and trs, crc, anc data checksum, and line number calculation and insertion. these features are all enabled/disabled collectively using the external i/o processing pin, but may be individually di sabled via internal registers accessible through the gspi host interface. finally, the GS2962 contains a jtag interface for boundary scan test implementations.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 27 of 82 4.2 parallel data inputs data signal inputs enter the device on the rising edge of pclk, as shown in figure 4-1 . fi g ure 4-1: gs 29 6 2 vi d eo host interfa c e timin g dia g rams ds1_0 transition zone ds2_0 transition zone pclk 3.36ns ds1_n-1 ds1_n-1 transition zone ds2_0 t su t h t h ds1_0 ddr interface note: ds = data stream as per smpte 425m ds2_* is launched on the negative edge of pclk by the source chip to the GS2962 ds1_* is launched on the positive edge of pclk by the source chip to the GS2962 t su data_1 transition zone data_1 data_0 transition zone pclk pclk period din[19:0], f_de, h_hsync, v_vsync data_0 t h sdr interface ds* is launched on the positive edge of pclk by the source chip to the GS2962 t su t h t su din[19:0], f_de, h_hsync, v_vsync t h t h table 4-1: GS2962 digital input ac electrical characteristics parameter symbol conditions min ty p max units input d ata set-up time t s u 50% levels; 1.8v operation 1.2 ?? ns input d ata hol d time t ih 0.8 ?? ns input d ata set-up time t s u 50% levels; 3.3v operation 1.3 ?? ns input d ata hol d time t ih 0.8 ?? ns table 4-2: GS2962 input video data format selections input data format pin/register bit settings din[9:0] din[19:10] 20bit /10bit rate _sel0 rate _sel1 smpte _bypass dvb_asi 20- b it d emultiplexe d 3 g format hi g hlowhi g hhi g hlowdata s tream two data s tream one 20- b it d ata input 3 g format hi g hlowhi g h low low data data
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 28 of 82 the GS2962 is a high performance 3gb/s capable transmitter. in order to optimize the output jitter performance across all operating conditions, input levels and overshoot at the parallel video data inputs of the device need to be controlled. in order to do this, source series termination resistors should be used to match the impedance of the pcb data trace line. ibis models can be used to simulate the board effects and then optimize the output drive strength and the termination resistors to allow for the best transition (one that produces minimal overshoot). if this is not viable, gennum recommends matching the source series resistance to the trace impedance, and then adjusting the output drive strength to the minimum value that will give zero errors. the above also applies to the pclk input line. hvf should also be well terminated, however due to the lower data rates and transition density, it is not as critical. 4.2.1 parallel input in smpte mode when the device is operating in smpte mode (smpte_bypass = high), data must be presented to the input bus in either multiplexed or demultiplexed form, depending on the setting of the 20bit/10bit pin. 20- b it d emultiplexe d hd format hi g hlow low hi g hlow c hroma luma 20- b it d ata input hd format hi g h low low low low data data 20- b it d emultiplexe d s d format hi g hhi g hx hi g hlow c hroma luma 20- b it d ata input s d format hi g hhi g h x low low data data 10- b it multiplexe d 3 g ddr format low low hi g hhi g hlow hi g h impe d an c e data s tream one/data s tream two 10- b it multiplexe d hd format low low low hi g hlow hi g h impe d an c e luma/ c hroma 10- b it d ata input hd format low low low low low hi g h impe d an c e data 10- b it multiplexe d s d format low hi g hx hi g hlow hi g h impe d an c e luma/ c hroma 10- b it multiplexe d s d format low hi g hx low low hi g h impe d an c e data 10- b it a s i input s d format low hi g h x low hi g hhi g h impe d an c e dvb-a s i d ata table 4-2: GS2962 input video data format selections (continued) input data format pin/register bit settings din[9:0] din[19:10] 20bit /10bit rate _sel0 rate _sel1 smpte _bypass dvb_asi
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 29 of 82 when operating in 20-bit mode (20bit/10bit = high), the input data format must be word aligned, demultiplexed luma and chroma data (sd or hd), or word aligned demultiplexed data stream one and data stream two data (3g). in 3g mode, by default, the device takes data stream one input from data port din[19:10] and data stream two input from din[9:0]. when operating in 10-bit mode (20bit/10bit = low), the input data format must be multiplexed luma (y) and chroma (c) data (sd, hd), or multiplexed data stream one and data stream two data (3g). c words precede y words, and data stream 2 words precede data stream 1 words. in this mode, the data must be presented on the din[19:10] pins. the din[9:0] inputs are ignored. in 3g 10-bit mode, the device operates in ddr mode. that is, the input data is sampled on both the rising and falling edges of the pclk. in 3g mode, data stream two words precede data stream one words. the data stream two words are sampled on the rising edge of the input pclk, and the data stream one words are sampled on the following falling edge. h, v and f timing pulses, if used, are sampled on the rising edge of pclk. 4.2.1.1 input data format in sdti mode sdti and hd-sdti are a sub-set of sdi and hd-sdi formats. they may contain sdti data on any line in the frame. those lines which contain sdti or hd-sdti data are identified with an sdti or hd-sdti header packet in the hanc space. the GS2962 does not differentiate between a signal carrying video and a signal carrying sdti or hd-sdti data in sd or hd formats. the user is responsible for ensuring that the headers and data are not corrupted. 4.2.2 parallel input in dvb-asi mode the GS2962 is in dvb-asi mode when the smpte_bypass pin is set low, the dvb_asi pin is set high, and the rate_sel0 pin is set high. in this mode, all smpte processing features are disabled. when operating in dvb-asi mode, the device must be set to 10-bit mode by setting the 20bit/10bit pin low. the device will accept 8-bit data words on din[17:10], where din17 = hin is the most significant bit of the encoded transport stream data and din10 = ain is the least significant bit. in addition, din19 and din18 will be configured as the dvb-asi control signals inssyncin and kin respectively. din19 = inssyncin din18 = kin din17~10 = hin ~ ain where ain is the least significant bit of the transport stream data. 4.2.3 parallel input in data-through mode data-through mode is enabled when the smpte_bypass pin and the dvb_asi pin are low. in this mode, data at the input bus is serialized without any encoding, scrambling or word alignment taking place.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 30 of 82 the input data width is controlled by the setting of the 20bit/10bit pin as shown in table 4-2 above. note: when in hd 10-bit mode, asserting the smpte_bypass low to put the device in smpte-bypass mode will create video errors. if the user desires to use the device as a simple serializer in hd 10-bit mode, all vi deo processing features may be disabled by setting the ioproc_en/dis pin low. 4.2.4 parallel input clock (pclk) the frequency of the pclk input signal of the GS2962 is determined by the input data format and operating mode selection. table 4-3 below lists the input pclk rates and input signal formats according to the external selection pins for the GS2962. table 4-3: GS2962 pclk input rates input data format pin settings pclk rate 20bit/10bit rate_ sel0 rate_ sel1 smpte_ bypass dvb-asi 20- b it d emultiplexe d 3 g format hi g hlowhi g hhi g h x 148.5 or 148.5/1.001mhz 20- b it d emultiplexe d hd format hi g h low low hi g h x 74.25 or 74.25/1.001mhz 20- b it d ata input 3 g format hi g hlowhi g h low low 148.5 or 148.5/1.001mhz 20- b it d ata input hd format hi g h low low low low 74.25 or 74.25/1.001mhz 20- b it d emultiplexe d s d format hi g hhi g hx hi g h low 13.5mhz 20- b it d ata input s d format hi g hhi g h x low low 13.5mhz 10- b it multiplexe d 3 g ddr format low low hi g hhi g h low 148.5 or 148.5/1.001mhz 10- b it multiplexe d hd format low low low hi g h low 148.5 or 148.5/1.001mhz 10- b it d ata input hd format low low low low low 148.5 or 148.5/1.001mhz 10- b it multiplexe d s d format low hi g hx hi g h x 27mhz 10- b it d ata input s d format low hi g h x low low 27mhz 10- b it a s i input s d format low hi g h x low hi g h 27mhz
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 31 of 82 4.3 smpte mode the function of this block is to carry out data scrambling according to smpte 424m/smpte 292m, and to carry out nrz to nrzi encoding prior to presentation to the parallel to serial converter. these functions are only enabled when the smpte_bypass pin is high. in addition, the GS2962 requires the dvb_asi pin to be set low to enable this feature. 4.3.1 h:v:f timing in smpte mode, the GS2962 can automatically detect the video standard and generate all internal timing signals. the total line length, active line length, total number of lines per field/frame and total active lines per field/frame are calculated for the received parallel video. when detect_trs is low, the video standard and timing signals are based on the externally supplied h_blanking, v_blanking, and f_digital signals. these signals are supplied by the h/hsync, v/vsync and f/de pins respectively. when detect_trs is high, the video standard timing signals will be extracted from the embedded trs id words in the parallel input data. both 8-bit and 10-bit trs code words will be identified by the device. note: i/o processing must be enabled for the device to remap 8-bit trs words to the corresponding 10-bit value for transmission. the GS2962 determines the video standard by timing the horizontal and vertical reference information supplied at the h/hsync, v/vsync, and f/de input pins, or contained in the trs id words of the received video data. therefore, full synchronization to the received video standard requires at least one complete video frame. once synchronization has been achieved, the GS2962 will continue to monitor the received trs timing or the supplied h, v, and f timing information to maintain synchronization. the GS2962 will lose all timing information immediately following loss of h, v and f. the h signal timing should also be configured via the h_config bit of the internal ioproc register as either active line based blanking or trs based blanking. active line based blanking is enabled when the h_config bit is set low. in this mode, the h input should be high for the entire horizontal blanking period, including the eav and sav trs words. this is the default h timing used by the device. the timing of these signals is shown in figure 4-5 , table 4-3 , table 4-4 , table 4-5 , table 4-6 , table 4-7 and table 4-8 .
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 32 of 82 fi g ure 4-2: h:v:f output timin g - 3 g level a an d hdtv 20- b it mo d e fi g ure 4-3: h:v:f output timin g - 3 g level a an d hdtv 10- b it mo d e 3 g level b 20- b it mo d e, ea c h 10- b it stream fi g ure 4-4: h:v:f output timin g - 3 g level b 10- b it mo d e fi g ure 4-5: h:v:f input timin g - hd 20- b it input mo d e pclk luma data chroma data h 000 000 3ff 000 000 3ff v f xyz (sav) 000 000 3ff 000 000 3ff xyz (sav) xyz (eav) xyz (eav) 000 000 3ff 3ff 000 000 pclk (hd) h v f multiplexed y?cbcr data (hd) multiplexed ds1/ds2 data (3g) pclk (3g ddr) 000 000 3ff 3ff 000 000 xyz (eav) multiplexed y?cbcr data (hd) multiplexed ds1/ds2 data (3g) h v f pclk (hd) pclk (3g ddr) h signal timing: h_config = low h_config = high hvf timingat sav hvf timingat eav xyz (eav) xyz (sav) xyz (sav) 3ff pclk (ddr) h v f multiplexed linka/linkb data 3ff 3ff 3ff 000 000 000 000 000 000 000 000 xyz (sav) xyz (sav ) xyz (sav) xyz (sav ) multiplexed linka/linkb data pclk (ddr) h v f 3ff 000 000 000 000 000 000 000 000 xyz (eav) xyz (eav) xyz (eav) xyz (eav) 3ff 3ff 3ff h signal timing: h_config = low h_config = high hvf timingat eav hvf timingat sav p c lk lu m a d a t a in p u t c hroma data input h x y z (eav) 000 000 3ff 000 000 3ff v f 000 000 3ff 000 000 3ff x y z (eav) x y z ( s av) x y z ( s av) h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 33 of 82 fi g ure 4- 6 : h:v:f input timin g - hd 10- b it input mo d e fi g ure 4-7: h:v:f input timin g - s d 20- b it mo d e fi g ure 4-8: h:v:f input timin g - s d 10- b it mo d e 4.3.2 cea 861 timing the GS2962 extracts timing information from externally provided hsync, vsync, and de signals when cea 861 timing mode is selected by setting detect_trs = low and tim_861 = high. horizontal sync (h), vertical sync (v), and data enable (de) timing must be provided via the h/hsync, v/vsync and f/de input pins. the host interface register bit h_config is ignored in cea 861 input timing mode. the GS2962 determines the eia/cea-861 standard and embeds eav and sav trs words in the output serial video stream. video standard detection is not dependent on the hsync pulse width or the vsync pulse width and therefore the GS2962 tolerates non-standard pulse widths. in addition, the device can compensate for up to 1 pclk cycle of jitter on vsync with respect to hsync and sample vsync correctly. note 1: the period between the leading edge of the hsync pulse and the leading edge of data enable (de) must follow the timing requirements described in the eia/cea-861 hvf timin g at s av 000 000 3ff 3ff 000 000 p c lk multiplexed y' cbc r d a t a in p u t h v f hvf timin g at eav p c lk 000 000 3ff 3ff x y z (eav) 000 000 multiplexed y' cbc r d a t a in p u t h v f x y z (eav) xyz ( s av) x y z ( s av) p c lk c hroma data input luma data input h 000 3ff x y z (eav) 000 v f 000 3ff 000 h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h x y z ( s av) multiplexed y' cbc r data input p c lk h v f x y z (eav) 000 000 3ff 000 000 3ff x y z ( s av) h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 34 of 82 specification. the GS2962 embeds trs words according to this timing relationship to maintain compatibility with the corresponding smpte standard. note 2: when cea 861 standards 6 & 7 [720(1440)x480i] are presented to the GS2962, the device embeds trs words corresponding to the timing defined in smpte 125m to maintain smpte compatibility. cea 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and 285 to 524 inclusive (240 active lines per field). smpte 125m defines the active area on lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1, 243 lines on field 2). therefore, in the first field, the GS2962 adds two active lines above and two active lines below the original active image. in the second field, it adds two lines above and one line below the original active image. the cea861 timing formats are summarized in table 4-4 . and are shown in figure 4-9 to figure 4-19 . table 4-4: cea861 timing formats format parameters 4 h:v:de input timin g 1280 x 720p @ 59.94/ 6 0hz 5 h:v:de input timin g 1920 x 1080i @ 59.94/ 6 0hz 6 &7 h:v:de input timin g 720 (1440) x 480i @ 59.94/ 6 0hz 19 h:v:de input timin g 1280 x 720p @ 50hz 20 h:v:de input timin g 1920 x 1080i @ 50hz 21&22 h:v:de input timin g 720 (1440) x 57 6 @ 50hz 1 6 h:v:de input timin g 1920 x 1080p @ 59.94/ 6 0hz 31 h:v:de input timin g 1920 x 1080p @ 50hz 32 h:v:de input timin g 1920 x 1080p @ 23.94/24hz 33 h:v:de input timin g 1920 x 1080p @ 25hz 34 h:v:de input timin g 1920 x 1080p @ 29.97/30hz
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 35 of 82 fi g ure 4-9: h:v:de input timin g 1280 x 720p @ 59.94/ 6 0 (format 4) fi g ure 4-10: h:v:de input timin g 1920 x 1080i @ 59.94/ 6 0 (format 5) 1 66 0 total horizontal c lo c ks per line 1280 c lo c ks for a c tive vi d eo data ena b le 220 c lo c ks 40 370 110 h s yn c pro g ressive frame: 30 verti c al blankin g lines 720 a c tive verti c al lines 1 6 50 c lo c ks data ena b le h s yn c 110 v s yn c 2 6 0 745 74 6 747 748 749 750 1 2 3 4 5 6 7 25 2 6 745 74 6 750 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c v s yn c 1123 1124 1125 1 2 3 4 5 6 7 8 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 fiel d 1: 22 verti c al blankin g lines 2200 c lo c ks 88 19 20 21 5 6 0 5 6 1 5 6 2 192 540 a c tive verti c al lines per fiel d 540 a c tive verti c al lines per fiel d fiel d 2: 23 verti c al blankin g lines 192 88 2200 c lo c ks 1100 v s yn c data ena b le h s yn c 5 6 0 5 6 1 5 6 2 5 6 3 5 6 4 5 6 5 5 66 5 6 7 5 6 8 5 6 9 570 582 583 584 1123 1124 1125 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 36 of 82 fi g ure 4-11: h:v:de input timin g 720 (1440) x 480i @ 59.94/ 6 0 (format 6 &7) fi g ure 4-12: h:v:de input timin g 1280 x 720p @ 50 (format 19) 1440 c lo c ks for a c tive vi d eo 27 6 data ena b le 171 6 total horizontal c lo c ks per line h s yn c data ena b le h s yn c v s yn c data ena b le h s yn c v s yn c 114 c lo c ks 124 38 fiel d 1: 22 verti c al blankin g lines 171 6 c lo c ks 238 240 a c tive verti c al lines per fiel d ~ ~ ~ ~ 38 240 a c tive verti c al lines per fiel d fiel d 2: 23 verti c al blankin g lines ~ ~ 524 525 1 2 3 4 5 6 7 8 9 21 22 ~ ~ ~ ~ 238 38 171 6 c lo c ks 858 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 66 2 6 7 2 6 8 2 6 9 270 271 524 525 1 284 285 2 6 1 2 6 2 2 6 3 220 c lo c ks 1280 c lo c ks for a c tive vi d eo 700 data ena b le h s yn c v s yn c 745 74 6 747 748 749 750 1 2 3 4 5 6 7 data ena b le h s yn c 1980 total horizontal c lo c ks per line 40 440 pro g ressive frame: 30 verti c al blankin g lines 1980 c lo c ks 440 745 74 6 2 6 0 720 a c tive verti c al lines ~ ~ ~ ~ ~ ~ ~ 25 2 6 ~ ~ ~ ~ 750
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 37 of 82 fi g ure 4-13: h:v:de input timin g 1920 x 1080i @ 50 (format 20) 148 clocks 1920 clocks for active video 720 data enable hsync 2640 total horizontal clocks per line 44 528 vsync 1123 1124 1125 1 2 3 4 5 6 7 8 data enable hsync field 1: 22 vertical blanking lines 2640 clocks 528 19 20 21 560 561 562 192 540 active vertical lines per field 540 active vertical lines per field field 2: 23 vertical blanking lines 192 528 2640 clocks 1320 vsync data enable hsync 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 38 of 82 fi g ure 4-14: h:v:de input timin g 720 (1440) x 57 6 @ 50 (format 21&22) fi g ure 4-15: h:v:de input timin g 1920 x 1080p @ 59.94/ 6 0 (format 1 6 ) 1440 c lo c ks for a c tive vi d eo 288 data ena b le 1728 total horizontal c lo c ks per line h s yn c 138 c lo c ks 12 6 24 data ena b le h s yn c v s yn c data ena b le h s yn c v s yn c fiel d 1: 24 verti c al blankin g lines 1728 c lo c ks 2 6 4 288 a c tive verti c al lines per fiel d ~ ~ ~ ~ 24 288 a c tive verti c al lines per fiel d fiel d 2: 25 verti c al blankin g lines ~ ~ 6 23 6 24 6 25 1 2 3 4 5 6 7 22 23 ~ ~ ~ ~ 2 6 4 24 1728 c lo c ks 8 6 4 310 311 312 313 314 315 31 6 317 318 319 320 6 23 6 24 6 25 335 33 6 310 311 312 ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2200 c lo c ks 88 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 39 of 82 fi g ure 4-1 6 : h:v:de input timin g 1920 x 1080p @ 50 (format 31) fi g ure 4-17: h:v:de input timin g 1920 x 1080p @ 23.94/24 (format 32) 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 720 data ena b le h s yn c 2 6 40 total horizontal c lo c ks per line 44 528 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2 6 40 c lo c ks 528 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 830 data ena b le h s yn c 2750 total horizontal c lo c ks per line 44 6 38 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2750 c lo c ks 6 38 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 40 of 82 fi g ure 4-18: h:v:de input timin g 1920 x 1080p @ 25 (format 33) fi g ure 4-19: h:v:de input timin g 1920 x 1080p @ 29.97/30 (format 34) 4.4 dvb-asi mode when operating in dvb-asi mode, all smpte processing features are disabled, and the device accepts 8-bit transport stream data and control signal inputs on the din[19:10] port. this mode is only enabled when smpte_bypass pin is low, dvb_asi pin is high and the rate_sel0 pin is high. the interface consists of eight data bits and two control signals, inssyncin and kin. 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 720 data ena b le h s yn c 2 6 40 total horizontal c lo c ks per line 44 528 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2 6 40 c lo c ks 528 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2220 c lo c ks 88 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 41 of 82 when inssyncin is set high, the GS2962 inserts k28.5 sync characters into the data stream. this function is used to assist system implementations where the GS2962 may be preceded by a data fifo. the fifo can be fed data at a rate somewhat less than 27mhz. the ?fifo empty? signal could be used to feed the inssyncin pin, causing the GS2962 to pad the data up to the transmission rate of 27mhz. when kin is set high the data input is interpreted as a special character (such as a k28.5 sync character), as defined by the dvb-asi standard. when kin is set low the input is interpreted as data. after sync signal insertion, the GS2962 8b/10b encodes the data, generating a 10-bit data stream for the parallel to serial conversion and transmission process. 4.5 data-through mode the GS2962 may be configured to operate as a simple parallel-to-serial converter. in this mode, the device passes data to the serial ou tput without performing any scrambling or encoding. data-through mode is enabled only when both the smpte_bypass and dvb_asi pins are set low. 4.6 standby mode the standby pin reduces power to a minimum by disabling all circuits except for the register configuration. upon removal of the signal to the standby pin, the device returns to its previous operating condition within 1 second, without requiring input from the host interface. in addition, the serial digital output signals becomes high-impedance when the device is powered-down. 4.7 anc data insertion horizontal or vertical ancillary data words may be inserted on up to four different lines per video frame. up to 512 data words may be inserted per frame with all data words - including the anc packet adf, dbn, dcnt, did, sdid and csum words - being provided by the user via host interface configuration. the csum word is re-calculated and inserted by the anc data checksum calculation and insertion function. note that any value may be used for the csum word, provided that it is outside the protected ranges from 000h to 003h and from 3fch to 3ffh. if a csum value in either of these ranges is used, it will not be corrected by the device.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 42 of 82 the GS2962 does not provide error checking or correction to the anc data provided by user via the host interface. it is the responsibility of the user to ensure that all data provided for insertion is fully standard compliant. in 3g level a mode, ancillary data packets are inserted into data stream one or data stream two as selected by the host interface. the default insertion will be in data stream one. see address 02dh, stream_type1_line_x. in 3g level b mode, ancillary data packets are inserted into the y or c video stream of link a or link b as selected by the user in the host interface. the default insertion will be in the y video stream of link a. for link a or link b, see register 02dh. for y or c, see registers 026h, 028h, 02ah and 02ch. in hd mode, anc data packets are inserted into the y or c video stream, as selected via the host interface. the default insertion will be in the y stream. for y or c, see registers 026h, 028h, 02ah and 02ch. in sd mode, the anc data packets are inserted into the multiplexed cbycr data stream. anc data insertion only takes place if the ioproc_en/dis pin is high and smpte_bypass is high. in addition to this, the GS2962 requires the anc_ins bit to be set low in the ioproc register. 4.7.1 anc insertion operating modes user selection of one of the two operating modes is provided through host interface configuration, using the anc_ins_mode register bit (see table 4-16: configuration and status registers ). the supported operating modes are concatenated mode and separate line operating mode. by default (at power up or after system reset), the separate line operating mode is enabled. ancillary data packets are programmed into the anc_packet_bank host register at addresses 040h to bffh. 4.7.1.1 separate line operating mode in separate line mode, it is possible to insert horizontal or vertical ancillary data on up to four lines per video frame. hanc or vanc can be specified, independently of each other, on a per-line basis. 025h first_line_number, 027h second_line_number, 029h third_line_number and 02bh fourth_line_number. for each of the four video lines, up to 128 8-bit hanc or vanc data words can be inserted. separate line mode is selected by setting the anc_ins_mode bit in the host interface low. by default, at power up, separate line mode is selected. the lines on which ancillary data is to be in serted is programmed in the host register addresses 025h to 02ch.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 43 of 82 for hd formats, the stream into which the ancillary data is to be inserted (luma or chroma) is also programmed in these register addresses. the non-zero video line numbers on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert per line must be provided via the host interface (see section 4.12 ). at power up, or after system reset, all ancillary data insertion line numbers and total number of words default to zero. if the total number of data words specified per line exceeds 128 only the first 128 data words will be inserted, the rest will be ignored. the data words are programmed as two 8-bit values per address, starting at host interface address 040h in the anc_packet_bank register (see table 4-16 ). the device automatically converts the provided 8-bit data words into the 10-bit data, formatted according to smpte 291m prior to insertion. 4.7.1.2 concatenated operating mode in concatenated mode, it is possible to insert up to 512 8-bit horizontal or vertical ancillary data words on one line per video frame. concatenated line mode can be selected by setting the anc_ins_mode bit in the host interface high. by default, at power up, separate line mode is selected. in concatenated mode, only the first_line registers of the host interface need to be programmed (addresses 025h and 026h). see table 4-16 . the non-zero video line number on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert must be provided via the host interface. at power up, or after system reset, the ancillary data insertion line number and total number of words default to zero. if the total number of data words specified exceeds 512 only the first 512 data words will be inserted, the rest will be ignored. the data words are programmed as two 8-bit values per address, starting at host interface address 040h in the anc_packet_bank register. see table 4-16 . the device automatically converts the provided 8-bit data words into the 10-bit data formatted according to smpte 291m prior to insertion. 4.7.2 3g anc insertion 4.7.2.1 level a mode when operating in 3g (rate _sel0 = lo w, rate_sel1 = high) level a mode, the GS2962 inserts vanc or hanc data packets into data stream one (default) or data stream two. the data stream for insertion is selectable fo r each of the anc insertion lines selected via the host interface. data stream one is selected when the stream_type_1 bit in the register associated with the insertion line is set low (default). data stream two is selected when the stream_type_1 bit associated with the insertion line is set high.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 44 of 82 anc data should be placed in ds1 first in level a mode, and only in ds2 as an overflow if ds1 is full. data insertion starts at the first available location in the hanc space following any pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs sav code, regardless of the number of data words actually inserted. the rest of the packet will be ignored. vertical ancillary data (vanc), is inserted into the data stream on the video line(s) defined by the user. data insertion starts at the first active pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and the line number on which the anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via the host interface register stream_type_1 (02dh). 4.7.2.2 level b mode when operating in 3g (rate_sel0 = lo w, rate_sel1 = high) level b mode, the GS2962 inserts vanc or hanc data packets into either the y or c data stream of data stream one (default) or data stream two, as selected by the stream_type_1 bit in the host interface on a per line basis. by default (at power up or after system reset), all anc data insertion takes place in the y data stream of data stream one. the user can select between the y or c data stream for insertion on a per line basis in separate line mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is selected when the stream_type_0 bit is high. the user can select between the y or c data stream for insertion on a single line basis in concatenated mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is selected when the stream_type_0 bit is high. horizontal ancillary data (hanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first available location in the hanc space following any pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion, starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs sav code, regardless of the number of data words actually inserted.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 45 of 82 vertical ancillary data (vanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first active pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and line number on which anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via the host interface. stream_type_1 = address 02dh, stream_type_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02ah (bit 14) and 02ch (bit 14). 4.7.3 hd anc insertion when operating in hd mode (rate_sel0 = low, rate_sel1 = low), the GS2962 inserts vanc or hanc data packets into either the y data stream or c data stream. by default (at power up or after system reset), all anc data insertion takes place in the y data stream. the user can select between y or c data stream for insertion on a per line basis in separate line mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is selected when the stream_type_0 bit is high. the user can select between y or c data stream for insertion on a single line basis in concatenated mode. the y data stream is selected when the stream_type_0 bit is low (default). the c data stream is selected when the stream_type_0 bit is high. horizontal ancillary data (hanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first available location in the hanc space, following any pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs sav code, regardless of the number of data words actually inserted. vertical ancillary data (vanc), is inserted into the y or c data stream on the video line(s) defined by the user. data insertion starts at the first active pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion, starting at the first active pixel.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 46 of 82 vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and the line number on which anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via host interface configuration. stream_type_1 = address 02dh, stream_type_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02ah (bit 14) and 02ch (bit 14). 4.7.4 sd anc insertion when operating in sd mode (rate_sel0 = high), the GS2962 inserts vanc or hanc data packets into the multiplexed cbycr data stream. horizontal ancillary data (hanc), is inserted on the video line(s) defined by the user. data insertion starts at the first available location in the hanc space following any pre-existing arbitrary data packets. all data words identified by the user are inserted in a contiguous fashion, starting at the first available data space. hanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs sav code, regardless of the number of data words actually inserted. for the case where hanc data insertion is required on the same line as the edh packet, data insertion is terminated by the start of the edh packet, regardless of the number of data words actually inserted. vertical ancillary data (vanc), is inserted into the data stream on the video line(s) defined by the user. data insertion starts at the first active cb pixel immediately following the last word of the trs sav code. all data words identified by the user are inserted in a contiguous fashion, starting at the first active pixel. vanc data insertion terminates when all data words identified by the user have been inserted; or by the start of the four word trs eav code, regardless of the number of data words actually inserted. the total number of data words to be inserted and the line number on which anc data insertion takes place is provided by the user via the host interface as part of the configuration of the anc data insertion function. the user data for insertion is provided via host interface configuration. stream_type_1 = address 02dh, stream_type_0 for the four lines of insertion is at addresses 026h (bit 14), 028h (bit 14), 02ah (bit 14) and 02ch (bit 14). anc data checksum insertion only takes place if the ioproc_en/dis pin is high, the smpte_bypass is high and the anc_csum_ins bit is set low in the ioproc register.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 47 of 82 4.8 additional processing functions the GS2962 contains a number of signal processing features. these features are only enabled in smpte mode of operation (smpte_bypass = high), and when i/o processing is enabled (ioproc_en/dis = high). signal processing features include: ? trs generation and insertion ? line number calculation and insertion ? line based crc calculation and insertion ? illegal code re-mapping ? smpte 352m payload identifier packet insertion ? anc checksum calculation and correction ?edh generation and insertion ? smpte 372m conversion to enable these features in the GS2962, the smpte_bypass pin must be high, the ioproc_en/dis pin must be high and the individual feature must be enabled via bits set in the ioproc register of the host interface. by default, all of the processing features are enabled, except for smpte 372m correction. 4.8.1 video format detection by using the timing parameters extracted from the received trs signals, or the supplied external timing signals, the GS2962 calculates the video format. the total samples per line, active samples per line, total lines per field/frame, and active lines per field/frame are measured and reported to the user via the four raset_struc_x registers in the host interface. these line and sample count registers are updated once per frame at the end of line 12. the raset_struc_x registers also contain two status bits: std_lock and int/prog . the std_lock bit is set high whenever the automatic video format detection circuit has achieved full synchronization. the int/prog bit is set low if the detected video standard is progressive, and is set high if the detected video standard is interlaced. the gennum video standard code (vd_std), as used in the gs2972, gs1582 and gs1572, is included in table 4-5 for reference purposes. note: if proper smpte video is applied and then removed from the input, the device does not flag that the h_lock, v_lock, vd_sdt etc. has changed (been lost). this is the case for either trs detect or hvf modes. this problem occurs only when the video data is removed, but not the pclk. usually, when a video signal is removed, it includes the clock, the video data, as well as the h, v, f as a whole. so the scenario is not likely to occur, but the user should be aware of this issue.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 48 of 82 table 4-5: supported video standards smpte standard active video area length of hanc length of active video total samples smpte 352m lines gennum vd_std [4:0] rate_ sel1 428.1m 2048x1080/24 (1:1) 6 90 2048 2750 10 1 c h1 428.1m 2048x1080/25 (1:1) 580 2048 2 6 40 10 1 c h1 425m (3 g ) 4:2:2 1920x1080/ 6 0 (1:1) 2 6 8 1920 2200 10 (18) 1 0bh 1 1920x1080/50 (1:1) 708 1920 2 6 40 10 (18) 1 0dh 1 425m (3 g ) 4:4:4 1920x1080/ 6 0 (2:1) or 1920x1080/30 (psf) 2 6 8 2 1920 2 2200 10, 572 0ah 1 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 2 1920 2 2 6 40 10, 572 0 c h1 1280x720/ 6 0 (1:1) 358 2 1280 2 1 6 50 10 (13) 1 00h 1 1280x720/50 (1:1) 6 88 2 1280 2 1980 10 (13) 1 04h 1 1920x1080/30 (1:1) 2 6 8 2 1920 2 2200 10 (18) 1 0bh 1 1920x1080/25 (1:1) 708 2 1920 2 2 6 40 10 (18) 1 0dh 1 1280x720/25 (1:1) 2 66 8 2 1280 2 39 6 0 10 (13) 1 0 6 h1 1920x1080/24 (1:1) 818 2 1920 2 2750 10 (18) 1 10h 1 1280x720/24 (1:1) 2833 2 1280 2 4125 10 (13) 1 08h 1 2 6 0m (hd) 1920x1035/ 6 0 (2:1) 2 6 8 1920 2200 10, 572 15h 0 295m (hd) 1920x1080/50 (2:1) 444 1920 237 6 10, 572 14h 0
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 49 of 82 274m (hd) 1920x1080/ 6 0 (2:1) or 1920x1080/30 (psf) 2 6 8 1920 2200 10, 572 0ah 0 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2 6 40 10, 572 0 c h0 1920x1080/30 (1:1) 2 6 8 1920 2200 10 (18) 1 0bh 0 1920x1080/25 (1:1) 708 1920 2 6 40 10 (18) 1 0dh 0 1920x1080/24 (1:1) 818 1920 2750 10 (18) 1 10h 0 1920x1080/24 (psf) 818 1920 2750 10, 572 11h 0 1920x1080/25 (1:1) ? em 324 2304 2 6 40 10 (18) 1 0eh 0 1920x1080/25 (psf) ? em 324 2304 2 6 40 10, 572 0fh 0 1920x1080/24 (1:1) ? em 338 2400 2750 10 (18) 1 12h 0 1920x1080/24 (psf) ? em 338 2400 2750 10, 572 13h 0 29 6 m (hd) 1280x720/30 (1:1) 2008 1280 3300 10 (13) 1 02h 0 1280x720/30 (1:1) ? em 408 2880 3300 10 (13) 1 03h 0 1280x720/50 (1:1) 6 88 1280 1980 10 (13) 1 04h 0 1280x720/50 (1:1) ? em 240 1728 1980 10 (13) 1 05h 0 1280x720/25 (1:1) 2 66 8 1280 39 6 0 10 (13) 1 0 6 h0 1280x720/25 (1:1) ? em 492 345 6 39 6 0 10 (13) 1 07h 0 1280x720/24 (1:1) 2833 1280 4125 10 (13) 1 08h 0 1280x720/24 (1:1) ? em 513 3 6 00 4125 10 (13) 1 09h 0 1280x720/ 6 0 (1:1) 358 1280 1 6 50 10 (13) 1 00h 0 1280x720/ 6 0 (1:1) ? em 198 1440 1 6 50 10 (13) 1 01h 0 table 4-5: supported video standards (continued) smpte standard active video area length of hanc length of active video total samples smpte 352m lines gennum vd_std [4:0] rate_ sel1
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 50 of 82 by default (at power up or after system reset), the four raster_struc_x, std_lock and int/prog registers are set to zero. these registers are also cleared when the smpte_bypass pin is low, or the locked pin is low. note 1: the line numbers in brackets refer to version zero smpte 352m packet locations, if they are different from the version one locations. note 2: 3g formats cannot be fully determined from these measurements. their detailed information will be derived from smpte 352m packets, which must be in the video stream as a mandatory requirement of the smpte 424m specification, as described below. 4.8.2 3g format detection format detection is more difficult for 3g signals, as there are two levels of signal (level a and level b) and multiple mappings within each level. timing information is not sufficient to fully deco de the video format. for this reason smpte 352m video payload identifier packets are mandatory for all smpte 424m serial signals. 125m ( s d) 1440x487/ 6 0 (2:1) (or d ual link pro g ressive) 280 1440 171 6 13, 27 6 1 6 hx 1440x507/ 6 0 (2:1) 280 1440 171 6 13, 27 6 17h x 525-line 487 g eneri c ?? 171 6 13, 27 6 19h x 525-line 507 g eneri c ?? 171 6 13, 27 6 1bh x itu-r bt. 6 5 6 ( s d) 1440x57 6 /50 (2:1) (or d ual link pro g ressive) 280 1440 1728 9, 322 18h x 6 25-line g eneri c (em) ?? 1728 9, 322 1ah x unknown hd rate_ s el0 = 0 ? ??? 1dh unknown s d rate_ s el0 = 1 ? ??? 1eh x unknown 3 g rate_ s el0 = 0 ? ??? 1fh 1 note s : 1. the line numbers in brackets refer to version zero smpte 352m packet locations, if they are different from version 1. 2. the part may provide full or limited functionality with sta ndards that are not included in this table. please consult a gennu m technical representative. table 4-5: supported video standards (continued) smpte standard active video area length of hanc length of active video total samples smpte 352m lines gennum vd_std [4:0] rate_ sel1
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 51 of 82 note: the only exception is when the smpte425m mapping is level b twin smpte292m streams, and one or both of the smpte292m streams carries hd-sdti data. in this case the hd-sdti header packets are used for payload identification. 4.8.2.1 level a and level b signals: the GS2962 uses smpte 352m packets to determine the video format. the smpte 352m packets used for format de tection will either be: ? when the 352_ins (address 000h bit 6) bit is low, then if either bit 6 or 7 of address 20ah are high, the format is 3g level b. if both are low, then it will look at the information programmed at address 00ah video_format_out_ds1_x. see smpte 425m standard for details. ? when the bit is high, the format is 3g level a. extraction of 352m packets cannot be done in 3g level b. the GS2962 uses the programmed smpte 352m packets if the 352_ins register bit in the ioproc register is high. if there are no smpte 352m packets embedded in the input signal, and the user does not embed smpte 352m packets from the host interface, the GS2962 assumes an input signal of 1080p/50 or 1080p/59.94. the GS2962 uses information from the raster_struc_x registers to select between these two frame rates. if there are no smpte 352m packets embedded in the input signal, the GS2962 will raise an error flag in the ?no_352_err? bit. if there are 352m packets present in the stream, the GS2962 reports the extracted smpte 352m packets in the video_format_352_in registers in the host interface. the user can use this information, along with the raster_struc_x registers, to determine the video format. if there is a conflict between the numbers in the registers and the format defined in the smpte 352m packets, the GS2962 will raise a timing_error_352 flag via the host interface. note: smpte 352m packets will not be present in an hd-sdti input stream, and will not be embedded in an output hd-sdti serial stream. this is controlled by the user as described in section 4.8.8.1 . by default (at power up or after system reset), the video_format_352_in registers are set to zero (undefined video format). these registers are also cleared when the smpte_bypass pin is set low, or the locked pin is low. the smpte 352m packet should be received once per field for interlaced systems and once per frame for progressive video systems. if the packet is not received for two complete video frames, the video_format_352_in registers are cleared to zero.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 52 of 82 4.8.2.2 level b signals: for level b inputs, the GS2962 does not extract the smpte 352m packets from the parallel input. the only source of smpte 352m packets in level b mode, to be used for format detection and for embedding in the output data streams, is from the user programmed registers in the host interface. 4.8.3 anc data blanking the GS2962 can blank the video input data du ring the h and v blanking periods. this function will be enabled by setting the anc_blank pin low. this function is only available when the device is operating in smpte mode (smpte_bypass = high). in this mode, input video data in the horizontal and vertical blanking periods will be replaced by smpte compliant blanking values. the blanking function will operate only on the video input signal and will remove all ancillary data already embedded in the input video stream. table 4-6: smpte 352m packet data register name bit name description r/w default video_format_352_in_word_2 15-8 video_format_in _d s 1_4 (byte 4) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in _d s 1_3 (byte 3) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_352_in_word_1 15-8 video_format_in _d s 1_2 (byte 2) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in _d s 1_1 (byte 1) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_352_in_word_4 15-8 video_format_in _d s 2_4 (byte 4) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in _d s 2_3 (byte 3) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_352_in_word_3 15-8 video_format_in _d s 2_2 (byte 2) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 7-0 video_format_in _d s 2_1 (byte 1) data will b e availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 53 of 82 in sd mode, sav and eav code words already embedded in the input video stream will be protected and will not be blanked. in hd and 3g modes, sav and eav code words, line numbers and line based crc's already embedded in the input video stream will be protected and will not be blanked. the above two statements are really implementation specific, and are provided only to ensure that the ?detect trs? function for timing generation is supported by the device, even when the blanking function is enabled. from a system perspective, use of the input blanking function is not recommended unless trs, line number and crc generation and insertion functions are enabled. the active image area will not be blanked. the input blanking function will not blank any of the ancillary data, trs words, line numbers, crc's, edh or smpte 352m payload identifiers inserted by the device itself. 4.8.4 anc data checksum calculation and insertion the GS2962 calculates checksums for all detected ancillary data packets presented to the device. anc data checksum insertion only takes place if the ioproc_en/dis pin is high, the smpte_bypass is high and the anc_csum_ins bit is set low in the ioproc register. note: the device will correct any csum value outside the protected ranges from 000h to 003h and from 3fch to 3ffh. if a csum valu e in either of these ranges is presented to the device, it will not be corrected. 4.8.5 trs generation and insertion the GS2962 is capable of generating and inserting trs codes. trs word generation and insertion are performed in accordance with the timing parameters generated by the timing circuits, which is locked to the externally provided h:v:f or cea-861 signals, or the trs signals embedded in the input data stream. the GS2962 will overwrite the trs signals if they're already embedded. when a 3g level a signal is applied to the GS2962, and when the conv_372 (bit 9 address 000h) is set low (level a to level b conversion), trs will be inserted according to 3g level b format. 10-bit trs code words are inserted at all times. the insertion of trs id words only take place if the ioproc_en/dis pin is high and the smpte_bypass pin is high. in addition to this, the GS2962 requires the trs_ins bit to be set low in the ioproc register. if the tim_861 pin is high, then the timing circuits are locked to cea-861 timing.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 54 of 82 4.8.6 hd and 3g line number calculation and insertion the GS2962 is capable of line number generation and insertion, in accordance with the relevant hd video standard, as determined by the automatic video standard detector. line numbers are inserted into both the y and c channels. note: line number generation and insertion only occurs in hd and 3g modes (rate_sel0 = low). the insertion of line numbers only take place if the ioproc_en/dis pin is high and smpte_bypass pin is high. in addition to this, the GS2962 requires the lnum_ins bit to be set low in the ioproc register. 4.8.7 illegal code re-mapping the GS2962 detects and corrects illegal code words within the active picture area. all codes within the active picture (outside the horizontal and vertical blanking periods), between the values of 3fch and 3ffh are re-mapped to 3fbh. all codes within the active picture area between the values of 000h and 003h are remapped to 004h. 8-bit trs code words and ancillary data preambles are also re-mapped to 10-bit values. the illegal code re-mapping will only take place if the ioproc_en/dis pin is high and smpte_bypass is high. in addition to this, the GS2962 requires the illegal_remap bit to be set low in the ioproc register. 4.8.8 smpte 352m payload id entifier packet insertion when enabled by the 352m_ins bit in the ioproc register, new smpte 352m payload identifier packets are inserted into the data stream. these packets are supplied by the user via the host interface. setting the 352m_ins bit low enables this insertion. the device will automatically calculate the checksum and generate version one compliant 352m ancillary data preambles: did, sdid, dbn, dc. the smpte 352m packet is inserted into the data stream according to the line number and sample position rules defined in the 2002 standard. for hdtv video systems the smpte 352m packet is placed in the y channel only. by default (at power up or after system reset), the four video_format_in_ds1 registers and the four video_format_out_ds1 registers are set to zero. 4.8.8.1 3g smpte 352m payload identifier packet insertion when enabled by the 352m_ins bit in the ioproc register (000h), new smpte 352m payload identifier packets are inserted into the data streams. setting this bit low enables insertion.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 55 of 82 insertion of smpte 352m packets into each data stream is controlled by the status format describing bit, sdti_tdm_ds1 and sdti_tdm_ds2 for data stream one and data stream two. if sdti_tdm_ds1 (default low) is set high by the user, the GS2962 does not insert smpte 352m packets into data stream one. similarly, smpte 352m packets are inserted in data stream two only if sdti_tdm_ds2 is set low. this allows the user to individually disable smpte 352m packets where the data stream is carrying an hd-sdti or tdm signal, which must not have smpte 352m packets embedded. note: the user must ensure that there is sufficient space in the horizontal blanking interval for the insertion of the smpte 352m packets. if the first_avail_position bit in the host interface registers is set high (by default), the smpte 352m packets are inserted in the first available position following any existing ancillary data. if the first_avail_position csr bit is set low, then the packets are inserted immediately after the eav/crc1. if there are pre-existing 352m packets, they will be overwritten if the first_avail_position csr bit is high. if the first_avail_position csr bit is low, the pre-existing 352m packet will be overwritten only if it is contiguous to the eav/crc1 sequence. 4.8.9 line based crc generation and insertion (hd/3g) when operating in hd mode (rate_sel0 pin = low, rate_sel1 pin = low), the GS2962 generates and inserts line based crc words into both the y and c channels of the data stream. when operating in 3g (rate_sel0 pin = low, rate_sel1 pin = high) level a mode, the GS2962 generates and inserts line based crc words into both data stream one and data stream two. when operating in 3g (rate_sel0 pin = low, rate_sel1 pin = high) level b mode, the GS2962 generates and inserts line based crc words into both y and c channels of both link a and link b. the line based crc insertion only takes place if the ioproc_en/dis pin is high and smpte_bypass is high. in addition to this, the GS2962 requires the crc_ins bit to be set low in the ioproc register. 4.8.10 edh generation and insertion when operating in sd mode, the GS2962 generates and inserts edh packets into the data stream. the edh packet generation and insertion only takes place if the ioproc_en/dis pin is high, smpte_bypass pin is high, the rate_sel0 pin is high and the edh_crc_ins bit is set low in the ioproc register. calculation of both full field (ff) and active picture (ap) crcs is carried out by the device.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 56 of 82 edh error flags edh, eda, idh, ida and ues for ancillary data, full field and active picture are also inserted. ? when the edh_crc_update bit of the host interface is set low, these flags are sourced from the anc_edh_flag, ff_edh_flag and ap_edh_flag registers of the device, where they are programmed by the application layer ? when the edh_crc_update bit of the host interface is set high, incoming edh flags are preserved and inserted in the outgoing edh packets. in this mode the anc_edh_flag, ff_edh_flag and ap_edh_flag registers contain the incoming edh flags, and will be read only the GS2962 generates all of the required edh packet data including all ancillary data preambles: did, dbn, dc, reserved code words and checksum. the prepared edh packet is inserted at the appropriate line of the video stream (in accordance with rp165). the start pixel position of the inserted packet is based on the sav position of that line, such that the last byte of the edh packet (the checksum) is placed in the sample immediately preceding the start of the sav trs word. note 1: when the edh_crc_update bit of the host interface is set low, it is the responsibility of the application interface to ensure that the edh flag registers are updated regularly (once per field). note 2: it is also the responsibility of the application interface to ensure that there is sufficient space in the horizontal blanking interval for the edh packet to be inserted. 4.8.11 smpte 372m conversion when the ioproc_en/dis pin is high and the conv_372 bit in the ioproc register is low, the GS2962 converts smpte 425m level a mapping 1 (1080p 4:2:2) to level b smpte 372m dual link prior to serialization. 4.8.12 processing feature disable the GS2962 contains an ioproc register. this register contains one bit for each processing feature, allowing the user to enable/disable each process individually. by default (at power up or after system reset), all of the ioproc register bits are low, except for the smpte 372m conversion. to disable an individual processing feature, the application interface must set the corresponding bit high in the ioproc register. to enable these features, the ioproc_en/dis pin must be high, and the individual feature must be enabled by setting bits low in the ioproc register of the host interface. the i/o processing functions supported by the GS2962 are shown in table 4-7 below.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 57 of 82 4.9 serial digital output the GS2962 has a single, low-impedance current mode differential output driver, capable of driving at least 800mv into a 75 single-ended load. the output signal amplitude, or swing, will be user-configurable using an external resistor on the rset pin. the serial digital output data rate supports smpte 424m, smpte 292 and smpte 259m-c operation. this is summarized in table 4-7 : the sdo and sdo pins of the device provide the serial digital output. compliance with all requirements defined in section 4.9.1 through section 4.9.4 is guaranteed when measured across a 75 terminated load at the output of 1m of belden 1694a cable, including the effects of the gennum recommended orl matching network, bnc and coaxial cable connection, except where otherwise stated. figure 4-20 illustrates this requirement, which is in accordance with the measurement methodology defined in smpte 424m, smpte 292 and smpte 259m. table 4-7: ioproc register bits i/o processing feature ioproc register bit tr s insertion tr s _in s (000h bit 0) y an d c line num b er insertion lnum_in s (000h bit 1) y an d c line b ase d c r c insertion c r c _in s (000h bit 2) an c illary d ata c he c ksum c orre c tion an c _ cs um_in s (000h bit 3) edh c r c error c al c ulation an d insertion edh_ c r c _in s (000h bit 4) ille g al wor d re-mappin g ille g al_word_remap (000h bit 5) s mpte 352m pa c ket insertion s mpte_352m_in s (000h bit 6 ) s mpte 372m c onversion c onv_372 (000h bit 9) an c illary d ata insertion an c _in s (000h bit 11) table 4-7: serial digital output - serial output data rate parameter symbol conditions min ty p max units s erial output data rate br s do s mpte 424m si g nal ? 2.97, 2.97/1.001 ? gb /s s mpte 292 si g nal ? 1.485, 1.485/1.001 ? gb /s s mpte 259m- c si g nal ? 270 ? m b /s
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 58 of 82 fi g ure 4-20: orl mat c hin g network, bn c an d c oaxial c a b le c onne c tion 4.9.1 output signal interface levels the serial digital output signals (sdo and sdo pins), of the device meet the amplitude requirements as defined in smpte 424m for an unbalanced generator (single-ended). the signal amplitude is controlled to better than +/-7% of the nominal level defined in smpte 424m, when an external 750 1% resistor is connected between the rset pin of the device and vcc. the output signal amplitude can be reduced to less than 1/10th of the nominal amplitude, defined above, by increasing the value of the resistor connected between the rset pin of the device and vcc. these requirements are met across all ambient temperature and power supply operating conditions described in the electrical characteristics on page 15 . the output amplitude of the GS2962 can be adjusted by changing the value of the rset resistor as shown in table 4-8 . for a 800mvp-p output a value of 750 is required. a 1% smt resistor should be used. the rset resistor is part of the high speed output circuit of the GS2962. the resistor should be placed as close as possible to the rset pin. in addition, an anti-pad should be used underneath the resistor. 4.9.2 overshoot/undershoot the serial digital output signal overshoot and undershoot is controlled to be less that 7% of the output signal amplitude, when operating as an unbalanced generator (single-ended). this requirement is met for nominal signal amplitudes as defined by smpte 292. dut GS2962 orl matching network bnc 1m belden 1694a 75 coaxial cable bnc 75 resistive load measuring device table 4-8: r set resistor value vs. output swing r set resistor values ( ) output swing (mv p-p ) 995 6 08 824 734 750 800 6 80 884
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 59 of 82 this requirement is met regardless of the output slew rate setting of the device. this requirement is met across all ambient temperature and power supply operating conditions described in the electrical characteristics on page 15 . this requirement is summarized in table 4-9 : 4.9.3 slew rate selection the GS2962 supports two user-selectable output slew rates. control of the slew rate is determined by the setting of the rate_sel0 input pin. when this pin is set high, the output slew rate matches the requirements as defined by the smpte 259m-c standard. when this pin is set low, the output slew rate is better than the requirements as defined by the smpte 424m standard. these requirements is met across all ambient temperature and power supply operating conditions described in the electrical characteristics on page 15 . this requirement is summarized in table 4-10 : 4.9.4 serial digital output mute when the sdo_en/dis pin is low, the serial digital output signals of the device become high-impedance, reducing system power. the serial digital output is also placed in the high-impedance state when the locked pin is low, or when the standby pin is high. 4.10 serial clock pll an internal vco provides the transmission clock rates for the GS2962. the power supply to the vco is provided to the vco_vdd/vco_gnd pins of the device. this vco is locked to the input pclk via an on-chip pll and charge pump. table 4-9: serial digital output - overshoot/undershoot parameter symbol conditions min ty p max units s erial output overshoot /un d ershoot ??? 07% table 4-10: serial digital output - rise/fall time parameter symbol conditions min ty p max units s erial output rise/fall time 20% ~ 80% s do tr s mpte 292/424m si g nal ?? 135 ps s mpte 259m- c si g nal 400 ? 800 ps
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 60 of 82 internal division ratios for the pclk are determined by the setting of the rate_sel0 pin, the rate_sel1 pin and the 20bit/10bit pin as shown in table 4-11 : as well as generating the serial digital output clock signals, the pll is also responsible for generating all internal clock signals required by the device. 4.10.1 pll bandwidth table 4-12 shows the GS2962 pll loop bandwi dth variations. pll bandwidth is a function of the external loop filter resistor and the charge pump current. we recommend using a 200 loop filter resistor, however, this value can be varied from 100 to 380 , depending on application. values other than 200 are not guaranteed. as the resistor is changed, the bandwidth will scale proportionately (for example, a change from a 200 to 300 resistor will cause a 50% increase in bandwidth). the charge pump current is preset to 100 a and should not be changed. the external loop filter capacitor does not affect the pll loop bandwidth. the external loop filter capacitor affects pll loop settling time, phase marg in and noise. it is selectable from 1 f to 33 f. however, it should be kept at 10 f for optimal performance. a smaller capacitor results in shorter lock time but less stability. a larger capacitor results in longer lock time but more stability. narrower loop bandwidths require a larger capacitor to be stable. in other words, a small loop filter resistor requires a larger loop capacitor. table 4-11: pclk and serial digital clock rates external pin setting supplied pclk rate serial digital output rate rate_sel0 rate_sel1 20bit/10bit low hi g hhi g h 148.5 or 148.5/1.001mhz 2.97 or 2.97/1.001 gb /s low hi g h low 148.5 or 148.5/1.001mhz (ddr) 2.97 or 2.97/1.001 gb /s low low hi g h 74.25 or 74.25/1.001mhz 1.485 or 1.485/1.001 gb /s low low low 148.5 or 148.5/1.001mhz 1.485 or 1.485/1.001 gb /s hi g hx hi g h 13.5mhz 270m b /s hi g h low low 27mhz 270m b /s table 4-12: GS2962 pll bandwidth mode pclk frequency (mhz) filter resistor ( ) charge pump current ( a) bandwidth (khz) s d 13.50 200 100 4.78 s d 27.00 200 100 9.57
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 61 of 82 4.10.2 lock detect the lock detect block controls the serial digital output signal and indicates to the application layer the lock status of the device. the locked output pin is provided to indicate the device operating status. the locked output signal is set high by the lock detect block under the following conditions (see table 4-13 ): any other combination of signal states not included in the above table results in the locked pin being low. note: when the locked pin is low, the serial digital output is in the muted state. 4.11 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the application layer to access additional status information through configuration registers in the GS2962. the gspi comprises a serial data input signal (sdin), serial data output signal (sdout), an active low chip select (cs) and a burst clock (sclk). because these pins can be shared with the jtag interface port for compatibility with the gs1582, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when jtag/host is high, the jtag interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pin is a non-clocked loop-through of sdin, and may be connected to the sdin of another device, allowing multiple devices to be connected to the gspi chain. the interface is illustrated in figure 4-21 below. hd 74.25 200 100 2 6 .32 hd 148.50 200 100 52. 6 3 3 g 148.50 200 100 52. 6 3 table 4-12: GS2962 pll bandwidth (continued) mode pclk frequency (mhz) filter resistor ( ) charge pump current ( a) bandwidth (khz) table 4-13: GS2962 lock detect indication reset pll lock smpte_bypass dvb_asi rate_sel0 hi g hhi g hhi g hlowx hi g hhi g hlow hi g hhi g h hi g hhi g hlow lowx
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 62 of 82 fi g ure 4-21: gs pi appli c ation interfa c e c onne c tion all read or write access to the GS2962 is initiated and terminated by the application host processor. each access always begins with a command/address word followed by a data read to or written from the GS2962. 4.11.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. figure 4-22 shows the command word format and bit configurations. command words are clocked into the GS2962 on the rising edge of the serial clock sclk, which operates in a burst fashion. when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be written into the address specified in the command word, and subsequent data words will be written into incremental addresses from the previous data word. this facilitates multiple address writes without sending a command word for each data word. note: all registers can be written to through single address access or through the auto-increment feature. however, the lsb of the video registers cannot be read through single address read-back. single address read-back will return a zero value for the lsb. if auto-increment is used to read back the values from at least two registers, the lsb value read will always be correct. therefore, for register read-back, it is recommended that auto-increment be used and that at least two registers be read back at a time. fi g ure 4-22: c omman d wor d format application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 GS2962 GS2962 cs a0 a1 a2 a3 a4 a5 a 6 a7 a8 a9 a11 m s b l s b a10 r/w r s vr s v autoin c
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 63 of 82 4.11.2 data read or write access serial data is transmitted or received msb first synchronous with the rising edge of the serial clock, sclk. the chip select (cs ) signal must be active low a minimum of 1.5ns (t0 in figure 4-24 ) before the first clock edge to ensure proper operation. during a read sequence (command word r/w bit set high), a wait state of 148ns (4 x 1/fpclk, t5 in figure 4-24 ) is required between writing the command word and reading the following data word. the read bits are clocked out on the negative edges of sclk. note 1: where several devices are connected to the gspi chain, only one cs _tms may be asserted during a read sequence. during a write sequence (command word r/w bit set low), a wait state of 37ns (1 x 1/fpclk, t4 in figure 4-24 ) is required between the command word and the following data word. this wait state must also be maintained between successive command word/data word write sequences. when auto-increment mode is selected (autoinc = 1), the wait state must be maintained between successive data words after the initial command word/data word sequence. during the write sequence, all command and following data words input at the sdin pin are output at the sdout pin as is. when several devices are connected to the gspi chain, data can be written simultaneously to all the devices which have cs set low. note 2: if the application interface performs a read or write access after power-up, prior to the application of a valid serial video input signal, the sclk frequency must not exceed 10mhz. fi g ure 4-23: data wor d format d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 m s b l s b
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 64 of 82 4.11.3 gspi timing write and read mode timing for the gspi interface is as shown in the following diagrams: fi g ure 4-24: write mo d e fi g ure 4-25: rea d mo d e fi g ure 4-2 6 : gs pi time delay sc lk_t c k cs _tm s s din_tdi s dout_tdo t 0 t 3 t 1 t 2 r/w t 8 t 4 t 7 r/w auto _in c auto _in c a11 a11 a10 a10 a9 a9 a8 a8 a7 a7 a 6 a 6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 d15 d15 d14 d14 d13 d13 d12 d12 d11 d11 d10 d10 d9 d9 d8 d8 d7 d7 d 6 d 6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 r s v r s v r s v r s v sc lk_t c k cs _tm s s din_tdi s dout_tdo r/w r/w auto _in c auto _in c a11 a11 a10 a10 a9 a9 a8 a8 a7 a7 a 6 a 6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 r s v r s v r s v r s v t 6 t 5 sdin_tdi data_0 sdin_tdi to sdout_tdo combinational path for daisy chain connection of multiple GS2962 devices. sdout_tdo data_0 t delay ta b le 4-14: gs pi time delay parameter symbol conditions min ty p max units delay time t delay 50% levels; 1.8v operation ?? 10.5 ns delay time t delay 50% levels; 3.3v operation ?? 8.7
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 65 of 82 table 4-15: gspi ac characteristics parameter symbol conditions min ty p max units cs low b efore sc lk risin g e dg e t 0 50% levels; 3.3v or 1.8v operation 1.5 ?? ns sc lk perio d t 1 12.5 ?? ns sc lk d uty c y c le t 2 40 50 6 0% input d ata setup time t 3 1.5 ?? ns time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? write c y c le. t 4 p c lk (mhz) ns ?? ns unlo c ke d 445 13.5 74.2 27.0 37.1 74.25 13.5 148.5 6 .7 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? rea d c y c le. t 5 p c lk (mhz) ns ?? ns unlo c ke d 1187 13.5 297 27.0 148.5 74.25 53.9 148.5 27 output hol d time (15pf loa d )t 6 1.5 ?? ns cs hi g h after last sc lk fallin g e dg e t 7 p c lk (mhz) ns ?? ns unlo c ke d 445 74.2 74.2 37.10 37.1 74.25 13.5 148.5 6 .7 input d ata hol d time t 8 1.5 ?? ns note: if the appli c ation interfa c e performs a rea d or write a cc ess after power-up, prior to the appli c ation of a vali d serial vi d eo input si g nal, the sc lk frequen c y must not ex c ee d 10mhz.
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 66 of 82 4.12 host interface register maps table 4-16: configuration and status registers address register name bit name bit description r/w default 000h iopro c r s vd 15 reserve d .r0 delay_line_enable 14 hi g h - ena b les the d elay line d elay. r/w 0 r s vd 13 reserve d .r0 edh_ c r c _update 12 hi g h - preserve in c omin g edh fla g s an d insert into out g oin g edh pa c kets. low - em b e d fla g s from 003 in edh pa c ket. r/w 0 an c _in s 11 hi g h - d isa b le an c illary d ata insertion. low - ena b le an c illary d ata insertion. r0 r s vd 10 reserve d .r/w0 c onv_372 9 hi g h - d isa b le level a-b c onversion. low - ena b le level a-b c onversion. r/w 1 h_ c onfi g 8 c hooses h c onfi g uration; low - a c tive pi c ture timin g hi g h - s mpte h timin g r/w 0 r s vd 7 reserve d .r/w0 s mpte_352m_in s6 hi g h - d isa b les insertion of s mpte 352m pa c kets. r/w 0 ille g al_word_remap 5 hi g h - d isa b les ille g al wor d remappin g . r/w 0 edh_ c r c _in s 4hi g h - d isa b les edh c r c error c orre c tion an d insertion. r/w 0 an c _ cs um_in s 3hi g h - d isa b les insertion of an c illary d ata c he c ksums. r/w 0 c r c _in s 2hi g h - d isa b les insertion of hd/3 g c r c wor d s. r/w 0 lnum_in s 1hi g h - d isa b les insertion of hd/3 g line num b ers. r/w 0 tr s _in s 0hi g h - d isa b les insertion of tr s wor d s. r/w 0
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 67 of 82 001h error_ s tat r s vd 15-7 reserve d .r0 tr s _perr 6 tr s prote c tion error. low - no errors in tr s . hi g h - errors in tr s . r0 y1_edh_ cs _err 5 s ame as cs _err b ut only up d ates its state when pa c ket b ein g inspe c te d is an edh pa c ket. r0 y1_ cs _err 4 hi g h in d i c ates that a c he c ksum error is d ete c te d . it is up d ate d every time a cs wor d is present on the output. note: this b it will not b e set for cs um values in the prote c te d ran g es (from 000h to 003h an d from 3f c h to 3ffh). r0 format_err 3 hi g h in d i c ates stan d ar d is not re c o g nize d for 8 6 1d c onversion. r0 timin g _err 2 hi g h in d i c ates that the ra s ter measurements d o not line up with the extra c te d 352m pa c ket information. r0 no_352m_err 1 hi g h in d i c ates no 352m pa c ket em b e dd e d in in c omin g vi d eo. r0 lo c k_err 0 hi g h in d i c ates pll lo c k error in d i c ation. r0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 68 of 82 002h edh_fla g _ext r s vd 15 reserve d .r0 an c _ue s _ext 14 an c illary d ata - unknown error status fla g . r0 an c _ida_ext 13 an c illary d ata - internal error d ete c te d alrea d y fla g . r0 an c _idh_ext 12 an c illary d ata - internal error d ete c te d here fla g . r0 an c _eda_ext 11 an c illary d ata - error d ete c te d alrea d y fla g . r0 an c _edh_ext 10 an c illary d ata - error d ete c te d here fla g . r0 ff_ue s _ext 9 edh full fiel d - unknown error status fla g . r0 ff_ida_ext 8 edh full fiel d - internal error d ete c te d alrea d y fla g . r0 ff_idh_ext 7 edh full fiel d - internal error d ete c te d here fla g . r0 ff_eda_ext 6 edh full fiel d - error d ete c te d alrea d y fla g . r0 ff_edh_ext 5 edh full fiel d - error d ete c te d here fla g . r0 ap_ue s _ext 4 edh a c tive pi c ture - unknown error status fla g . r0 ap_ida_ext 3 edh a c tive pi c ture - internal error d ete c te d alrea d y fla g . r0 ap_idh_ext 2 edh a c tive pi c ture - internal error d ete c te d here fla g . r0 ap_eda_ext 1 edh a c tive pi c ture - error d ete c te d alrea d y fla g . r0 ap_edh_ext 0 edh a c tive pi c ture - error d ete c te d here fla g . r0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 69 of 82 003h edh_fla g _p g mr s vd 15 reserve d .r0 an c _ue s _p g m14an c illary d ata - unknown error status fla g . r0 an c _ida_p g m13an c illary d ata - internal error d ete c te d alrea d y fla g . r/w 0 an c _idh_p g m12an c illary d ata - internal error d ete c te d here fla g . r/w 0 an c _eda_p g m11an c illary d ata - error d ete c te d alrea d y fla g . r/w 0 an c _edh_p g m10an c illary d ata - error d ete c te d here fla g . r/w 0 ff_ue s _p g m 9 edh full fiel d - unknown error status fla g . r/w 0 ff_ida_p g m 8 edh full fiel d - internal error d ete c te d alrea d y fla g . r/w 0 ff_idh_p g m 7 edh full fiel d - internal error d ete c te d here fla g . r/w 0 ff_eda_p g m 6 edh full fiel d - error d ete c te d alrea d y fla g . r/w 0 ff_edh_p g m 5 edh full fiel d - error d ete c te d here fla g . r/w 0 ap_ue s _p g m 4 edh a c tive pi c ture - unknown error status fla g . r/w 0 ap_ida_p g m 3 edh a c tive pi c ture - internal error d ete c te d alrea d y fla g . r/w 0 ap_idh_p g m 2 edh a c tive pi c ture - internal error d ete c te d here fla g . r/w 0 ap_eda_p g m 1 edh a c tive pi c ture - error d ete c te d alrea d y fla g . r/w 0 ap_edh_p g m 0 edh a c tive pi c ture - error d ete c te d here fla g . r/w 0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 70 of 82 004h data_format r s vd 15-10 reserve d .r0 vd_ s td 9-5 dete c te d vi d eo stan d ar d .r0 int_pro g b4hi g h - interla c e d si g nal low - pro g ressive si g nal r0 c onv_372_lo c ked 3 c onvert 372 lo c k in d i c ation. a c tive hi g h. r0 s td_lo c k2 s tan d ar d lo c k in d i c ation. a c tive hi g h. r0 v_lo c k 1 verti c al lo c k in d i c ation. a c tive hi g h. r0 h_lo c k 0 horizontal lo c k in d i c ation. a c tive hi g h. r0 005h r s vd r s vd 15-0 reserve d .r0 00 6 hv s d_for c er s vd 15- 6 reserve d .r0 v s d_for c e 5 use the cs r re g ister s td value rather than the flywheels s td value. a c tive hi g h. r/w 0 vid_ s td_for c e 4-0 for c e vid s td cs r. r/w 0 007h edh_ s tatu s r s vd 15-2 reserve d .r0 ff_ c r c _v 1 full fiel d extra c te d v b it. r 0 ap_ c r c _v 0 a c tive pi c ture extra c te d v b it. r 0 008h fir s t_avail_ po s ition r s vd 15-1 reserve d .r0 fir s t_avail_po s ition 0 hi g h - 352m insertion o cc urs on first availa b le an c spa c e. low - insert 352m pa c kets ri g ht after eav/ c r c 1. r/w 1 009h r s vd re s erved_7 15-0 ? r0 00ah video_format _352_out_ word_1 video_format_out_d s 1_ 2 15-8 s mpte 352m d s 1 em b e dd e d pa c ket - b yte 2. r/w 0 video_format_out_d s 1_ 1 7-0 s mpte 352m d s 1 em b e dd e d pa c ket - b yte 1. r/w 0 00bh video_format _352_out_ word_2 video_format_out_d s 1_ 4 15-8 s mpte 352m d s 1 em b e dd e d pa c ket - b yte 4. r/w 0 video_format_out_d s 1_ 3 7-0 s mpte 352m d s 1 em b e dd e d pa c ket - b yte 3. r/w 0 00 c h video_format _352_out_ word_3 video_format_out_d s 2_ 2 15-8 s mpte 352m d s 2 em b e dd e d pa c ket - b yte 2. r/w 0 video_format_out_d s 2_ 1 7-0 s mpte 352m d s 2 em b e dd e d pa c ket - b yte 1. r/w 0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 71 of 82 00dh video_format _352_out_ word_4 video_format_out_d s 2_ 4 15-8 s mpte 352m d s 2 em b e dd e d pa c ket - b yte 4. r/w 0 video_format_out_d s 2_ 3 7-0 s mpte 352m d s 2 em b e dd e d pa c ket - b yte 3. r/w 0 00eh video_format _352_in_ word_1 video_format_in_d s 1_2 15-8 s mpte 352m d s 1 extra c te d pa c ket - b yte 2. r0 video_format_in_d s 1_1 7-0 s mpte 352m d s 1 extra c te d pa c ket - b yte 1. r0 00fh video_format _352_in_ word_2 video_format_in_d s 1_4 15-8 s mpte 352m d s 1 extra c te d pa c ket - b yte 4. r0 video_format_in_d s 1_3 7-0 s mpte 352m d s 1 extra c te d pa c ket - b yte 3. r0 010h video_format _352_in_ word_3 video_format_in_d s 2_2 15-8 s mpte 352m d s 2 extra c te d pa c ket - b yte 2. r0 video_format_in_d s 2_1 7-0 s mpte 352m d s 2 extra c te d pa c ket - b yte 1. r0 011h video_format _352_in_ word_4 video_format_in_d s 2_4 15-8 s mpte 352m d s 2 extra c te d pa c ket - b yte 4. r0 video_format_in_d s 2_3 7-0 s mpte 352m d s 2 extra c te d pa c ket - b yte 3. r0 012h ra s ter_ s tru c _ 1 r s vd 15-11 reserve d .r0 line s _per_frame 10-0 total lines per frame. r 0 013h ra s ter_ s tru c _ 2 r s vd 15-14 reserve d .r0 word s _per_line 13-0 total wor d s per line. r 0 014h ra s ter_ s tru c _ 3 r s vd 15-13 reserve d .r0 a c tive_word s _per _line 12-0 wor d s per a c tive line. r 0 015h ra s ter_ s tru c _ 4 r s vd 15-11 reserve d .r0 a c tive_line s _per_field 10-0 a c tive lines per frame. r 0 01 6 h - 023h r s vd r s vd ? reserve d .r0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 72 of 82 024h fir s t_line_ number_ s tatu s r s vd 15-2 reserve d .r0 pa c ket_mi ss ed 1 an c d ata pa c ket c oul d not b e inserte d in its entirety. hi g h - an c pa c ket c annot b e inserte d in it ? s entirety. r0 rw_ c onfli c t0 s ame ram a dd ress was rea d an d written to at the same time. hi g h - one of the a dd resses from 040h to 13fh was rea d an d written to at the same time. r0 025h fir s t_line_ number r s vd 15-12 reserve d .r0 an c _in s _mode 11 an c d ata insertion mo d e. hi g h - c on c atenate low - s eparate r/w 0 fir s t_line_number 10-0 first line num b er to insert an c pa c ket on. r/w 0 02 6 hfir s t_line_ number_of_ word s fir s t_line_number_an c _t ype 15 an c re g ion to insert pa c ket in hi g h - van c , low - han c . r/w 0 fir s t_line_number _ s tream_type 14 s tream to insert pa c ket in hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d .r0 fir s t_line_number _of_word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in first line. r/w 0 027h s e c ond_line_ number r s vd 15-11 reserve d .r0 s e c ond_line_number 10-0 s e c on d line num b er to insert an c pa c ket on in s eparate line mo d e. r/w 0 028h s e c ond_line_ number_of_ word s s e c ond_line_number _an c _type 15 an c re g ion to insert pa c ket in hi g h - van c , low - han c . r/w 0 s e c ond_line_number _ s tream_type 14 s tream to insert pa c ket in hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d .r0 s e c ond_line_number _of_word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in se c on d line. r/w 0 029h third_line_ number r s vd 15-11 reserve d .r0 third_line_number 10-0 thir d line num b er to insert an c pa c ket on in s eparate line mo d e. r/w 0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 73 of 82 02ah third_line_ number_of_ word s third_line_number _an c _type 15 an c re g ion to insert pa c ket in. hi g h - van c , low - han c . r/w 0 third_line_number _ s tream_type 14 s tream to insert pa c ket in. hi g h - c stream, low - y stream. r/w 0 r s vd 13-10 reserve d .r 0 third_line_number _of_word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in thir d line. r/w 0 02bh fourth_line_ number r s vd 15-11 reserve d .r0 fourth_line_number 10-0 fourth line num b er to insert an c pa c ket on in s eperate line mo d e. r/w 0 02 c h fourth_line_ number_of_ word s fourth_line_number _an c _type 15 an c re g ion to insert pa c ket in hi g h - van c , low - han c . r/w 0 fourth_line_number _ s tream_type 14 s tream to insert pa c ket in 1- c stream, 0-y stream. r/w 0 r s vd 13-10 reserve d .r0 fourth_line_number _of_word s 9-0 total num b er of wor d s in an c pa c ket to b e inserte d in fourth line. r/w 0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 74 of 82 02dh s tream_type_ 1 r s vd 15-5 reserve d .r0 edh_line_ c he c k_en 4 hi g h - an c b lo c k will not insert d ata into the edh re g ion of the han c spa c e. low - an c b lo c k will insert d ata into the edh re g ion. r/w 1 s tream_type1_line_4 3 hi g h - d ata for the fourth line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 s tream_type1_line_3 2 hi g h - d ata for the thir d line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 s tream_type1_line_2 1 hi g h - d ata for the se c on d line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 s tream_type1_line_1 0 hi g h - d ata for the first line in separate mo d e is inserte d into data s tream two. low - data s tream one. parameter only appli c a b le for 3 g . r/w 0 02eh - 03fh r s vd r s vd 15-0 reserve d .r0 040h - 07fh an c _pa c ket _bank_1 an c _pa c ket_bank 15-0 first b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.7 an c data insertion . ?? 080h - 0bfh an c _pa c ket _bank_2 an c _pa c ket_bank 15-0 first b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.7 an c data insertion . ?? 0 c 0h - 0ffh an c _pa c ket _bank_3 an c _pa c ket_bank 15-0 first b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.7 an c data insertion . ?? table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 75 of 82 100h - 13fh an c _pa c ket _bank_4 an c _pa c ket_bank 15-0 first b ank of user- d efine d 8- b it an c illary d ata. bit 15 - 8: 2n d b yte (m s b to l s b) bit 7 - 0: 1st b yte (m s b to l s b) s ee 4.7 an c data insertion . ?? 140h - 209h r s vd r s vd ? reserve d .r0 20ah s dti_tdm r s vd 15-8 reserve d .r0 s dti_tdm_d s 27hi g h in d i c ates an s dti type si g nal on input for data s tream two. r/w 0 s dti_tdm_d s 1 6 hi g h in d i c ates an s dti type si g nal on input for data s tream one. r/w 0 r s vd 5-0 reserve d .r0 20bh - 20 c h r s vd r s vd 15-0 reserve d .r0 20dh levelb_ indi c ation r s vd 15-9 reserve d .r0 level_b 8 hi g h in d i c ates level b d ete c te d . only relevant for 3 g input streams. r0 r s vd 7-0 reserve d .r0 20eh drive_ s tren g th r s vd 15-4 reserve d .r/w0 lo c ked_d s 3-2 drive stren g th value for lo c ked pin. 00: 4ma; 01: 6 ma; 10: 8ma(1.8v), 10ma(3.3v); 11: 10ma(1.8v), 12ma(3.3v) r/w 0 s dout_tdo_d s 1-0 drive stren g th value for s dout_tdo pin. 00: 4ma; 01: 6 ma; 10: 8ma(1.8v), 10ma(3.3v); 11: 10ma(1.8v), 12ma(3.3v) r/w 2 20fh r s vd r s vd 15-0 reserve d .r/w0 210h drive_ s tren g th2 tdo_d s 15-14 drive stren g th value for tdo pin. 00: 4ma; 01: 6 ma; 10: 8ma(1.8v), 10ma(3.3v); 11: 10ma(1.8v), 12ma(3.3v) r/w 0 r s vd 13-0 reserve d .r/w0 211h - 232h r s vd r s vd 15-0 reserve d .r0 table 4-16: configuration and status registers (continued) address register name bit name bit description r/w default
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 76 of 82 4.13 jtag id codeword the platform id for the 297x family is 0fh. the part number field of the jtag id codeword for the GS2962 is set to 0f00h. 4.14 jtag test operation when the jtag/host pin is high, the gspi host interface port is configured for jtag test operation. in this mode the sclk, sdin, sdout and cs become tck, tdi, tdo and tms. in addition, the trst pin becomes active. boundary scan testing using the jtag interface is enabled in this mode. when the jtag/host pin is low, the dedicated jtag interface is used. in this mode the tck, tdi, tdo and tms pins are active. this is the recommended mode for new designs. 4.15 device power-up because the GS2962 is designed to operate in a multi-voltage environment, any power-up sequence is allowed. the charge pump, phase detector, core logic, serial digital output and i/o buffers can all be powered up in any order. 4.16 device reset note: at power-up, the device must be reset to operate correctly. in order to initialize all internal operating conditions to their default states, hold the reset signal low for a minimum of t reset = 1ms after all power supplies are stable. there are no requirements for power supply sequencing. when held in reset, all device outputs will be driven to a high-impedance state. fi g ure 4-27: reset pulse s upply volta g e re s et 95% of nominal level nominal level reset reset t reset t reset
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 77 of 82 5. application reference design 5.1 typical application circuit sdo sdo tdo tck tms tdi pclk cd_vdd gnd_a gnd_a +1.2v_a gnd_a +1.2v io_vdd gnd_a +1.2v_a gnd_a cd_vdd gnd_a gnd_a +3.3v_a return loss compensation network sdi output video data, clock & timing input (subject to change) notes: 1. dnp (do not populate). 2. the value of the series resistors on video data, clock, and timing connections should be determined by board signal integrity test. (see section 4.1.1) 3. for analog power and ground isolation refer to pcb layout guide. 4. for critital 3g signal layout refer to pcb layout guide. 5. for impedance controlled signals refer to pcb layout guide. close to GS2962. close to GS2962. sdo sdo pclk vco_vdd b7 vbg a8 vco_gnd b8 tdi e7 rsv a9 tim_861 g3 pclk b4 io_vdd g1 din 18 a2 din 19 b3 lf a7 a_vdd a10 b10 din 17 a1 core_vdd k8 h6 detect_trs f3 core_gnd e6 a_gnd b9 din 16 b2 core_vdd g10 pll_vdd a6 pll_vdd b6 d5 standby d3 k7 j7 j6 din 14 c2 din 15 b1 core_gnd c5 core_gnd b5 d6 d7 dvb_asi g5 locked h4 h5 k6 din 12 c3 din 13 c1 d8 tms e8 tdo f8 rate_sel0 e3 core_gnd e5 core_vdd e1 k5 io_vdd h10 din 10 d2 din 11 d1 rsv f4 tck j8 core_gnd g9 20bit/10bit g4 core_gnd f5 core_vdd a5 j5 io_gnd g2 din 8 f2 din 9 f1 f7 cd_gnd f9 cd_gnd e9 ioproc_en/dis g7 smpte_bypass g6 reset g8 j4 anc_blank h3 din 6 h2 din 7 h1 cd_gnd d9 core_gnd e2 h7 cs_tms k9 sclk_tck j10 sdout_tdo j9 k4 h/hsync a4 din 4 j2 din 5 j1 core_gnd f6 pll_gnd c8 pll_gnd c7 pll_gnd c6 sdo_en/dis d4 sdin_tdi k10 v/vsync c4 io_gnd h9 din 2 k2 din 3 k1 rset f10 cd_vdd e10 sdo c10 sdo d10 cd_gnd c9 jtag/host h8 f/de a3 rate_sel1 e4 din 0 k3 din 1 j3 GS2962-ibe3 10u 200r 75r 1u 1 3 2 5n6 75r 1 3 2 5n6 10n 4u7 dnp 105r 4u7 10n dnp 75r 10n 10u 100p 75r 750r 10n din[19:0] +1.2v_a 0r 10n +1.2v 10n 10n 10n 10n io_vdd +1.2v 10n power filtering 10n 10n gnd_a +3.3v_a 0r 10n 10n gnd_a 1u 1u 1u 1u power decoupling place close to GS2962 1u 1u io_vdd 1u +3.3v cd_vdd 0r 10n 10n gnd_a tim_861 detect_trs standby dvb_asi rate_sel0 20bit/10bit ioproc_en/dis smpte_bypass anc_blank sdo_en/dis rate_sel1 locked reset cs_tms sclk_tck sdout_tdo sdin_tdi jtag/host h/hsync v/vsync f/de cd_vdd 0r gnd_a gnd_a a_gnd rsv rsv rsv rsv rsv rsv rsv rsv rsv core_gnd core_gnd core_gnd core_gnd core_gnd rsv rsv
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 78 of 82 6. references & relevant standards s mpte 125m c omponent vi d eo si g nal 4:2:2 ? b it parallel interfa c e s mpte 259m 10- b it 4:2:2 c omponent an d 4fs c c omposite di g ital s i g nals - s erial di g ital interfa c e s mpte 2 6 0m 1125 / 6 0 hi g h d efinition pro d u c tion system ? d i g ital representation an d b it parallel interfa c e s mpte 2 6 7m bit parallel d i g ital interfa c e ? c omponent vi d eo si g nal 4:2:2 1 6 x 9 aspe c t ratio s mpte 272m formattin g ae s /ebu au d io an d auxiliary data into di g ital vi d eo an c illary data s pa c e s mpte 274m 1920 x 1080 s c annin g analo g an d parallel d i g ital interfa c es for multiple pi c ture rates s mpte 291m an c illary data pa c ket an d s pa c e formattin g s mpte 292 bit- s erial di g ital interfa c e for hi g h-definition television s ystems s mpte 293m 720 x 483 a c tive line at 59.94hz pro g ressive s c an pro d u c tion ? d i g ital representation s mpte 29 6 m 1280 x 720 s c annin g , analo g an d d i g ital representation an d analo g interfa c e s mpte 305m s erial data transport interfa c e s mpte 348m hi g h data-rate s erial data transport interfa c e (hd- s dti) s mpte 352m vi d eo payloa d i d entifi c ation for di g ital television interfa c es s mpte 372 dual link 292m interfa c e for 1920 x 1080 pi c ture raster s mpte 424 3 gb /s s i g nal/data s erial interfa c e s mpte 425 3 gb /s s i g nal/data s erial interfa c e - s our c e ima g e format mappin g s mpte rp1 6 5 error dete c tion c he c kwor d s an d s tatus fla g s for use in bit- s erial di g ital interfa c es for television s mpte rp1 6 8 definition of verti c al interval s wit c hin g point for s yn c hronous vi d eo s wit c hin g c ea 8 6 1vi d eo timin g requirements
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 79 of 82 7. package & ordering information 7.1 package dimensions 0.366 (0.366) 1.700
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 80 of 82 7.2 packaging data 7.3 marking diagram table 7-1: packaging data parameter value pa c ka g e type 11mm x 11mm 100- b all lb g a pa c ka g e drawin g referen c e j ede c m0192 (with ex c eptions note d in pa c ka g e dimensions on pa g e 79 ). moisture s ensitivity level 3 j un c tion to c ase thermal resistan c e, j- c 10.4 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 37.1 c /w j un c tion to boar d thermal resistan c e, j- b 2 6 .4 c /w psi, 0.4 c /w p b -free an d roh s c ompliant yes GS2962 xxxxxxe3 yyww pin 1 id xxxxxx - last 6 digits (excluding decimal) of sap batch assembly (fin) as listed on packing slip. e3 - pb-free & green indicator yyww - date code
GS2962 3g/hd/sd-sdi serializer with complete smpte video support data sheet 48005 - 7 october 2010 81 of 82 7.4 solder reflow profiles the GS2962 is available in a pb-free package. it is recommended that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 7-1 . fi g ure 7-1: p b -free s ol d er reflow profile 7.5 ordering information 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max part number package pb-free temperature range gs 29 6 2-ibe3 100- b all b g a yes -20 c to 85 c
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