technical data 15 dual 4-input nand gate high-voltage silicon-gate cmos the iw4012b nand gates provide the system designer with direct emplementation of the nand function. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package- temperature range; 100 na at 18 v and 25 c ? noise margin (over full package temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply iw4012b ordering information iw4012bn plastic IW4012BD soic t a = -55 to 125 c for all packages logic diagram pins 6, 8 = no connection pin 14 =v cc pin 7 = gnd pin assignment nc = no connection function table inputs output abcd y lxxx h xlxx h xxlx h xxxl h hhhh l x = don?t care
iw4012b 16 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4012b 17 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c 25 c 125 c unit v ih minimum high-level input voltage v out =0.5 v or v cc - 0.5 v v out =1.0 v or v cc - 1.0 v v out =1.5 v or v cc - 1.5 v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low -level input voltage v out = v cc - 0.5v v out = v cc - 1.0 v v out = v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in = v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 0.25 0.5 1.0 5.0 0.25 0.5 1.0 5.0 7.5 15 30 150 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma
iw4012b 18 ac electrical characteristics (c l =50pf, r l =200k ? , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c25 c 125 c unit t plh , t phl maximum propagation delay, input a, b,c or d to output y (figure 1) 5.0 10 15 250 120 90 250 120 90 500 240 180 ns t tlh , t thl maximum output transition time, any output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance - 7.5 pf figure 1. switching waveforms expanded logic diagram (1/2 of the device)
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