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  SM8707E/f clock generator with dual plls seiko npc corporation - 1 overview the 8707e/f are dual-pll clock generator ics, using a 27mhz master clock, that generate independent audio clock, video clock, and signal processor clock outputs needed in dvd player/recorder applications. each pll loop filter and crystal oscillator circuit are bu ilt-in and require no external components, resulting in high-precision clocks. the lineup includes devices that support both 44.1/48khz audio sampling frequencies (fs), switchable using a control pin. the sampling frequency can be switched during operation without generating any output spike noise. features supply voltage: 3.0 to 3.6v pll loop filter built-in low current consumption: 35ma typ. crystal oscillator circuit built-in (v dd =3.3v, all outputs with no load) sampling frequency fs: 44.1/48khz 27mhz master clock 16-pin vsop package (pb free) (internal pll reference clock) generated clocks SM8707E sm8707f video system output 27.0000mhz 27.0000mhz audio system output 512fs 768fs signal processor system output 33.8688mhz 16.9344mhz 33.8688mhz low jitter output (1-sigma output load capacitance typical values) SM8707E sm8707f video system output 20ps 20ps audio and signal processor system output 55ps 40ps applications package dimensions dvd players/recorders (unit : mm) dvd car navigation system weight: 0.07g ordering infomation device package SM8707Ev sm8707fv 16pin vsop
SM8707E/f seiko npc corporation - 2 pinout (top view) 1 89 16 vdd1 vdd3 vss1 mo1 mo2(e ver.) nc(f ver.) vdd2 vss2 vss3 xti nc xto so2 ao2 ao1 so1 fsel pin description no. name i/o description 1 vdd1 - supply for digital block 2 vss1 - ground for digital block 3 mo1 o video system output mo2(e ver.) o video system output 4 nc(f ver.) - non connection output (leave pin open circuit) 5 vdd2 - supply for analog block 6 vss2 - ground for analog block 7 xti i crystal oscillator connection or external clock input 8 xto o crystal oscillator connection 9 ao1 o audio system output 10 ao2 o audio system output 11 vss3 - ground for digital block 12 vdd3 - supply for digital block 13 so1 o signal processor system output 14 fsel i sampling frequency select 15 so2 o signal processor system output 16 nc - non connection (leave pin open circuit or connect to vdd)
SM8707E/f seiko npc corporation - 3 block diagram reference divider 0 phase detector 0 loop divider 0 charge pump 0 lpf 0 vco 0 x tal osc reference divider 1 phase detector 1 loop divider 1 charge pump 1 lpf 1 xto xti fse l ao1 ao2 so1 so2 mo1 vco 1 control logic mo2(e ver.) nc (f ver.)
SM8707E/f seiko npc corporation - 4 note: unless otherwise noted, vdd applies to vdd1, vdd2, and vdd3. similarly, vss applies to vss1, vss2, and vss3. specifications absolute maximum ratings parameter symbol rating unit supply voltage range v dd1 , v dd2 , v dd3 -0.3 to +6.5 v supply voltage deviation v dd1 -v dd2 , v dd1 -v dd3 , v dd2 -v dd3 0.1 v input voltage range v in -0.3 to v dd +0.3 v output voltage range v out -0.3 to v dd +0.3 v power dissipation p d 165 mw storage temperature range t stg -55 to +125 ? c recommended operating conditions v ss =v ss1 =v ss2 =v ss3 =0v unless otherwise noted. SM8707E rating parameter symbol condition min typ max unit supply voltage ranges v dd1 ,v dd2 ,v dd3 note 1,2,3 +3.0 - +3.6 v output load capacitance 1 c l1 mo1 output - - 40 pf output load capacitance 2 c l2 mo2 output - - 25 pf output load capacitance 3 c l3 so1,so2,ao1,ao2 outputs - - 15 pf master clock frequency f xtal when using crystal oscillator - 27.0000 - mhz operating temperature range t opr -10 - +75 sm8707f rating parameter symbol condition min typ max unit supply voltage ranges v dd1 ,v dd2 ,v dd3 note 1,2,3 +3.0 - +3.6 v output load capacitance 1 c l1 mo1,so1,so2 outputs - - 25 pf output load capacitance 2 c l2 ao1,ao2 outputs - - 15 pf master clock frequency f xtal when using crystal oscillator - 27.0000 - mhz operating temperature range t opr -40 - +85 note 1. the supply voltage is defined relative to v ss =0v. note 2. the supply voltages applied on vdd1, vdd2 and vdd3 should be derived from a common supply source. note 3. if the supp ly voltages on vdd1, vdd2 and vdd3 are from different sources, they should be applied simultaneously. the sm8707 may be damaged if the supp ly voltage timing is different.
SM8707E/f seiko npc corporation - 5 dc electrical characteristics SM8707E f xtal =27.0000mhz, v dd =3.3v 0.3v, v ss =0v, t a =-10 to +75 q c unless otherwise noted. sm8707f f xtal =27.0000mhz, v dd =3.3v 0.3v, v ss =0v, t a =-40 to +85 q c unless otherwise noted. rating parameter symbol pins condition min typ max unit current consumption i dd vdd v dd =3.3v,t a =25 ,fs=48khz, crystal oscillat or connected, no load on all outputs - 35 45 ma v ih 0.8v dd - - input voltage v il fsel,xti v dd =3.3v - - 0.2v dd v i ih1 v in =v dd - - 1 i il1 fsel *1 v in =0v -100 - - i ih2 v in =v dd - - 40 input current i il2 xti v in =0v -40 - - p a v oh i oh =-2ma v dd -0.4 - - output voltage v ol all outputs excluding xto i ol =2ma - - 0.4 v *1. fsel pin has schmitt-trigger input and built-in pull-up resistor.
SM8707E/f seiko npc corporation - 6 ac electrical characteristics SM8707E f xtal =27.0000mhz, v dd =3.3v0.3v, v ss =0v, t a =-10 to +75 ? c unless otherwise noted. rating parameter symbol pins condition min typ max unit external input clock frequency *1 f xti xti applies to external clock input use only - 27.0000 - mhz mo1 c l =40pf, transition between v ol =0.2v dd and v oh =0.8v dd - 2.0 - mo2 c l =25pf, transition between v ol =0.2v dd and v oh =0.8v dd - 2.0 - output clock rise time *2 t r so1,so2, ao1,ao2 c l =15pf, transition between v ol =0.2v dd and v oh =0.8v dd - 2.0 - ns mo1 c l =40pf, transition between v oh =0.8v dd and v ol =0.2v dd - 2.0 - mo2 c l =25pf, transition between v oh =0.8v dd and v ol =0.2v dd - 2.0 - output clock fall time *2 t f so1,so2, ao1,ao2 c l =15pf, transition between v oh =0.8v dd and v ol =0.2v dd - 2.0 - ns mo1 t a =25 ,c l =40pf,v o =0.5v dd - 20 - mo2 t a =25 ,c l =25pf,v o =0.5v dd - 20 - output clock jitter *3 t jitter (1-sigma) so1,so2, ao1,ao2 t a =25 ,c l =15pf,v o =0.5v dd - 55 - ps mo1 t a =25 ,c l =40pf,v o =0.5v dd 45 50 55 mo2 t a =25 ,c l =25pf,v o =0.5v dd 45 50 55 output clock duty cycle *2 dt so1,so2, ao1,ao2 t a =25 ,c l =15pf,v o =0.5v dd 45 50 55 % settling time *2 t s ao1,ao2 - - 1 ? s power-up time *2*4 t p all outputs excluding xto - 1 5 ms *1. when using an external clock input, the xti duty should be 50% with 3.3v cloc k signal amplitude leve l. the input signal voltage should not exceed the absolute maximum rating, otherwise damage may occur. *2. the numeric values are measured values obtained using the circuit in figure 1 and the npc standard evaluation board. *3. the numeric values are measured values obtained using the circuit in figure 2 and the npc standard evaluation board. *4. this is the time, after the supply is turned on from the off state, until the output clock reaches 0.1% of the specified frequency.
SM8707E/f seiko npc corporation - 7 sm8707f f xtal =27.0000mhz, v dd =3.3v0.3v, v ss =0v, t a =-40 to +85 ? c unless otherwise noted. rating parameter symbol pins condition min typ max unit external input clock frequency *1 f xti xti applies to external clock input use only - 27.0000 - mhz mo1,so1, so2 c l =25pf, transition between v ol =0.2v dd and v oh =0.8v dd - 2.0 - output clock rise time *2 t r ao1,ao2 c l =15pf, transition between v ol =0.2v dd and v oh =0.8v dd - 2.0 - ns mo1,so1, so2 c l =25pf, transition between v oh =0.8v dd and v ol =0.2v dd - 2.0 - output clock fall time *2 t f ao1,ao2 c l =15pf, transition between v oh =0.8v dd and v ol =0.2v dd - 2.0 - ns mo1 - 20 - so1,so2 t a =25 ,c l =25pf,v o =0.5v dd - 40 - output clock jitter *3 t jitter (1-sigma) ao1,ao2 t a =25 ,c l =15pf,v o =0.5v dd - 40 - ps mo1,so1, so2 t a =25 ,c l =25pf,v o =0.5v dd 45 50 55 output clock duty cycle *2 dt ao1,ao2 t a =25 ,c l =15pf,v o =0.5v dd 45 50 55 % settling time *2 t s all outputs excluding xto - - 1 ? s power-up time *2*4 t p all outputs excluding xto - 1 5 ms *1. when using an external clock input, the xti duty should be 50% with 3.3v cloc k signal amplitude leve l. the input signal voltage should not exceed the absolute maximum rating, otherwise damage may occur. *2. the numeric values are measured values obtained using the circuit in figure 1 and the npc standard evaluation board. *3. the numeric values are measured values obtained using the circuit in figure 2 and the npc standard evaluation board. *4. this is the time, after the supply is turned on from the off state, until the output clock reaches 0.1% of the specified frequency. active probe (hp1152a) oscilloscope (infinium hp54845a) passive probe (hp10435a) frequency & time interval analyzer (hp5371a) dut 27mhz dut:device under test active probe (hp54701a) oscilloscope (hp54720d + hp54721a) jitter measurement system (asa,m1) dut 27mhz dut:device under test figure 1. measurement circuit 1 figure 2. measurement circuit 2
SM8707E/f seiko npc corporation - 8 functional description 27mhz master clock the SM8707E/f 27mhz master clock circuit is configured, as shown in figure 3 with the crystal oscillator element connected between xti(pin 7) and xto(pin 8). alternatively, the 27mhz master clock can be supplied fro m an external master clock input on xti, as shown in figure 4. if an external input clock on xti is used, it is recommended that the frequency be 27.0000mhz, with 50% duty, and 3.3v voltage amplitude level. furthermore, when using an external clock input, the input signal voltage should not exceed the absolute maximum rating, otherwise damage may occur. internal circuits oscillator xti(pin 7) xto(pin 8) c1 c2 c1,c2=5 to 33pf mo figure 3. crystal oscillator connection internal circuits oscillator xti(pin 7) xto(pin 8) mo external clock open figure 4. external clock input
SM8707E/f seiko npc corporation - 9 sampling frequency and output clock frequency SM8707E the SM8707E sampling frequency fs can be switched between 44.1khz when fsel(pin 14) is low, and 48khz when fsel is high. the audio outputs(ao1 and ao2) are equivalent to 512fs, where fs is determined by the setting on fsel. in addition, the signal processor outputs(so1 and so2) are 33.8688mhz clocks derived from the master clock. and the video outputs(mo1 and mo2) are 27mhz clocks, identical to the master clock. the SM8707E supported clock frequencies are shown in table 1. output clock frequency [mhz] fsel (pin 14) sampling frequency fs [khz] ao1 (pin 9) ao2 (pin 10) so1 (pin 13) so2 (pin15) mo1 (pin 3) mo2 (pin 4) high 48 24.5760 (512fs) 24.5760 (512fs) 33.8688 33.8688 27.0000 27.0000 low 44.1 22.5792 (512fs) 22.5792 (512fs) 33.8688 33.8688 27.0000 27.0000 table 1. sampling frequency and output clock frequency (27.0000mhz master clock frequency) sm8707f the sm8707f sampling frequency fs can be switched be tween 44.1khz when fsel(pin 14) is high, and 48khz when fsel is low. the audio outputs(ao1 and ao2) are equivalent to 768fs, where fs is determined by the setting on fsel. in addition, the signal processor outputs(so1 and so2) are 16.9344mhz and 33.8688mhz clocks, respectively, derived from the master clock. the video output (mo1) is a 27mhz clock, identical to the master clock. the sm8707f supported clock frequencies are shown in table 2. output clock frequency [mhz] fsel (pin 14) sampling frequency fs [khz] ao1 (pin 9) ao2 (pin 10) so1 (pin 13) so2 (pin15) mo1 (pin 3) high 44.1 33.8688 (768fs) 33.8688 (768fs) 16.9344 33.8688 27.0000 low 48 36.8640 (768fs) 36.8640 (768fs) 16.9344 33.8688 27.0000 table 2. sampling frequency and output clock frequency (27.0000mhz master clock frequency)
SM8707E/f seiko npc corporation - 10 spike noise prevention function sm8707f/e have a spike noise prevention circuit that prevents any spike noise generation in the audio output clocks when the sampling frequency is switched using fsel. the state of the aox output before and afte r fsel is switched is shown in figure 5. when fsel is switched, either from low to high or high to low, the sp ike noise prevention circuit stops the aox clock output by a maximum of 1 ? s, and then the output clock changes to reflect the current fsel setting. e version : fs=48khz f version : fs=44.1khz e version : fs=44.1khz f version : fs=48khz f se l aox 1 s(max) figure 5. spike noise prevention circuit timing at sampling frequency switching sampling frequency switching settling time the clock output response when the sampling frequency is switched using fsel is shown in figure 6. SM8707E/f have a spike noise prevention circuit which stops the output aox clocks for a fixed interval, which means the settling time is a maximum 1 ? s when the sampling frequency is switched. e version : fs=44.1khz f version : fs=48khz e version : fs=44.1khz f version : fs=48khz fsel 0.8v dd ts ts 0.2v dd aox 27.0000mhz mox sox e version : fs=48khz f version : fs=44.1khz 33.8688mhz (e version) 16.9344/33.8688mhz (f version) figure 6. output signal switching timing
SM8707E/f seiko npc corporation - 11 SM8707E/f output frequency listing output clock frequency [mhz] version fsel polarity (pin 14) sampling frequency fs [khz] pin 3 pin 4 pin 9 pin 10 pin 13 pin 15 h 48.0 27.0000 27.0000 24.5760 (512fs) 24.5760 (512fs) 33.8688 33.8688 l 44.1 27.0000 27.0000 22.5792 (512fs) 22.5792 (512fs) 33.8688 33.8688 output load capacitance [pf] 40 25 15 15 15 15 SM8707E pin name mo1 mo2 ao1 ao2 so1 so2 h 44.1 27.0000 33.8688 (768fs) 33.8688 (768fs) 16.9344 33.8688 l 48.0 27.0000 - 36.8640 (768fs) 36.8640 (768fs) 16.9344 33.8688 output load capacitance [pf] 25 - 15 15 25 25 sm8707f pin name mo1 nc ao1 ao2 so1 so2
SM8707E/f seiko npc corporation - 12 please pay your attention to the following points at time of using the products shown in this document. 1. the products shown in this document (hereinafter ?produc ts?) are designed and manufactured to the generally accepted standar ds of reliability as expected for use in general electronic and electrical equipment, such as personal equipment, machine tools and measurement equipment. the products are no t designed and manufactured to be used in any other special equipment requiring extremely high level of reliability and safety, such as aero space equipment, nuclear power control equipment, medical equipment , transportation equipment, disaster prev ention equipment, security equipment. the products are not designed and manufactured to be used for the apparatus that exerts harmful influence on the huma n lives due to the defects, failure or malfunction of the produ cts. if you wish to use the products in that apparatus, please contact our sales section in advance. in the event that the products are used in such apparatus wi thout our prior approval, we assume no responsibility whatsoever for any damages resulting from the use of that apparatus. 2. npc reserves the right to change the specifications of the pr oducts in order to improve the c haracteristics or reliability t hereof. 3. the information described in this document is presented only as a guide for using the products. no responsibility is assumed by us for any infringements of patents or other rights of the third parties whic h may result from its use. no license is granted by implicati on or otherwise under any patents or other rights of the third parties. then, we assume no responsibility whatsoever for any damages resulting from that infringements. 4. the constant of each circuit shown in this document is descri bed as an example, and it is not guaranteed about its value of the mass production products. 5. in the case of that the products in this document falls unde r the foreign exchange and foreign trade control law or other ap plicable laws and regulations, approval of the export to be based on those laws and regulations are necessary. cu stomers are r equested appropriat ely take steps to obtain required permissions or appr ovals from appropriate government agencies. seiko npc corporation 1-9-9, hatchobori, chuo-ku, tokyo 104-0032, japan telephone: +81-3-5541-6501 facsimile: +81-3-5541-6510 http://www.npc.co.jp/ email:sales@npc.co.jp nd12003-e-00 2012.1


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