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august 2008 rev 1 1/42 AN2815 application note high-efficiency step-down controller with embedded 2 a ldo regulator introduction the pm6675as device consists of a single, high-efficiency step-down controller and an independent low dropout (ldo) linear regulator. the constant on-time (cot) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. an embedded integrator control loop compensates the dc voltage error due to the output ripple. selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. the low-noise mode sets the minimum switching frequency to 33 khz for audio- sensitive applications. the ldo linear regulator can sink and source up to 2 apk. two fixed current limits (1 a and 2 a) can be chosen. an active soft-end is independently performed on both the switching and the linear regulators outputs when disabled. figure 1. pm6675as demonstration board !-v www.st.com
contents AN2815 2/42 contents 1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 switching section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 ldo section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 jp3 fixed or adjustable output voltage (vsel pin) . . . . . . . . . . . . . . . . . . 14 6.2 jp1 power-saving mode (noskip pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 jp2 ldo current limit (lilim pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 jp5 compensation network (comp pin) . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 pm6675as demonstration tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 v out and l out turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 v out working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.3 v out and l out load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.4 v out and l out load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.5 v out efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.6 v out gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.7 v out and l out turn-off (soft-end) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.8 uv, ov and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9 v out current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.10 l out current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AN2815 contents 3/42 9.11 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.12 thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of figures AN2815 4/42 list of figures figure 1. pm6675as demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pm6675as demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. jp3 (vsel) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. jp1 (noskip) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. jp2 (lilim) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. jp5 (comp) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. pm6675as demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. v out soft-start at 150 mw load, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. l out turn-on, v out in pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. v out = 1.5 v, v in = 24 v, i vout = 0 a, forced-pwm mode . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. v out = 1.5 v, v in = 24 v, i vout = 0 a, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. v out = 1.5 v, v in = 24 v, no load, non-audible pulse-skip mode (33 khz) . . . . . . . . . . . . 23 figure 19. v out load regulation - v in = 24 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 20. l out load regulation - ldoin = v out , v out in forced pwm mode . . . . . . . . . . . . . . . . . 25 figure 21. v out load transient (v in =24 v, load=0 a to 7 a at 2.5 a/s), pulse-skip mode. . . . . . . . 26 figure 22. v out load transient (v in = 24 v, load=0 a to 7 a at 2.5 a/s), pulse-skip mode. . . . . . . 27 figure 23. forced pwm (blue), non-audible pulse-skip (green), pulse-skip (red), efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. external mosfet gate signals (v in = 24 v, load = 0), pulse-skip mode . . . . . . . . . . . . 29 figure 25. external mosfet gate signals (v in = 24 v, load = 7 a), pulse-skip mode . . . . . . . . . . 29 figure 26. v out and l out output voltages, v out soft-end, l out powered by an auxiliary rail. . . . . . 30 figure 27. v out and l out output voltages, l out soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 28. uv protection, pulse-skip mode, l out powered by an auxiliary rail . . . . . . . . . . . . . . . . . . 32 figure 29. ov protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 30. v out and l out rails, thermal shutdown, pulse-skip mode, l out powered by v out . . . . . 34 figure 31. v out current limit protection during a load transient (0 a to 9 a at 2.5 a/s . . . . . . . . . . . 35 figure 32. l out current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 33. switching frequency vs. input voltage, v out = 1.5 v, i vout = 2 a, forced pwm mode . . . 37 figure 34. forced pwm (blue), non-audible pulse-skip (green) and pulse-skip (red), switching frequency vs. output current, v out = 1.5 v, v in = 24 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 35. i lout = 0 a, average ic temperature = 31.0 c, max internal ic temperature = 33.1 c. . 39 figure 36. i lout = 0.2 a, average ic temperature = 38.2c, max internal ic temperature = 40.7 c . 39 figure 37. i lout = 0.5 a, average ic temperature = 38.2 c, max internal ic temperature = 41.5 c 40 figure 38. i lout = 1.0 a, average ic temperature = 48c, max internal ic temperature = 55.2 c . . 40
AN2815 main features 5/42 1 main features 1.1 switching section 4.5 v to 36 v input voltage range 0.6 v, 1% voltage reference 1.5 v fixed output voltage 0.6 v to 3.3 v adjustable output voltage 1.237 v 1% reference voltage available very fast load transient response constant on-time loop control no-r sense current sensing using low-side mosfets' r ds(on) negative current limit latched ovp, uvp and thermal shutdown fixed 3 ms soft-start selectable pulse-skip ping at light load selectable non-audible (33 khz) pulse-skip mode all ceramic output capacitor applications supported output voltage ripple compensation output soft-end 1.2 ldo section 0.6 v to 3.3 v adjustable output voltage selectable 1 a or 2 a current limit dedicated power good signal ceramic output capacitors supported output soft-end
main features AN2815 6/42 figure 2. pm6675as demonstration board schematic am0096 3 v1 0 0 j2 vout 1 j 3 pgnd 1 j9 pgnd 1 j1 vin 1 j5 vcc 1 r21 100k jp 3 v s el 0 0 0 u1 pm6675a s lout 24 lin 2 3 boot 22 hgate 21 pha s e 20 c s n s 19 vcc 1 8 lgate 17 pgnd 16 s pg 15 len 14 s wen 1 3 lilim 12 comp 11 v s el 10 v s n s 9 vo s c 8 vref 7 avcc 6 s gnd 5 lpg 4 no s kip 3 lfb 2 lgnd 1 thpd 25 j10 vccgnd 1 q2 s 7nf60l 5 4 1 6 7 8 2 3 0 q1 s 7nf60l 5 4 1 6 7 8 2 3 r22 33 k j11 lgnd 1 2x umk 3 25bj106km-t j6 lin 1 r19 7.5k r20 10k d1 bat41j 2 1 r4 3 r 3 1 2 0 r 3 1k5 1 2 r1 33 0k 1 2 r2 1 8 k 1 2 l1 1.5 u 1 2 d2 2 1 c1 10 u 1 2 c2 10 u 1 2 c 3 220 u 1 2 c4 220 u 1 2 c10 1 2 c9 100n 1 2 r7 3 r9 1 2 0 c19 n.m. 1 2 c1 3 100n 1 2 c20 n.m. 1 2 s w1 1 2 4 3 r11 100k 1 2 r12 100k 1 2 r1 8 100k 0 0 vcc r14 7k5 r15 6k 8 c15 6n 8 1 2 c16 1n 1 2 c17 n.m. 1 2 c6 10 u 1 2 r17 0 vcc vcc vcc vcc c11 10 u 1 2 c14 100n 1 2 tp1 gnd_tp j4 s pg 1 r1 3 100k 1 2 0 c5 1 u 1 2 jp5 int-ve s r jp2 lilim 1 2 3 4 5 6 jp1 no s kip 1 2 3 4 5 6 d 3 s tp s 1l60a 2 1 0 0 c21 100p 1 2 0 c7 10 u 1 2 0 0 c22 100p 1 2 r 8 12k r9 1 3 k r6 0 s tp s 1l60a r10 0 2x 4tpe220mf mlc 15 38 -152ml c12 100n 1 2 len- s wen j7 lout 1 j 8 lpg 1 c1 8 1n 1 2 r16 4r7 0 0
AN2815 bill of material 7/42 2 bill of material table 1. pm6675as demonstration board bill of material qty component description package part number manufacturer value 2c1, c2 ceramic, 50 v, x5r, 20% smd 1210 umk325bj106km-t taiyo yuden 10 f 2c3, c4 poscap, 4 v, 15 m ? , 20% smd d case 4tpe220mf sanyo 220 f 1c5 ceramic, 6.3 v, x5r, 10% smd 1206 standard 1 f 3 c6, c7, c11 ceramic, 6.3 v, x5r, 10% smd 0805 jmk212bj106kg-t taiyo yuden 10 f 4 c9, c10, c13, c14 ceramic, 50 v, x7r, 20% smd 0603 standard 100 n 1c12 ceramic, 50 v, x7r, 10% smd 0805 standard 100 n 1c15 ceramic, 50 v, x7r, 10% smd 0603 standard 6n8 1c16 ceramic, 50 v, x7r, 10% smd 0603 standard 1 n 1 c17 ceramic, 20% smd 0603 standard n.m. 1c18 ceramic, 50 v, x7r, 10% smd 0805 standard 1 n 2c19, c20 ceramic, 6.3 v, x5r, 10% smd 0805 jmk212bj106kg-t taiyo yuden n.m. 2c21, c22 ceramic, 50 v, x7r, 10% smd 0603 standard 100 p 1r1 chip resistor, 0.1w, 1% smd 0603 standard 330 k ? 1r2 chip resistor, 0.1 w, 1% smd 0603 standard 18 k ? 1r3 chip resistor, 0.1 w, 1% smd 0603 standard 1.5 k ? 2r4, r7 chip resistor, 0.1 w, 1% smd 0603 standard 3r3 1r6 chip resistor, 0.1 w, 1% smd 0805 standard 0 1r8 chip resistor, 0.1 w, 1% smd 0603 standard 12 k ? 1r9 chip resistor, 0.1 w, 1% smd 0603 standard 13 k ?
bill of material AN2815 8/42 3 r10, r17, r21 chip resistor, 0.1 w, 1% smd 0603 standard 0 4 r11, r12, r13,r18 chip resistor, 0.1 w, 1% smd 0603 standard 100 k ? 1r14 chip resistor, 0.1 w, 1% smd 0805 standard 15 k ? 1r15 chip resistor, 0.1 w, 1% smd 0603 standard 3k9 1r16 chip resistor, 0.1 w, 1% smd 0805 standard 4r7 1r19 chip resistor, 0.1 w, 1% smd 0603 standard 7k5 1r20 chip resistor, 0.1 w, 1% smd 0603 standard 10 k ? 1r22 chip resistor, 0.1 w, 1% smd 0603 standard n.m. 1l1 smt, 10.6 arms, 4.36 m ? 13.8x13.2 mm mlc1538-152ml coilcraft 1.5 h 2q1, q2 n-channel, 60 v so-8 sts7nf60l stmicroelectronics 1d1 schottky, 100 v, 0.2 a sod-323 bat41j stmicroelectronics 1d2 schottky, 60 v, 1 a do214-ac stps1l60a st microelectronics 1d3 n.m. 1 u1 controller vfqfpn-24 pm6675as stmicroelectronics 11 j1, j2, j3, j4, j5, j6, j7, j8, j9, j10,j11 header, single pin 3 jp1, jp2, jp3 jumper, 2x3, 100 mils jp4 n.m. 1jp5 pcb pads selector 1 tp6 test point 1 sw1 dip switch 2 dip-2 standard table 1. pm6675as demonstration board bill of material (continued) qty component description package part number manufacturer value
AN2815 component assembly and layout 9/42 3 component assembly and layout figure 3. top side component placement figure 4. top view am00964v1 am00965v1
component assembly and layout AN2815 10/42 figure 5. layer 2 view figure 6. layer 3 view am00966v1 am00967v1
AN2815 component assembly and layout 11/42 figure 7. bottom view figure 8. bottom side component placement am0096 8 v1 am00969v1
i/o interface AN2815 12/42 4 i/o interface the pm6675as demonstration board has the following test points as shown in ta b l e 2 . table 2. pm6675as demonstration kit input and output interface test point description vin battery input voltage positive terminal v out switching regulator output pgnd battery input and vout output common return l in ldo linear regulator input l out ldo linear regulator output lgnd ldo linear regulator output return lpg ldo linear regulator power good signal vcc +5 v supply, positive terminal vccgnd signal ground and vcc supply return spg v out sw regulator power good signal tp1 connection point between power and signal grounds
AN2815 recommended equipment 13/42 5 recommended equipment 4 v to 36 v, 30 w power supply active loads digital mutimeters 200 mhz four-trace oscilloscope
configuration AN2815 14/42 6 configuration the pm6675as demonstration board allows the user to choose the desired mode of operation using four jumpers (jp1, jp2, jp3 and jp5) and two resistors. refer to the following configuration description. 6.1 jp3 fixed or adjustable output voltage (vsel pin) the jp3 jumper is used to choose between fixed output voltage (1.5 v) and a user - defined output voltage in the range 0.6 v to 3.3 v. when connected in the lower position, the fixed 1.5 v output voltage is selected ( figure 8 ). if jp3 is in the upper position, the output voltage is given by: equation 1 the r8 and r9 resistors are set to 12 k ? and 13 k ? respectively (1.25 v output voltage) and can be changed by the user. 6.2 jp1 power-saving mode (noskip pin) the jp1 jumper allows choosing the mode of operation of the switching section. three options (forced-pwm, pulse-skip and non-audib le pulse-skip) can be selected by changing the jp1 setting as shown in figure 9 : figure 9. jp3 (vsel) setting 8 r 9 r 8 r 6 . 0 vout adj + ? = !-v 6 fixedoutput voltage defaultposition !djustableoutputvoltage
AN2815 configuration 15/42 6.3 jp2 ldo current limit (lilim pin) the jp2 jumper is used to select the ldo curr ent limit. in the upper position the ldo output current limit is set to 2 a, while in the lower position the current limit is set to 1 a. the middle position is not used. figure 10. jp1 (noskip) setting am00971v1 forced pwm (def au lt po s ition) no- au di b le p u l s e- s kip p u l s e- s kip figure 11. jp2 (lilim) setting am00972v1 2 a ldo c u rrent limit 1 a ldo c u rrent limit
configuration AN2815 16/42 6.4 jp5 compensation network (comp pin) the jp5 jumper is located on the bottom side of the pm6675as board and allows connecting the integrator input (comp pin) to the output through a simple capacitor (integrative compensation) or using the "virtual esr" network for very low esr output capacitor applications (e.g. all ceramic output cap applications). the integrative compensation is set by default. refer to the pm6675as datasheet for details about the all- ceramic output capacitor applications and the virtual esr design. figure 12. jp5 (comp) setting !-v )ntegrativecompensation defaultposition 6irtual%32net w ork
AN2815 test setup 17/42 7 test setup figure 12 shows the suggested setup connections between the pm6675as demonstration board, the loads and the external supply. the ldo input (lin) is connected to v out by default (r6 = 0 ? ). figure 13. pm6675as demonstration board test setup am00974v1
getting started AN2815 18/42 8 getting started the following step-by-step power-up and power-down sequences are provided in order to correctly evaluate the pm6675as demonstration board performance. power-up sequence ? working in an esd-protected environment is highly recommended. check all wrist straps and ground mat connections before handling the pm6675as demonstration board ? connect power supplies as shown in the pm6675as demonstration board test setup ( figure 12 ) and insert the meters in order to perform the desired performance evaluation. connect the scope-probes as desired ? set the jp1 through jp5 jumpers in order to properly configure the pm6675as board (default position suggested). set the swen-len switches to the on position (upper position); do not change jumper settings when the board is powered ? set the v cc supply to 5 v5% and the current limit to 100 ma ?set the v in supply to a voltage in the range 4.5 v to 36 v. an initial test at 24 v and 2 a current limit is suggested ? set all the loads to 0 a ? turn-on the v in supply ? turn-on the v cc supply ?vary the v out load from 0 a to 8 a ?vary the l out load from 0 a to 2 a to test sour ce capability. if a different ldo input is desired, connect the external rail as dashed in figure 12 and remove the r6 resistor. all changes must be don e when the board is not powered ? vary vin supply from 4.5 v to 36 v power-down sequence ? decrease l out loads to 0 a ? reduce v out load to 0 a ? decrease v cc supply from 5 v to 3.8 v in order to test the uvlo ? increase v cc supply from 3.8 v to 5 v to restart the device ? use the swen-len switches to test so ft-start and soft-end on both outputs ? turn-off the v out load ? turn-off the v cc supply ? turn-off the v in supply
AN2815 pm6675as demonstration tests 19/42 9 pm6675as demonstration tests 9.1 v out and l out turn-on (soft-start) the v out soft-start is divided in 4 steps. in each step the current limit is increased by ? of the nominal value. this behavior is well understood by loading the rail, as performed in the test. l out soft-start is performed at its maximum available current. figure 14. v out soft-start at 150 m ? load, pulse-skip mode am00975v1
pm6675as demonstration tests AN2815 20/42 9.2 v out working mode v out forced pwm mode when the forced pwm working mode is select ed (jp1 in the upper position), the inductor current is allowed to become negative and the following waveform can be captured. figure 15. l out turn-on, v out in pulse-skip mode am00976v1
AN2815 pm6675as demonstration tests 21/42 v out pulse-skip mode the default working mode is the pulse-skip algorithm, in which the low-side mosfet is turned off when the inductor current becomes equal to zero. this behavior allows reaching the maximum efficiency. figure 16. v out = 1.5 v, v in = 24 v, i vout = 0 a, forced-pwm mode am00977v1
pm6675as demonstration tests AN2815 22/42 figure 17. v out = 1.5 v, v in = 24 v, i vout = 0 a, pulse-skip mode am0097 8 v1
AN2815 pm6675as demonstration tests 23/42 v out non-audible pulse-skip mode in order to avoid too low switching frequencies, the non-audible pulse-skip mode can be selected (jp1 in the middle). doing so, the minimum switching frequency allowed is 33 khz as depicted in figure 18 . figure 18. v out = 1.5 v, v in = 24 v, no load, non-audible pulse-skip mode (33 khz) am00979v1
pm6675as demonstration tests AN2815 24/42 9.3 v out and l out load regulation figure 19 and 20 refer to v out and l out output voltage variations versus load current. the switching section directly supplies the linear ldo. figure 19. v out load regulation - v in = 24 v !-v 6/54 loadregulation #urrent;!= 6oltage;6= &orced07- 0ulseskip .onaudible03
AN2815 pm6675as demonstration tests 25/42 figure 20. l out load regulation - ldoin = v out , v out in forced pwm mode !-v ,/54 loadregulation #urrent;!= 6oltage;6=
pm6675as demonstration tests AN2815 26/42 9.4 v out and l out load transient responses transient load responses are evaluated by loading v out and l out output rails with a current slew rate of 2.5a/s. figure 21. v out load transient (v in =24 v, load=0 a to 7 a at 2.5 a/s), pulse-skip mode am009 8 2v1
AN2815 pm6675as demonstration tests 27/42 figure 22. v out load transient (v in = 24 v, load=0 a to 7 a at 2.5 a/s), pulse-skip mode am009 83 v1
pm6675as demonstration tests AN2815 28/42 9.5 v out efficiency the three working modes lead to different power efficiency. the test setup is v in =24 v, fsw = 330 khz, v out = 1.5 v. figure 23 summarizes the results. 9.6 v out gate drivers the pm6675as internal mosfet driver turns on and off the high-side and low-side external mosfet, avoiding cross-conduction. in the following two pictures the gates signals are shown in two different load conditions: without load ( figure 24 ) and with load ( figure 25 ). figure 23. forced pwm (blue), non-audible pulse-skip (green), pulse-skip (red), efficiency vs. output current !-v 6/54 %fficienc y #urrent;!= %fficienc y ;= )rufhg3:0 3xovh6nls 1rq$xgleoh36
AN2815 pm6675as demonstration tests 29/42 figure 24. external mosfet gate signals (v in = 24 v, load = 0), pulse-skip mode figure 25. external mosfet gate signals (v in = 24 v, load = 7 a), pulse-skip mode am009 8 5v1 am009 8 6v1
pm6675as demonstration tests AN2815 30/42 9.7 v out and l out turn-off (soft-end) v out soft-end when the swen pin is pulled down, the swit ching section performs the output capacitor discharge by turning on the discharge mosfet. the external low-side mosfet is turned on when the output voltage is lower than about 400 mv. figure 26. v out and l out output voltages, v out soft-end, l out powered by an auxiliary rail am009 8 7v1
AN2815 pm6675as demonstration tests 31/42 l out soft-end by pulling down the len pin the linear regulator is forced to discharge its output capacitor, by turning on its discharge mosfet. doing so, the l out rail is turned off in a safe way, avoiding output voltage under ground spikes. table 3. typical discharge mosfets r ds(on) resistance description v out output l out output typical discharge mosfets r ds(on) 25 ? 25 ? figure 27. v out and l out output voltages, l out soft-end am009 88 v1
pm6675as demonstration tests AN2815 32/42 9.8 uv, ov and thermal protections latched uv protection if the switching section output voltage is lower than the 70% nominal value, the undervoltage state is entered and the discharge mosfet is turned on (as in the the soft-end state). figure 28. uv protection, pulse-skip mode, l out powered by an auxiliary rail am009 8 9v1
AN2815 pm6675as demonstration tests 33/42 latched ov protection if the switching section output voltage is higher than the 115% nominal value, the overvoltage state is entered and the low-side mosfet is turned on in order to quickly discharge the output capacitor and avoid load damages. figure 29. ov protection, pulse-skip mode am00990v1
pm6675as demonstration tests AN2815 34/42 latched thermal shutdown if the junction temperature rises above 150 deg the thermal protection circuit turns off the device and discharges the switching section ou tput capacitor by performing the soft-end. figure 30. v out and l out rails, thermal shutdown, pulse-skip mode, l out powered by v out am00991v1
AN2815 pm6675as demonstration tests 35/42 9.9 v out current limit the valley current limit avoids any high-side turn -on if the inductor current is higher than the programmed value. this current limit can be designed with the following equation: equation 2 the current sensing is performed by comparing the voltage drop in the low-side mosfet, during the toff period, with the voltage drop given by an injected current and the current limit resistor. figure 31. v out current limit protection during a load transient (0 a to 9 a at 2.5 a/ s dson ls ilim cl r r a i , 100 ? = am00992v1
pm6675as demonstration tests AN2815 36/42 9.10 l out current limit (foldback) the linear ldo regulator has a fo ldback protection feature which reduces the current limit to about 1 a when the output voltage is outside the 10% power good window. the current limit is restored to about 2 a when the output voltage re-enters the power good window. figure 32. l out current limit during an output short am0099 3 v1
AN2815 pm6675as demonstration tests 37/42 9.11 switching frequency switching frequency vs. input voltage the constant on-time controller leads to a q uasi-constant switchin g frequency, slightly following the input voltage. figure 33. switching frequency vs. input voltage, v out = 1.5 v, i vout = 2 a, forced pwm mode !-v 37frequenc y vsinputvoltage 6oltage ;6= &requenc y ;k( z =
pm6675as demonstration tests AN2815 38/42 switching frequency vs. output current the switching frequency can decrease to very low values in pulse-sk ip mode but in non- audible pulse-skip there is a lower limit (about 33khz). by increasing the load, however, the switching frequency increases a bit, as a co nsequence of conduction and switching losses. 9.12 thermal behavior the ic internal maximum and average temperature can be monitored by an ir camera. for the following measures the test setup is: ?v in = 24 v ?f sw = 330 khz ? pulse-skip mode ?v out = 1.5 v at i vout = 4 a ?l out = 1.05 v, powered by v out ?t amb = 23 c by increasing the l out current the ic temperature changes as depicted in figure 35 through 38 . figure 34. forced pwm (blue), non-audible pulse-skip (green) and pulse-skip (red), switching frequency vs. output current, v out = 1.5 v, v in = 24 v !-v 37frequenc y vs6/54load #urrent;!= &requenc y ;k( z = &orced07- 0ulseskip .on audible03
AN2815 pm6675as demonstration tests 39/42 figure 35. i lout = 0 a, average ic temperature = 31.0 c, max internal ic temperature = 33.1 c figure 36. i lout = 0.2 a, average ic temperature = 38.2c, max internal ic temperature = 40.7 c am00996v1 am00997v1
pm6675as demonstration tests AN2815 40/42 figure 37. i lout = 0.5 a, average ic temperature = 38.2 c, max internal ic temperature = 41.5 c figure 38. i lout = 1.0 a, average ic temperature = 48c, max internal ic temperature = 55.2 c am0099 8 v1 am00999v1
AN2815 revision history 41/42 10 revision history table 4. document revision history date revision changes 20-aug-2008 1 initial release
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