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po wer ma nage m ent and m ulti m ark e t high - p erf or manc e dr bl ad e 6.6 mm x 4.5 mm x 0.6 mm td a21 321 dat a she et revision 2.4 , 2015 - 07 - 16
edition 2015 - 07 - 16 26 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologi es hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non - infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and c onditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life - support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonab ly be expected to cause the failure of that life - support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and su stain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TDA21321 data sheet 3 revision 2.4 , 2015 - 07 - 16 revision history page or item su bjects (major changes since previous revision) revision 2.4 , 2015 - 07 - 16 package drawings figures 18 C 20 updated inserted chapter 10 (packaging information) trademarks of infineon technologies ag aurix?, bluemoon?, c166?, canpak?, cipos?, cipurse?, comneon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modst ack?, my - d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pro - sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x - gold?, x - pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent technologies, amba?, arm?, multi - ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat - iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexray consortium. hyperterminal? of hilgraev e incorporated. iec? of commission electrotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucl eus? of mentor graphics corporation. mifare? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc . openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektronix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited . last trademarks update 2010 - 10 - 26
TDA21321 applications data sheet 4 revision 2.4 , 2015 - 07 - 16 1 applications ? desktop and server vcore and non - vcore buck - converter ? single phase and multiphase pol ? cpu/gpu regulation in notebook, desktop graphics cards, ddr memory, graphi c memory ? high power density voltage regulator modules (vrm). 2 features ? input voltage range +4.5 v to +16 v ? maximum average current up to 5 0 a ? for synchronous buck step down voltage applications ? power mosfets rated 25 v for safe operation under all conditions ? f ast switching technology for improved performance at h igh switching frequencies (> 7 50 k hz) ? includes bootstrap diode ? shoot through protection ? max + 8 v v gs , high - side and low - side mosfet gate driving voltage ? compatible to standard +3.3 v pwm controller integrated circuits ? tri - state pwm input functionality ? small package: lg - wiqfn - 38 - 1 (6.6x4.5x0.6 mm3) ? rohs compliant ? integrated temperature sense ? integrated current sense table 1 product identification par t number temp range package marking TDA21321 - 25 ? ? figure 1 picture of the product
TDA21321 description data sheet 5 revision 2.4 , 2015 - 07 - 16 3 description 3.1 pinout figure 2 pinout, numbering and name of pins (transparent top view) table 2 i/o signals pin no. name pin type buffer type function 2 pwm i /o +3.3 v logic pwm drive logic input , status output for vcin the tri - state pwm input is compatible with 3.3 v. 3 off# i +3.3 v logic deactivates ls - mosfet pull low to prevent ls - fet turn - on . leave open if not used. ( if traced out i n noisy layout it may require external pull up.) 4 imon o analog load current sensing provides a voltage proportional to the high/ low - side mosfet current s ; leave open if not used. 5 imonref o analog load current sensing reference to pin 4 ; leave open if not used. 7 t mon/fault o analog / digital thermal sensing / fault pin temperature reporting, fault signaling by logic h ; status output of vdrv, leave open if not used. 8 boot i analog bootstrap voltage pin connect to boot capacitor 9 phase i analog switch node in put internally connected to sw pin s , connect to boot capacitor as reference pin for boot voltage 33 - 38 (pad s ) sw o analog switch node output high current output switching node
TDA21321 description data sheet 6 revision 2.4 , 2015 - 07 - 16 table 3 power supply pin no. name pin type function 13 C 15, 20, 23 - 28 (pads) vin power input voltage converter input voltage (connected to drain of the high - side mosfet and driver) 21 vdrv power mos fet gate drive supply voltage high and low - side gate drive 22 vcin power driver l ogic supply voltage bias voltage for the internal logic table 4 ground pins pin no. name pin type function 1 cgnd gnd control signal ground should be connected to local pgnd externally, preferably by vias to gnd plane 16 C 19, 29 - 32 (pads) pgnd gnd power ground all these pins must be connected to the power gnd plane through multiple low inductance vias. table 5 not connected pin no. name pin type function 6, 10, 11, 12 nc C no internal connection leave pin floating , tie to vin or gnd.
TDA21321 description data sheet 7 revision 2.4 , 2015 - 07 - 16 3.2 general description the infineon TDA21321 is a multichip module that incorporates infineons premier mosfet technology into a single high - side and a single low - side mosfet . this is coupled with a robust, high performance, high switching freq uency gate driver on a single 38 pin lg - wiqfn - 38 - 1 (6.6x4.5x0.6 mm3) package. the optimized gate timing enables significant light load efficiency improvements over discrete solutions. state of the art mosfet technology provides exceptional perform ance at full and light load . when combined with infineons primarion? controller family of digital multi - phase controllers, the TDA21321 forms a complete core - voltage regulator solution for advanced micro and graphics processors as well as point - of - load applications. the d evice package height is 0.6 mm . it is an excellent choice for applications with critical height limitations and has reduced thermal impedance from junction to top case compared to drmos, allow ing for top side cooling. the power density for transmitted power of this approach is approximately 5 0 w within a 28 mm 2 area. figure 3 simplified block diagram attention: gh and gl are not accessible on this package, but are mentioned for clarity in this block diagram.
TDA21321 electrical specification data sheet 8 revision 2.4 , 2015 - 07 - 16 4 electrical s pecification 4.1 absolute maximum ratings note: t a = 25c stresses above those listed in table 6 absolute maximum ratings and figure 4 repetiti ve voltage stress at phase node - safe operating area may cause permanent damage to the device. these are absolute stress ratings only and operation of the device is not implied or recommended at these or any other conditions in excess of those given in t he operational sections of this specification. exposure over values of the recommended ratings (table 8) for extended periods may adversely affect the operation and reliability of the device. table 6 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. frequency of the pwm input f sw 0.01 (in ccm) C out C C C in (dc) - 0.30 C C cin (dc) - 0.30 C C drv (dc) - 0.30 C C sw (dc) - 1 C C sw (ac) - 10 1 C 1 v C phase (dc) - 1 C C phase (ac) - 10 1 C 1 v C boot (dc) - 0.3 C C boot (ac) C C 1 v C boot - phase (dc) - 0.3 C C off# - 0.3 C ? j ? pwm - 0.3 C t mon/fault - 0.3 C C i mon - 0.3 C C imonref - 0.3 C C jmax - 40 C ? C stg - 55 C ? C note: all rated voltages are relative to voltages on the cgnd and pgnd pins unless otherwise specified. 1 ac is limited to 10 ns
TDA21321 electrical specification data sheet 9 revision 2.4 , 2015 - 07 - 16 figure 4 repetitive voltage stress at phase node - safe operating area note: t on refers to the on - time of the hs - mosfet. for input voltages below 10 v no limits on the duration of t on need to be applied. information: a) - area of typical computing applications with 12 v input supply voltage
TDA21321 electrical specification data sheet 10 revision 2.4 , 2015 - 07 - 16 4.2 thermal characteristics table 7 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance to case (soldering point) j c C 3.5 C k/w C thermal resistance to top of package j ctop C 3.7 C C thermal resistance to ambient j a C 14 C p loss = 4.5 w, t a = 70 c, 8 layer server board (2 oz copper) 4.3 recommended operating conditions and electrical characteristics 2 note: v in = 12v, v drv = v cin = 5 v, t a = 25 c unless otherwise specified table 8 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. input voltage v in 4.5 C 16 v C mosfet driver voltage v drv 4.5 C 8 v C logic supply voltage v cin 4.5 C 8 C frequency of the pwm f sw 1 0 0 C 800 k hz ccm operation with stated current sense accuracy junction temperature t jop - 25 C +125 c C 2 exposure over values of the recommended ratings for extended periods may adversely affect the operation and reliability of the device. min/max values are based on empirical cpk .
TDA21321 electrical specification data sheet 11 revision 2.4 , 2015 - 07 - 16 table 9 voltage supply and biasing current parameter symbol values unit note / test condition min. typ. max. uvlo vcin rising v uvlo1_r 3. 0 C uvlo1_f 2. 6 C uvlo2_r 4.1 6 4.25 4.34 v gl, gh and tmon/fault enable threshold; when uvlo vcin is enabled then: above threshold gl is enabled, gh depends on uvlo boot, tmon/fault is released to report driver temperature uvlo vdrv falling v uvlo2_f 3.7 3.8 3. 9 gl, gh and tmon/fault disable threshold; when uvlo vcin is enabled: below threshold after 3 consecutive cycles or 15 s (typ.) the driver outputs gl/gh are disabled, tmon/fault stops temperature reporting and is held low by pull - down resistor uvlo boot rising v uvloboot_r 3. 88 4.0 5 4. 22 v v boot - v sw rising, gh enable threshold; when uvlo vcin and uvlo vdrv are active: above threshold gh responds to pwm uvlo boot falling v uvloboot_f 3.5 3.6 3 3.7 6 v boot - v sw falling, gl/gh disable threshold; when uvlo vcin and uvlo vdrv are enabled: below threshold counter starts, after 3 consecutive pwm cycles driver outputs are disabled driver current i vdrv_6 00khz C C f sw = 6 00 khz i vdrv_1mhz C C f sw = 1 mhz ic current (control) i vcin_o C C cin + i drv C C sw_0 C pwm_s ), vcin = v drv = 5v, internal pull - down resistor 1.5 k ? table 10 current sense parameter symbol values unit note / test condition min. typ. max. imon voltage range v imo n 0. 8 C imon 0.2 C k? cs - 6.67 - a/a leakage current i leak - 2 0 2 a i d = 0, v cm = 1.5 , pwm in tri - state current monitoring zero current offset i offset - 3 0 3 a corresponds to 2 . 2 5 mv at 5 mv/a (r imon = 750?) 125 c drv = 5 v 10 % v cin = 5 v 10 % a11 - 3 C ocptrip tested at 25 a , other guaranteed by design a12 - 2 .5 C for 25 a iout 45 a C C a iout
TDA21321 electrical specification data sheet 12 revision 2.4 , 2015 - 07 - 16 table 11 temperature sense parameter symbol values unit note / test condition min. typ. max. temp. sense and accuracy temp. fault t tmax 140 145 150 c temperature monitors driver junction. circuit reports temperatures to - 25 c accurately (0.4v). the maximum temperature reported is t tmax . above t tmax a logic h is asserted to indicate a fault tmon_h 2.6 C C tmon 0.4 C 3 t tmondeg C C 4 t tmon - 25 C 5 tc C C 25c C C 125 c tmon - 4 C c 125 c, unspecified below - 25 c table 12 other logic functions, inputs/outputs and thresholds parameter symbol values unit note / test condition min. typ. max. off# input low v off#_l C C v off# falling input high v off#_h 2.0 C C v off# rising pwm input low v pwm_l C C v pwm falling input high v pwm_h 2.4 C C v pwm rising input resistance r in - pwm 6 C ? v pwm = 1 v open voltage v pwm_o C C v pwm_o tri - state shutdown window 6 v pwm_s 1.2 C C 7 t pwmdetect 5 C 8 t pwmmin C C pwmmin will be extended to t pwmmin ocp overcurrent protection i ocptrip 58 65 72 a duty cycle limitation at i ocptrip , fault asserted and latched after 10 truncated consecutive switching cycles hss high - side - short protection v hsstrip C C hsstrip , fault is asserted and latched. 3 guaranteed by design 4 guaranteed by design 5 guaranteed by design 6 maximum voltage range for tri - state 7 guaranteed by design 8 guaranteed by design
TDA21321 electrical specification data sheet 13 revision 2.4 , 2015 - 07 - 16 table 13 timing characteristics 9 parameter symbol values unit note / test condition min. typ. max. pwm tri - state to sw falling delay t_pts2 C C out prebiased at 1 v, other conditions as for t_pts pwm tri - state to sw rising delay t_pts C C load = 0, vdrv = vcin = 5 v, vin = 12 v, fsw = 600 khz phase shutdown hold - off time from pwm low t_tsshd C C C C C C C C C C C C diagrams can be found under section gate driver timing diagram. 9 all timing data are guaranteed by design
TDA21321 theory of operation data sheet 14 revision 2.4 , 2015 - 07 - 16 5 theory of operation the TDA21321 features a power stage with mosfet driver. temperature and current are being monitored. data and various fault conditions can be reported to the controller. the power mosfets are optimized for 5 v gat e drive enabling excellent high load and light load efficiency. the gate driver is a robust high - performance driver rated at the switching node for dc voltages ranging from - 1 v to + 18 v. 5.1 driver characteristics the gate driver has 2 voltage inputs, vcin and vdrv. vcin is the 5 v logic supply for the driver. vdrv sets the driving voltage for the high - side and low - side mosfets. the reference for the gate driver control circuit (vcin) is cgnd. to decouple the sensit ive control circuitry (logic supply) from a noisy environment a ceramic capacitor must be placed between vcin and cgnd close to the pins. vdrv needs also to be decoupled using a ceramic capacitor (mlcc) between vdrv and pgnd in close proximity to the pins. pgnd serves as reference for the power circuitry including the driver output stage. 5.2 power - up sequence without the logic supply vcin the device remains off . pwm is held low by an internal pull down resistor. pwm information cannot be fed to the driver. vcin supplies power to the driver logic. with the presence of vcin o n power - up of the gate drive voltage vdrv , the driver and the pwm input will be enabled , the unforced pwm level will be within its tri - state window. this signals that the driver supply vol tage s ha ve cleared their respective uvlo threshold s . tmon/fault reports temperature. the pwm controller is expected to wait for this to happen before initiating pwm signals to start up the system . note that with vcin and vdrv present, the switching node c an rise up to v sw_0 with pwm in t ri - state condition. 5.3 inputs to the internal control circuits pwm is the control input to the ic from an external pwm controller and is compatible with 3.3 v logic. the pwm input has tri - state functionality. when the voltage remains in the specified pwm - shutdown - window for at least the pwm - shutdown - holdoff time t_tsshd, the operation will be suspended by keeping both mosfet gate outputs low. once left open, the pin is held internally at a tri - state level of v pwm_o . the pwm sig nal must prevail for at least t pwmmin to initiate a response from the driver. the pwm threshold voltages v pmw_o , v pwm_h , v pwm_l do not vary over the wide range of vcin supply voltages (4.5 v to 8 v). the off# pin provides a means to keep the low - side mosfet disabled regardless of the pwm signal. it is an active low signal. an internal pull up resistor ensures regular operation when the pin is not used. when pulled low, the low - side mosfet is kept in off - state. in multiphase systems the off# pins of al l phases may be connected together . one controller output is then able to toggle the ls - fet operation mode .
TDA21321 theory of operation data sheet 15 revision 2.4 , 2015 - 07 - 16 table 14 pwm and off# pin functionality , driver outputs pwm logic level off# logic level gate hs - fet (gh) gate ls - fet (gl) high any high low open (tri - state: left floating, or high impedance) low low low high or open high 5.4 monitoring and protection circuits the TDA21321 is designed with the various protection functions. most of these protection features require a pwm controller that reacts properly on the assertion of a fault signal at tmon/fault to shutdown the circuit. fault assertion is latched and is being removed wh en vcin and/or vdrv will be re - cycled . a reported fault is always indicating a critical condition with high stress levels on the device and/or load that requires immediate action in form of shutdown to prevent imminent catastrophic failure. in multiphase r egulators the tmon/fault outputs of the power stages will have to be connected together. the tmon/fault output voltage follows the highest voltage output of any phase connected. the pull - down capability of any tmon/fault output is weak so that a fault asse rtion of any phase will always override other phase outputs. 5.4.1 high - side short protection (hss) the voltage at the switching node is being monitored during the ls - mosfet being driven in on - state. when during that time the switching node voltage exceeds a cri tical threshold of v hsstrip the hss fault is being asserted by pulling tmon/fault to high. the pwm controller has to shut down the power stage to prevent catastrophic failure. tmon/fault is latched and will be released when vcin and/or vdrv will be re - cy cled. hss can lead to a very sudden current rise that can impact voltage potentials in and in vicinity of the power device so that early reset events could potentially occur. therefore, it is important to always have the system controller terminate the pow er supply as soon as a critical event has been reported by the power stage. 5.4.2 thermal p rotection and t emperature monitoring the driver monitors and reports its temperature . in multiphase systems with connected tmon/fault pins only the highest temperature of any of the connected phases will be reported. the pwm controller is supposed to react on the reported temperature with power throttling commands to the load. if the system fails to respond and the temperature continues to rise to a value of t tmax for at least t tmondeg , tmon/fault is being pulled high to report a n over - temperature f ault (otp) . tmon/fault is latched and will be released when vcin and/or vdrv will be re - cycle d. a t otp fault the driver outputs will be deactivated until vcin and/or vdrv have been re - cycled. the pwm controller is ecxpected to shut down the power stage to prevent catastrophic failure.
TDA21321 theory of operation data sheet 16 revision 2.4 , 2015 - 07 - 16 figure 5 thermal monitoring and protection note: temperature reporting below t tmon_min occurs with limited accuracy. t tmon_min is being defined by the corresponding cont roller detection threshold for l ogic l. the reported voltage as function of temperature follows this equation: ( 1 ) 5.4.3 u ndervoltage lockout (uvlo) the power stage should not be operated when its supply voltages are out of the nominal range. uvlo conditions occurring during power up and power down must be accommodated by proper sequencing. an uvlo condition under normal operation can indicate a problem with the driver voltage and must be handled with a shutdown to prevent damage to the power stage. a primary uvlo circuit monitors vcin. only after having vcin in regulation range the uvlo monitoring on vdrv takes place. during startup uvlo on vdrv is being signaled by keeping tmon/fault low. with v cin being below v uvlo 1 _r at startup the driver is inactive, pwm and tmon/fault are held low. when vcin exceeds v uvlo 1 _r the driver becomes active, pin pwm is being enabled as input and held internally at its tri - state level of v pwm_o . then vdrv determines tmon/fault: - b elow v uvlo2_r tmon/fault remains low. - when vdrv exceeds v uvlo2_r tmon/fault is released and reports temperature. - when vdrv falls below v uvlo2_f for 3 consecutive cycles or 15 s (typ.) tmon/fault is being pulled low . if at startup vcin and/or vdrv are below their respective undervoltage lockout rising thresholds ( v uvlo1_r , v uvlo2_r ) gl and gh remain disabled. once these thresholds have been cleared, the driver provides gl output ? ? c t k mv v v tmon ? ? ? ? 8 6 . 0
TDA21321 theory of operation data sheet 17 revision 2.4 , 2015 - 07 - 16 signal following pwm. when the voltage v boot - v sw has been exceeding v uvloboot_r , gh is being released to respond to pwm. when vcin and/or vdrv are falling below their respective undervoltage lockout falling thresholds ( v uvlo1_f , v uvlo2_f ) the driver disables its outputs gh and gl to drive the mosfets. when the voltage v boot - v sw has been falling below v uvloboot_f for 3 consecutive pwm cycles the driver will be disabled. figure 6 output signal at tmon/fault 5.4.4 boot - undervoltage protection (uvlo boot ) the voltage between boot and sw pins (boot - voltage) is being monitored when vcin and vdrv have been clearing their respective uvlo conditions . at startup, the ls - mosfet gate (gl) is enabled to respond to the pwm signal when vdrv is being active. if the voltage at the boot capacitor is insufficient to clear the v uvloboot_r threshold, gh remains disabled until the active ls - mosfet has forced sufficient charge onto the boot capacitor during the pwm l state. when the boot capacitor voltage exceeds v uvloboot_r , the gh output for the gate drive of the hs - mosfet is enabled. at startup and anytime when the boot voltage is below v uvloboot_f an internal boot - error fl ag is set. the boot - error flag is being reset when the boot voltage exceeded v uvloboot_r . if during the falling edge of the pwm (from h to tri - state or from h to l) the uvlo boot error flag is set, an internal counter increases by one. when the counte r reaches three, the driver outputs gh/gl are being disabled (i.e. latched in tri - state), regardless of the pwm input. to reset the driver and resume operation, the pwm input has to be held in tri - state for 19 s (typ). after that, the uvlo boot counter i s being reset to zero and the driver performs a startup sequence as described before in order to bring sufficient charge onto the boot capacitor.
TDA21321 theory of operation data sheet 18 revision 2.4 , 2015 - 07 - 16 the uvlo boot counter is also being reset to zero whenever during the falling edge of the pwm the uvlo boot erro r flag was not set, i.e. the error condition had been temporary for less than three consecutive instances of the falling edge of the pwm signal. to prevent depletion of the boot capacitor during extended time in tri - state during regular operation, a boot refresh circuit will engage after 19 s (typ) in consecutive tristate condition when the voltage at the boot capacitor has fallen below v uvloboot_ f . this circuit remains active until v uvloboot_r has been reached or the pwm input signal leaves the region of tri - state . the boot refresh circuit is powered by v in . to ensure full effectiveness the voltage difference (v in - v sw ) should be more than 4.8 v. if the driver was disabled due to an uvlo boot error, it will be reset to resume operation when vc in and/or vdr v will be re - cycled or pwm will be held at tri - state level for more than 19 s (typ). in case of an uvlo boot error it is expected that the system controller d iscover s a missing phase, phase current mismatch, excessive temperature or ocp events on other phases and initiate s shutdown. 5.4.5 current monitoring and overcurrent protection (ocp) the TDA21321 senses and reports current back to the controller via the voltage at imon. this voltage is a filtered representation of the voltage at imonref. imonref is a current source output: ( 2 ) the voltage at imo nref depends on the impedance its current is being passed through. a recommended target voltage at zero output current is 1.5v (common mode voltage). the series resistor r imon ref between imonref and the common mode voltage reference sets the voltage gain o f the current sense according to: ( 3 ) the output current is now represented by the voltage difference between imon and v imonref_cm . v imonref_cm is the voltage at imonref when the load current is zero. ( 4 ) a cs is given in table 10 for vdrv = 5v. if vdrv has been chosen to be different, a cs has to be calculated as: ( 5 ) a filter capacitor c imon of 10 pf has to be placed between imon and v imonref_cm (reference voltage pin of r imon ref ). c imon and r imon ref have to be arranged in a tight loop close to the pins of the TDA21321 . an additional resistor r imon has to be connected in parallel to c imon . its location is flexible and can also be at the controller. the va lue for r imon should be chosen identical to r imon ref within the range of 200 to 1 k . at the voltage receiver side the measurement loop has to be closed. it is important to not inject noise into this loop. therefore differential routing of imon and imon ref is required. cs out imonref a i i ? ? monref imonref cm imonref imonref i r v v ? ? ? _ cs imonref out cm imonref imon a r i v v ? ? ? ? _ ? ? ? ? ? ? 012 . 0 5 1 67 . 6 ? ? ? ? ? v vdrv a a a cs ?
TDA21321 theory of operation data sheet 19 revision 2.4 , 2015 - 07 - 16 for example, having a permissible 500 mv voltage range at the receiver side to report positive current of 100 a, the resistor that has to be used in the imonref path can be calculated as: ( 6 ) having a resistor value of 348 ? will result in the following voltage difference: ( 7 ) the sensing of current occurs in the hs - mosfet and the ls - mosfet during their respective on - times . during tri - state condition both mosfets are in off - state without sensing. the current reported is then zero . if the tri - state condition was present for more than 19 s (typ.), current reporting resumes with a delay of 1 s (typ.). ocp: by design of th e application the current should never exceed the ocp tripping threshold i ocptrip . the duty cycle is being truncated by the TDA21321 when the current exceeds i ocptrip . this prevents the part from being destroy ed by excessive current. a counter is being increased counting consecutive pwm duty cycle truncations. the counter is being reset at the first non - truncated pwm duty cycle. when the counter reaches the value of 10 , a fault will be reported at tmon/fault by pulling it to high level signaling the pwm controller the need for immediate action to prevent catastrophic failure. this fault is latched and will be released when vcin and/or vdrv are being re - cycled. 5.4.6 shoot through protection the TDA21321 driver includes gate drive functionality to protect against shoot through. in order to protect the power stage from overlap, both high - side and low - side mosfets being on at the same time, the adaptive control circuitry monitors specific voltages. when the pwm signal transitions to low, the high - side mosfet will begin to turn - off after the propagation delay time t_pdlu. when v gs of the high - side mosfet is discharged below 1 v (a threshold below which the high - side mosfet is off), a secondary delay t_pdhl is initiated. after that delay the low - side mosfet turns on regardless of the state of the phase pin. it ensures that the converter can si nk current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. see figure 9 for more detail. ? ? ? ? ? ? ? ? ? ? ? 750 10 67 . 6 100 500 500 6 _ _ a mv a i v v r mv v v cs out cm imonref imon imonref cm imonref imon mv a a i r v v cs out imonref cm imonref imon 232 10 67 . 6 100 348 6 _ ? ? ? ? ? ? ? ? ? ? ?
TDA21321 application data sheet 20 revision 2.4 , 2015 - 07 - 16 6 appl ication 6.1 implementation figure 7 pin interconnection outline (transparent top view) note: 1. pin 9 (phase) is internally connected to the sw pads 33 - 38. 2. the capacitor c tmon is used to filter noise from the tmon/fault connection. the capacitor has to be placed at the inp ut of the controller. its value should be set between 0.1 nf and 0.5 nf. 3. r imon should be chosen identical to r imon ref . 4. c imon and r imon ref have to be arranged in a tight loop close to the pins of the TDA21321 . 5. to lower the pre - bias voltage at vout to below v sw_0 , place a resistor from vout to gnd. 6. c in should consist of a 0.1 f and a 1 f very close to the pins 15/16 and a 1 f capacitor at pins 19/20. in addition place sufficient mlccs in relative proximity of each power stage to deliver energy for the on - time of the hs - mosfet. 7. the value of capacitor c boot should be chosen according to the corresponding application note .
TDA21321 application data sheet 21 revision 2.4 , 2015 - 07 - 16 6.2 typical application figure 8 six - phase voltage regulator - typical application (simplified schematic)
TDA21321 gate driver timing diagram data sheet 22 revision 2.4 , 2015 - 07 - 16 7 gate driver timing diagram figure 9 adaptive gate driver timing diagram figure 10 off# timing diagram tri - state v pwm_l t_tsshd t_pdll t_pdlu v pwm_h v pwm_l t_tssh d t_pts 2 t_pts v pwm_h note : sw during entering/exit ing tri - state behaves dependen d on inductor current. sw pwm v pwm_h 90% v sw 10% v sw off# sw t_pdl(off# ) v off#_l t_pdh(off# ) v off#_ h ls - fet on ls - fet on ls - fet off (body diode conducting) note : pwm is low. - v f
TDA21321 performance curves C typical data data sheet 23 revision 2.4 , 2015 - 07 - 16 8 performance curves C typical data operating conditions (unless otherwise specified): vin = +12 v, vcin = vdrv = +5 v, vout = +1.8 v, f sw = 750 khz, 1 8 0nh ( delta , hcb118080d - 181 , dcr = 0. 1 9 m) inductor, t a = 25 c, airflow = 2 00 lfm, no heatsink. efficiency and power loss reported herein include only TDA21321 losses. 8.1 driver current versus switching frequency figure 11 driver current over swi t ching frequency in ccm operation
TDA21321 performance curves C typical da ta data sheet 24 revision 2.4 , 2015 - 07 - 16 8.2 efficiency and power loss versus output voltage figure 12 efficiency at vin = 12 v, vcin = vdrv = 5 v, f sw = 7 5 0 khz , parameter: vout figure 13 power loss at vin = 12 v, vcin = vdrv = 5 v, f sw = 750 khz, parameter: vout
TDA21321 performance curves C typical data data sheet 25 revision 2.4 , 2015 - 07 - 16 8.3 efficiency and power loss versus input voltage figure 14 efficiency at f sw = 7 5 0 khz , vcin = vdrv = 5 v, vout = 1.8 v, parameter: vin figure 15 power loss at f sw = 7 5 0 khz, vcin = vdrv = 5 v, vout = 1.8 v, parameter: vi n
TDA21321 performance curves C typical data data sheet 26 revision 2.4 , 2015 - 07 - 16 8.4 e fficiency and power loss versus switching frequency figure 16 efficiency at vin = 12 v , vcin = vdrv = 5 v, vout = 1.8 v, parameter: f sw figure 17 power loss at vin = 12 v , vcin = vdrv = 5 v, vout = 1.8 v, parameter: f sw
TDA21321 mechanical drawing lg - wiqfn - 38 - 1 (6.6x4.5x0.6 mm3) data sheet 27 revision 2.4 , 2015 - 07 - 16 9 mechanical drawing lg - wiqfn - 38 - 1 (6.6x4.5x0.6 mm 3) figure 18 mechanical dimensions of package (top and side view) in mm
TDA21321 mechanical drawing lg - wiqfn - 38 - 1 (6.6x4.5x0.6 mm3) data sheet 28 revision 2.4 , 2015 - 07 - 16 figure 19 mechanical dimensions of package (bottom view) in mm
TDA21321 mechanical drawing lg - wiqfn - 38 - 1 (6.6x4.5x0.6 mm3) data sheet 29 revision 2.4 , 2015 - 07 - 16 figure 20 landing pattern and stencil dimensions (sw on upper end) in mm
TDA21321 packaging informatio n data sheet 30 revision 2.4 , 2015 - 07 - 16 10 packaging information figure 21 p ackagin g information in mm
TDA21321 board layout recommendations data sheet 31 revision 2.4 , 2015 - 07 - 16 11 board layout recommendations the pcb (printed circuit board) layout design follows the listed industry standards: - recommended vias: 1 0 mil 10 hole with 20 mil via pad diameter, 12 mil hole with 24 mil via pad diameter - minimum (typical) via to via center distance: 25 mil (30 35 mil) - minimum feature width: 5 mil - minimum (typical) clearance: 5 mil (15 20 mil) commonly, 10 mil via drill diameters are used for pcbs up to 150 mil thicknesses (usually 22 layers). for thicker boards, 12 mil vias are recommended. to reduce voltage spikes caused by parasitic circuit inductance, all primary decoupling capacitors for vin, vdrv, boot and vcin shou ld be of mlcc type, x6s or x7r rated and located at the same board side as the powerstage close to their respective pins. this is especially important for the vin to pgnd mlccs. electrical and thermal connection of the powerstage to the pcb is crucial for achieving high efficiency. therefore, vias in vin and pgnd pads are required in the pad areas to connect most effectively to other power and pgnd layers. bigger value mlcc input capacitors should be placed at the bottom side of the pcb close to the vias of the powerstages vin and pgnd pads. to reduce the stray inductance in the current commutation loop it is strongly recommended to have the 2 nd layers from the top and the bottom of the board to be monolithic ground planes. all logic and signal connections between powerstage and controller should be embedded between two ground layers. the routing of the current sense lines back to the controller has to be done differentially, for example with 5 mil spacing and 10 C 15 mil distances to other potentials. if th e pcb features more than 10 layers, the passive components associated with the current sense lines should be located only at the top side of the board. all resistors and capacitors near the powerstage should be in 0402 case size. for minimizing distributio n loss to the load and maintaining signal integrity, have multiple layers/planes in parallel and ensure that the copper cross section for pgnd is at least as big as it is for vout. figure 22 generic board design 10 unit conversion: 1 mil = 25.4 m
w w w . i n f i n e o n . c o m published by infineon technologies ag

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