View IRMCF171-15_8361482.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

irmcf171 1 www.irf.com ? 2013 international rectifier april 20, 2013 high performance sensorless motor control ic description irmcf171 is a high performance flash memory based motion control ic designed primarily for appliance applications. irmcf171 is designed to achieve low cost ye t high performance control solutions for advanced inverterized appliance motor control. irmcf171 contains two computation engines integrated into one monolithic chip. one is the flexible motion control engine (mce tm ) for sensorless control of permanent magnet or induction motors; the other is an 8-bit high-speed microcontroller (8051). the user can program a motion control algorithm by connecting control elements using a graphic compiler. key components of the complex sensorless control algorithms, such as the angle estimator, are prov ided as complete pre-defined control blocks. a unique analog/digital circuit and algorithm fully supports singl e or leg shunt current reconstruction. the mce and 8051 microcontroller communicate via dual port ram for signal monitoring and command input. an advanced graphic compiler for the mce tm is seamlessly integrated into the matl ab/simulink environment, while third party jtag- based emulator tools are supported for 8051 software development including a flash programmer. irmcf171 comes in a 48 pin qfp package. features ? mce tm (flexible motion control engine) - dedicated computation engine for high efficiency sinusoidal sensorless motor control ? built-in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits ? supports induction machine and both interior and surface permanent magnet motor sensorless control ? loss minimization space vector pwm ? two-channel analog output (pwm) ? embedded 8-bit high speed microcontroller (8051) for flexible i/o and man-machine control ? jtag programming port for emulation/debugger ? serial communication interface (uart) ? i2c/spi serial interface ? three general purpose timers/counters ? two special timers: periodic timer, capture timer ? watchdog timer with independent internal clock ? internal 64 kbyte flash memory ? 5v tolerant i/o ? 3.3v single supply product summary maximum clock input (f crystal ) 60 mhz maximum internal clock (sysclk) 120mhz maximum 8051 clock (8051clk) 30mhz sensorless control computation time 35 sec@100mhz mce tm computation data range 16 bit signed 8051 program flash 52kb 805/mce data ram 4kb mce program ram 12kb gatekill latency (digital filtered) 2 sec pwm carrier frequency 20 bits/ sysclk a/d input channels 7 a/d converter resolution 12 bits a/d converter conversion speed 2 sec analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps number of digital i/o (max) 14 package (lead free) qfp48 typical 3.3v operating current 30ma base part number package type standard pack orderable part number form quantity irmcf171 lqfp48 tape and reel 2000 irmcf171tr irmcf171 lqfp48 tray 2500 irmcf171ty release datasheet rev. a
irmcf171 2 www.irf.com ? 2013 international rectifier april 20, 2013 table of contents 1 overview ...................................................................................................................... . 5 2 pinout ........................................................................................................................ ... 6 3 irmcf171 block diagram and main func tions ............................................................ 7 4 application connection and pin func tion ....................................................................... 9 4.1 8051 peripheral in terface group.................................................................................. 10 4.2 motion peripheral in terface gr oup ............................................................................... 11 4.3 analog interface group ................................................................................................ 11 4.4 power interface group ................................................................................................. 12 4.5 test interf ace gr oup .................................................................................................... 12 5 dc characteri stics ...................................................................................................... 13 5.1 absolute maximu m ratings ......................................................................................... 13 5.2 system clock frequency and power consum ption ..................................................... 13 5.3 digital i/o dc char acteristics ...................................................................................... 14 5.4 pll and oscillator dc characteri stics ......................................................................... 15 5.5 analog i/o dc char acteristics ..................................................................................... 15 5.6 under voltage lockout dc characteri stics .................................................................. 16 5.7 itrip comparator dc characteristics .............................................................................. 16 5.8 cmext and aref ch aracterist ics .............................................................................. 16 6 ac characte risti cs ...................................................................................................... 17 6.1 digital pll ac characterist ics ..................................................................................... 17 6.2 analog to digital converter ac characte ristics ........................................................... 18 6.3 op amp ac char acterist ics ......................................................................................... 19 6.4 sync to svpwm and a/d conversion ac timing ...................................................... 20 6.5 gatekill to svpwm ac timi ng ............................................................................... 21 6.6 itrip ac timing ............................................................................................................. 2 1 6.7 interrupt ac timing ...................................................................................................... 22 6.8 i 2 c ac timi ng .............................................................................................................. 23 6.9 spi ac ti ming ............................................................................................................. 24 spi write ac timing ........................................................................................................... 24 spi read ac timing .......................................................................................................... 25 6.10 uart ac ti ming ...................................................................................................... 26 6.11 capture input ac timi ng ...................................................................................... 27 6.12 jtag ac ti ming ....................................................................................................... 28 7 i/o structure ............................................................................................................... 2 9 8 pin list ...................................................................................................................... .. 32 9 package dimens ions .................................................................................................. 34 10 part marking in formation ............................................................................................ 35 11 qualification information ? ........................................................................................... 35 ?
irmcf171 3 www.irf.com ? 2013 international rectifier april 20, 2013 list of tables table 2. absolute maximum ratings ....................................................................................... 13 table 3. system clock fr equency ........................................................................................... 13 table 4. digital i/o dc characteri stics .................................................................................... 14 table 5 pll dc char acteristics .............................................................................................. 1 5 table 6. analog i/o dc characteri stics ................................................................................... 15 table 7. uvcc dc ch aracterist ics ........................................................................................... 16 table 8. itrip dc characteri stics ............................................................................................. . 16 table 9. cmext and aref dc characte ristics ...................................................................... 16 table 10. pll ac ch aracteristics ............................................................................................ 1 7 table 11 . a/d converter ac characte risti cs .......................................................................... 18 table 12 current sensing op amp ac charac teristics ........................................................... 19 table 13. sync ac c haracterist ics ........................................................................................ 20 table 14. gatekill to svpwm ac ti ming ........................................................................... 21 table 15. itrip ac ti ming ..................................................................................................... .... 21 table 16. interrupt ac timing .................................................................................................. 22 table 17. i 2 c ac timi ng .......................................................................................................... 23 table 18. spi writ e ac timing ................................................................................................ 24 table 19. spi read ac timing ................................................................................................ 25 table 20. uart ac timing ..................................................................................................... 26 table 21. capture ac timing .............................................................................................. 27 table 22. jtag ac ti ming ...................................................................................................... 28 table 23. pi n list ............................................................................................................ ......... 33
irmcf171 4 www.irf.com ? 2013 international rectifier april 20, 2013 list of figures figure 1. typical application bl ock diagram usi ng irmcf171 ................................................. 5 figure 2. pinout of irmcf171 .................................................................................................. . 6 figure 3. irmcf171 block diagr am .......................................................................................... 7 figure 4. irmcf171 leg shunt connection diagram ............................................................... 9 figure 5. irmcf171 single shunt connection diagram ......................................................... 10 figure 6. crystal circuit example ............................................................................................. 17 figure 7. voltage droop and s/h hold time .............................................................................. 18 figure 8 op amp out put capacit or ........................................................................................... 19 figure 9. sy nc timi ng ......................................................................................................... .... 20 figure 10. gateki ll timing .................................................................................................... ..... 21 figure 11. it rip ti ming ....................................................................................................... ..... 21 figure 12. interrupt timing ........................................................................................................ 22 figure 13. i 2 c timing ............................................................................................................... 23 figure 14. spi write timing ....................................................................................................... 24 figure 15. spi read timing .................................................................................................... ... 25 figure 16. uart timing ........................................................................................................ ... 26 figure 17. capt ure ti ming .................................................................................................... 27 figure 18. jt ag ti ming ........................................................................................................ .... 28 figure 19. pwmul/pwmuh/pwmvl/ pwmvh/pwmwl/pw mwh output ............................. 29 figure 20. all digital i/o ex cept motor pw m output ................................................................. 29 figure 21. reset, gatekill i/o ........................................................................................... 29 figure 22. a nalog in put........................................................................................................ .... 30 figure 24 analog operational amplifie r output and aref i/o struct ure .................................. 30 figure 25. vss,avss pi n i/o stru cture ................................................................................... 30 figure 26. vdd1,vddcap pin i/o structure ............................................................................ 31 figure 27. xtal0/xtal1 pins stru cture .................................................................................. 31
irmcf171 5 www.irf.com ? 2013 international rectifier april 20, 2013 1 overview irmcf171 is a new generation international rectifier in tegrated circuit device primarily designed as a one-chip solution for complete inverterized appliance motor cont rol applications. unlike a traditional microcontroller or dsp, the irmcf171 provides a built-in closed loop sensor less control algorithm using the unique flexible motion control engine (mcetm) for permanent magnet motors as well as induction motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmcf171 also employs a un ique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to elimi nate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulinktm development environment. sequencing, user interface, host communication, and upper layer control tasks can be impl emented in the 8051 high-speed 8-bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application sc hematic using the irmcf171. irmcf171 contains 64 kbytes of flash program memory . the irmck171 contains 32 kbytes otp memory and is intended for high volume production purposes while the irmcf171 is intended for flexible volume production. both the flash and rom versions come in a 48-pin qfp package with identical pin config uration to facilitate pc board layout and transition to mass production. irmcf171 power supply irs2336 d pm motor ipm or spm or im motor passive emi fillter digital i/o analog input host communication (rs232c) appliance pm motor drive 3.3v gate signal 15 v eeprom 6 2 8 galvanic isolation optional figure 1. typical application block diagram using irmcf171
irmcf171 6 www.irf.com ? 2013 international rectifier april 20, 2013 2 pinout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 16 3 12 4 11 5 6 7 8 9 10 2 1 xtal0 xtal1 p1.1/rxd p1.2/txd vdd1 vss vddcap p1.3/sync/sck p1.4/cap p3.2/int0 34 35 36 33 46 37 45 38 44 43 42 41 40 39 47 48 vss vddcap avss aref p2.7/aopwm1 pwmuh pwmvh pwmwh pwmul pwmvl pwmwl gatekill ifbo if b+ ifb- reset p1.5 tck tdi/p5.1 tdo tms/p5.2 sda/cs0 scl/so-si irmcf171 (top view) ain2 cmext p2.0/nmi p1.0/t2 p3.0/cs1 13 ain3 ain4 vdd1 ain1 ain0 ain5+ ain5- ain5o p3.3/int1 p3.1/aopwm2 figure 2. pinout of irmcf171
irmcf171 7 www.irf.com ? 2013 international rectifier april 20, 2013 3 irmcf171 block diagram and main functions irmcf171 block diagram for leg shunt mode is shown in figure 3. motion control sequencer dual port ram 2 kb mce program ram 12 kb program flash 64 kb 8bit up address/data bus motion control bus a/d mux s/h d/a (pwm) timer counnter 0,1,2 watchdog timer motion control modules uart i2 c snd rcv 6 low loss svpwm ain0 gatekill to igbt gate drive flexible motion control engine (mce) monitoring host interface digital i/os 8bit (8051) microcontroller ain1 ain2 jtag emulator debugger 4 freq synthesizer 2 ceramic resonator (4mhz) 20mhz ain3 analog input 2 capture interrupt control single shunt motor current reconstruction from shunt resistor speed command port 1 scl sda port 2 port 3 ain4 8bit cpu core local ram 2 kb 120mhz ifb 3 ain5 3 figure 3. irmcf171 block diagram irmcf171 contains the following functions for sensorless ac motor control applications: motion control engine (mce tm ) ? sensorless foc (complete sensorless field oriented control) ? proportional plus integral block ? low pass filter ? differentiator and lag (high pass filter) ? ramp ? limit ? angle estimate (sensorless control) ? inverse clark transformation ? vector rotator ? bit latch ? peak detect ? transition ? multiply-divide (signed and unsigned) ? adder ? divide (signed and unsigned) 8051 microcontroller ? two 16 bit timer/counters ? one 16 bit periodic timer ? one 16 bit watchdog timer ? one 16 bit capture timer ? up to 14 discrete digital i/os ? seven-channel 12 bit a/d o buffered (current sensing) two channels (0 ? 1.2v input) o unbuffered five channels (0 ? 1.2v input) ? jtag port (4 pins) ? up to two channels of analog output (8 bit pwm) ? uart ? i 2 c/spi port ? 2k byte data ram
irmcf171 8 www.irf.com ? 2013 international rectifier april 20, 2013 ? subtractor ? comparator ? counter ? accumulator ? switch ? shift ? atan (arc tangent) ? function block (any curve fitting, nonlinear function) ? 16 bit wide logic operations (and, or, xor, not, negate) ? mce tm program memory and dual port ram (6k byte) ? mce tm control sequencer ? 64k byte flash memory
irmcf171 9 www.irf.com ? 2013 international rectifier april 20, 2013 4 application connection and pin function figure 4 shows the application connections in leg shunt mode. figure 5 shows the application connections in single shunt mode. p1 .2 /txd p1 .1/ rxd p1.3/ sync/sck xtal0 pw muh pw mul pwmvh pw mvl pw mw h pwmwl gatekill ain0 ? ain4 host microcontroller (rs232c) digital i/o control system clock 4m hz crystal analog output xtal1 p1.4/cap p 3.0 /cs1 reset p5.1/ tdi jtag control (flash programming & emulation) tck p5 .2/ tms tdo av r ef ifbc+ ifbc- ifbco analog inputs (0- 1 .2v ) avdd 1. 8v avss vdd1 3. 3v vss cmext ain5 + ain 5- ain5 o optional exter nal voltage refer ence ( 0 .6v ) p2 .7/ aopw m1 scl /so-si sda/ cs0 other communication (i 2 c) frequency synthesizer rs232 c i 2 c/spi port1 port2 reset pwm1 jtag interface low loss space vector pwm s/h s/h 8051 cpu dual port memory (2 kb) & mce memory (12 kb) motion control modules motion control sequencer 12bit a/d & mux system clock local ram (2 kb) program flash (64 kb) system reset watchdog timer timers irmcf171 aref port3 p 1.0 /t2 p1 .5 p2 .0/nmi p 3.2 /int0 5 3. 3v 1.8v voltage regulator vddcap 3. 3v p 3.3 /int1 motor hvic gate drive irs2336 d av r ef single shunt current sensing p3 .1/ aopw m2 pwm1 figure 4. irmcf171 leg shunt connection diagram
irmcf171 10 www.irf.com ? 2013 international rectifier april 20, 2013 p1 .2 /txd p1 .1/ rxd p1.3/ sync/sck xtal0 pw muh pw mul pwmvh pw mvl pw mw h pwmwl gatekill ain0 ? ain4 host microcontroller (rs232c) digital i/o control system clock 4m hz crystal analog output xtal1 p1 .4/ cap p 3.0 /cs1 reset p5.1/ tdi jtag control (flash programming & emulation) tck p5 .2/ tms tdo av r ef ifbc+ ifbc- ifbco analog inputs (0- 1 .2v ) avdd 1. 8v avss vdd1 3. 3v vss cmext ain5 + ain 5- ain5 o optional exter nal voltage refer ence ( 0 .6v ) p2 .7/ aopw m1 scl /so-si sda/ cs0 other communication (i 2 c) frequency synthesizer rs232 c i 2 c/spi port1 port2 reset pwm1 jtag interface low loss space vector pwm s/h s/h 8051 cpu dual port memory (2 kb) & mce memory (12 kb) motion control modules motion control sequencer 12bit a/d & mux system clock local ram (2 kb) program flash (64 kb) system reset watchdog timer timers irmcf171 aref port3 p 1.0 /t2 p1.5 p2 .0/nmi p 3.2 /int0 5 3. 3v 1.8v voltage regulator vddcap 3. 3v p 3.3 /int1 motor hvic gate drive irs2336 d av r ef single shunt current sensing p3 .1/ aopw m2 buffered analog input pwm2 figure 5. irmcf171 single shunt connection diagram 4.1 8051 peripheral interface group uart interface p1.2/txd output, transmit data from irmcf171 p1.1/rxd input, receive data to irmcf171 discrete i/o interface p1.0/t2 input/output port 1.0, can be configured as timer/counter 2 input p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, c an be configured as txd output p1.3/sync/sck input/output port 1.3, can be configured as syn c output or spi clock output p1.4/cap input/output port 1.4, can be configured as capture timer input p1.5 input/output port 1.5 p2.0/nmi input/output port 2.0, can be c onfigured as non-maskable interrupt input p2.7/aopwm1 input/output port 2.7, c an be configured as aopwm1 output p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 p3.1/aopwm2 input/output port 3.1, c an be configured as aopwm2 output p3.2/nint0 input/output port 3.2, can be configured as int0 input p3.3/nint1 input/output port 3.3, can be configured as int1 input p5.1/tdi input port 5.1, configured as jtag port by default
irmcf171 11 www.irf.com ? 2013 international rectifier april 20, 2013 p5.2/tms input port 5.2, confi gured as jtag port by default analog output interface p2.7/aopwm1 input/output, can be configured as 8-bit pwm output 1 with programmable carrier frequency p3.1/aopwm2 input/output, can be configured as 8-bit pwm output 2 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset input and output, system reset, doesn?t require external rc time constant i 2 c interface scl/so-si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 i 2 c/spi interface scl/so-si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 p1.3/sync/sck input/output port 1.3, can be configured as syn c output or spi clock output p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal, internally pulled down by 58k ?, configured high true at a power up pwmul output, pwm phase u low side gate signal, internally pulled down by 58k ?, configured high true at a power up pwmvh output, pwm phase v high side gate signal, internally pulled down by 58k ?, configured high true at a power up pwmvl output, pwm phase v low side gate signal, internally pulled down by 58k ?, configured high true at a power up pwmwh output, pwm phase w high side gate signal, internally pulled down by 58k ?, configured high true at a power up pwmwl output, pwm phase w low side gate signal, internally pulled down by 58k ?, configured high true at a power up pfcpwm output, pfcpwm output signal, internally pulled up by 70k ? , configured low true at a power up fault gatekill input, upon assertion this negates all six pwm signals, active low, internally pulled up by 70k ? 4.3 analog interface group avss analog power return, (analog internal 1.8v power is shared with vddcap) aref 0.6v buffered output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. ifb+ input, operational amplifier positive input for shunt resistor current sensing
irmcf171 12 www.irf.com ? 2013 international rectifier april 20, 2013 ifb- input, operational amplifier negative in put for shunt resistor current sensing ifbo output, operational amplifier output for shunt resistor current sensing ain0 input, analog input channel 0 (0 ? 1.2 v) , typically configured for dc bus voltage input ain1 input, analog input cha nnel 1 (0 ? 1.2 v), needs to be pulled down to avss if unused ain2 input, analog input cha nnel 2 (0 ? 1.2 v), needs to be pulled down to avss if unused ain3 input, analog input cha nnel 3 (0 ? 1.2 v), needs to be pulled down to avss if unused ain4 input, analog input cha nnel 4 (0 ? 1.2 v), needs to be pulled down to avss if unused ain5+ input, operational amplifier positive input for shunt resistor current sensing ain5- input, operational amplifier negative in put for shunt resistor current sensing ain5o output, operational amplifier output fo r ain5 output, there is a single sample/hold circuit on the output 4.4 power interface group vdd1 digital power (3.3v) vddcap internal 1.8v output, requires capacitors to the pin. shared with analog power pad internally note: the internal 1.8v supply is not design ed to power any external circuits or devices. only capacitors shoul d be connected to this pin. vss digital common 4.5 test interface group p5.2/tms jtag test mode input or input digital port tdo jtag data output p5.1/tdi jtag data input, or input digital port tck jtag test clock
irmcf171 13 www.irf.com ? 2013 international rectifier april 20, 2013 5 dc characteristics 5.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage -0.3 v - 3.6 v respect to vss v ia analog input voltage -0.3 v - 1.98 v respect to avss v id digital input voltage -0.3 v - 6.0 v respect to vss t a ambient temperature -40 ? c - 85 ? c t s storage temperature -65 ? c - 150 ? c table 1. absolute maximum ratings caution: stresses beyond those listed in ?absolute ma ximum ratings? may cause permanent damage to the device. these are stress ratings only and function of t he device at these or any ot her conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 system clock frequenc y and power consumption c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25 ? c. symbol parameter min typ max unit sysclk system clock 32 - 120 mhz p d power consumption 100 1) - mw table 2. system clock frequency note 1) the value is based on the condition of mce clock=120mhz, 8051 clock 30mhz with a actual motor running by a typical mce application program and 8051 code.
irmcf171 14 www.irf.com ? 2013 international rectifier april 20, 2013 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v il input low voltage -0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3. digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so-si, sda/cs0 pins. (3) applied to all digital i/o pins except scl/so-si and sda/cs0 pins.
irmcf171 15 www.irf.com ? 2013 international rectifier april 20, 2013 5.4 pll and oscillator dc characteristics c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25 ? c. symbol parameter min typ max condition v il osc oscillator (xtal0,1) input low voltage 0 - 0.2* v ddcap v ddcap = voltage at vddcap pin v ih osc oscillator (xtal0,1) input high voltage 0.8* v ddcap - v ddcap v ddcap = voltage at vddcap pin table 4 pll dc characteristics 5.5 analog i/o dc characteristics - op amps for current sensing (i fb+,ifb-,ifbo, ain5+,ain5-,ain5o) c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25 ? c. symbol parameter min typ max condition v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested between ifbo and ifb- op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5. analog i/o dc characteristics note: (1) data guaranteed by design.
irmcf171 16 www.irf.com ? 2013 international rectifier april 20, 2013 5.6 under voltage lockout dc characteristics unless specified, ta = 25 ? c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 2.78 v 3.04 v 3.23 v (1) uv cc- uvcc negative going threshold 2.78 v 2.97 v 3.23 v uv cc h uvcc hysteresys - 73 mv - (1) table 6. uvcc dc characteristics note: (1) data guaranteed by design. 5.7 itrip comparator dc characteristics unless specified, vdd1=3.3v, ta = 25 ? c. symbol parameter min typ max condition itrip + itrip positive going threshold - 1.22v - v dd1 = 3.3 v itrip - itrip negative going threshold - 1.10v - v dd1 = 3.3 v itriph itrip hysteresys - 120mv - table 7. itrip dc characteristics 5.8 cmext and aref characteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv v vdd1 = 3.3 v v aref buffer output voltage 495 mv 600 mv 700 mv v vdd1 = 3.3 v ?v o load regulation (v dc -0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 8. cmext and aref dc characteristics note: (1) data guaranteed by design.
irmcf171 17 www.irf.com ? 2013 international rectifier april 20, 2013 6 ac characteristics 6.1 digital pll ac characteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 9. pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 =15pf c 2 =15pf figure 6. crystal circuit example
irmcf171 18 www.irf.com ? 2013 international rectifier april 20, 2013 6.2 analog to digital converter ac characteristics unless specified, ta = 25 ? c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 10 . a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage figure 7. voltage droop and s/h hold time
irmcf171 19 www.irf.com ? 2013 international rectifier april 20, 2013 6.3 op amp ac characteristics unless specified, ta = 25 ? c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/ sec - vdd1 = 3.3 v, cl = 33 pf (1) op imp op input impedance - 10 8 ? - (1) (2) t set settling time - 400 ns - vdd1 = 3.3 v, cl = 33 pf (1) table 11 current sensing op amp ac characteristics note: (1) data guaranteed by design. (2) to guarantee stability of the oper ational amplifier, it is recomm ended to load the output pin by a capacitor of 47pf, see figure 8. here only the singl e shunt current amplifier is shown but all op amp outputs should be loaded with this capacitor value. avref ifb + ifb- ifbo irmcf171 ic external com ponents 47 pf figure 8 op amp output capacitor
irmcf171 20 www.irf.com ? 2013 international rectifier april 20, 2013 6.4 sync to svpwm and a/d conversion ac timing sync iu,iv, iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 figure 9. sync timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0-4, adch, adcl analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 12. sync ac characteristics note: (1) ain1 ? ain5 channels are c onverted once every 5 sync events
irmcf171 21 www.irf.com ? 2013 international rectifier april 20, 2013 6.5 gatekill to svpwm ac timing gatekill pwmux,pwmvx,pwmwx t wgk t dgk figure 10. gatekill timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 13. gatekill to svpwm ac timing 6.6 itrip ac timing itrip pw muh, pw mul, pw mvh,pw mvh, pw mw h, pw mw l t itr ip figure 11. itrip timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t itrip itrip propagation delay - - 100(sysclk)+1.0usec sysclk+usec table 14. itrip ac timing
irmcf171 22 www.irf.com ? 2013 international rectifier april 20, 2013 6.7 interrupt ac timing p3 .2/ int0 p3 .3/ int1 internal progr am counter internal vector fetch t wint t dint figure 12. interrupt timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 15. interrupt ac timing
irmcf171 23 www.irf.com ? 2013 international rectifier april 20, 2013 6.8 i 2 c ac timing scl sda t i2st1 t i2 st 2 t i2 w setu p t i2 c l k t i2whold t i2rsetup t i2rhold t i2 c l k t i2en1 t i2en2 figure 13. i 2 c timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 16. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
irmcf171 24 www.irf.com ? 2013 international rectifier april 20, 2013 6.9 spi ac timing spi write ac timing p1. 3/sync /sck scl/s o-si t spic l k t wrdelay t cshold sda /cs0 p3. 0/int2/cs1 t cshigh bit 7(msb) bit 0(lsb ) t spic l kh t t spic l kl t t csdelay figure 14. spi write timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 17. spi write ac timing
irmcf171 25 www.irf.com ? 2013 international rectifier april 20, 2013 spi read ac timing p1. 3/sync /sck scl/ so-si t spic l k t rdsu t cshold sda /cs0 p3. 0/int2/cs1 t cshigh bit 7(msb) bit 0(lsb ) t spic l kh t t spic l kl t t csrd t rdhold figure 15. spi read timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 18. spi read ac timing
irmcf171 26 www.irf.com ? 2013 international rectifier april 20, 2013 6.10 uart ac timing txd rxd data and parity bit start bit t bau d stop bit t uartfil figure 16. uart timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 19. uart ac timing note: (1) each bit including start and stop bit is sampled thr ee times at center of a bi t at an interval of 1/16 t baud . if three sampled values do not agree, th en uart noise error is generated.
irmcf171 27 www.irf.com ? 2013 international rectifier april 20, 2013 6.11 capture input ac timing p1. 4/cap crev(h,l) internal register t c aph igh t capclk t crdelay t caplow t cldelay clast (h,l) internal register t in td el ay interr upt vector fetch interr upt figure 17. capture timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 20. capture ac timing
irmcf171 28 www.irf.com ? 2013 international rectifier april 20, 2013 6.12 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms figure 18. jtag timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 21. jtag ac timing
irmcf171 29 www.irf.com ? 2013 international rectifier april 20, 2013 7 i/o structure the following figure shows the motor pwm out put (pwmuh/pwmul/pwmvh/pwmvl/pwmwh/pwmwl) figure 19. pwmul/pwmuh/pwmv l/pwmvh/pwmwl/pwmwh output the following figure shows the digital i/o structure except the motor pwm output figure 20. all digital i/o except motor pwm output the following figure shows reset and gatekill i/ o structure. 270 ? 6.0 v 6.0v reset gatekill circuit vdd1 (3.3v) 70 k ? pin vss figure 21. reset, gatekill i/o
irmcf171 30 www.irf.com ? 2013 international rectifier april 20, 2013 the following figure shows the analog input structure. 1 ? 6.0 v 6.0v analog input pin avss analog cir cuit vddcap(1.8 v) figure 22. analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6.0 v 6.0v analog out put pin avss analog cir cuit vddcap(1. 8v) figure 23 analog operational amplifier output and aref i/o structure the following figure shows t he vss,avss pin i/o structure pin vdd1 avdd 6.0 v figure 24. vss,avss pin i/o structure
irmcf171 31 www.irf.com ? 2013 international rectifier april 20, 2013 the following figure shows the vdd1,vddcap pin i/o structure pin vss 6.0v figure 25. vdd1,vddcap pin i/o structure the following figure shows the xtal0 and xtal1 pins structure 1 ? 6.0 v 6.0v pin vss vddcap(1. 8v) figure 26. xtal0/xtal1 pins structure
irmcf171 32 www.irf.com ? 2013 international rectifier april 20, 2013 8 pin list pin number pin name internal pull-up /pull-down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.0/t2 i/o discrete programmable i/o or timer/counter 2 input 4 scl/so-si i/o i 2 c clock output (open drain, need pull up) or spi data 5 sda/cs0 i/o i 2 c data (open drain, need pull up) or spi chip select 0 6 p1.3/sync/sck i/o discrete programmable i/o or sync output or spi clock output 7 p1.4/cap i/o discrete programma ble i/o or capture timer input 8 vdd1 p 3.3v digital power 9 vss p digital common 10 vddcap p internal 1.8v output, capacitor(s) to be connected 11 p2.0/nmi i/o discrete progra mmable i/o or non-maskable interrupt input 12 p3.2/int0 i/o discrete prog rammable i/o or interrupt 0 input 13 p2.7/aopwm1 i/o discrete programmable i/o or pwm 1 digital output 14 ain0 i analog input channel 0, 0-1.2v range, needs to be pulled down to avss if unused 15 ain1 i analog input channel 1, 0-1.2v range, needs to be pulled down to avss if unused 16 ain2 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 17 ain3 i analog input channel 3, 0-1.2v range, needs to be pulled down to avss if unused 18 ain4 i analog input channel 4, 0-1.2v range, needs to be pulled down to avss if unused 19 ifb- i single shunt current sensing op amp input (-) 20 ifb+ i single shunt current sensing op amp input (+) 21 ifbo o single shunt current sensing op amp output 22 cmext o unbuffered 0.6v output. capacitor needs to be connected. 23 aref o analog reference voltage output (0.6v) 24 ain5- i analog input channel 5, 0-1.2v range, needs to be pulled down to avss if unused 25 ain5+ i analog input channel 5, 0-1.2v range, needs to be pulled down to avss if unused 26 ain5o o analog output 5, 0-1.2v range, 27 avss p analog common 28 vddcap p internal 1.8v output, capacitor(s) to be connected 29 vdd1 p 3.3v digital power 30 vss p digital common 31 p3.1/aopwm2 i/o discrete programmable i/o or pwm 2 digital output 32 pwmwl 58 k ? pull down o pwm gate drive for phase w low side, configurable either high or low true. 33 pwmvl 58 k ? pull down o pwm gate drive for phase v low side, configurable either high or low true
irmcf171 33 www.irf.com ? 2013 international rectifier april 20, 2013 pin number pin name internal pull-up /pull-down pin type description 34 pwmul 58 k ? pull down o pwm gate drive for phase u low side, configurable either high or low true 35 pwmwh 58 k ? pull down o pwm gate drive for phase w high side, configurable either high or low true 36 pwmvh 58 k ? pull down o pwm gate drive for phase v high side, configurable either high or low true 37 pwmuh 58 k ? pull down o pwm gate drive for phase u high side, configurable either high or low true 38 p1.5 i/o discrete programmable i/o. 39 gatekill 70 k ? pull up i pwm shutdown input, configurable digital filter, active low input. 40 p3.0/int2/cs1 70 k ? pull up i/o discrete programmable i/o or external interrupt 2 input or spi chip select 1 41 p5.2/tms i jtag test mode input or input digital port 42 tdo o jtag test data output 43 p5.1/tdi i jtag test data input or input digital port 44 tck i jtag test clock 45 reset i reset, low tr ue, schmitt trigger input 46 p1.1/rxd i/o uart receiver input or discrete programmable i/o 47 p1.2/rxd i/o uart transmitter output or discrete programmable i/o 48 p3.3/int1 i/o interrupt 1 input or discrete i/o table 22. pin list
irmcf171 34 www.irf.com ? 2013 international rectifier april 20, 2013 9 package dimensions ?
irmcf171 35 www.irf.com ? 2013 international rectifier april 20, 2013 10 part marking information irmcf171 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier 11 qualification information ? qualification level industrial ?? (per jedec jesd 47e) moisture sensitivity level msl3 ??? (per ipc/jedec j-std-020c) esd machine model class b (per jedec standard jesd22-a114d) human body model class 2 (per eia/jedec standar d eia/jesd22-a115-a) rohs compliant yes ? qualification standards can be found at inter national rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales repr esentative for further information. ??? higher msl ratings may be available for the specif ic package types listed here. please contact your international rectifier sales representative for further information. revision history rev a (march 10, 2013) first revision
irmcf171 36 www.irf.com ? 2013 international rectifier april 20, 2013 data and specifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information

▲Up To Search▲

Price & Availability of IRMCF171-15

	To Download IRMCF171-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .