? semiconductor components industries, llc, 2015 january, 2015 ? rev. 2 1 publication order number: ncp81152/d ncp81152 synchronous buck dual mosfet driver the ncp81152 is a high?performance dual mosfet gate driver optimized to drive the gates of both high?side and low?side power mosfets in a synchronous buck converter. two drivers are co?packaged into a 2.5 mm x 3.5 mm qfn16 package that greatly reduces the footprint compared to two discrete drivers. adaptive anti?cross?conduction circuitry and power saving operation provides a low?switching?loss and high?efficiency solution for notebook systems. the under?voltage lockout function guarantees the outputs are low when the supply voltage is low. features ? adaptive anti?cross?conduction circuit ? integrated bootstrap diode ? zero cross detection ? floating top driver accommodates boost voltages up to 35 v ? output disable control turns off both mosfets ? under?voltage lockout ? power saving operation under light load conditions ? thermally enhanced package ? these are pb?free devices typical applications ? vcore power for notebook systems ? power systems for ddr and graphics device package shipping ? ordering information NCP81152MNTWG qfn16 (pb?free) 3000 / tape & reel qfn16 mn suffix case 485aw marking diagram www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. pin connections 1 81152 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 81152 alyw (note: microdot may be in either location) sw1 gnd1 drvl1 drvh2 sw2 gnd2 pwm1 en1 vcc1 bst2 pwm2 en2 vcc2 drvl2 bst1 drvh1 (top view) flag 116
ncp81152 www. onsemi.com 2 figure 1. block diagram bst2 pwm2 logic drvh2 sw2 anti?cross conduction vcc2 drvl2 vcc2 en2 uvlo zero cross detection bst1 pwm1 logic drvh1 sw1 anti?cross conduction vcc1 drvl1 vcc1 en1 uvlo zero cross detection
ncp81152 www. onsemi.com 3 table 1. pin descriptions pin no. symbol description 1, 5 bst1, bst2 floating bootstrap supply pin for high?side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 2, 6 pwm1, pwm2 control input. the pwm signal has three states: pwm = high enables the high?side fet; pwm = mid enables zero cross detection; pwm = low enables the low?side fet. 3, 7 en1, en2 logic input. three?state logic input: en = high enables the driver; en = mid goes into diode braking mode (both high?side and low?side gate drive signals are low); en = low disables the driver. 4, 8 vcc1, vcc2 power supply input. connect a bypass capacitor (0.1 f) from this pin to ground. 9, 13 drvl1, drvl2 low?side gate drive output. connect to the gate of the low?side mosfet. 10, 14 gnd1, gnd2 bias and reference ground. all signals are referenced to this node. 11, 15 sw1, sw2 switch node. connect this pin to the source of the high?side mosfet and drain of the low?side mosfet. 12, 16 drvh1, drvh2 high?side gate drive output. connect to the gate of the high?side mosfet. 17 flag thermal flag. there is no electrical connection to the ic. connect to ground plane. table 2. absolute maximum ratings pin symbol pin name v max v min vcc1, vcc2 main supply voltage input 6.5 v ?0.3 v bst1, bst2 bootstrap supply voltage 35 v wrt/ gnd 40 v 50 ns wrt/ gnd 6.5 v wrt/ sw ?0.3 v wrt/sw sw1, sw2 switching node (bootstrap supply return) 35 v 40 v 50 ns ?5 v ?10 v (200 ns) drvh1, drvh2 high side driver output bst+0.3 v ?0.3 v wrt/sw ?2 v (<200 ns) wrt/sw drvl1, drvl2 low side driver output vcc+0.3 v ?0.3 v dc ?5 v (<200 ns) pwm1, pwm2 drvh and drvl control input 6.5 v ?0.3 v en1, en2 enable pin 6.5 v ?0.3 v gnd1, gnd2 ground 0 v 0 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *all signals referenced to agnd unless noted otherwise. table 3. thermal information parameter symbol value unit thermal characteristic (note 1) r ja 29 c/w operating junction temperature range t j ?40 to +150 c operating ambient temperature range t a ?40 to +100 c maximum storage temperature range t stg ?55 to +150 c moisture sensitivity level ? qfn package msl 1 *the maximum package power dissipation must be observed. 1. 1 in 2 cu., 1 oz. thickness.
ncp81152 www. onsemi.com 4 table 4. ncp81152 driver electrical characteristics unless otherwise stated: ?40 c < t a < +100 c; vcc = 4.5 v ~ 5.5 v; bst?sw = 4.5 v ~ 5.5 v; bst = 4.5 v ~ 30 v; swn = 0 v ~ 21 v. parameter test conditions min typ max units supply voltage vcc1, vcc2 operation voltage 4.5 5.5 v undervoltage lockout (vcc1, vcc2) start threshold 3.8 4.35 4.5 v hysteresis 150 200 250 mv supply current normal mode i cc1 + i cc2 + i bst1 + i bst2 en1, en2 = 5 v, pwm1 & pwm2 oscillating at 100 khz, c load = 3 nf 9.4 ma shutdown mode i cc1 + i cc2 + i bst1 + i bst2 en1, en2 = gnd 22 40 a standby current 1 i cc1 + i cc2 + i bst1 + i bst2 en1, en2 = logic high, pwm1, pwm2 = logic low, no loading on drvh1/2 & drvl1/2 1.8 ma standby current 2 i cc1 + i cc2 + i bst1 + i bst2 en1, en2 = logic high, pwm1, pwm2 = logic high, no loading on drvh1/2 & drvl1/2 2.2 ma bootstrap diode forward voltage vcc = 5 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input input high 3.4 v mid?state 1.3 2.45 v input low 0.7 v zcd blanking timer 350 ns high side driver (drvh1, drvh2) output resistance, sourcing current bst ? sw = 5 v 0.9 1.7 output resistance, sinking current bst ? sw = 5 v 0.7 1.7 rise time, tr drvh vcc = 5 v, 3 nf load, bst ? sw = 5 v 16 25 ns fall time, tf drvh vcc = 5 v, 3 nf load, bst ? sw = 5 v 11 18 ns turn?off propagation delay, tpdl drvh c load = 3 nf 10 30 ns turn?on propagation delay, tpdh drvh c load = 3 nf 10 40 ns sw pull?down resistance sw to pgnd 45 k drvh pull?down resistance drvh to sw, v bst ?v sw = 0 v 45 k low side driver (drvl1, drvl2) output resistance, sourcing current 0.9 1.7 output resistance, sinking current 0.4 0.8 rise time, tr drvh c load = 3 nf 16 25 ns fall time, tf drvh c load = 3 nf 11 15 ns turn?off propagation delay, tpdl drvh c load = 3 nf 10 30 ns turn?on propagation delay, tpdh drvh c load = 3 nf 5 25 ns drvl pull?down resistance drvl to pgnd, vcc = pgnd 45 k
ncp81152 www. onsemi.com 5 table 4. ncp81152 driver electrical characteristics unless otherwise stated: ?40 c < t a < +100 c; vcc = 4.5 v ~ 5.5 v; bst?sw = 4.5 v ~ 5.5 v; bst = 4.5 v ~ 30 v; swn = 0 v ~ 21 v. parameter units max typ min test conditions enable input (en1, en2) input high 3.3 v mid?state 1.35 1.8 v input low 0.6 v normal mode bias current ?1 1 a propagation delay time 20 40 ns switch node (sw1, sw2) sw leakage current 20 a zero cross detection threshold voltage sw to ?20 mv, ramp slowly until bg goes off ?6 mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 5. pwm/en truth table pwm input zcd drvl drvh pwm high zcd reset low high pwm mid positive current through the inductor high low pwm mid zero or negative current through the inductor low low pwm low zcd reset high low enable at mid x low low pwm drvl drvh? sw 90% 10% 1 v 10% 90% 1 v 10% 90% 90% 10% figure 2. timing diagram tf drvl tpdl drvl tpdh drvh tr drvh tpdh drvl tr drvl tf drvh tpdl drvh
ncp81152 www. onsemi.com 6 pwm drvh?sw drvl il figure 3. logic diagram
ncp81152 www. onsemi.com 7 application information the ncp81152 is a high?performance dual mosfet gate driver optimized to drive the gates of both high?side and low?side power mosfets in a synchronous buck converter. t wo drivers are co?packaged into a 2.5 mm x 3.5 mm qfn16 package that greatly reduces the footprint compared to two discrete drivers. undervoltage lockout drvh and drvl are low until vcc reaches the vcc uvlo threshold, typically 4.35 v. when vcc reaches this threshold, the pwm signal controls the states of drvh and drvl. there is a 200 mv hysteresis on vcc uvlo. there are pull?down resistors on drvh, drvl and sw that prevent the gates of the mosfets from accumulating enough charge to turn on when the driver is powered off. three?state en signal placing en into a logic?high or logic?low turns the driver on and off, respectively, as long as vcc is greater than the uvlo threshold. the en threshold limits are specified in the electrical characteristics table in this datasheet. setting the en voltage to a mid?state level pulls both drvh and drvl low. setting en to the mid?state level can be used for body diode braking to quickly reduce the inductor current. by turning the ls fet off and having the current conduct through the ls fet body diode, the voltage at the switch node is at a greater negative potential compared to having the ls fet on. this greater negative potential on switch node allows there to be a greater voltage across the output inductor, since the opposite terminal of the inductor is connected to the converter output voltage. the larger voltage across the inductor causes there to be a greater inductor current slew rate, allowing the current to decrease at a faster rate. pwm input and zero cross detect (zcd) the pwm input, along with en and zcd, controls the state of drvh and drvl. when pwm is set high, drvh is set high after the adaptive non?overlap delay. when pwm is set low, drvl is set high after the adaptive non?overlap delay. when pwm is set to the mid?state, drvh is set low, and after the adaptive non?overlap delay, drvl is set high. drvl remains high until the zcd blanking time expires. when the timer expires, the voltage on the sw pin is monitored for zero cross detection (whether it has crossed the zcd threshold voltage). after zero cross is detected, drvl is set low. low?side driver the low?side driver is designed to drive a ground?referenced low?r ds(on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vcc and gnd pins. high?side driver the high?side driver is designed to drive a floating low?r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the sw pin. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. when the ncp81152 is starting up, the sw pin is held at ground, allowing the bootstrap capacitor to charge up to vcc through the bootstrap diode. when the pwm input is driven high, the high?side driver turns on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the sw pin rises. when the high?side mosfet fully turns on, sw settles to vin and bst settles to vin + vcc (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the high?side driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used for c bst . thermal considerations as power in the ncp81152 increases, it may be necessary to provide thermal relief. the maximum power dissipation supported by the device depends upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the ncp81152 has good thermal conductivity through the pcb, the junction temperature is relatively low with high power applications. the maximum d issipation the ncp81152 can handle is given by: p d(max) t j(max) t a r ja (eq. 1) since t j is not recommended to exceed 150 c, the ncp81152, soldered on to a 645 mm 2 copper area, using 1 oz. copper and fr4, can dissipate up to 4.3 w when the ambient temperature (t a ) is 25 c. the power dissipated by the ncp81152 can be calculated from the following equation: p d vcc (n hs qg hs n ls qg ls ) f i standby (eq. 2) where n hs and n ls are the number of high?side and low?side fets, respectively, qg hs and qg ls are the gate charges of the high?side and low?side fets, respectively and f is the switching frequency of the converter.
ncp81152 www. onsemi.com 8 package dimensions qfn16, 2.5x3.5, 0.5p case 485aw issue o dim min max millimeters a a1 0.00 0.05 a3 b 0.20 0.30 d 2.50 bsc d2 0.85 1.15 e 3.50 bsc e2 e 0.50 bsc k 0.20 --- notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 0.20 ref b d2 l pin one e2 1 8 15 10 d e b a c 0.15 c 0.15 2x 2x e 2 16x 16x 0.10 c 0.05 c a b note 3 a 16x k a1 (a3) seating plane c 0.08 c 0.10 0.80 1.00 l 0.35 0.45 1.85 2.15 l1 detail a l alternate terminal constructions l ??? ??? *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.80 3.80 1.10 0.50 0.60 16x 0.30 16x dimensions: millimeters 1 reference top view side view note 4 c 0.15 c a b 0.15 c a b detail a bottom view e/2 l1 --- 0.15 2.10 pitch package outline on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81152/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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