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| this is information on a product in full production. june 2015 docid025022 rev 5 1/92 powerstep01 system-in-package integrating microstepping controller and 10 a power mosfets datasheet - production data features ? power system-in-package integrating a programmable microstepping controller and 8 n-channel power mosfets. ? operating voltage: 7.5 v - 85 v ? dual full bridge with r ds(on) = 16 m ? ? 10 a r.m.s. maximum output current ? adjustable output slew rate ? programmable speed profile ? up to 1/128 microstepping ? sensorless stall detection ? integrated voltage regulators ? spi interface ? low quiescent standby currents ? programmable non-dissipative overcurrent protection ? overtemperature protection applications ? high power bipolar stepper motor ? stage lighting ? surveillance systems ? textile and sewing machines ? pick and place machines description the powerstep01 is a a system-in-package integrating 8 n-channel 16 m ? mosfets for stepper applications up to 85 v with a spi programmable controller, providing fully digital control of the motion through a speed profile generation and positioning calculations. it integrates a dual low r ds(on) full bridge with embedded non-dissipative overcurrent protection. the device can operate with both voltage mode driving and advanced current control fitting different application needs. the digital control core can generate user defined motion profiles with acceleration, deceleration, speed or a target position easily programmed through a dedicated register set. all application commands and data registers, including those used to set analog values (i.e. current protection trip point, deadtime, pwm frequency, etc.) are sent through a standard 5-mbit/s spi. a very rich set of protections (thermal, low bus voltage, overcurrent and motor stall) make the powerstep01 ?bullet proof?, as required by the most demanding motor control applications. vfqfpn 11 x 14 mm table 1. device summary order code package packing powerstep01 vfqfpn 11 x 14 x 1.0 mm tray POWERSTEP01TR vfqfpn 11 x 14 x 1.0 mm tape and reel www.st.com
contents powerstep01 2/92 docid025022 rev 5 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 device power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 logic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 automatic full-step and boost modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 absolute position counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 programmable speed profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7 motor control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.1 constant speed commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.2 positioning commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.3 motion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.7.4 stop commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.7.5 step-clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.7.6 gountil and releasesw commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.8 internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.8.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.8.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.9 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.10 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 docid025022 rev 5 3/92 powerstep01 contents 92 7.11 vs undervoltage lockout (uvlo_adc) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.12 thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.13 reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.14 external switch (sw pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.15 integrated power mosfets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.16 programmable slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.17 deadtime and blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.18 integrated analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.19 supply management and internal voltage regulators . . . . . . . . . . . . . . . . 36 7.20 busy/sync pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.21 flag pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 phase current control: voltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1 pwm sinewave generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2 sensorless stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.3 low speed optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.4 bemf compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.5 motor supply voltage compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6 winding resistance thermal drift compensation . . . . . . . . . . . . . . . . . . . . 42 9 phase current control: current mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 46 9.4 torque regulation (setting the output current) . . . . . . . . . . . . . . . . . . . . . 47 10 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.1 register and flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.1.1 abs_pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.2 el_pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.3 mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.4 speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1.5 acc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 contents powerstep01 4/92 docid025022 rev 5 11.1.6 dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.7 max_speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.8 min_speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.9 fs_spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.10 kval_hold, kval_run, kval_acc and kval_dec . . . . . . . . . . . 56 11.1.11 int_speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1.12 st_slp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1.13 fn_slp_acc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.1.14 fn_slp_dec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.1.15 k_therm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.1.16 tval_hold, tval_run, tval_acc and tval_dec . . . . . . . . . . . . 58 11.1.17 t_fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.1.18 ton_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1.19 toff_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1.20 adc_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1.21 ocd_th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1.22 stall_th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1.23 step_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1.24 alarm_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.1.25 gatecfg1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.1.26 gatecfg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.1.27 config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1.28 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2 application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.1 command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.2 nop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.3 setparam (param, value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.4 getparam (param) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.2.5 run (dir, spd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.2.6 stepclock (dir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.2.7 move (dir, n_step) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.8 goto (abs_pos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.9 goto_dir (dir, abs_pos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.10 gountil (act, dir, spd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.2.11 releasesw (act, dir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.12 gohome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.13 gomark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 docid025022 rev 5 5/92 powerstep01 contents 92 11.2.14 resetpos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.15 resetdevice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.16 softstop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.2.17 hardstop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.2.18 softhiz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.2.19 hardhiz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2.20 getstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 vfqfpn package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 list of tables powerstep01 6/92 docid025022 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. typical application values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. cl values according to external oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. uvlo thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. thermal protection summarizing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. integrated mosfets characteristics at t j = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. output slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13. el_pos register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 14. min_speed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. fs_spd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. voltage amplitude regulation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. winding resistance thermal drift compensation coe fficient . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18. torque regulation by tval_h old, tval_acc, tval_dec and tval_run registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 19. t_fast register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 20. maximum fast decay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 21. minimum on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 22. minimum off-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. adc_out value and motor supply voltage compen sation feature . . . . . . . . . . . . . . . . . . 60 table 24. adc_out value and torque regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 25. overcurrent detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 26. stall detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27. step_mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 28. control mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 29. step mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30. sync clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 31. sync clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 32. alarm_en register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 33. gatecfg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 34. igate parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 35. tcc parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 36. tboost parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 37. gatecfg2 register (voltage mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 38. tdt parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 39. tblank parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 40. config register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 41. oscillator management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 42. external switch hard stop interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 43. overcurrent event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 44. programmable vcc voltage regulator output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 45. programmable uvlo thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 table 46. motor supply voltage compensation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 47. pwm frequency: integer division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 docid025022 rev 5 7/92 powerstep01 list of tables 92 table 48. pwm frequency: multiplication factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 49. available pwm frequen cies [khz]: 8 mhz oscillator frequency . . . . . . . . . . . . . . . . . . . . . 69 table 50. available pwm frequen cies [khz]: 16 mhz oscillator frequency . . . . . . . . . . . . . . . . . . . . 69 table 53. external torque regulation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 51. available pwm frequen cies [khz]: 24 mhz oscillator frequency . . . . . . . . . . . . . . . . . . . . 70 table 52. available pwm frequen cies [khz]: 32 mhz oscillator frequency . . . . . . . . . . . . . . . . . . . . 70 table 54. motor supply voltage compensation enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 55. switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 56. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 57. status register th_status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 58. status register dir bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 59. status register mot_status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 60. application commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 61. nop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 62. setparam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 63. getparam command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 64. run command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 65. stepclock command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 66. move command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 67. goto command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 68. goto_dir command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 69. gountil command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 70. releasesw command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 table 71. gohome command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 72. gomark command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 73. resetpos command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 74. resetdevice command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 75. softstop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 76. hardstop command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 77. softhiz command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 78. hardhiz command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 79. getstatus command structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 80. vfqfpn 11 x 14 x 1.0 - 9 die pads - 89 leads, , , , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 81. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 list of figures powerstep01 8/92 docid025022 rev 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. typical application schematic - voltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. typical application schematic - current mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5. charge pump circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. normal mode and microstepping (128 microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 7. automatic full-step switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. automatic full-step switching in boost mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. constant speed command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. positioning command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. motion command examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. oscin and oscout pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 13. overcurrent detection - principle scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 14. external switch connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 15. device supply pin management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. current distortion and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. bemf compensation curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. motor supply voltage compensation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. predictive current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. non-predictive current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. adaptive decay - fast decay tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. adaptive decay - switch from normal to slow + fast decay mode and vice versa . . . . . . . . 46 figure 23. fast decay tuning during the fa lling steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24. current sensing and reference voltage generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 25. spi timings diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 26. daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27. command with 3-byte argument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 28. command with 3-byte response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 29. command response aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 30. vfqfpn 11 x 14 x 1.0 - 9 die pads drawing - side view . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 31. vfqfpn 11 x 14 x 1.0 - 9 die pads drawing - bott om view . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 32. vfqfpn 11 x 14 x 1.0 - 9 die pads drawing - pin identifier . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 33. recommended footprint - suggested landpattern (overall view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 34. recommended footprint - lead land positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 35. recommended footprint - l and size and exposed pad positioning . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 36. recommended footprint - detail a and b drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 docid025022 rev 5 9/92 powerstep01 block diagram 92 1 block diagram figure 1. block diagram $ ' & & k d u j h s x p s 9 g g 6 3 , & . 6 ' 2 6 ' , 6 : 6 7 & . 9 ' ' $ ' & , 1 9 6 9 6 9 6 9 6 2 8 7 $ 6 ( 1 6 ( $ b 3 6 ( 1 6 ( % b 3 2 8 7 $ 2 8 7 % 2 8 7 % 9 & & & 3 9 % 2 2 7 * 1 ' 9 6 6 7 % < 5 ( 6 ( 7 ) / $ * & 6 % 8 6 < 6 < 1 & & 2 5 ( / 2 * , & 9 % 2 2 7 9 % 2 2 7 9 & & 9 & & 9 r o w d j h u h j 9 & & 9 6 5 ( * 9 & & 5 ( * ( [ w r v f g u l y h u d q g & o r f n j h q 2 6 & , 1 2 6 & 2 8 7 6 ( 1 6 ( $ b 6 6 ( 1 6 ( % b 6 0 + ] r v f l o o d w r u 7 h p s h u d w x u h v h q v l q j 9 5 ( * 9 r o w d j h u h j 9 5 ( * 2 y h u f x u u h q w g h w h f w l r q & x u u h q w f r q w u r o 9 % 2 2 7 9 % 2 2 7 9 & & 9 & & $ 0 y electrical data powerstep01 10/92 docid025022 rev 5 2 electrical data 2.1 absolute maximum ratings table 2. absolute maximum ratings symbol parameter test conditions value unit v dd logic interface supply voltage 5.5 v v reg logic supply voltage 3.6 v s motor supply voltage 95 v v cc low-side gate driver supply voltage 18 v v boot boot voltage 100 v ? v boot high-side gate driver supply voltage (v boot - v s ) 0 to 20 v v sreg internal v cc regulator supply voltage 95 v v ccreg internal v reg regulator supply voltage 18 v v out1a v out2a v out1b v out2b output voltage dc -5 to v boot v ac -15 to v boot i out1a i out2a i out1b i out2b output current dc 10 a r.m.s. sr out full bridge output slew rate (10% - 90%) 10 v/ns v adcin integrated adc input voltage range (adcin pin) -0.3 to 3.6 v v out_diff differential voltage between vboot, vs, out1a, out2a, pgnd and vboot, vs, out1b, out2b, pgnd pins 100 v v in logic input voltage range -0.3 to 5.5 v t op t s storage and operating junction temperature -40 to 150 c docid025022 rev 5 11/92 powerstep01 electrical data 92 2.2 recommended operating conditions table 3. recommended operating conditions symbol parameter test cond itions min. typ. max. unit v dd logic interface supply voltage 3.3 v logic outputs 3.3 v 5 v logic outputs 5 v reg logic supply voltage 3.3 v v s motor supply voltage v sreg 85 v v sreg internal v cc voltage regulator supply voltage v cc voltage internally generated v cc +3 v s v v cc, ext gate driver supply voltage v cc voltage imposed by external source (v sreg = v cc ) 7.5 15 v v ccreg internal v reg voltage regulator supply voltage v reg voltage internally generated 6.3 v cc v v adc integrated adc input voltage (adcin pin) 0v reg v electrical characteristics powerstep01 12/92 docid025022 rev 5 3 electrical characteristics v s = 48 v; v cc = 7.5 v; v dd = 3.3 v; t j = 25 c, unless otherwise specified. table 4. electrical characteristics symbol parameter test conditions min. typ. max. unit general v ccthon v cc uvlo turn-on threshold uvlo_val set high (1) 9.9 10.4 10.9 v uvlo_val set low (1) 6.5 6.9 7.3 v v ccthoff v cc uvlo turn-off threshold uvlo_val set high (1) 9.5 10 10.5 v uvlo_val set low (1) 5.9 6.3 6.7 v ? v bootthon v boot - v s uvlo turn-on threshold uvlo_val set high (1) 8.6 9.2 9.94 v uvlo_val set low (1) 5.7 6 6.35 v ? v bootthoff v boot - v s uvlo turn-off threshold uvlo_val set high (1) 8.2 8.8 9.65 v uvlo_val set low (1) 5.3 5.5 5.9 v v regthon v reg turn-on threshold (1) 2.8 3 3.18 v v regthoff v reg turn-off threshold (1) 2.2 2.4 2.5 v i vregqu undervoltage v reg quiescent supply current v ccreg = v reg < 2.2 v (1) 40 ? a i vregq quiescent v reg supply current v ccreg = v reg = 3.3 v internal oscillator selected (1) 3.8 ma i vsregq quiescent v sreg supply current v ccreg = v cc = 15 v 6.5 ma thermal protection t j(wrn)set thermal warning temperature 135 c t j(wrn)rec thermal warning recovery temperature 125 c t j(off)set thermal bridge shutdown temperature 155 c t j(off)rec thermal bridge shutdown recovery temperature 145 c t j(sd)set thermal device shutdown temperature 170 c t j(sd)rec thermal device shutdown recovery temperature 130 c charge pump v pump voltage swing for charge pump oscillator v cc v f pump,min minimum charge pump oscillator frequency (2) 660 khz f pump,max maximum charge pump oscillator frequency (2) 800 khz docid025022 rev 5 13/92 powerstep01 electrical characteristics 92 r pumphs charge pump high-side r ds(on) resistance 10 ? r pumpls charge pump low-side r ds(on) resistance 10 ? i boot average boot current 2.6 ma power outputs r ds(on) high-side and low-side on resistance v cc = 15 v at 25 c 16 21 m ? at 125 c 23 sr out output slew rate igate = 96 ma 980 v/ ? s igate = 32 ma 520 i dss leakage current out = v s 0.1 ma out = gnd -0.1 ma deadtime and blanking t dt programmable deadtime 2 tdt = '00000' 125 ns tdt =?11111? 4000 t blank programmable blanking time 2 tblank = '000' 125 ns tblank =?111? 1000 logic v il low level logic input voltage 0.8 v v ih high level logic input voltage 2 v i ih high level logic input current v in = 5 v, v dd = 5 v 1 a i il low level logic input current v in = 0 v, v dd = 5 v -1 a v ol low level logic output voltage (3) v dd = 3.3 v, i ol = 4 ma 0.3 v v dd = 5 v, i ol = 4 ma 0.3 v oh high level logic output voltage v dd = 3.3 v, i oh = 4 ma 2.4 v v dd = 5 v, i oh = 4 ma 4.7 r pucs cs pull-up resistor 430 k ? r pdrst stby/reset pull-down resistor 450 r pusw cs pull-up resistor 80 t high,stck step-clock input high time 300 ns t low,stck step-clock input low time 300 ns internal oscillator and external oscillator driver f osc,int internal oscillator frequency t j = 25 c -5% 16 +5% mhz f osc,ext programmable external oscillator frequency 832mhz table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit electrical characteristics powerstep01 14/92 docid025022 rev 5 v oscouth oscout clock source high level voltage internal oscillator 2.4 v v oscoutl oscout clock source low level voltage internal oscillator 0.3 v t roscout t foscout oscout clock sour ce rise and fall time internal oscillator 10 ns t high oscout clock source high ti me internal oscillator 31.25 ns t extosc internal to external oscillator switching delay 3ms t intosc external to internal oscillator switching delay 100 s spi f ck,max maximum spi clock frequency (4) 5mhz t rck t fck spi clock rise and fall time (4) 1s t hck t lck spi clock high and low time (4) 90 ns t setcs chip select setup time (4) 30 ns t holcs chip select hold time (4) 30 ns t discs deselect time (4) 625 ns t setsdi data input setup time (4) 20 ns t holsdi data input hold time (4) 30 ns t ensdo data output enable time (4) 95 ns t dissdo data output disable time (4) 95 ns t vsdo data output valid time (4) 35 ns t holsdo data output hold time (4) 0ns pwm modulators f pwm programmable pwm frequency (2) f osc = 32 mhz f_pwm_int=?11x? f_pwm_dec=?000? 5.6 khz f osc = 32 mhz f_pwm_int=?000? f_pwm_dec=?111? 125 khz n pwm pwm resolution 8 bit current control v ref, max maximum reference voltage 1000 mv v ref, min minimum reference voltage 7.8 mv table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit docid025022 rev 5 15/92 powerstep01 electrical characteristics 92 overcurrent protection v ocd programmable overcurrent detection voltage v ds threshold ocd_th = ?00000? 27 31 35 mv ocd_th = ?01001? 270 312.5 344 mv ocd_th = ?10011? 500 625 688 mv ocd_th = '11111' 800 1000 1100 mv t ocd,comp ocd comparator delay 100 200 ns t ocd,flag ocd to flag signal delay time 230 530 ns t ocd,sd ocd to shutdown delay time i gate = 4 ma, t cc = maximum 4200 6000 ns stall detection v stall programmable stall detection v ds voltage threshold stall_th = '11111' 1000 mv stall_th = '00000' 31 standby i stby standby mode supply current (vsreg pin) v cc = v ccreg = 7.5 v v sreg = 48 v 42 a v cc = v ccreg = 7.5 v v sreg = 18 v 37.5 i stby,reg standby mode supply current (vreg pin) 6a t stby,min minimum standby time 0.5 ms t logicwu logic power-on and wake-up time 500 s t cpwu charge pump power-on and wake-up time power bridges disabled, c p = 10 nf, c boot = 220 nf, v cc = 15 v 1ms internal voltage regulators v ccout internal v cc voltage regulator output voltage low (default), i cc = 10 ma 7.3 7.5 v high, i cc = 10 ma 14 15 v sreg, drop v sreg to v cc dropout voltage i cc = 50 ma 3 v p cc internal v cc voltage regulator power dissipation 2.5 w v regout internal v reg voltage regulator output voltage i reg = 10 ma 3.13 5 3.3 v v ccreg, drop v ccreg to v reg dropout voltage i reg = 50 ma 3 v i regout internal v reg voltage regulator output current 125 ma table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit electrical characteristics powerstep01 16/92 docid025022 rev 5 i regout,stby internal v reg voltage regulator output standby current 55 ma p reg internal v reg voltage regulator power dissipation 0.5 w integrated analog to digital converter n adc analog to digital converter resolution 5 bit v adc,ref analog to digital converter reference voltage 3.3 v f s analog to digital converter sampling frequency voltage mode (2) f pwm khz current mode (2) f osc /512 khz v adc,uvlo adcin uvlo threshold 1.05 1.16 1.35 v 1. guaranteed in the temperature range -25 to 125 c . 2. the value accuracy is dependent on oscillator frequen cy accuracy ( section 7.8 on page 29 ). 3. flag and busy open-drain outputs included. 4. see figure 25 on page 49 . table 4. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit docid025022 rev 5 17/92 powerstep01 pin connection 92 4 pin connection figure 2. pin connection (top view) 9 6 2 8 7 $ 2 8 7 $ 9 6 ( 3 $ ' ( 3 $ ' ( 3 $ ' ( 3 $ ' 6 ( 1 6 ( $ b 3 6 ( 1 6 ( $ b 3 6 ( 1 6 ( $ b 3 6 ( 1 6 ( $ b 3 6 ( 1 6 ( $ b 3 6 ( 1 6 ( $ b 3 2 8 7 $ 2 8 7 $ 2 8 7 $ 2 8 7 $ * 1 ' ( 3 $ ' 2 8 7 % 2 8 7 $ * 1 ' 2 6 & 2 8 7 2 6 & , 1 9 5 ( * 9 6 5 ( * 9 & & 5 ( * 9 & & & 3 9 % 2 2 7 9 6 $ ' & , 1 * 1 ' & 6 & . 6 ' , 9 ' ' , 2 6 ' 2 % 8 6 < ? 6 < 1 & ) / $ * 6 7 & . 6 : 6 7 % < ? 5 ( 6 ( 7 2 8 7 % 2 8 7 $ 6 ( 1 6 ( $ b 6 6 ( 1 6 ( % b 6 * 1 ' 9 6 2 8 7 % 2 8 7 % 9 6 ( 3 $ ' ( 3 $ ' ( 3 $ ' ( 3 $ ' ( 3 $ ' ( 3 $ ' ( 3 $ ' ( 3 $ ' 6 ( 1 6 ( % b 3 6 ( 1 6 ( % b 3 6 ( 1 6 ( % b 3 6 ( 1 6 ( % b 3 6 ( 1 6 ( % b 3 6 ( 1 6 ( % b 3 2 8 7 % 2 8 7 % 2 8 7 % 2 8 7 % $ 0 y pin list powerstep01 18/92 docid025022 rev 5 5 pin list table 5. pin description no. name type function 1, 2, 3, 4, 5, 6, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 86, 87, 88, 89, epad1, epad2, epad5, epad6 vs supply motor supply voltage (drain of the high-side mosfets) 38, 42, 53, epad4 outa1 power output half-bridge a1 output 22, 33, 37, epad3 outa2 power output half-bridge a2 output 65, 76, 80, epad7 outb1 power output half-bridge b1 output 7, 81, 85, epad8 outb2 power output half-bridge b2 output 8, 21, 59, epad9 gnd ground ground 34, 35, 36, 39, 40, 41, epad10, epad11 sensea_p sense (power) tail of full bridge a (source of the respective low-side mosfets) 20 sensea_s analog input current control comparator input 77, 78, 79, 82, 83, 84, epad12, epad13 senseb_p sense (power) tail of full bridge b (source of the respective low-side mosfets) 9 senseb_s analog input current control comparator input 60 vccreg power supply internal v reg voltage regulator supply voltage 62 vreg power supply logic supply voltage 13 vddio power supply logic interface supply voltage 61 vsreg power supply internal v cc voltage regulator supply voltage 58 vcc power supply gate driver supply voltage 63 oscin analog input oscillator pin 1. to connect an external oscillator or clock source. 64 oscout analog output oscillator pin 2. to connect an external oscillator. when the internal oscillator is used this pin can supply a 2/4/8/16 mhz clock. 57 cp output charge pump oscillator output 56 vboot power supply bootstrap voltage needed for driving the high-side power dmos of both bridges (a and b). 54 adcin analog input internal analog to digital converter input 55 vs power supply motor supply voltage 18 sw logical input external switch input pin 14 sdo logic output data output pin for serial interface docid025022 rev 5 19/92 powerstep01 pin list 92 12 sdi logic input data input pin for serial interface 11 ck logic input serial interface clock 10 cs logic input chip select input pin for serial interface 15 busy /sync open-drain output by default busy/sync pin is forced low when the device is performing a command. the pin can be programmed in order to generate a synchronization signal. 16 flag open-drain output status flag pin. an internal open-drain transistor can pull the pin to gnd when a programmed alarm condition occurs (step loss, ocd, thermal pre-warning or shutdown, uvlo, wrong command, non performable command). 19 stby /reset logic input standby and reset pin. low logic level puts the device in standby mode and reset logic. if not used, should be connected to v reg 17 stck logic input step clock input. table 5. pin description (continued) no. name type function typical applications powerstep01 20/92 docid025022 rev 5 6 typical applications table 6. typical application values name value c vspol 220 f c vs 220 nf c boot 470 nf c fly 47 nf c vsreg 100 nf c vcc 470 nf c vccreg 100 nf c vreg 100 nf c vregpol 22 f c vdd 100 nf d1 charge pump diodes r pu 39 k ? r a 1.8 k ? (v s = 85 v) r b 91 k ? (v s = 85 v) r sensea 0.1 ? (maximum i peak = 10 a) r senseb 0.1 ? (maximum i peak = 10 a) docid025022 rev 5 21/92 powerstep01 typical applications 92 figure 3. typical application schematic - voltage mode figure 4. typical application schematic - current mode outa1 outa2 outb1 outb2 vs vs cp vboot vsreg vcc vddio gnd vreg flag busy\sync stby\reset stck cs ck sdo sdi sw oscin oscout vccreg adcin vs sensea_p senseb_p powerstep01 c fly c vs c vcc c vccreg c vdd c vsreg c boot c vspol c vs v s c vreg c vregpol (10.5v - 85v) d1 motor sensea_s senseb_s r b r a r pu r pu host am16760v1 outa1 outa2 outb1 outb2 vs vs cp vboot vsreg vcc vddio gnd vreg flag busy\sync stby\reset stck cs ck sdo sdi sw oscin oscout vccreg adcin vs sensea_p senseb_p c fly c vs c vcc c vccreg c vd d c vs r e g c boot c vspol c vs v s c vr e g c vregpol ) v 5 8 - v 5 . 0 1 ( d1 motor sensea_s senseb_s r b r a r sensea r pu r pu host r senseb powerstep01 am16761v1 functional description powerstep01 22/92 docid025022 rev 5 7 functional description 7.1 device power-up during power-up, the device is under reset (a ll logic ios disabled and power bridges in high impedance state) until the following conditions are satisfied: ? v reg is greater than v regthon ? internal oscillator is operative ? stby /reset input is forced high. after power-up, the device state is the following: ? parameters are set to default ? internal logic is driven by internal oscillator and a 2- mhz clock is provided by the oscout pin ? bridges are disabled (high impedance). ? flag output is forced lo w (uvlo failure indication). after power-up, a period of t logicwu must pass before applying a command to allow proper oscillator and logic startup. any movement command makes the device exit from high z state (hardstop and softstop included). 7.2 logic i/o pins cs , ck, sdi, stck, sw and stby /reset are ttl/cmos 3.3 v to 5 v compatible logic inputs. pin sdo is a ttl/cmos compatible logic out put. vdd pin voltage imposes logical output voltage range. pins flag and busy /sync are open-drain outputs. sw and cs inputs are internally pulled up to v dd and stby /reset input is internally pulled down to ground. 7.3 charge pump to ensure the correct driving of the high-side integrated mosfets, a voltage higher than the motor power supply voltage needs to be applied to the vboot pin. the high-side gate driver supply voltage v boot is obtained through an os cillator and a few external components realizing a charge pump (see figure 5 ). docid025022 rev 5 23/92 powerstep01 functional description 92 figure 5. charge pump circuitry 7.4 microstepping the driver is able to divide the single step into up to 128 microsteps. stepping mode can be programmed by the step_sel paramete r in the step_mode register ( table 27 on page 61 ). in current mode driving the maximum microstepping resolution is 1/16 th of the step. step mode can only be changed when bridges are disabled. every time the step mode is changed, the electrical position (i. e. the poin t of microstepping sinewave that is generated) is reset to zero and the absolute position counter value ( section 7.5 ) becomes meaningless. figure 6. normal mode and microstepping (128 microsteps) v s d2 v cp f pump to high-side gate drivers v s cp v d1 c boot c fly d1 d2 vboot cp v dd v charge pump oscillator + v v s cp v d1 + v am12827v1 step 1 step 1 step 2step 3step 4 step 1 reset position step 1 step 2 step 3 step 4 normal driving microstepping phase a current phase b current phase a current phase b current microsteps 128 steps 128 steps 128 steps 128 steps reset position am12828v1 functional description powerstep01 24/92 docid025022 rev 5 automatic full-step and boost modes when motor speed is greater than a program mable full-step speed threshold, the device switches automatically to full- step mode; the driving mode re turns to microstepping when motor speed decreases below the full-step speed threshold. the switching between the microstepping and full-step mode and vice-versa is always performed at an electrical position multiple of ? /4 ( figure 7 and figure 8 ). full-step speed threshold is set through the related parameter in the fs_spd register ( section 11.1.9 on page 55 ). when the boost_mode bit of the fs_spd regist er is low (default), the amplitude of the voltage squarewave in full-step mode is equal to the peak of the voltage sinewave multiplied by sine( ? /4) ( figure 7 ). this avoids the current drop between the two driving modes. when the boost_mode bit of the fs_spd regi ster is high, the amplitude of the voltage squarewave in full- step mode is equal to the peak of the voltage sinewave ( figure 8 ). that improves the output current increasing the maximum motor torque. figure 7. automatic full-step switching in normal mode phase a phase b (2n+1) x /4 (2n+1) x /4 full-step microstepping microstepping v peak sin( /4 )x v peak am12829v1 docid025022 rev 5 25/92 powerstep01 functional description 92 figure 8. automatic full-step switching in boost mode 7.5 absolute position counter an internal 22-bit register (abs_pos) records all the motor motions according to the selected step mode; the stored value unit is e qual to the selected step mode (full, half, quarter, etc.). the position range is from -2 21 to +2 21 -1 steps (see section 11.1.1 on page 53 ). 7.6 programmable speed profiles the user can easily program a customiz ed speed profile defining independently acceleration, deceleration, maximum and minimum speed values by acc, dec, max_speed and min_speed regi sters respectively (see section 11.1.5 on page 54 , 11.1.6 on page 54 , 11.1.7 on page 54 and 11.1.8 on page 55 ). when a command is sent to the device, th e integrated logic generates the microstep frequency profile that performs a motor motion compliant to speed profile boundaries. all acceleration parameters are expressed in step/tick 2 and all speed parameters are expressed in step/tick; the unit of measur ement does not depend on the selected step mode. acceleration and deceleration parameters range from 2 -40 to (2 12 -2) 2 -40 step/tick 2 (equivalent to 14.55 to 59590 step/s 2 ). minimum speed parameter ranges from 0 to (2 12 - 1 ) 2 -24 step/tick (equivalent to 0 to 976.3 step/s). maximum speed parameter ranges from 2 -18 to (2 10 -1) 2 -18 step/tick (equivalent to 15.25 to 15610 step/s). phase a phase b (2n+1) x /4 (2n+1) x /4 full-step microstepping microstepping v peak v peak am12850v1 functional description powerstep01 26/92 docid025022 rev 5 7.7 motor control commands the powerstep01 can accept different types of commands: ? constant speed commands (run, gountil, releasesw) ? absolute positioning commands (goto, goto_dir, gohome, gomark) ? motion commands (move) ? stop commands (softstop, hardstop, softhiz, hardhiz). for detailed command descriptions refer to section 11.2 on page 73 . 7.7.1 constant speed commands a constant speed command produces a motion in order to reach and maintain a user- defined target speed starting from the prog rammed minimum speed (s et in the min_speed register) and with the programmed acceleration/de celeration value (set in the acc and dec registers). a new constant speed command can be requested anytime. figure 9. constant speed command examples 7.7.2 positioning commands an absolute positioning command produces a motion in order to reach a user-defined position that is sent to the device together with the command. the position can be reached performing the minimum path (minimum physic al distance) or forcing a direction (see figure 10 ). performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). note that with some speed profiles or positioning commands, the deceleration phase can start before the maximum speed is reached. am12856v1 spd1 spd2 spd3 spd4 run(spd2,fw) time speed (step frequency) run(spd3,fw) run(spd1,fw) run(spd4,bw) minimum speed minimum speed docid025022 rev 5 27/92 powerstep01 functional description 92 figure 10. positioning command examples 7.7.3 motion commands motion commands produce a motion in order to perform a user-defined number of microsteps in a user-defined direction that ar e sent to the device together with the command (see figure 11 ). performed motor motion is compliant to programmed speed profile boundaries (acceleration, deceleration, minimum and maximum speed). note that with some speed profiles or motion commands, the deceleration phase can start before the maximum speed is reached. figure 11. motion command examples 7.7.4 stop commands a stop command forces the motor to stop. stop commands can be sent anytime. the softstop command causes the motor to decelerate with a programmed deceleration value until min_speed value is reached an d then stops the moto r keeping the rotor position (a holding torque is applied). am12857v1 forward direction 0 -2 21 +2 21 -1 0 -2 21 +2 21 -1 present position target position present position target position goto(target pos) goto_dir(target pos,fw) programmed acceleration speed programmed maximum speed programmed minimum speed time programmed deceleration programmed number of microsteps programmed acceleration speed programmed maximum speed programmed minimum speed time programmed deceleration programmed number of microsteps note: with some acceleration/decelaration profiles the programmed maximum speed is never reached am15163v1 functional description powerstep01 28/92 docid025022 rev 5 the hardstop command stops the motor instantly, ignoring deceleration constraints and keeping the rotor position (a holding torque is applied). the softhiz command causes the motor to decelerate with a programmed deceleration value until the min_speed valu e is reached and then forces the bridges into high impedance state (no holding torque is present). the hardhiz command instantly forces the bridges into high impedance state (no holding torque is present). 7.7.5 step-clock mode in step-clock mode the motor motion is defined by the step-clock signal applied to the stck pin. at each step-clock rising edge, the motor is moved one microstep in the programmed direction and absolute position is consequently updated. when the system is in step-clock mode th e sck_mod flag in the status register is raised, the speed register is se t to zero and motor status is considered stopp ed regardless of the stck signal frequency (the mot_status parameter in the status register equal to ?00?). 7.7.6 gountil and releasesw commands in most applications the powe r-up position of the stepper motor is undefined, so an initialization algorithm driving the motor to a known position is necessary. the gountil and releasesw commands can be us ed in combination with external switch input (see section 7.14 on page 33 ) to easily initialize the motor position. the gountil command makes the motor run at ta rget constant speed until the sw input is forced low (falling edge). when this event oc curs, one of the following actions can be performed: ? abs_pos register is set to ze ro (home position) and the motor decelerates to zero speed (as a softstop command) ? abs_pos register value is stor ed in the mark register an d the motor decelerates to zero speed (as a softstop command). if the sw_mode bit of the config register is se t to ?0?, the motor do es not decelerate but it immediately stops (as a hardstop command). the releasesw command makes the motor run at a programmed minimum speed until the sw input is forced high (rising edge). when this event occurs, one of the following actions can be performed: ? abs_pos register is set to ze ro (home position) and the motor immediately stops (as a hardstop command) ? abs_pos register value is st ored in the mark register and the motor immediately stops (as a hardstop command). if the programmed minimum speed is less than 5 step/s, the motor is driven at 5 step/s. docid025022 rev 5 29/92 powerstep01 functional description 92 7.8 internal oscillator and oscillator driver the control logic clock can be supplied by t he internal 16-mhz osc illator, an external oscillator (crystal or ceramic reso nator) or a direct clock signal. these working modes can be selected by ext_clk and osc_sel parameters in the config register (see table 41 on page 66 ). at power-up the device st arts using the internal oscillator and provides a 2-mhz clock signal on the oscout pin. attention: in any case, before changing clock source configuration, a hardware reset is mandatory. switching to different clock configurations during operation may cause unexpected behavior. 7.8.1 internal oscillator in this mode the internal oscillator is activa ted and oscin is unused. if the oscout clock source is enabled, the oscout pin provides a 2, 4, 8 or 16-mhz clock signal (according to osc_sel value); otherwise it is unused (see figure 12 ). 7.8.2 external clock source two types of external clock source can be sele cted: crystal/ceramic resonator or direct clock source. four programmable clock frequencies ar e available for each external clock source: 8, 16, 24 and 32-mhz. when an external crystal/resonator is select ed, the oscin and oscout pins are used to drive the crystal/resonator (see figure 12 ). the crystal/resonator and load capacitors (c l ) must be placed as close as possible to the pins. refer to table 7 for the choice of the load capacitor value accord ing to the external oscillator frequency. if a direct clock source is used, it must be connected to the oscin pin and the oscout pin supplies the inverted oscin signal (see figure 12 ). the powerstep01 integrates a clock detection syst em that resets the device in case of the failure of the external clock source (direct or crystal/resonator). the monitoring of the clock source is disabled by default, it can be enabled setting high the wd_en bit in the table 7. cl values according to external oscillator frequency crystal/resonator freq. (1) 1. first harmonic resonance frequency. c l (2) 2. lower esr value allows dr iving greater load capacitors. 8 mhz 25 pf (esr max = 80 ? ) 16 mhz 18 pf (esr max = 50 ? ) 24 mhz 15 pf (esr max = 40 ? ) 32 mhz 10 pf (esr max = 40 ? ) functional description powerstep01 30/92 docid025022 rev 5 gatecfg1 register ( section 11.1.25 on page 63 ). when the external clock source is selected, the device cont inues to work with the in tegrated osc illator for t extosc milliseconds and then the clock management system switches to the oscin input. figure 12. oscin and oscout pin configuration note: when oscin is unused, it should be left floating. when oscout is unused, it should be left floating. 7.9 overcurrent detection the powerstep01 measures the load current of each half-bridge sensing the v ds voltage of the integrated mosfet ( figure 13 ). when any of the v ds voltages rise over the programmed threshold, the ocd flag in the st atus register is forced low until the event expires and a getstatus command is sent to the device ( section 11.1.28 on page 71 and section 11.2.20 on page 82 ). the overcurrent event expires when all the mosfet v ds voltages fall below the programmed threshold. the overcurrent threshold can be programmed by the ocd_th register in one of 32 available values listed in table 25 on page 61 . unused oscin oscout oscin oscout oscin oscout 2/4/8/16 mhz 8/16/24/32 mhz 8/16/24/32 mhz external oscillator configuration external clock source configuration internal oscillator configuration with clock generation oscin oscout internal oscillator configuration without clock source unused unused osc_sel = "1xx" osc_sel = "0xx" c l c l ext_clk = "0" ext_clk = "1" am12830v1 docid025022 rev 5 31/92 powerstep01 functional description 92 figure 13. overcurrent detection - principle scheme the overcurrent detection comparators are disabled, in order to avoid wrong voltage measurements, in following cases: ? the respective half-bridge is in high impedance state (both mosfets forced off); ? the respective half-bridge is commutating; ? the respective half-bridge is commutated and the programmed blanking time is not elapsed yet; ? the respective gate is turned off. it is possible to set if an overcurrent event c auses the bridges turn-off or not through the oc_sd bit in config register. when the power bridges are turned off by an overcurrent event, they cannot be turned on until the ocd flag is released by a getstatus command. 7.10 undervoltage lockout (uvlo) the powerstep01 provides a programmable ga te driver supply voltage uvlo protection. when one of the supply voltages of the gate driver (v cc for the low-sides and v boot - v s for the high-sides) falls below the respective turn-off threshold, an undervoltage event occurs. in this case, all mosfets are immedi ately turned off and the uvlo flag in the status register is forced low. the uvlo flag is forced low and the mosfets are kept off until the gate driver supply voltages return to above the respective turn-on threshold; in this case the undervoltage event expires and the uvlo flag can be released through a getstatus command. the uvlo thresholds can be selected between two sets according to the uvloval bit value in the config register. outxx + - + - blanking ocd_hsxx ocd_lsxx current dac oc threshold gnd vs gnd logic core voltage comparator voltage comparator am16762v1 functional description powerstep01 32/92 docid025022 rev 5 7.11 v s undervoltage lo ckout (uvlo_adc) the device provides an undervoltage signal of the integrated adc input voltage (the uvlo_adc flag in the status register). when v adcin falls below the v adc,uvlo value the uvlo_adc flag is forced low a nd it is kept in this state un til the adcin voltage is greater than v adc,uvlo and a getstatus command is sent to the device. the adcin undervoltage event doesn?t turn-off the power bridges. the motor supply voltage undervoltage detection can be performed by means of this feature, connecting the adcin pin to v s through a voltage divider as described in section 8.5 on page 41 . 7.12 thermal warning and thermal shutdown an integrated sensor allows detection of th e internal temperature and implementation of a 3-level protection. when the t j(wrn)set threshold is reached, a warning signal is generated. this is the thermal warning condition and it expires when the temperature falls below the t j(wrn)rel threshold. when the t j(off)set threshold is reached, all the mosfets are turned off and the gate driving circuitry is disabled (miller clamps are still operative). this c ondition expires when the temperature falls below the t j(off)rel threshold. when the t j(sd)off threshold is reached, all the mosfets are tu rned off using miller clamps, the internal v cc voltage regulator is disabled and the current capability of the internal v reg voltage regulator is reduced (thermal shutdown). in this condition logic is still active (if supplied). the thermal shutdown co ndition only expires when the temperature goes below t j(sd)on . the thermal condition of the device is shown by th_status bits in the status register ( table 9 ). table 8. uvlo thresholds uvloval 01 low-side gate driver supply turn-off threshold (v ccthoff ) 6.3 v 10 v low-side gate driver supp ly turn-on threshold (v ccthon ) 6.9 v 10.4 v high-side gate driver supply turn-off threshold ( ? v bootthoff ) 5.5 v 8.8 v high-side gate driver supply turn-on threshold ( ? v bootthon ) 6 v 9.2 v docid025022 rev 5 33/92 powerstep01 functional description 92 7.13 reset and standby the device can be reset and put into standby mode through the stby /reset pin. when it is forced low, all the mosfets are turned off (high z state), the charge pump is stopped, the spi interface and control logic are disabled and the internal v reg voltage regulator maximum output current is limited; as a result , the powerstep01 heavily reduces the power consumption. at the same time the register values are reset to their default and all the protection functions are disabled. the stby /reset input must be forc ed low at least for t stby,min in order to ensure the comple te switch to standby mode. on exiting standby mode, as we ll as for ic power-up, a delay must be given before applying a new command to allow proper oscillator and charge pump startu p. actual delay could vary according to the values of the charge pump external components. on exiting standby mode all the mosfets are off and the hiz flag is high. the registers can be reset to the default val ues without putting the device into standby mode through the resetdevice command ( section 11.2.14 on page 80 ). 7.14 external switch (sw pin) the sw input is inte rnally pulled up to v dd and detects if the pin is open or connected to ground (see figure 14 ). the sw_f bit of the status register indicates if the switch is open (?0?) or closed (?1?) ( section 11.1.28 on page 71 ); the bit value is refreshed at every system clock cycle (125 ns). the sw_evn flag of the status re gister is raised when a switch turn-on event (sw input falling edge) is detected ( section 11.1.28 ). a getstatus command releases the sw_evn flag ( section 11.2.20 on page 82 ). by default, a switch turn-on event causes a hardstop interrupt (sw_mode bit of config register set to ?0?). otherwise (sw_mode bit of config regist er set to ?1?), switch input events do not cause interrupts and the switch st atus information is at the user?s disposal ( table 42 on page 67 ). table 9. thermal protection summarizing table state set condition release condition description th_status normal normal operation state. 00 warning t j > tj(wrn)set t j< tj(wrn)rel temperature warning: operation is not limited. 01 bridge shutdown t j > tj(off)set t j < tj(off)rel high temperature protection: the mosfets are turned off and the gate drivers are disabled. 10 device shutdown t j > tj(sd)set t j < tj(sd)rel overtemperature protection: the mosfets are turned off, the gate drivers are disabled, the internal v cc voltage regulator is disabled, the current capability of the internal v reg voltage regulator is limited, and the charge pump is disabled. 11 functional description powerstep01 34/92 docid025022 rev 5 the switch input can be used by gount il and releasesw commands as described in section 11.2.10 on page 78 and section 11.2.11 on page 79 . if the sw input is not used, it should be connected to v dd . figure 14. external switch connection 7.15 integrated power mosfets the typical characteristics of the 8 n-channel mosfets integrated into the system-in- package are listed in table 10 . 7.16 programmable slew rate the powerstep01 integrates eight programmable gate drivers which allow the output slew rate to be fixed in a wide range of values. the following parameters can be adjusted: ? gate sink/source current (i gate ) ? controlled current time (t cc ) ? turn-off over-boost time (t ob ). during the turn-on, th e gate driver charges the gate forcing an i gate current for all the controlled current time period. at the end of the controlled current phase the gate of the integrated mosfet should be completely charged. during the turn-off the gate driver discharges the gate sinking an i gate current for all the controlled current time period. at the beginnin g of the turn-off an overboost phase can be added: in this case the gate driver sinks an i ob current for the programmed t ob period in order to rapidly reach the plateau region. at the end of the controlled current time the gate of the integrated mosfet should be completely discharged. am12833v1 external switch sw v dd table 10. integrated mosfets characteristics at t j = 25 c symbol parameter typical value unit v gs(th) gate threshold voltage 3 v q g total gate charge at v gs = 10 v 25 nc v sd source-drain diode forward on voltage at i sd = 10 a 0.8 v docid025022 rev 5 35/92 powerstep01 functional description 92 the gate current can be set to one of following values: 4, 8, 16, 24, 32, 64 and 96 ma through the i gate parameter in the gatecfg1 register. controlled current time can be programmed within range from 125 ns to 3.75 ? s with a resolution 125 ns (tcc parameter in gatecfg1 register). turn-off overboost time can be set to one of following values: 0, 62.5, 125, 250 ns (tboost parameter in gatecfg1 register). the 62.5 ns value is only available when clock frequency is 16 mhz or 32 mhz; when clock frequency is 8 mhz it is changed to 125 ns and when a 24 mhz clock is used it is changed to 83.3 ns. 7.17 deadtime and blanking time during the bridge commutation, a deadtime is added in order to avoid cross conductions. the deadtime can be programmed within a range from 125 ns to 4 ? s with a resolution of 125 ns (tdt parameter in the gatecfg2 register) (see section 11.1.26 on page 64 ). at the end of each commutation the overcurrent and stall detection comparators are disabled (blanking) in order to avoid the respective systems detecting body diodes turn-off current peaks. the duration of blanking time is progra mmable through the tblank parameter in the gatecfg2 register at one of the following values: 125, 250, 375, 500, 625, 750, 875, 1000 ns (see section 11.1.26 ). 7.18 integrated analog -to-digital converter the powerstep01 integrates an n adc bit ramp-compare analog to digital converter with a reference voltage equal to v reg . the analog to digital converter input is available through the adcin pin and the conversion result is available in the adc_out register ( section 11.1.20 on page 60 ). the adc_out value can be used for motor supply voltage compensation or can be at the user?s disposal. table 11. output slew rate slew rate (v s = 4 8 v ) i gate t cc t dt t blank t boost 980 v/s 96 ma 375 ns 125 ns 500 ns 0 ns 790 v/s 64 ma 500 ns 125 ns 375 ns 0 ns 520 v/s 32 ma 875 ns 125 ns 250 ns 0 ns 400 v/s 24 ma 1000 ns 125 ns 250 ns 0 ns 220 v/s 16 ma 1600 ns 125 ns 250 ns 0 ns 114 v/s 8 ma 3125 ns 125 ns 250 ns 0 ns functional description powerstep01 36/92 docid025022 rev 5 7.19 supply management and internal voltage regulators the powerstep01 integrates two linear voltage regulators: the first one can be used to obtain gate driver supply starting from a higher voltage (e.g.: the motor supply one). its output voltage can be set to 7.5 v or 15 v according to the vccval bit value (config register). the second linear voltage regulator can be used to obtain the 3.3 v logic supply voltage. the regulator is designed to supply the internal circuitry of the ic and should not be used to supply external components. the input and output voltages of both regulat ors are connected to external pins and the regulators are totally independent: in this way a very flexible supply management can be performed using external components or external supply voltages ( figure 15 ). figure 15. device supply pin management if v cc is externally supplied, the vsreg and vcc pins must be shorted (v sreg must be compliant with v cc range). if v reg is externally supplied, th e vccreg and vreg pins must be shorted and equal to 3.3 v. v sreg must be always less than v boot in order to avoid related esd protection diode turn- on. the device can be protected from this event by adding an external low drop diode between the vsreg and vs pins, charge pump diodes should be low drop too. v ccreg must be always less than v cc in order to avoid esd protection diode turn-on. the device can be protected from this event by a dding an external low drop diode between the vccreg and vsreg pins. both regulators provide a short circuit protection limiting the load current within the respective maximum ratings. vboot cp vs vs r e g v cc vccreg vreg 7v5 - 15v 3v3 vboot cp v s vs r e g v cc vc c r e g vreg 7v5 - 15v 3v3 vbus using external components (zener diodes, resistors, ...) it is possible to reduce internal power dissipation constrains. vbus vcc 3.3 v all voltages are internally generated all voltages are externally supplied am12834v1 docid025022 rev 5 37/92 powerstep01 functional description 92 7.20 busy/sync pin this pin is an open-drain output which can be used as busy flag or synchronization signal according to the sync_en bit value (step_mode register) (see section 11.1.23 on page 61 ). 7.21 flag pin by default, an internal open-d rain transistor pulls the flag pin to ground when at least one of the following conditions occurs: ? power-up or standby/reset exit ? stall detection on bridge a ? stall detection on bridge b ? overcurrent detection ? thermal warning ? thermal shutdown ? uvlo ? uvlo on adc input ? switch turn-on event ? command error it is possible to mask one or more alarm conditions by programming the alarm_en register (see table 32 on page 63 ). if the corresponding bit of the alarm_en register is low, the alarm condition is masked and it does not cause a flag pin transition; all other actions imposed by alarm conditions are performed anyway. in case of daisy chain configuration, flag pins of different ics can be or-wired to save host controller gpios. phase current control: voltage mode powerstep01 38/92 docid025022 rev 5 8 phase current control: voltage mode when the voltage mode driving is selected (cm_ vm bit in step_mode register is set to 0), the powerstep01 controls the phase current applying a sinusoidal voltage to motor windings. phase current amplitude is not dire ctly controlled but depends on phase voltage amplitude, load torque, motor electrical c haracteristics and rotation speed. sinewave amplitude is proportional to the motor su pply voltage multiplied by a coefficient (k val ). k val ranges from 0 to 100% and the sinewave amplitude can be obtained through the following formula: equation 1 different k val values can be programmed for acceleration, deceleration and constant speed phases and when the motor is stopped (h old phase) through kval_acc, kval_dec, kval_run and kval_hold registers ( section 11.1.10 on page 56 ). kval value is calculated according to the following formula: equation 2 where k val_x is the starting k val value programmed for the present motion phase (kval_acc, kval_dec, kval_run or kval_hold), bemf_comp is the bemf compensation curve value, vscomp and k_therm are the motor supply voltage and winding resistance compensation factors and microstep is the current microstep value (fraction of target peak current). the powerstep01 offers various methods to guarantee a stable current value, allowing the compensation of: ? low speed distortion ( section 8.3 ) ? back electromotive force ( section 8.4 ) ? motor supply voltage variation ( section 8.5 ) ? winding resistance variation ( section 8.6 on page 42 ) v out v s k val ? = k val k val_x bemf_comp + ?? vscomp k_therm ? ? ?? microst ? ep = docid025022 rev 5 39/92 powerstep01 phase current control: voltage mode 92 8.1 pwm sinewave generators the two voltage sinewaves applied to the stepper motor phases are generated by two pwm modulators. the pwm frequency (f pwm ) is proportional to th e oscillator frequency (f osc ) and can be obtained through th e following formula: equation 3 ' n ' is the integer division factor and ' m ' is the multiplication factor. 'n' and 'm' values can be programmed by f_pwm_int and f_pwm_dec parameters in the config register (see table 47 on page 68 and table 48 on page 69 ). available pwm frequencies are listed in section 11.1.27 on page 66 from table 49 on page 69 to table 52 on page 70 . 8.2 sensorless stall detection the powerstep01 is able to detect a motor stall caused by an excessive load torque. when the motor is driven using the voltage mode approach, a stall condition corresponds to an unexpected increase of the phase current. im posing a current threshol d slightly above the operative current, it is possible to detect the stall condition without speed or position sensors. the powerstep01 measures the load cu rrent of each phase sensing the v ds voltage of the low-side power mosfets. when any of the v ds voltages rise over the programmed threshold, the step_loss_x flag in the st atus register of the respective bridge (step_loss_a or step_loss_b) is forced low. the failure fl ag is kept low until the v ds voltages fall below the programmed threshold and a getstatus command is sent to the device ( section 11.1.27 and section 11.2.20 on page 82 ). the stall detection threshold can be programmed in one of 32 available values ranging from 31.25 mv to 1 v with steps of 31.25 mv (see section 11.1.22 on page 61 ). stall detection comparators are disabled, in order to avoid wrong voltage measurements, in the following cases: ? the respective half-bridge is in high impedance state (both mosfets forced off). ? the respective half-bridge is commutating. ? the respective half-bridge is commutated and the programmed blanking time has not yet elapsed. ? the respective low-side gate is turned off. 8.3 low speed optimization when the motor is driven at a very low speed using a small driving voltage, the resulting phase current can be distorted. as a consequenc e, the motor position is different from the ideal one (see figure 16 ). the device implements a low speed optimization in order to remove this effect. f pwm f osc 512 n ? ------------------ m ? = phase current control: voltage mode powerstep01 40/92 docid025022 rev 5 figure 16. current distortion and compensation the optimization can be enabled setting high the lspd_opt bi t in the min_speed register ( section 11.1.8 on page 55 ) and is active in a speed range from zero to min_speed. when low speed optimization is enabled, speed profile minimum speed is forced to zero. 8.4 bemf compensation using the speed information, a compensation curve is added to the amplitude of the voltage waveform applied to the motor winding in order to compensate the bemf variations during acceleration and deceleration (see figure 17 ). the compensation curve is approximated by a stacked line with a starting slope (st_slp) when speed is lower than a programmable threshold speed (int_speed) and a fine slope (fn_slp_acc and fn_slp_dec) when speed is greater than the threshold speed (see sections 11.1.11 on page 56 , 11.1.12 on page 56 , 11.1.13 on page 57 and 11.1.14 on page 57 ). i phase i phase without low speed optimizazion w ith low speed optimizazion am12851v1 current distortion is heavily reduced docid025022 rev 5 41/92 powerstep01 phase current control: voltage mode 92 to obtain different current values during acceleration and deceleration phase, two different final slope values, and consequently two different compensation curves, can be programmed. acceleration compensation curve is applied when the motor runs. no bemf compensation is applied when the motor is stopped. 8.5 motor supply voltage compensation the sinewave amplitude generated by the pwm modulators is directly proportional to the motor supply voltage (v s ). when the motor supply voltage is different from its nominal value, the motor phases are driven with an incorrect voltage. the powerstep01 can compensate motor supply voltage variations in order to avoid this effect. the motor supply voltage should be connected to the integrated adc input through a resistor divider in order to obtain v reg /2 voltage at the adcin pin when v s is at its nominal value (see figure 18 ). the adc input is sampled at f s frequency, which is equal to pwm frequency. figure 17. bemf compensation curve am12835v1 speed compensation value int_speed st_slp fn_slp_acc fn_slp_dec figure 18. motor supply voltage compensation circuit am12836v1 adcin adc 5 f pwm adc_out v s v reg r a r b v adcin = v s x r b / (r a + r b ) phase current control: voltage mode powerstep01 42/92 docid025022 rev 5 motor supply voltage compensation can be en abled setting high the en_vscomp bit of the config register (see table 46 on page 68 ). if the en_vscomp bit is low, the compensation is disabled and the internal anal og to digital converter is at the user?s disposal; the sampling rate is always equal to pwm frequency. 8.6 winding resistance thermal drift compensation the higher the winding resistance the greater the voltage to be applied in order to obtain the same phase current. the powerstep01 integrates a register (k _therm) which can be used to compensate phase resistance increment due to temperature rising. the value in the k_therm register ( section 11.1.15 on page 57 ) multiplies duty cycle value allowing the higher phase resistance value to be faced. the compensation algorithm and the eventual motor temperature measurement should be implemented by microcontroller firmware. docid025022 rev 5 43/92 powerstep01 phase current control: current mode 92 9 phase current control: current mode when the current mode driving is selected (cm_ vm bit in step_mode re gister is set to 1), the powerstep01 performs a new current co ntrol technique, named predictive current control, allowing the device to obtain the target average phase current. this method is described in detail in section 9.1 . furthermore, the powerstep01 automatically selects the better decay mode in order to follow the current profile. current control algorithm parameters can be programmed by t_fast, ton_min, toff_min and config registers (see section 11.1.11 on page 56 , 11.1.12 on page 56 , 11.1.19 on page 59 and 11.1.27 on page 66 for details). different current amplitude can be set for acceleration, deceleration and constant speed phases and when the motor is stopped th rough tval_acc, tval_dec, tval_run and tval_hold registers (see section 11.1.16 on page 58 ). the output current amplitude can also be regulated by the adcin voltage value (see section 9.4 ). each bridge is driven by an independent control system that shares with the other bridge the control parameters only. 9.1 predictive current control unlike classical peak current control systems, that make the phase current decay when the target value is reached, this new method keeps the power bridge on for an extra time after reaching the current threshold. at each cycle the system measures the time required to reach the target current (t sense ). after that the power stage is kept in a ?predictive? on state (t pred ) for a time equal to the mean value of t sense in the last two control cycles (actual one and previous one), as shown in figure 19. figure 19. predictive current control at the end of the predictive on state the power stage is set in off state for a fixed time, as in a constant t off current control. during the off state both slow and fast decay can be performed; the better decay combination is au tomatically selected by the powerstep01, as described in section 9.2 . predictive on state off state t sense (n-1) t off t off t pred (n) = t sense (n-1) + t sense (n) 2 i ref i out t pred (n-1) t sense (n) t pred (n) am15048v1 phase current control: current mode powerstep01 44/92 docid025022 rev 5 as shown in figure 19 , the system is able to center the triangular wave on the desired reference value, improving dramatically the accu racy of the current control system: in fact the average value of a triangular wave is exactly equal to the middle point of each of its segment and at steady-state the predictive curr ent control tends to equalize the duration of the t sense and the t pred time. furthermore, the t off value is recalculated each time a new current value is requested (microstep change) in order to keep the pwm frequency as near as possible to the programmed one (tsw parameter in the config register). the device can be forced to work using cl assic peak current control setting low the pred_en bit in the config register (default condition). in this case, after the sense phase (t sense ) the power stage is set in off state, as shown in figure 20 . figure 20. non-predictive current control 9.2 auto-adjusted decay mode during the current control, the device automat ically selects the better decay mode in order to follow the curren t profile reducing the current ripple. at reset, the off-time is performed turning on both the low-side mos of the power stage and the current recirculates in the lowe r half of the bridge (slow decay). if, during a pwm cycle, the target current thre shold is reached in a time shorter than the ton_min value, a fast decay of toff_fast/8 (t_fast register) is immediately performed turning on the opposite mos of both half-bridges and the current recirculates back to the supply bus. after this time, the bridge returns to on state: if the time needed to reach the target current value is still less than ton_min, a new fast decay is performed with a period twice the previous one. otherwise, the normal contro l sequence is followe d as described in section 9.1 . the maximum fast decay duration is set by the toff_fast value. sense on state off state t off t off i ref i out am15049v1 docid025022 rev 5 45/92 powerstep01 phase current control: current mode 92 figure 21. adaptive decay - fast decay tuning when two or more fast decays are performed with the present target current, the control system adds a fast decay at the end of every off-time keeping the off state duration constant (t off is split into t off , slow and t off , fast). when the cu rrent threshold is increased by a microstep change (rising step), the system returns to normal decay mode (slow decay only) and the t fast value is halved. stopping the motor or reaching the current sinewave zero crossing causes the current control system to retu rn to the reset state. reference current 1 st fast decay: tfast = toff_fast/8 2 nd fast decay (*): tfast = toff_fast/4 (*)note: starting from 2 nd fast decay the system combines fast and slow decay during the off phase. 3 rd fast decay: tfast = toff_fast/2 ton > ton_min tfast = toff_fast/2 am15050v1 phase current control: current mode powerstep01 46/92 docid025022 rev 5 9.3 auto-adjusted fast deca y during the falling steps when the target current is dec reased by a microstep change (falling step), the device performs a fast decay in order to reach the new value as fast as possible. however, exceeding the fast duration could cause a strong ripple on the step change. the powerstep01 automatically adjusts these fast decays reducing the current ripple. at reset the fast decay value (t fall ) is set to fall_step/4 (t_fast register). the t fall value is doubled every time, within the same fallin g step, an extra fast decay is necessary to obtain an on-time greater than ton_min (see section 11.1.18 on page 59 ). the maximum t fall value is equal to fall_step. at the next falling step, the system uses the last t fall value of the previous falling step. stopping the motor or reaching the current sinewave zero crossing causes the current control system to retu rn to the reset state. figure 22. adaptive decay - switch from normal to slow+ fast decay mode and vice versa time time reference current 1 st fast decay target current is increased (raising step) 2 nd fast decay system returns to slow decay mode and t fast vaule is halved switch to fast + slow decay mode t fast t off,fast t off,slow t off t off reference current am15051v1 docid025022 rev 5 47/92 powerstep01 phase current control: current mode 92 figure 23. fast decay tuning during the falling steps 9.4 torque regulation (s etting the output current) the phase currents are monitored through two shunt resistors (one for each power bridge) connected to the respective sense pin (see figure 24 ). the integrated comparator compares the sense resistor voltage with the internal reference generated using the peak value, which is proportional to the output cu rrent amplitude, and the microstepping code. the comparison result is provided to the logi c in order to implement the current control algorithm as described in previous sections. the peak reference voltage can be regulated in two ways: writing tval_acc, tval_dec, tval_run and tval_hold r egisters or varying the adcin voltage value. the en_tqreg bit (config register) sets the torq ue regulation method. if this bit is high, adc_out prevalue is used to regulate output current amplitude (see table 24 on page 60 ). otherwise the internal analog-to-digital converte r is at the user?s disposal and the output current amplitude is managed by tval_h old, tval_run, tval_acc and tval_dec registers (see table 18 on page 58 ). the voltage applied to the adcin pin is sampled at f s frequency and converted in an nadc bit digital signal. the analog-to-digital conv ersion result is available in the adc_out register. falling step 1 st fast decay: t fall = fall_step/4 falling step 1 st fast decay: t fall = fall_step/2 2 nd fast decay: t fall = fall_step/2 time reference current am15052v1 phase current control: current mode powerstep01 48/92 docid025022 rev 5 figure 24. current sensing and reference voltage generation / r d g 5 v h q v h 7 r j d w h g u l y h u v 7 r f x u u h q w f r q w u r o o r j l f 3 h d n u h i h u h q f h ' $ & 7 9 $ / b ; r u $ ' & , 1 0 l f u r v w h s 0 l f u r v w h s s l q j ' $ & 7 r j d w h g u l y h u v 7 r j d w h g u l y h u v 7 r j d w h g u l y h u v 9 u h i 6 ( 1 6 ( ; b 3 2 8 7 ; 2 8 7 ; 6 ( 1 6 ( ; b 6 $ 0 9 docid025022 rev 5 49/92 powerstep01 serial interface 92 10 serial interface the integrated 8-bit serial peripheral interf ace (spi) is used for a synchronous serial communication between the host microproce ssor (always master) and the device (always slave). the spi uses chip select (cs ), serial clock (ck), serial da ta input (sdi) and serial data output (sdo) pins. when cs is high the device is unselected and the sdo line is inactive (high impedance). the communication starts when cs is forced low. the ck line is used for synchronization of data communication. all commands and data bytes are shifted into the device through the sdi input, most significant bit first. the sdi is samp led on the rising edges of the ck. all output data bytes are shifted out of the de vice through the sdo ou tput, most significant bit first. the sdo is latched on the falling edges of the ck. when a return value from the device is not available, an all zero byte is sent. after each byte transmission the cs input must be raised and be kept high for at least t discs in order to allow the device to decode the received command and put the return value into the shift register. all timing requirements are shown in figure 25 (see section 3 on page 12 for values). multiple devices can be connected in daisy chain configuration, as shown in figure 26 . figure 25. spi timings diagram am12837v1 ck sdi sdo cs msb lsb lsb n-1 n-2 msb hiz n-1 n-2 t setcs t ensdo t setsdi t holsdi t vsdo t holsdo t rck t fck t hck t lck t dissdo t holcs t discs msb serial interface powerstep01 50/92 docid025022 rev 5 figure 26. daisy chain configuration am12838v1 host host spi signals dev 1 cs sdo m sdi m cs ck sdi sdo cs ck sdi m sdo m dev 2 cs ck sdi sdo dev n cs ck sdi sdo byte n byte n byte n byte n byte n-1 byte n-1 byte 1 byte 1 docid025022 rev 5 51/92 powerstep01 programming manual 92 11 programming manual 11.1 register and flag description following a map of the user available regist ers (detailed description in respective paragraphs): table 12. register map address [hex] register name register function length [bit] reset [hex] reset value remarks (1) general configuration h01 abs_pos current position 22 000000 0 r, ws h02 el_pos electrical position 9 000 0 r, ws h03 mark mark position 22 000000 0 r, wr h04 speed current speed 20 00000 0 step/tick (0 step/s) r h05 acc acceleration 12 08a 125.5e-12 step/tick 2 (2008 step/s 2 )r, ws h06 dec deceleration 12 08a 125.5e-12 step/tick 2 (2008 step/s 2 )r, ws h07 max_speed maximum speed 10 041 248e- 6 step/tick (991.8 step/s) r, wr h08 min_speed minimum speed 12 000 0 step/tick (0 step/s) r, ws h12 adc_out adc output 5 xx( 2 )0 r h13 ocd_th ocd threshold 5 8 tbd r, wr h15 fs_spd full-step speed 11 027 150.7e- 6 step/tick (602.7 step/s) r, wr h16 step_mode step mode 8 7 busy/sync output used as busy, 128 microsteps, voltage mode r, wh h17 alarm_en alarm enables 8 ff all alarms enabled r, ws h18 gatecfg1 gate driver configuration 11 tbd i gate = 4 ma, t cc = 125 ns, no boost r, wh h19 gatecfg2 gate driver configuration 8tbdt blank = 125 ns, t dt = 125 ns r, wh h1b status status 16 xxxx (2) high impedance state, motor stopped, reverse direction, all fault flags released uvlo/reset flag set r h1a config ic configuration 16 tbd internal 16 mhz oscillator (oscout at 2 mhz), sw event causes hardstop, overcurrent shutdown, v cc = 7.5 v, uvlo threshold low r, wh programming manual powerstep01 52/92 docid025022 rev 5 voltage mode configuration h09 kval_hold holding k val 8 29 0.16 v s r, wr h0a kval_run constant speed k val 8 29 0.16 v s r, wr h0b kval_acc acceleration starting k val 8 29 0.16 v s r, wr h0c kval_dec deceleration starting k val 8 29 0.16 v s r, wr h0d int_speed intersect speed 14 0408 15 .4e-6 step/tick (61.5 step/s) r, wh h0e st_slp start slope 8 19 250.038% s/step r, wh h0f fn_slp_acc acceleration final slope 8 29 0.063% s/step r, wh h10 fn_slp_dec deceleration final slope 8 29 0.063% s/step r, wh h11 k_therm thermal compensation factor 40 1.0 r, wr h14 stall_th stall threshold 5 10 tbd r, wr h1a config ic configuration 16 tbd motor supply voltage compensation disabled, f pwm = f osc / 1024 r, wh current mode configuration h09 tval_hold holding reference voltage 829 328 mv r, wr h0a tval_run constant speed reference voltage 829 328 mv r, wr h0b tval_acc acceleration reference voltage 829 328 mv r, wr h0c tval_dec deceleration reference voltage 829 328 mv r, wr h0e t_fast fast decay setting 8 19 1 s / 5 s r, wh h0f ton_min minimum on-time 8 29 20.5 s r, wh h10 toff_min minimum off-time 8 29 20.5 s r, wh h1a config ic configuration 16 tbd predictive current control disabled, t sw = 44 ? s r, wh 1. r: readable, wh: writable when the outputs are in high impedance only, ws: writable when the motor is stopped only, wr: always writable. 2. according to startup conditions. table 12. register map (continued) address [hex] register name register function length [bit] reset [hex] reset value remarks (1) docid025022 rev 5 53/92 powerstep01 programming manual 92 11.1.1 abs_pos the abs_pos register contains the current motor absolute po sition in agreement with the selected step mode; the stored value unit is e qual to the selected step mode (full, half, quarter, etc.). the value is in 2 's complement format and it ranges from -2 21 to +2 21 -1. at power-on the register is init ialized to ?0? (home position). any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 on page 71 ). 11.1.2 el_pos the el_pos register contains the current elec trical position of the motor. the two msbits indicate the current step and the other bits in dicate the current microstep (expressed in step/128) within the step. when the el_pos register is written by the user the new electrical position is instantly imposed. when the el_pos register is written, its value must be masked in order to match with the step mode selected in the step_mo de register in order to avoid a wrong microstep value generation ( section 11.1.23 on page 61 ); otherwise the resulting microstep sequence is incorrect. when the device operates in current mode, the bit number 0, 1 and 2 of the el_pos register are meaningless because the maximum microstepping resolution is 1/16 th of step. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 ). 11.1.3 mark the mark register contains an absolute position called mark, according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). it is in 2's complement format and it ranges from -2 21 to +2 21 -1. 11.1.4 speed the speed register contains the current moto r speed, expressed in step/tick (format unsigned fixed point 0.28). in order to convert the speed value in st ep/s the following fo rmula can be used: equation 4 where speed is the integer number stored in the register and tick is 250 ns. the available range is from 0 to 15625 st ep/s with a resolution of 0.015 step/s. note: the range effectively av ailable to the user is limit ed by the max_speed parameter. table 13. el_pos register bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 step microstep step/s ?? speed 2 28 ? ? tick ------------------------------------- = programming manual powerstep01 54/92 docid025022 rev 5 any attempt to write the register causes the command to be ignored and the cmd_error flag to rise ( section 11.1.28 on page 71 ). 11.1.5 acc the acc register contains the speed prof ile acceleration expressed in step/tick 2 (format unsigned fixed point 0.40). in order to convert the acc value in step/s 2 the following formula can be used: equation 5 where acc is the integer number stored in the register and tick is 250 ns. the available range is from 14.55 to 59590 step/s 2 with a resolution of 14.55 step/s 2 . the 0xfff value of the register is re served and it should never be used. any attempt to write to the re gister when the motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 ). 11.1.6 dec the dec register contains the speed prof ile deceleration expr essed in step/tick 2 (format unsigned fixed point 0.40). in order to convert the dec value in step/s 2 the following formula can be used: equation 6 where dec is the integer number stored in the register and tick is 250 ns. the available range is from 14.55to 59590 step/s2 with a resolution of 14.55 step/s2. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 ). 11.1.7 max_speed the max_speed register contains the spee d profile maximum sp eed expres sed in step/tick (format unsigned fixed point 0.18). in order to convert it in step/s, the following formula can be used: equation 7 where max_spee d is the integer number stored in the register and tick is 250 ns. the available range is from 15.25 to 15610 step/s with a resolution of 15.25 step/s. step/s 2 ?? acc 2 40 ? ? tick 2 ---------------------------- - = step/s 2 ?? dec 2 40 ? ? tick 2 ---------------------------- - = step/s ?? max_speed 2 18 ? ? tick ----------------------------------------------------- = docid025022 rev 5 55/92 powerstep01 programming manual 92 11.1.8 min_speed the min_speed register contains the following parameters: the min_speed parameter contai ns the speed profile mini mum speed. its value is expressed in step/tick and to convert it in step/s the following formula can be used: equation 8 where min_speed is the integer number stored in the register and tick is the ramp 250 ns. the available range is from 0 to 976.3 step/s with a resolution of 0.238 step/s. when the lspd_opt bit is set high, low speed optimization feature is enabled (voltage mode driving only) and the min_speed value indica tes the speed threshold below which the compensation works. in this case the minimu m speed of the speed profile is set to zero. any attempt to write the register when the mo tor is running causes the cmd_error flag to rise. 11.1.9 fs_spd the fs_spd register contains the following parameters: the fs_spd threshold speed value over which the step mode is autom atically switched to full-step two-phase on. its value is expressed in step/tick (format unsigned fixed point 0.18) and to convert it in step/s the following formula can be used: equation 9 if fs_spd value is set to hff (max.) the system always works in microstepping mode (speed must go over the threshold to switch to full-step mode). setting fs_spd to zero does not have the same effect as setting the step mode to full-step two-phase on: the zero fs_spd value is equivalent to a speed threshold of about 7.63 step/s. the available range is from 7.63 to 15625 step/s with a resolution of 15.25 step/s. the boost_mode bit sets the amplitude of the voltage squarewave during the full-step operation (see section on page 24 ). table 14. min_speed register bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lspd_opt min_speed step/s ?? min_speed 2 24 ? ? tick --------------------------------------------------- = table 15. fs_spd register bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 boost_mode fs_spd step/s ?? fs_spd 0.5 + ?? 2 18 ? ? tick ---------------------------------------------------------- - = programming manual powerstep01 56/92 docid025022 rev 5 11.1.10 kval_hold, kval_run, kval_acc and kval_dec these registers are specific fo r voltage mode driving (see section 8 on page 38 ). the kval_hold register contains the k val value that is assigned to the pwm modulators when the motor is stopped (compensations excluded). the kval_run register contains the k val value that is assigned to the pwm modulators when the motor is running at constant speed (compensations excluded). the kval_acc register contains the starting k val value that can be assigned to the pwm modulators during acceleration (compensations excluded). the kval_dec register contains the starting k val value that can be assigned to the pwm modulators during deceleration (compensations excluded). the available range is from 0 to 0.996 x v s with a resolution of 0.004 x v s , as shown in table 16 . 11.1.11 int_speed this register is specific fo r voltage mode driving (see section 8 ). the int_speed register contains the speed va lue at which the bemf compensation curve changes slope ( section 8.4 on page 40 for details). its value is expressed in step/tick and to convert it in [step/s] the following formula can be used: equation 10 where int_speed is the integer number stored in the register and tick is 250 ns. the available range is from 0 to 976.5 step/s with a resolution of 0.0596 step/s. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 on page 71 ). 11.1.12 st_slp this register is specific fo r voltage mode driving (see section 8 ). the st_slp register contains the bemf compen sation curve slope that is used when the speed is lower than the intersect speed ( section 8.4 ). its value is expressed in s/step and the available range is from 0 to 0.004 with a resolution of 0.000015. table 16. voltage amplitude regulation registers kval_x [7?0] output voltage 00000000 0 00000001 v s x (1/256) ? ? ? ? ? ? ? ? ? 11111110 v s x (254/256) 11111111 v s x (255/256) step/s ?? int_speed 2 18 ? ? tick ------------------------------------------------- - = docid025022 rev 5 57/92 powerstep01 programming manual 92 when st_slp, fn_slp_acc and fn_slp_dec parameters are set to zero, no bemf compensation is performed. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 on page 71 ). 11.1.13 fn_slp_acc this register is specific fo r voltage mode driving (see section 8 on page 38 ). the fn_slp_acc register contains the bemf compensation curve slope that is used when the speed is greater than the intersect speed during acceleration ( section 8.4 on page 40 for details). its value is expre ssed in s/step and the available range is from 0 to 0.004 with a resolution of 0.000015. when st_slp, fn_slp_acc and fn_slp_dec parameters are set to zero, no bemf compensation is performed. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 ). 11.1.14 fn_slp_dec this register is specific fo r voltage mode driving (see section 8 ). the fn_slp_dec register cont ains the bemf compensation curve slope that is used when the speed is greater than the intersect speed during deceleration ( section 8.4 for details). its value is expressed in s/step and the available r ange is from 0 to 0.004 with a resolution of 0.000015. when st_slp, fn_slp_acc and fn_slp_dec parameters are set to zero, no bemf compensation is performed. any attempt to write the register when t he motor is running causes the command to be ignored and the cmd_e rror flag to rise ( section 11.1.28 ). 11.1.15 k_therm this register is specific fo r voltage mode driving (see section 8 ). the k_therm register contains the value used by the winding resistance thermal drift compensation system ( section 8.6 on page 42 ). the available range is from 1 to 1.46875 with a resolution of 0.03125, as shown in table 17 . table 17. winding resistance thermal drift compensation coefficient k_therm [3 ? 0] compen sation coefficient 0000 1 0001 1.03125 ? ? ? ? ? 1110 1.4375 1111 1.46875 programming manual powerstep01 58/92 docid025022 rev 5 11.1.16 tval_hold, tval_run, tval_acc and tval_dec these registers are specific fo r current mode driving (see section 9 on page 43 ). the tval_hold register contains the referenc e voltage that is assigned to the torque regulation dac when the motor is stopped. the tval_run register contains the referenc e voltage that is assigned to the torque regulation dac when the motor is running at constant speed. the tval_acc register contains the reference voltage that is assigned to the torque regulation dac during acceleration. the tval_dec register contains the reference voltage that is assigned to the torque regulation dac dur ing deceleration. the available range is from 7.8 mv to 1 v with a resolution of 7.8 mv, as shown in table 16 . 11.1.17 t_fast this register is specific fo r current mode driving (see section 9 ). the t_fast register contains the maximum fast decay time (toff_fast) and the maximum fall step time (fall_step) us ed by the current control system ( section 9.2 on page 44 and section 9.3 on page 46 for details): the available range for both parameters is from 2 s to 32 s. table 18. torque regulation by tval_hol d, tval_acc, tval_dec and tval_run registers tval_x [6?0] peak reference voltage 0000000 7.8 mv 0000001 15.6 mv ? ? ? ? ? ? ? ? 1111110 992.2 mv 1111111 1 v table 19. t_fast register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 toff_fast fast_step docid025022 rev 5 59/92 powerstep01 programming manual 92 any attempt to write to the re gister when the motor is running causes the command to be ignored and cmd_error to rise ( section 11.1.28 on page 71 ). 11.1.18 ton_min this register is specific fo r current mode driving (see section 9 on page 43 ). this parameter is used by the current control system when current mode operation is selected. the ton_min register contains the minimum on-time value used by the current control system (see section 9.2 on page 44 ). the available range for both parame ters is from 0.5 s to 64 s. any attempt to write to the re gister when the motor is running causes the command to be ignored and the cmd_error to rise (see section 11.1.28 ). 11.1.19 toff_min this register is specific fo r current mode driving (see section 9 ). this parameter is used by the current control system when current mode operation is selected. the toff_min register contains the minimum of f-time value used by the current control system (see section 9.1 on page 43 for details). the available range for both parameters is from 0.5 s to 64 s. table 20. maximum fast decay times toff_fast [3 ? 0] fast_step [3 ? 0] fast decay time 0 0 0 0 2 s 0 0 0 1 4 s ? ? ? ? ? 1 1 1 0 28 s 1 1 1 1 32 s table 21. minimum on-time ton min [6 ? 0] time 0 0 0 0 0 0 0 0.5 s 0 0 0 0 0 0 1 1 s ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 63.5 s 1 1 1 1 1 1 1 64 s programming manual powerstep01 60/92 docid025022 rev 5 any attempt to write to the re gister when the motor is running causes the command to be ignored and cmd_error to rise (see section 11.1.28 on page 71 ). 11.1.20 adc_out the adc_out register contains the result of t he analog to digital conversion of the adcin pin voltage. any attempt to write to the register causes the command to be ignored and the cmd_er- ror to rise. table 22. minimum off-time toff min [6 ? 0] time 0 0 0 0 0 0 0 0.5 s 0 0 0 0 0 0 1 1 s ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 63.5 s 1 1 1 1 1 1 1 64 s table 23. adc_out value and motor supply voltage compensation feature v s v adcin / v reg adc_out [4 ? 0] compensation coefficient greater than v s , nom + 50% > 24/32 1 1 x x x 0.65625 v s , nom + 50% 24/32 1 1 0 0 0 0.65625 ? ? ? ? ? ? ? ? v s , nom 16/32 10000 1 ? ? ? ? ? ? ? ? v s , nom ? 50% 8/32 0 1 0 0 0 1.968875 lesser than v s , nom ? 50% < 8/32 0 0 x x x 1.968875 table 24. adc_out value and torque regulation feature v adcin / v reg adc_out [4 ? 0] reference voltage 0 00000 31.25 mv 1/32 0 0 0 0 1 62.5 mv ? ? ? ? ? ? ? 30/32 1 1 1 1 0 968.8 mv 31/32 1 1 1 1 1 1000 mv docid025022 rev 5 61/92 powerstep01 programming manual 92 11.1.21 ocd_th the ocd_th register contains the overcurrent threshold value ( section 7.9 on page 30 for details). the available range is from 31.25 mv to 1 v, steps of 31.25 mv, as shown in table 25 . 11.1.22 stall_th this register is specific fo r voltage mode driving (see section 8 on page 38 ). the stall_th register contains the stall detect ion threshold value. the available range is from 31.25 mv to 1 v with a resolution of 31.25 mv. 11.1.23 step_mode the step_mode register has the following structure: the cm_vm bit sets the current control method between voltage and current mode: table 25. overcurrent detection threshold ocd_th [4 ? 0] overcurrent detection threshold 0 0 0 0 0 31.25 mv 00001 62.5 mv ????? ? 11110 968.75 mv 11111 1 v table 26. stall detection threshold stall_th [4 ? 0] stal l detection threshold 0 0 0 0 0 31.25 mv 00001 62.5 mv ????? ? 11110 968.75 mv 11111 1 v table 27. step_mode register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sync_en sync_sel cm_vm step_sel table 28. control mode selection cm_vm control mode 0 voltage mode 1 advanced current cont rol (current mode) programming manual powerstep01 62/92 docid025022 rev 5 step_sel selects one of eight possible stepping modes: every time the step mode changes, the electric al position (i.e.: the point of microstepping sinewave that is generated) resets at the first microstep. it is important to note that every time step_ sel changes, the value in abs_pos register loses meaning and then it should be reset. when sync clock is disabled, busy/sync output is used as busy (command state machine busy signaling), otherwise busy/sync output provides a clock signal according to sync_sel parameter. any attempt to write to the register, when the motor is running, causes the command to be ignored and the cmd_error to rise (see section 11.1.28 on page 71 ). table 29. step mode selection step_sel[2 ? 0] step mode (cm_vm = 0) step mode (cm_vm = 1) 000 full-step full-step 0 0 1 half-step half-step 0 1 0 1/4 microstep 1/4 microstep 0 1 1 1/8 microstep 1/8 microstep 1 0 0 1/16 microstep 1/16 microstep 1 0 1 1/32 microstep 1/16 microstep 1 1 0 1/64 microstep 1/16 microstep 1 1 1 1/128 microstep 1/16 microstep table 30. sync clock enable sync_en sync clock 0 disabled 1 enabled table 31. sync clock selection sync_sel[2 ? 0] step information (cm_vm = 0) step information (cm_vm = 1) 0 0 0 full-step full-step 0 0 1 half-step half-step 0 1 0 1/4 microstep 1/4 microstep 0 1 1 1/8 microstep 1/8 microstep 1 0 0 1/16 microstep 1/16 microstep 1 0 1 1/32 microstep always low 1 1 0 1/64 microstep always low 1 1 1 1/128 microstep always low docid025022 rev 5 63/92 powerstep01 programming manual 92 11.1.24 alarm_en the alarm_en register allows the selection of which alarm signals are used to generate the flag output. if the respective bit of the al arm_en register is set high, the alarm condition forces the flag pin output down. 11.1.25 gatecfg1 the gatecfg1 register has the following structure: the igate parameter selects the sink/source current used by gate driving circuitry to charge/discharge the respective gate during commutations. seven possible values ranging from 4 ma to 96 ma are available, as shown in table 34 . table 32. alarm_en register alarm_en bit ala rm condition 0 (lsb) overcurrent 1 thermal shutdown 2 thermal warning 3uvlo 4 adc uvlo 5 stall detection (voltage mode only) 6 switch turn-on event 7 (msb) command error table 33. gatecfg1 register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 wd_en tboost bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 igate tcc table 34. igate parameter igate [2 ? 0} gate current [ma} 000 4 001 4 010 8 011 16 100 24 101 32 110 64 111 96 programming manual powerstep01 64/92 docid025022 rev 5 the tcc parameter defines the duration of constant current phase during gate turn-on and turn-off sequences ( section 7.16 on page 34 ). the tboost parameter defines the duration of the overboost phase during gate turn-off ( section 7.16 ). the wd_en bit enables the clock source monitoring ( section 7.8.2 on page 29 ). 11.1.26 gatecfg2 the gatecfg2 register has the following structure: table 35. tcc parameter tcc [4 ? 0] constant current time [ns] 00000 125 00001 250 ????? ? 1 1 1 0 0 3625 1 1 1 0 1 3750 1 1 1 1 0 3750 1 1 1 1 1 3750 table 36. tboost parameter tboost [2 ? 0] turn-off boost time [ns] 000 0 00162.5 (1) / 83.3 (2) / 125 (3) 1. clock frequency equal to 16 mhz or 32 mhz. 2. clock frequency equal to 24 mhz. 3. clock frequency equal to 8 mhz. 010 125 011 250 100 375 101 500 110 750 1 1 1 1000 table 37. gatecfg2 register (voltage mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tblank tdt docid025022 rev 5 65/92 powerstep01 programming manual 92 the tdt parameter defines the deadtime duration between the gate turn-off and the opposite gate turn-on sequences ( section 7.17 on page 35 ). the tblank parameter defines the duration of the blanking of the current sensing comparators (stall detection and overcurrent) after each commutation ( section 7.17 ). table 38. tdt parameter tdt [4 ? 0] deadtime [ns] 00000 125 00001 250 ????? ? 11110 3875 11111 4000 table 39. tblank parameter tblank [2 ? 0] blanking time [ns] 000 125 001 250 ??? ? 110 875 111 1000 programming manual powerstep01 66/92 docid025022 rev 5 11.1.27 config the config register has the following structure: the osc_sel and ext_clk bits set the system clock source: table 40. config register cm_vm bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0 f_pwm_int f_pwm_dec vccval uvloval 1 pred_en tsw vccval uvloval bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 oc_sd en_vscomp sw_mode ext_clk osc_sel 1 oc_sd en_tqreg sw_mode ext_clk osc_sel table 41. oscillator management ext_clk osc_sel [2 ? 0] clock source oscin oscout 0 000 internal oscillator: 16 mhz unused unused 0 001 0 010 0 011 1 0 0 0 internal oscillator: 16 mhz unused supplies a 2 mhz clock 1 0 0 1 internal oscillator: 16 mhz unused supplies a 4 mhz clock 1 0 1 0 internal oscillator: 16 mhz unused supplies a 8 mhz clock 1 0 1 1 internal oscillator: 16 mhz unused supplies a 16 mhz clock 0 100 external crystal or resonator: 8 mhz crystal/resonator driving crystal/resonator driving 0 101 external crystal or resonator: 16 mhz crystal/resonator driving crystal/resonator driving 0 110 external crystal or resonator: 24 mhz crystal/resonator driving crystal/resonator driving docid025022 rev 5 67/92 powerstep01 programming manual 92 the sw_mode bit sets the external switch to act as hardstop interrupt or not: the oc_sd bit sets if an overcurrent event causes or not the bridges to turn-off; the ocd flag in status register is forced low anyway: the vccval bit set the internal v cc regulator output voltage: 0 111 external crystal or resonator: 32 mhz crystal/resonator driving crystal/resonator driving 1 100 ext clock source: 8 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1 101 external clock source: 16 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1 110 external clock source: 24 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal 1 111 external clock source: 32 mhz (crystal/resonator driver disabled) clock source supplies inverted oscin signal table 41. oscillator management (continued) ext_clk osc_sel [2 ? 0] clock source oscin oscout table 42. external switch hard stop interrupt mode sw_mode switch mode 0 hardstop interrupt 1 user disposal table 43. overcurrent event oc_sd overcurrent event 1 bridges shut down 0 bridges do not shut down table 44. programmable v cc voltage regulator output vccval v cc voltage 0 7.5 v 115 v programming manual powerstep01 68/92 docid025022 rev 5 the uvloval bit sets the uvlo protection thresholds: when the device operates in voltage mode, the en_vscomp bit sets if the motor supply voltage compensation is enabled or not. when the device operates in voltage mode, the f_pwm_int bits set the integer division factor of pwm frequency generation: table 45. programmable uvlo thresholds uvloval v ccthon v ccthoff dv bootthon dv bootthoff 0 6.9 v 6.3 v 6 v 5.5 v 1 10.4 v 10 v 9.2 v 8.8 v table 46. motor supply voltage compensation enable en_vscomp motor supply voltage compensation 0 disabled 1 enabled table 47. pwm frequency: integer division factor f_pwm_int [2 ? 0] integer division factor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 docid025022 rev 5 69/92 powerstep01 programming manual 92 when the device operates in voltage mode, the f_pwm_dec bits set the multiplication factor of pwm frequency generation: in the following tables all available pwm fr equencies are listed a ccording to oscillator frequency, f_pwm_int and f_pwm_dec valu es (config register osc_sel parameter has to be correctly programmed). table 48. pwm frequency: multiplication factor f_pwm_dec [2 ? 0] mu ltiplication factor 000 0.625 001 0.75 010 0.875 011 1 100 1.25 101 1.5 110 1.75 111 2 table 49. available pwm frequencies [khz]: 8 mhz oscillator frequency f_pwm_dec f_pwm_int 000 001 010 011 100 101 110 111 000 9.8 11.7 13.7 15.6 19.5 23.4 27.3 31.3 001 4.9 5.9 6.8 7.8 9.8 11.7 13.7 15.6 010 3.3 3.9 4.6 5.2 6.5 7.8 9.1 10.4 011 2.4 2.9 3.4 3.9 4.9 5.9 6.8 7.8 100 2.0 2.3 2.7 3.1 3.9 4.7 5.5 6.3 101 1.6 2.0 2.3 2.6 3.3 3.9 4.6 5.2 110 1.4 1.7 2.0 2.2 2.8 3.3 3.9 4.5 table 50. available pwm frequencies [khz]: 16 mhz oscillator frequency f_pwm_dec f_pwm_int 000 001 010 011 100 101 110 111 000 19.5 23.4 27.3 31.3 39.1 46.9 54.7 62.5 001 9.8 11.7 13.7 15.6 19.5 23.4 27.3 31.3 010 6.5 7.8 9.1 10.4 13.0 15.6 18.2 20.8 011 4.9 5.9 6.8 7.8 9.8 11.7 13.7 15.6 100 3.9 4.7 5.5 6.3 7.8 9.4 10.9 12.5 programming manual powerstep01 70/92 docid025022 rev 5 when the device operates in current mode, t he en_tqreg bit sets if the peak current is adjusted through the adcin input or not. 101 3.3 3.9 4.6 5.2 6.5 7.8 9.1 10.4 110 2.8 3.3 3.9 4.5 5.6 6.7 7.8 8.9 table 51. available pwm frequencies [khz]: 24 mhz oscillator frequency f_pwm_dec f_pwm_int 000 001 010 011 100 101 110 111 000 29.3 35.2 41.0 46.9 58.6 70.3 82.0 93.8 001 14.6 17.6 20.5 23.4 29.3 35.2 41.0 46.9 010 9.8 11.7 13.7 15.6 19.5 23.4 27.3 31.3 011 7.3 8.8 10.3 11.7 14.6 17.6 20.5 23.4 100 5.9 7.0 8.2 9.4 11.7 14.1 16.4 18.8 101 4.9 5.9 6.8 7.8 9.8 11.7 13.7 15.6 110 4.2 5.0 5.9 6.7 8.4 10.0 11.7 13.4 table 52. available pwm frequencies [khz]: 32 mhz oscillator frequency f_pwm_dec f_pwm_int 000 001 010 011 100 101 110 111 000 39.1 46.9 54.7 62.5 78.1 93.8 109.4 125.0 001 19.5 23.4 27.3 31.3 39.1 46.9 54.7 62.5 010 13.0 15.6 18.2 20.8 26.0 31.3 36.5 41.7 011 9.8 11.7 13.7 15.6 19.5 23.4 27.3 31.3 100 7.8 9.4 10.9 12.5 15.6 18.8 21.9 25.0 101 6.5 7.8 9.1 10.4 13.0 15.6 18.2 20.8 110 5.6 6.7 7.8 8.9 11.2 13.4 15.6 17.9 table 53. external torque regulation enable en_tqreg peak current adjust. through adcin 0 disabled 1 enabled table 50. available pwm frequencies [khz]: 16 mhz oscillator frequency (continued) f_pwm_dec f_pwm_int 000 001 010 011 100 101 110 111 docid025022 rev 5 71/92 powerstep01 programming manual 92 when the device operates in current mode, t he pred_en bit sets if the predictive current control method is enabled or not. when the device operates in current mode, the tsw bits set the target switching period of the current control algorithm: any attempt to write the config register when the outputs are enabled causes the command to be ignored and the cmd_error flag to rise (see section 11.1.28 ). 11.1.28 status the status register has the following structure: when hiz flag is high it indi cates that the bridges are in high impedance state. whichever motion command makes the device to exit from high z state (hardstop and softstop included), unless error flags forcing a high z state are active. the uvlo flag is active low and is set by an undervoltage lock out or reset events (power- up included). the uvlo_adc flag is active low and indicates an adc undervoltage event. the ocd flag is active low and indi cates an overcurrent detection event. the stall_a and stall_b flags are forced low when a stall condition is detected on bridge a or bridge b respectively. the stall de tection is operative only when the voltage mode control is selected. table 54. motor supply voltage compensation enable pred_en predictive current control 0 disabled 1 enabled table 55. switching period tsw [4 ? 0] switching period 00000 4 s (250 khz) 00001 4 s (250 khz) 00010 8 s (125 khz) ? ? 11111 124 s (8 khz) table 56. status register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 15 stall_a stall_b ocd th_status uvlo_adc uvlo stck_mod bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd_err or mot_status dir sw_evn sw_f busy hiz programming manual powerstep01 72/92 docid025022 rev 5 the cmd_error flag is active high and indica tes that the command received by spi can't be performed or does not exist at all. the sw_f report the sw input status (low for open and high for closed). the sw_evn flag is active high and indicates a switch tu rn-on event (sw input falling edge). th_status bits indicate the curr ent device thermal status (see section 7.12 on page 32 ): uvlo, uvlo_adc, ocd, step_loss_a, st ep_loss_b, cmd_error, sw_evn and th_status bits are latched: when the respecti ve conditions make them active (low or high) they remain in that state until a getstatus command is sent to the ic. the busy bit reflects the busy pin status. th e busy flag is low when a constant speed, positioning or motion command is under exec ution and is released (high) after the command have been completed. the stck_mod bit is an active high flag indicati ng that the device is working in step clock mode. in this case the step clock signal should be provided through stck input pin. the dir bit indicates the current motor direction: mot_status indicates the current motor status: any attempt to write to the register causes the command to be ignored and the cmd_error flag to rise. table 57. status register th_status bits th_status status 0 0 normal 01 warning 1 0 bridge shutdown 1 1 device shutdown table 58. status register dir bit dir motor direction 1forward 0 reverse table 59. status register mot_status bits mot_status motor status 0 0 stopped 0 1 acceleration 10 deceleration 1 1 constant speed docid025022 rev 5 73/92 powerstep01 programming manual 92 11.2 application commands the command summary is given in table 60 . table 60. application commands command mnemonic comman d binary code action [7?5] [4] [3] [2?1] [0] nop 000 0 0 00 0 nothing setparam(param,value) 000 [param] writes value in param register getparam(param) 001 [param] returns the stored value in param register run(dir,spd) 010 1 0 00 dir sets the tar get speed and the motor direction stepclock(dir) 010 1 1 00 dir puts the device in step-clock mode and imposes dir direction move(dir,n_step) 010 0 0 00 dir makes n_step (micro)step s in dir direction (not performable wh en motor is running) goto(abs_pos) 011 0 0 00 0 brings motor in abs_pos position (minimum path) goto_dir(dir,abs_pos) 011 0 1 00 dir brings motor in abs_pos position forcing dir direction gountil(act,dir,spd) 100 0 act 01 dir performs a motion in dir direction with speed spd until sw is closed, the act action is executed then a softstop takes place relesesw(act, dir) 100 1 act 01 dir performs a motion in dir direction at minimum speed until the sw is released (open), the act action is executed then a hardstop takes place gohome 011 1 0 00 0 brings the motor in home position gomark 011 1 1 00 0 brings the motor in mark position resetpos 110 1 1 00 0 resets the abs_pos register (sets home position) resetdevice 110 0 0 00 0 device is reset to power-up conditions softstop 101 1 0 00 0 stops motor with a deceleration phase hardstop 101 1 1 00 0 stops motor immediately softhiz 101 0 0 00 0 puts the bridges in high impedance status after a deceleration phase hardhiz 101 0 1 00 0 puts the bridges in high impedance status immediately getstatus 110 1 0 00 0 returns the status register value reserved 111 0 1 01 1 reserved command reserved 111 1 1 00 0 reserved command programming manual powerstep01 74/92 docid025022 rev 5 11.2.1 command management the host microcontroller can control motor mo tion and configure the powerstep01 through a complete set of commands. all commands are composed by a single byte. after the command byte, some bytes of arguments should be needed (see figure 27 ). argument length can vary from 1 to 3 bytes. figure 27. command with 3-byte argument by default, the device returns an all zero response for any received byte, the only exceptions are getparam and getstatus commands. when one of these commands is received, the following response bytes represent the related register value (see figure 28 ). response length can va ry from 1 to 3 bytes. figure 28. command with 3-byte response during response transmission, new commands can be sent. if a command requiring a response is sent before the previous response is completed, the response transmission is aborted and the new response is loaded into the output communication buffer (see figure 29 ). figure 29. command response aborted when a byte that does not correspond to a comma nd is sent to the ic it is ignored and the cmd_error flag in the status regi ster is raised (see paragraph section 11.1.28 ). 6 ' , 6 ' 2 & r p p d q g e \ w h $ u j x p h q w e \ w h 0 6 % $ u j x p h q w e \ w h / 6 % $ u j x p h q w e \ w h [ [ [ [ i u r p k r v w w r k r v w $ 0 y 6 ' , 6 ' 2 & r p p d q g e \ w h 5 h v s r q v h e \ w h 0 6 % 5 h v s r q v h e \ w h / 6 % 5 h v s r q v h e \ w h [ 1 2 3 1 2 3 1 2 3 i u r p k r v w w r k r v w $ 0 y 6 ' , 6 ' 2 & r p p d q g e \ w h u h v s h [ s h f w h g & r p p d q g e \ w h u h v s h [ s h f w h g 5 h v s r q v h e \ w h 0 6 % 5 h v s r q v h e \ w h 0 6 % 5 h v s r q v h e \ w h [ & r p p d q g q r u h v s h [ s h f w h g 5 h v s r q v h e \ w h / 6 % i u r p k r v w w r k r v w & r p p d q g q r u h v s h [ s h f w h g & r p p d q g q r u h v s h [ s h f w h g & r p p d q g u h v s r q v h l v d e r u w h g $ 0 y docid025022 rev 5 75/92 powerstep01 programming manual 92 11.2.2 nop nothing is performed. 11.2.3 setparam (param, value) the setparam command sets the param register value equal to value; param is the respective register address listed in table 12 on page 51 . the command should be followed by the new register value (most significant byte first). the number of bytes composing the value argu ment depends on the length of the target register (see table 12 ). some registers cannot be written (see table 12 ); any attempt to write one of those registers causes the command to be ignored and the cmd_error flag to rise at the end of the command byte, as if an unknown command code were sent (see section 11.1.28 on page 71 ). some registers can only be writte n in particular conditions (see table 12 ); any attempt to write one of those registers when the conditions are not satisfied causes the command to be ignored and the cmd_error flag to rise at the end of the last argument byte (see section 11.1.28 ). any attempt to set an inexistent register (wrong address value) causes the command to be ignored and the cmd_error flag to rise at the end of the command byte as if an unknown command code were sent. 11.2.4 getparam (param) table 61. nop command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000000 from host table 62. setparam command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 param from host value byte 2 (if needed) value byte 1 (if needed) value byte 0 table 63. getparam command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 0 0 1 param from host ans byte 2 (if needed) to host ans byte 1 (if needed) to host ans byte 0 to host programming manual powerstep01 76/92 docid025022 rev 5 this command reads the current param register value; param is the respective register address listed in table 12 on page 51 . the command response is the current value of the register (most significant byte first). the number of bytes composing the command resp onse depends on the length of the target register (see table 12 ). the returned value is the register one at the moment of getparam command decoding. if register values change after this moment , the response is not accordingly updated. all registers can be read anytime. any attempt to read an inexistent register (wrong address value) causes the command to be ignored and the cmd_error flag to rise at the end of the command byte as if an unknown command code were sent. 11.2.5 run (dir, spd) the run command produces a motion at spd s peed; the direction is selected by the dir bit: '1' forward or '0' reverse. the spd value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the speed register ( section 11.1.4 on page 53 ). note: the spd value should be lower th an max_speed and greater than min_speed, otherwise the run co mmand is executed at max_speed or min_spe ed respectively. this command keeps the busy flag low until the target speed is reached. this command can be given anytim e and is immediately executed. 11.2.6 stepclock (dir) the stepclock command switches the device in step-clock mode ( section 7.7.5 on page 28 ) and imposes the forward (dir = '1') or reverse (dir = '0') direction. when the device is in step-clock mode, the sck_ mod flag in the status register is raised and the motor is always considered stopped ( section 7.7.5 and section 11.1.28 on page 71 ). the device exits step-clock mode when a cons tant speed, absolute positioning or motion command is sent through spi. motion directio n is imposed by the respective stepclock table 64. run command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 0101000dir from host xxxx spd (byte 2) from host spd (byte 1) from host spd (byte 0) from host table 65. stepclock command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0101100dirfrom host docid025022 rev 5 77/92 powerstep01 programming manual 92 command argument and can by changed by a new stepclock command without exiting step-clock mode. events that cause bridges to be forced into high impedance state (overtemperature, overcurrent, etc.) do not cause the device to leave step-clock mode. the stepclock command does not force the busy flag low. this command can only be given when the motor is stopped. if a motion is in progress, the mo tor should be stopped and it is then possible to send a stepclock command. any attempt to perform a stepclock command when the motor is running causes the command to be ignored and the cmd_error flag to rise ( section 11.1.28 on page 71 ). 11.2.7 move (dir, n_step) the move command produces a motion of n_step microsteps; the direction is selected by the dir bit ('1' forward or '0' reverse). the n_step value is always in agreement wi th the selected step mode; the parameter value unit is equal to th e selected step mode (full, half, quarter, etc.). this command keeps the busy flag low until the target number of steps is performed. this command can only be performed when the motor is stopped. if a motion is in progress the motor must be stopped and it is then possible to perform a move command. any attempt to perform a move command when the motor is running causes the command to be ignored and the cmd_error flag to rise ( section 11.1.28 ). 11.2.8 goto (abs_pos) the goto command pr oduces a motion to abs_ pos absolute position through the shortest path. the abs_pos value is always in agre ement with the select ed step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.). the goto command keeps the busy flag low until the target position is reached. table 66. move command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0100000dirfrom host x x n_step (byte 2) from host n_step (byte 1) from host n_step (byte 0) from host table 67. goto command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 1 00000 from host x x abs_pos (byte 2) from host abs_pos (byte 1) from host abs_pos (byte 0) from host programming manual powerstep01 78/92 docid025022 rev 5 this command can be given only when the previous motion command as been completed (busy flag released). any attempt to perform a goto command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error flag to rise ( section 11.1.28 on page 71 ). 11.2.9 goto_dir (dir, abs_pos) the goto_dir command produces a motion to abs_pos absolute position imposing a forward (dir = '1') or a re verse (dir = '0') rotation. the abs_pos value is always in agreement with the selected st ep mode; the paramete r value unit is equa l to the selected step mode (full, half, quarter, etc.). the goto_dir command keeps the busy flag low until the target speed is reached. this command can be given only when the previous motion command has been completed (busy flag released). any attempt to perform a goto_dir command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error flag to rise ( section 11.1.28 ). 11.2.10 gountil (act, dir, spd) the gountil command produces a motion at spd speed imposing a forward (dir = '1') or a reverse (dir = '0') direction. when an external switch turn-on event occurs ( section 7.14 on page 33 ), the abs_pos register is reset (if act = '0') or the abs_pos register value is copied into the mark register (if act = '1'); the system then performs a softstop command. the spd value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the speed register ( section 11.1.4 on page 53 ). the spd value should be lower than max_speed and greater than min_speed, otherwise the target speed is imposed at max_speed or min_speed respectively. table 68. goto_dir command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0110100dirfrom host x x abs_pos (byte 2) from host abs_pos (byte 1) from host abs_pos (byte 0) from host table 69. gountil command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 0 act 0 1 dir from host x x x x spd (byte 2) from host spd (byte 1) from host spd (byte 0) from host docid025022 rev 5 79/92 powerstep01 programming manual 92 if the sw_mode bit of the config register is set low, the external switch turn-on event causes a hardstop interrupt instead of the softstop one ( section 7.14 on page 33 and section 11.1.27 on page 66 ). this command keeps the busy flag low until the switch turn-o n event occurs and the motor is stopped. this command can be give n anytime and is i mmediately executed. 11.2.11 releasesw (act, dir) the releasesw command produces a motion at minimum speed imposing a forward (dir = '1') or reverse (dir = '0') rotation. when sw is released (opened) the abs_pos register is reset (act = '0') or the abs_pos register value is copied into the mark register (act = '1'); the system then performs a hardstop command. note that, resetting the abs_pos register is equivalent to setting the home position. if the minimum speed value is less than 5 step /s or low speed optimi zation is enabled, the motion is performed at 5 step/s. the releasesw command keeps the busy flag lo w until the switch i nput is released and the motor is stopped. 11.2.12 gohome the gohome command produces a motion to the home position (zero position) via the shortest path. note that, this command is equivalent to th e ?goto(0?0)? command. if a motor direction is mandatory, the goto_dir command must be used ( section 11.2.9 on page 78 ). the gohome command keeps the busy flag low until the home position is reached. this command can be given only when the previous motion command has been completed. any attempt to perform a gohome command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error to rise ( section 11.1.28 on page 71 ). table 70. releasesw command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 1 act 0 1 dir from host table 71. gohome command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 01110000 from host programming manual powerstep01 80/92 docid025022 rev 5 11.2.13 gomark the gomark command produces a motion to th e mark position performing the minimum path. note that, this command is equivalent to th e ?goto (mark)? command. if a motor direction is mandatory, the goto_dir command must be used. the gomark command keeps the busy flag low until the mark position is reached. this command can be given only when the previous motion command has been completed (busy flag released). any attempt to perform a gomark command when a previous command is under execution (busy low) causes the command to be ignored and the cmd_error flag to rise ( section 11.1.28 on page 71 ). 11.2.14 resetpos the resetpos command resets the abs_pos register to zero. the zero position is also defined as the home position ( section 7.5 on page 25 ). 11.2.15 resetdevice the resetdevice command resets the device to power-up conditions ( section 7.1 on page 22 ). note: at power-up the power bridges are disabled. table 72. gomark command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01111000from host table 73. resetpos command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 11011000 from host table 74. resetdevice command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 11000000 from host docid025022 rev 5 81/92 powerstep01 programming manual 92 11.2.16 softstop the softstop command causes an immediate dece leration to zero speed and a consequent motor stop; the deceleration value used is the one stored in the dec register ( section 11.1.6 on page 54 ). when the motor is in high impedance state, a softstop command forces the bridges to exit from high impedance state; no motion is performed. this command can be given anytime and is immediately executed. this command keeps the busy flag low until the motor is stopped. 11.2.17 hardstop the hardstop command causes an immediate motor stop with infinite deceleration. when the motor is in high impedance state, a hardstop command forces the bridges to exit high impedance state; no motion is performed. this command can be given anytime and is immediately executed. this command keeps the busy flag low until the motor is stopped. 11.2.18 softhiz the softhiz command disables the power bridges (high impedance state) after a deceleration to zero; the deceleration value used is the one stored in the dec register ( section 11.1.6 ). when bridges are disabled, the hiz flag is raised. when the motor is stopped, a softhiz command forces the bridges to enter high impedance state. this command can be given anytime and is immediately executed. this command keeps the busy flag low until the motor is stopped. table 75. softstop command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 10110000 from host table 76. hardstop command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 10111000 from host table 77. softhiz command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10100000 from host programming manual powerstep01 82/92 docid025022 rev 5 11.2.19 hardhiz the hardhiz command immediately disables th e power bridges (high impedance state) and raises the hiz flag. when the motor is stopped, a hardhiz command forces the bridges to enter high impedance state. this command can be given anytim e and is immediately executed. this command keeps the busy flag low until the motor is stopped. 11.2.20 getstatus the getstatus command returns the status register value. the getstatus command resets the status re gister warning flags. the command forces the system to exit from any error state. the getstatus co mmand does not reset the hiz flag. table 78. hardhiz command structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10101000 from host table 79. getstatus command structure bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 11010000 from host status msbyte to host status lsbyte to host docid025022 rev 5 83/92 powerstep01 package information 92 12 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. vfqfpn package information figure 30. vfqfpn 11 x 14 x 1.0 - 9 die pads drawing - side view package information powerstep01 84/92 docid025022 rev 5 figure 31. vfqfpn 11 x 14 x 1.0 - 9 die pads drawing - bottom view docid025022 rev 5 85/92 powerstep01 package information 92 figure 32. vfqfpn 11 x 14 x 1.0 - 9 die pads drawing - pin identifier package information powerstep01 86/92 docid025022 rev 5 table 80. vfqfpn 11 x 14 x 1.0 - 9 die pads - 89 leads (1) , (2) , (3) , (4) , (5) 1. the pin #1 identifier must exist on the top surface of the package by using indentation mark or other feature of package body. exact shape and size of this feature is optional. 2. dimensioning and tolerances conform to asme y14.5-2009. 3. all dimensions ar e in millimeters. 4. the location of the marked terminal #1 identifier is within the hatched area. 5. coplanarity applies to the terminals and all other bottom surface metalization. symbol dimensions (mm) note min. typ. max. a 0.80 0.90 1.00 (6) 6. vfqfpn stands for ?thermally enhanced very th in fine pitch quad flat packages no lead?. very thin: 0.80 mm < a1.00 mm / fine pitch: e < 1.00 mm. a1 0.00 0.02 0.05 a3 --- 0.20 ref. --- b 0.15 0.2 0.25 (7) 7. dimension b applies to the metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has a radius on the other end of it, dimension b should not be measured in that radius area. d 10.90 11.00 11.10 e 13.90 14.00 14.10 d1 2.00 2.15 2.25 e1 2.70 2.85 2.95 d2 5.35 5.50 5.60 e2 4.54 4.69 4.79 d3 2.17 2.32 2.42 e3 2.88 3.03 3.13 d4 1.01 1.16 1.26 e4 0.54 0.69 0.79 l 0.3 0.4 0.5 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 n 89 (8) 8. n is the total number of terminals. lf part no. 443448 docid025022 rev 5 87/92 powerstep01 package information 92 figure 33. recommended footprint - suggested landpattern (overall view) (1) 1. all dimensions are in mm. " . package information powerstep01 88/92 docid025022 rev 5 figure 34. recommended footprint - lead land positioning (1) 1. all dimensions are in mm. " . docid025022 rev 5 89/92 powerstep01 package information 92 figure 35. recommended footprint - la nd size and exposed pad positioning (1) 1. all dimensions are in mm. " . package information powerstep01 90/92 docid025022 rev 5 figure 36. recommended footprint - detail a and b drawing (1) 1. all dimensions are in mm. " . docid025022 rev 5 91/92 powerstep01 revision history 92 13 revision history 2 table 81. document revision history date revision changes 22-jul-2013 1 initial release. 16-jun-2014 2 several modifications. 03-oct-2014 3 updated main title on page 1 (replaced ?8-n channel? by ?10 a?). updated package silhouette on page 1 (replaced by new figure). updated section : applications on page 1 (added sub-list). updated table 2 on page 10 (removed ?p tot ?, ?peak? and unit of i out1x symbol). updated table 4 on page 12 (updated ?test conditions? and values of r ds(on) , sr out , i dss and t ocd,sd symbols). added section 7.15 on page 34 . minor modifications throughout document. 22-apr-2015 4 document updated from ?prelim inary? to ?production data?. updated table 4 on page 12 (updated max. values). updated table 5 on page 18 (updated pin no. of outa1). updated table 8 on page 32 [replaced ?of? by ?on? in high- side gate driver supply turn- on threshold ?? v bootthon )]. updated table 12 on page 51 (updated length column of step_mode and fs_spd). updated table 15 on page 55 (removed bit 11 column). updated section 12: package information on page 83 (replaced figure 30 to figure 32 and table 80 by new figures/table). minor modifications throughout document. 10-jun-2015 5 updated table 4 on page 12 (updated max. values). updated table 45 on page 68 (updated values). added figure 33 on page 87 to figure 36 on page 90 . minor modifications throughout document. powerstep01 92/92 docid025022 rev 5 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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