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1 features ? single voltage operation C 5v read C 5v reprogramming ? fast read access time - 90 ns ? internal erase/program control ? sector architecture C one 8k words (16k bytes) boot block with programming lockout C two 8k words (16k bytes) parameter blocks C one 488k words (976k bytes) main memory array block ? fast sector erase time - 10 seconds ? word-by-word programming - 50 m s/word ? hardware data protection ? data polling for end of program detection ? low power dissipation C 50 ma active current C 300 m a cmos standby current ? typical 10,000 write cycles description the at49f8192 is a 5-volt-only, 8 megabit flash memory organized as 512k words of 16 bits each. manufactured with atmel's advanced nonvolatile cmos technology, the device offers access times to 90 ns with power dissipation of just 275 mw. when deselected, the cmos standby current is less than 300 m a. pin configurations pin name function a0 - a18 addresses ce chip enable oe output enable we write enable reset reset i/o0 - i/o15 data inputs/outputs nc no connect 0588d-aC10/97 tsop top view type 1 soic (sop) 8-megabit (512k x 16) 5-volt only cmos flash memory at49f8192 at49f8192t
at49f8192/8192t 2 the device contains a user-enabled boot block protection feature. two versions of the feature are available: the at49f8192 locates the boot block at lowest order addresses (bottom boot); the at49f8192t locates it at highest order addresses (top boot). to allow for simple in-system reprogrammability, the at49f8192 does not require high input voltages for pro- gramming. five-volt-only commands determine the read and programming operation of the device. reading data out of the device is similar to reading from an eprom; it has standard ce , oe , and we inputs to avoid bus conten- tion. reprogramming the at49f8192 is performed by first erasing a block of data and then programming on a word- by-word basis. the device is erased by executing the erase command sequence; the device internally controls the erase opera- tion. the memory is divided into three blocks for erase operations. there are two 8k word parameter block sec- tions and one sector consisting of the boot block and the main memory array block. the at49f8192 is programmed on a word-by-word basis. the device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. once the boot block programming lockout feature is enabled, the data in the boot block can- not be changed when input levels of 5.5 volts or less are used. the typical number of program and erase cycles is in excess of 10,000 cycles. the optional 8k word boot block section includes a repro- gramming lock out feature to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. block diagram device operation read: the at49f8192 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus conten- tion. command sequences: when the device is first pow- ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the command definitions table (i/o8 - i/o15 are don't care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respec- tively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address loca- tions used in the command sequences are not affected by entering the command sequences. reset: a reset input pin is provided to ease some sys- tem applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. by applying a 12v 0.5v input signal to the reset pin the boot block array can be repro- grammed even if the boot block program lockout feature has been enabled (see boot block programming lockout override section). v cc gnd oe control logic data inputs/outputs i/o0 - i/o15 data inputs/outputs i/o0 - i/o15 we ce reset address inputs y decoder input/output buffers input/output buffers program data latches program data latches y-gating at49f8192 at49f8192t y-gating 7ffff 7ffff main memory (488k words) boot block 8k words parameter block 2 8k words parameter block 1 8k words parameter block 1 8k words parameter block 2 8k words boot block 8k words main memory (488k words) 06000 05fff 7e000 7dfff 04000 03fff 7c000 7bfff x decoder 02000 01fff 7a000 79fff 00000 00000
at49f8192/8192t 3 erasure: before a word can be reprogrammed, it must be erased. the erased state of the memory bits is a logical 1. the entire device can be erased at one time by using a 6-byte software code. after the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time needed to erase the whole chip is t ec . chip erase: if the boot block lockout has been enabled, the chip erase function is disabled; sector erases for the parameter blocks and main memory block will still operate. after the full chip erase the device will return back to read mode. any command during chip erase will be ignored. sector erase: as an alternative to a full chip erase, the device is organized into three sectors that can be indi- vidually erased. there are two 8k word parameter block sections and one sector consisting of the boot block and the main memory array block. the sector erase command is a six bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched at the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operation is internally controlled; it will automatically time to completion. when the boot block pro- gramming lockout feature is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued. word programming: once a memory block is erased, it is programmed (to a logical 0) on a word-by- word basis. programming is accomplished via the internal device command register and is a 4 bus cycle operation. the device will automatically generate the required internal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset hap- pens during programming, the data at the location being programmed will be corrupted. please note that a data 0 cannot be programmed back to a 1; only erase operations can convert 0s to 1s. programming is completed after the specified tbp cycle time. the data polling feature may also be used to indicate the end of a program cycle. boot block programming lockout: the device has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 8k words. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be acti- vated; the boot block's usage as a write protected region is optional to the user. the address range of the 48f8192 boot block is 00000h to 01fffh while the address range of the 49f8192t is 7e000h to 7ffffh. once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5v or less are used. data in the main memory block can still be changed through the regular programming method. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the command definitions table. boot block lockout detection: a software method is available to determine if programming of the boot block section is locked out. when the device is in the soft- ware product identification mode (see software product identification entry and exit sections) a read from address location 00002h will show if programming the boot block is locked out. if the data on i/o0 is low, the boot block can be programmed; if the data on i/o0 is high, the program lock- out feature has been enabled and the block cannot be pro- grammed. the software product identification exit code should be used to return to standard operation. boot block programming lockout over- ride: the user can override the boot block programming lockout by taking the reset pin to 12 volts during the entire chip erase, sector erase or word programming oper- ation. when the reset pin is brought back to ttl levels the boot block programming lockout feature is again active. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at49f8192 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sec- tor erase operation, an attempt to read the device will give a 0 on i/o7. once the program or erase cycle has com- pleted, true data will be read from the device. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the at49f8192 provides another method for determining the end of a pro- gram or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data
at49f8192/8192t 4 will be read. examining the toggle bit may begin at any time during a program cycle. hardware data protection: hardware features protect against inadvertent programs to the at49f8192 in the following ways: (a) v cc sense: if v cc is below 3.8v (typical), the program function is inhibited. (b) v cc power on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (don't care); i/o7 - i/o0 (hex) 2. the 8k word boot sector has the address range 00000h to 01fffh for the at49f8192 and 7e000h to 7ffffh for the at49f8192t. 3. either one of the product id exit commands can be used. 4. sa = sector addresses: for the at49f8192 sa = 03xxx for parameter block 1 sa = 05xxx for parameter block 2 sa = 7fxxx for main memory array for the at49f8192t sa = 7dxxx for parameter block 1 sa = 7bxxx for parameter block 2 sa = 79xxx for main memory array 5. when the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together (form the same sector erase command). once the boot region has been pro- tected, only the main memory array sector will erase when its sector erase command is issued. command definition (in hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (4)(5) 30 word program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (2) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (3) 3 5555 aa 2aaa 55 5555 f0 product id exit (3) 1xxxxf0 absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyong those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground ......................... -0.6v to v cc to +0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
at49f8192/8192t 5 dc and ac operating range operating modes notes: 1. x can be v il or v ih . 2. refer to ac programming characteristics. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh, device code: a0h (49f8192), a3h (49f8192t). 5. see details under software product identification entry/exit. dc characteristics note: 1. in the erase mode, i cc is 90 ma. at49f8192-90 at49f8192-12 operating temperature (case) com. 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% mode ce oe we reset ai i/o read v il v il v ih v ih ai d out program/erase (2) v il v ih v il v ih ai d in standby/write inhibit v ih x (1) xv ih xhigh z program inhibit x x v ih v ih program inhibit x v il xv ih output disable x v ih xv ih high z reset x x x v il xhigh z product identification hardware v il v il v ih v ih a1 - a18 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a18 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a18 = v il manufacturer code (4) a0 = v ih , a1 - a18 = v il device code (4) symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 300 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .45 v v oh1 output high voltage i oh = -400 m a2.4v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v
at49f8192/8192t 6 ac read characteristics ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact in t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. symbol parameter at49f8192-90 at49f8192-12 units min max min max t acc address to output delay 90 120 ns t ce (1) ce to output delay 90 120 ns t oe (2) oe to output delay 0 40 0 50 ns t df (3, 4) ce or oe to output float 0 25 0 30 ns t oh output hold from oe , ce or address, whichever occurred first 0 0 ns input test waveforms and measurement level t r , t f < 5 ns output test load pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. typ max units conditions c in 46 pfv in = 0v c out 812 pfv out = 0v
at49f8192/8192t 7 ac word load characteristics ac word load waveforms we controlled ce controlled symbol parameter min max units t as , t oes address, oe set-up time 10 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 10 ns t wph write pulse width high 90 ns
at49f8192/8192t 8 program cycle characteristics program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 5555. for sec- tor erase, the address depends on what sector is to be erased. (see note 4 under command definitions.) 3. for chip erase, the data should be 10 h , and for sector erase, the data should be 30 h . symbol parameter min max units t bp word programming time 50 m s t as address set-up time 10 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 10 ns t wp write pulse width 90 ns t wph write pulse width high 90 ns t ec erase cycle time 10 seconds
at49f8192/8192t 9 data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms toggle bit characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling the input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
at49f8192/8192t 10 software product identification entry (1) software product identifcation exit (1)(6) notes: 1. data format: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex) address format: a14 - a0 (hex). 2. a1 - a18 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1fh device code: a0h (49f8192), a3h (49f8192t) 6. either one of the product id exit commands can be used. boot block lockout enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (dont care); i/o7 - i/o7 (hex) address format: a14 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 or load data f0 to any address load data 55 to address 2aaa exit product identification mode (4) load data f0 to address 5555 exit product identification mode (4) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 second
at49f8192/8192t 11 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 90 50 0.3 at49f8192-90tc 48t commercial at49f8192-90rc 44r (0 to 70 c) 50 0.3 at49f8192-90ti 48t industrial at49f8192-90ri 44r (-40 to 85 c) 120 50 0.3 at49f8192-12tc 48t commercial at49f8192-12rc 44r (0 to 70 c) 50 0.3 at49f8192-12ti 48t industrial at49f8192-12ri 44r (-40 to 85 c) 90 50 0.3 at49f8192t-90tc 48t commercial at49f8192t-90rc 44r (0 to 70 c) 50 0.3 at49f8192t-90ti 48t industrial at49f8192t-90ri 44r (-40 to 85 c) 120 50 0.3 at49f8192t-12tc 48t commercial at49f8192t-12rc 44r (0 to 70 c) 50 0.3 at49f8192t-12ti 48t industrial at49f8192t-12ri 44r (-40 to 85 c) package type 48t 48-lead, thin small outline package (tsop) 44r 44-lead, 0.525" wide, plastic gull wing small outline package (soic/sop)

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