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1 negative voltage hot swap controllers with adc and i 2 c monitoring the lt c ? 4261/ltc4261-2 negative voltage hot swap tm controllers allow a board to be safely inserted and removed from a live backplane. using an external n-channel pass transistor, the board supply voltage can be ramped at an adjustable rate. the devices feature independently adjust - able inrush current and overcurrent limits to minimize stresses on the pass transistor during start-up, input step and output short conditions. the l tc4261 defaults to latch-off while the l tc4261-2 defaults to auto-retry on overcurrent faults. an i 2 c interface and onboard 10-bit adc allow monitoring of board current, voltage and fault status. a single-wire broadcast mode is available to simplify the interface by eliminating two optoisolators. the controllers have additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a board and turn off the pass transistor if an external supply monitor fails to indicate power good within a timeout period. n advancedtca systems n telecom infrastructure n C48v distributed power systems n power monitors n allows safe insertion into live C48v backplanes n 10-bit adc monitors current and voltages n i 2 c/smbus interface or single-wire broadcast mode n floating topology allows very high voltage operation n independently adjustable inrush and overcurrent limits n controlled soft-start inrush n adjustable uv/ov thresholds and hysteresis n sequenced power good outputs with delays n adjustable power good input timeout n programmable latchoff or auto-retry after faults n alerts host after faults n available in 28-lead narrow ssop and 24-lead (4mm 5mm) qfn packages C48v/200w hot swap controller with i 2 c and adc + pgi alert sdao sdai scl adin pgio pg uvl uvh adin2 ov intv cc on ramp drain gate ltc4261cgn v in v ee en tmr ss sense 1m 4 1k in series 1/4w each 453k 1% ?48v rtn ?48v input uv = 38.5v uv release at 43v ov release at 71v ov = 72.3v 16.9k 1% 11.8k 1% 10nf 100v 5% 47nf 0.1f 1f 220nf 47nf 0.008 1% 10 v out q1 irf1310ns 1k 330f 100v load on 42612 ta01 v in + v in ? start-up behavior typical application features applications description ?48v input 50v/div v out 50v/div sense 0.5a/div pg 50v/div 10ms/div 42612 ta01b l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7382167, 8194379, 8230151. ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
2 v in (note 3) .......................................... C0. 3v to 10.65v drain (note 4) .......................................... C 0.3v to 3.5v pgi , on, alert , sdao, sdai, scl, adin, adin2, ov, sense, adr1, adr0, flti n , tmr, ss, ramp voltages ................... C 0.3v to intv cc + 0.3v uvl, uvh, en ............................................ C 0.3v to 10v gate voltage .................................. C 0.3v to v in + 0.3v pg , pgio voltages .................................... C 0.3v to 80v supply voltage (intv cc ) .......................... C0 .3v to 5.5v (notes 1, 2) operating ambient temperature range lt c4261c ................................................ 0 c to 70c l tc4261i ............................................. C 40c to 85c storage temperature range s sop ................................................. C 65c to 150c qf n .................................................... C 65c to 125c lead temperature (soldering, 10 sec) ss op only ........................................................ 3 00c absolute maximum ratings 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pgi on alert sdao sdai scl intv cc uvl uvh adin2 ov nc v ee sense pgio pg en adr1 adr0 adin fltin v in tmr ss ramp nc drain gate t jmax = 125c, ja = 85c/w 8 9 top view 25 ufd package 24-lead (4mm 5mm) plastic qfn 10 11 12 24 23 22 21 20 6 5 4 3 2 1 sdao sdai scl intv cc uvl uvh ov en adr1 adr0 adin v in tmr ss alert on pgi pgio pg v ee sense gate drain ramp 7 14 15 16 17 18 19 13 t jmax = 125c, ja = 45c/w exposed pad (pin 25) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc4261cgn#pbf ltc4261cgn#trpbf ltc4261cgn 28-lead plastic ssop 0c to 70c ltc4261ign#pbf ltc4261ign#trpbf ltc4261ign 28-lead plastic ssop C40c to 85c ltc4261cgn-2#pbf ltc4261cgn-2#trpbf ltc4261ign-2 28-lead plastic ssop 0c to 70c ltc4261ign-2#pbf ltc4261ign-2#trpbf ltc4261ign-2 28-lead plastic ssop C40c to 85c ltc4261cufd#pbf ltc4261cufd#trpbf 4261 24-lead (4mm 5mm) plastic qfn 0c to 70c ltc4261iufd#pbf ltc4261iufd#trpbf 4261 24-lead (4mm 5mm) plastic qfn C40c to 85c ltc4261cufd-2#pbf ltc4261cufd-2#trpbf 42612 24-lead (4mm 5mm) plastic qfn 0c to 70c ltc4261iufd-2#pbf ltc4261iufd-2#trpbf 42612 24-lead (4mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
3 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at i in = 5ma, t a = 25c. (note 2) symbol parameter conditions min typ max units general v z shunt regulator voltage at v in i in = 5ma l 10.65 11.2 11.8 v dv z shunt regulator load regulation i in = 5ma to 25ma l 370 600 mv i in v in supply current v in = v z C 0.3v l 2 5 ma v in(uvlo) v in undervoltage lockout threshold v in rising l 8.5 9 9.5 v dv in(uvlo) v in undervoltage lockout hysteresis l 0.3 0.7 1 v intv cc internal regulator voltage i load = 1ma to 20ma, i in = 25ma l 4.75 5 5.25 v gate drive v gateh gate pin output high voltage v in = 10.65v l 10 10.25 10.5 v i gate(up) gate pin pull-up current v gate = 4v l C7.5 C11.5 C15.5 a i gate(off) gate turn-off current v sense = 400mv, v gate = 4v l 45 90 120 ma gate off, v gate = 4v l 60 110 140 ma t phl(sense) sense high to current limit v sense = 100mv, gate open l 0.5 1.5 s propagation delay v sense = 300mv, gate open l 0.2 0.5 s t phl(gate) gate off propagation delay input high (ov, en, pgi), input low (on, uvl), gate open l 0.2 0.5 s t phlcb circuit breaker gate off delay v gate < 2v, gate open l 440 530 620 s i ramp ramp pin current v ss = 2.56v l C18 C20 C22 a v ss ss pin clamp voltage l 2.43 2.56 2.69 v i ss(up) ss pin pull-up current v ss = 0v l C7 C10 C13 a i ss(dn) ss pin pull-down current v ss = 2.56v l 6 12 20 ma input pins v uvh(th) uvh threshold voltage v uvh rising ltc4261c ltc4261i l l 2.534 2.522 2.56 2.56 2.586 2.598 v v uvl(th) uvl threshold voltage v uvl falling ltc4261c ltc4261i l l 2.263 2.254 2.291 2.291 2.319 2.328 v d v uv(hyst) built-in uv hysteresis uvh and uvl tied together l 256 269 282 mv dv uv uvh, uvl minimum hysteresis 15 mv v uvlr(th) uvl reset threshold voltage v uvl falling l 1.12 1.21 1.30 v dv uvlr(hyst) uvl reset hysteresis 60 mv v ov(th) ov pin threshold voltage v ov rising ltc4261c ltc4261i l l 1.744 1.735 1.770 1.770 1.796 1.805 v d v ov(hyst) ov pin hysteresis l 18 37.5 62 mv dv sense current limit sense voltage threshold v sense C v ee l 45 50 55 mv v input(th) on, en, pgi, fltin threshold voltage on, en, pgi, fltin falling or rising l 0.8 1.4 2 v dv input(hyst) on, en, pgi, fltin hysteresis 170 mv v pgio(th) pgio pin input threshold voltage v pgio rising l 1.10 1.25 1.40 v dv pgio(hyst) pgio pin input hysteresis 100 mv i input on, en , uvh, uvl, ov, sense, pgi, fltin input current on, en , uvh, uvl, ov, sense, pgi, fltin = 3v l 0 2 a electrical characteristics ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
4 symbol parameter conditions min typ max units timer v tmr(h) tmr pin high threshold v tmr rising l 2.43 2.56 2.69 v v tmr(l) tmr pin low threshold v tmr falling l 40 75 110 mv i tmr(up) tmr pin pull-up current turn-on and auto-retry (except oc) delays, v tmr = 0.2v l C7 C10 C13 a power good, pgi check and oc auto-retry delays, v tmr = 0.2v l C3.5 C5 C6.5 a i tmr(dn) tmr pin pull-down current delays except pgi check or oc auto-retry, v tmr = 2.56v l 6 12 20 ma pgi check and oc auto-retry delays, v trm = 2.56v l 3 5 7 a output pins v pwrgd pg, pgio pins output low i pg , i pgio = 3ma i pg , i pgio = 500a l l 0.8 0.15 1.6 0.4 v v i pwrgd pg, pgio pins leakage current pg, pgio = 80v l 0 10 a adc resolution (no missing codes) (note 5) l 10 bits inl integral nonlinearity sense l 0.5 2.5 lsb adin2/ov, adin l 0.25 1.25 lsb v os offset error sense l 1.75 lsb adin2/ov, adin l 1.25 lsb full-scale voltage sense l 62.8 64 65.2 mv adin2/ov, adin l 2.514 2.560 2.606 v total unadjused error sense l 1.8 % adin2/ov, adin l 1.6 % conversion rate l 5.5 7.3 9 hz r adin adin, adin2 pins input resistance adin, adin2 = 1.28v l 2 10 mw i adin adin, adin2 pins input current adin, adin2 = 2.56v l 0 2 a i 2 c interface v adr(h) adr0, adr1 input high threshold l intv cc C 0.8 int v cc C 0.5 int v cc C 0.3 v v adr(l) adr0, adr1 input low threshold l 0.3 0.5 0.8 v i adr(in) adr0, adr1 input current adr0, adr1 = 0v, 5v l 80 a adr0, adr1 = 0.8v, (intv cc C 0.8v) l 10 a v alert (ol) alert pin output low voltage i alert = 4ma l 0.2 0.4 v v sdao(ol) sdao pin output low voltage i sdao = 4ma l 0.2 0.4 v i sdao, alert(in) sdao, alert input current sdao, alert = 5v l 0 5 a v sdai,scl(th) sdai, scl input threshold l 1.6 1.8 2 v i sdai,scl(in) sdai, scl input current sdai, scl = 5v l 0 2 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at i in = 5ma, t a = 25c. (note 2) electrical characteristics ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
5 symbol parameter conditions min typ max units i 2 c interface timing (note 5) f scl(max) maximum scl clock frequency 400 khz t low minimum scl low period 0.65 1.3 s t high minimum scl high period 50 600 ns t buf(min) minimum bus free time between stop/ start condition 0.12 1.3 s t hd,sta(min) minimum hold time after (repeated) start condition 140 600 ns t su,sta(min) minimum repeated start condition set-up time 30 600 ns t su,sto(min) minimum stop condition set-up time 30 600 ns t hd,dati(min) minimum data hold time input C100 0 ns t hd,dato(min) minimum data hold time output 300 600 900 ns t su,dat(min) minimum data set-up time input 30 100 ns t sp(max) maximum suppressed spike pulse width 50 110 250 ns t rst stuck-bus reset time scl or sdai held low 25 66 ms c x scl,sda input capacitance sdai tied to sdao 5 10 pf the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at i in = 5ma, t a = 25c. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive, all voltages are referenced to device gnd (v ee ) unless otherwise specified. note 3: an internal shunt regulator limits the v in pin to a minimum of 10.65v. driving this pin to voltages beyond 10.65v may damage the part. the pin can be safely tied to higher voltages through a resistor that limits the current below 50ma. note 4: an internal clamp limits the drain pin to a minimum of 3.5v. driving this pin to voltages beyond the clamp may damage the part. the pin can be safely tied to higher voltages through a resistor that limits the current below 2ma. note 5: guaranteed by design and not subject to test. electrical characteristics ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
6 shunt regulator voltage vs input current shunt regulator voltage vs temperature intv cc vs load current gate output high voltage vs temperature gate pull-up current vs gate voltage ramp pin current vs temperature uvh threshold vs temperature uvl threshold vs temperature i in = 5ma, t a = 25c, unless otherwise noted shunt regulator voltage at v in (v) 10.8 0 v in pin input current (ma) 5 10 15 20 25 30 11 11.2 11.4 11.6 42612 g01 11.8 temperature (c) ?50 11.10 shunt regulator voltage at v in (v) 11.15 11.20 11.25 11.30 11.35 ?25 0 25 50 42612 g02 75 100 i in = 5ma load current (ma) 0 intv cc voltage (v) 5.00 5.02 20 42612 g03 4.98 4.96 5 10 15 5.06 5.04 i in = 25ma temperature (c) ?50 10.0 gate output high voltage (v) 10.1 10.2 10.3 10.4 ?25 0 25 50 42612 g04 75 100 10.5 v in = 10.65v gate turn-off current vs sense voltage temperature (c) ?50 2.545 uvh threshold voltage (v) 2.550 2.555 2.560 2.565 2.575 ?25 0 25 50 42612 g08 75 100 2.570 temperature (c) ?50 2.275 uvh threshold voltage (v) 2.280 2.285 2.290 2.295 2.305 ?25 0 25 50 42612 g09 75 100 2.300 gate voltage (v) 0 ?12 gate pull-up current (a) ?2 ?4 ?6 ?8 0 2 4 6 8 42612 g05 10 12 ?10 temperature (c) ?50 ?19.0 ramp pin current (a) ?19.5 ?20.0 ?20.5 ?21.0 ?22.0 ?25 0 25 50 42612 g07 75 100 ?21.5 typical performance characteristics v sense (mv) i gate(off) (ma) 100 42612 g06 1 10 100 500 400 300 200 0 v gate = 4v ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
7 ov threshold vs temperature ov hysteresis vs temperature current limit voltage vs temperature current limit propagation delay (t phl(sense) ) vs v sense pg, pgio output low vs load current adc total unadjusted error vs code (adin pin) adc full-scale error vs temperature (adin pin) adc inl vs code (adin pin) adc dnl vs code (adin pin) i in = 5ma, t a = 25c, unless otherwise noted temperature (c) ?50 1.755 ov threshold voltage (v) 1.760 1.765 1.770 1.775 1.785 ?25 0 25 50 42612 g10 75 100 1.780 temperature (c) ?50 25 ov hysteresis (mv) 30 35 40 45 50 ?25 0 25 50 42612 g11 75 100 typical performance characteristics temperature (c) ?50 49.0 current limit sense voltage (mv) 49.5 50.0 50.5 51.0 52.0 ?25 0 25 50 42612 g12 75 100 51.5 v sense (mv) 0 t phl(sense) (ns) 400 42612 g13 100 100 200 300 500 1000 c gate = 1pf load current (ma) 0 0 pg output low voltage (v) 1 2 3 4 5 6 2 4 6 8 42612 g14 10 t a = 85c t a = 25c t a = ?40c code 0 adc total unadjusted error (lsb) 0 0.5 1024 42612 g15 ?0.5 ?1.0 256 512 768 1.0 temperature (c) ?50 ?3 adc full-scale error (lsb) ?2 ?1 0 1 3 ?25 0 25 50 42612 g16 75 100 2 code 0 adc inl (lsb) 0 0.5 1024 42612 g17 ?0.5 ?1.0 256 512 768 1.0 code 0 adc dnl (lsb) 0 0.5 1024 42612 g18 ?0.5 ?1.0 256 512 768 1.0 ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
8 adin (pin 23/pin 16): adc input. a voltage between 0v and 2.56v applied to this pin is measured by the on-chip adc. tie to v ee if unused. adin2 (pin 10/na): second adc input. not available on qfn package. adr0, adr1 (pins 24, 25/pins 17, 18): serial bus ad - dress inputs. tying these pins to v ee , open or intv cc configures one of nine possible addresses. see table 1 in applications information. alert (pin 3/pin 24): fault alert output. open-drain logic output that pulls to v ee when a fault occurs to alert the host controller. a fault alert is enabled by the alert register. see applications information. connect to v ee if unused. drain (pin 16/pin 11): drain sense input. connect an external 1m resistor between this pin and the drain terminal (v out ) of the n-channel fet. when the drain pin volt - age is less than 1.77v and the gate pin voltage is above v z C 1.2v the power good outputs are asserted after a delay. the voltage at this pin is internally clamped to 4v. en (pin 26/pin 19): device enable input. pull low to enable the n-channel fet to turn-on after a start-up debounce delay set by the tmr pin. when this pin is pulled high, the fet is off. transitions on this pin will be recorded in the fault register. a high-to-low transition activates the logic to read the state of the on pin and clear faults. requires external pull-up. debouncing with an external capacitor is recommended when used to monitor board present. connect to v ee if unused. exposed pad (pin 25, qfn only): exposed pad may be left open or connected to device ground (v ee ). fltin (pin 22/na): general purpose fault input. if this pin pulls low, the fault register bit b7 is latched to 1. this pin is used to sense an external fault condition and its status does not affect the fet control functions of the ltc4261. not available on the qfn package. connect to intv cc if unused. gate (pin 15/pin 10): n-channel fet gate drive output. this pin is pulled up by an internal current source i gate (11.5a when the ss pin reaches its clamping voltage). gate stays low until v in and intv cc cross the uvlo thresholds, uv and ov conditions are satisified and an adjustable timer delay expires. during turn-off, caused by faults or undervoltage lockout (v in or intv cc ), a 110ma pull-down current between gate and v ee is activated. intv cc (pin 7/pin 4): low voltage (5v) supply output. this is the output of the internal linear regulator with an internal uvlo threshold of 4.25v. this voltage powers up the data converter and logic control circuitry. bypass this pin with a 0.1f capacitor to v ee . on (pin 2/pin 23): on control input. a rising edge turns on the external n-channel fet while a falling edge turns it off. this pin is also used to configure the state of the fet on register bit d3 in the control register (and hence the external fet) at power-up. for example if the on pin is tied high, then the register bit d3 goes high one timer cycle after power-up. likewise, if the on pin is tied low, then the device remains off after power-up until the register bit d3 is set high using the i 2 c bus. a high-to-low transition on this pin clears faults. ov (pin 11/pin 7): overvoltage detection input. connect this pin to an external resistive divider from v ee . if the voltage at the pin rises above 1.77v, the n-channel fet is turned off. the overvoltage condition does not affect the status of the power good outputs. on the qfn package, this pin is also measured by the on-chip adc. connect to v ee if unused. pg (pin 27/pin 20): power good status output. this open- drain pin pulls low and stays latched a timer delay after the fet is on (when gate reaches v z C 1.2v and drain is within 1.77v of v ee ). the power good output is reset in all gate pull-down events except an overvoltage fault. connect to v ee if unused. pin functions (ssop/qfn) ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
9 pgi (pin 1/pin 22): power good input. this pin along with the pgi check timer serves as a watchdog to monitor the power-up of the dc/dc converter. the pgi pin must be low before the pgi check timer expires, otherwise the gate pin pulls down and stays latched and a power bad fault is logged into the fault register. the pgi timer is started after the second power good is latched and its delay is equal to four times the start-up debounce delay. connect to v ee if unused. pgio (pin 28/pin 21): general purpose input/output. open-drain logic output and logic input. defaults to pull low a timer delay after the pg pin goes low to indicate a second power good output. configure according to table 6. ramp (pin 18/pin 12): inrush current ramp control pin. the inrush current is set by placing a capacitor (c r ) between the ramp pin and the drain terminal of the fet. at start-up, the gate pin is pulled up by i gate(up) until the pass transistor begins to turn on. a current, i ramp , then flows through c r to ramp down the output voltage v out . the value of i ramp is controlled by the ss pin voltage. when the ss pin reaches its clamp voltage (2.56v), i ramp = 20a. the ramp rate of v out and the load capacitor c l set the inrush current: i inrush = (c l /c r ) ? i ramp . scl (pin 6/pin 3): serial bus clock input. data at the sdai pin is shifted in and data at the sdao pin is shifted out on rising edges of scl. this is a high impedance pin that is generally connected to the output of the incoming optoisolator driven by the scl port of the master controller. an external pull-up resistor or current source is required. pull up to intv cc if unused. sdai (pin 5/pin 2): serial bus data input. this is a high impedance input pin used for shifting in command bits, data bits and sdao acknowledge bits. an external pull-up resistor or current source is required. normally connected to the output of the incoming optoisolator that is driven by the sda port of the master controller. if the master controller separates sdai and sdao, data read at sdao needs to be echoed back to sdai for proper i 2 c commu- nication. pull up to intv cc if unused. sdao (pin 4/pin 1): serial bus data output. open-drain output used for sending data back to the master controller or acknowledging a write operation. an external pull-up resistor or current source is required. normally connected to the input of the outgoing optoisolator that outputs to the sda port of the master controller. in the single-wire broadcast mode, the sdao pin sends out selected data that is encoded with an internal clock. sense (pin 14/pin 9): current limit sense input. load current through the external sense resistor (r s ) is moni - tored and controlled by an active current limit amplifier to 50mv /r s . once v sense reaches 50mv, a circuit breaker timer starts and turns off the pass transistor after 530s. in the event of a catastrophic short circuit, if v sense crosses 250mv, a fast response comparator immediately pulls the gate pin down to control the current of the n-channel fet. ss (pin 19/pin 13): soft-start input. connect a capaci - tor to this pin to control the rate of rise of inrush current (di/dt) during start-up. an internal 10a current sour ce charging the external soft-start capacitor (c ss ) creates a voltage ramp. this voltage is converted to a current to charge the gate pin up and to ramp the output voltage down. the ss pin is internally clamped to 2.56v limiting i gate(up) to 11.5a and i ramp to 20a. if the ss capacitor is absent, the ss pin ramps from 0v to 2.56v in 220s. tmr (pin 20/pin 14): delay timer input. connect a capaci - tor (c tmr ) to this pin to create timing delays at start-up, when power good outputs pull down, during pgi check and when auto-retrying after faults (except overvoltage fault). internal pull-up currents of 10a and 5a and pull-down currents of 5a and 12ma configure the delay periods as multiples of a nominal delay of 256ms ? c tmr / f. delays for start-up and auto-retry following undervolt - age or power bad fault are the same as the nominal delay. delays for sequenced power good outputs are twice of the nominal delay . delays for pgi check and auto-retry fol - lowing overcurrent fault are four times the nominal delay. (ssop/qfn) pin functions ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
10 v ee (pin 13/pin 8): negative supply voltage input and device ground. connect this pin to the negative side of the power supply. v in (pin 21/pin 15): positive supply input. connect this pin to the positive supply through a dropping resistor. an internal shunt regulator clamps v in at 11.2v. an internal undervoltage lockout (uvlo) circuit holds the gate low until v in is above 9v. bypass this pin with a 1f capacitor to v ee . uvh (pin 9/pin 6): undervoltage high level input. con - nect this pin to an external resistive divider from v ee . if the voltage at the uvh pin rises above 2.56v the pass transistor is allowed to turn on. a small capacitor at this pin prevents transients and switching noise from affecting the uvh threshold. connect to intv cc if unused. uvl (pin 8/pin 5): undervoltage low level input. con- nect this pin to an external resistive divider from v ee . if the voltage at the uvl pin drops below 2.291v, the pass transistor is turned off and the power good outputs go high impedance. pulling this pin below 1.21v resets faults and allows the pass transistor to turn back on. connect to intv cc if unused. pin functions (ssop/qfn) ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
11 block diagram + ? uvlo: v in = 9v intv cc = 4.25v v ee v ee v ee v sense 50mv v ee v ee v in v in v cc ssa ssc acl uvl uvh ov 20a intv cc gate ramp sense 2.56v 2.291v 10a 50na 3pf 5v 11.2v + ? + ? + ? + ? + ? + ? + ? 2.56v 1.77v + ? 2.56v 5a 5a tmr tmr adr0 v ee adr1 i 2 c device address single-wire enable ov uvh uvl ss 12ma 5a 8 + ? logic adin adin2/ov a0 v sense mux register i 2 c interface ? ? a7 a8 10 10 v ref = 2.56v 10-bit adc 42612 bd v ee v ee v ee + ? 40 pg pgio fltin pgi en on 1.77v dc gc 4v v z ? 1.2v gate drain scl sdai sdao alert decoder ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
12 the ltc4261/ltc4261-2 are designed to turn a boards supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live C 48v back plane. the devices also feature an onboard 10-bit adc and i 2 c interface that allows monitoring board current, voltages and faults. the main functional circuits of the ltc4261/ltc4261-2 are illustrated in the block diagram. in normal operation after a start-up debounce delay, the gate pin turns on the external n-channel fet passing power to the load. the gate pin is powered by a shunt regulated 11.2v supply on the v in pin that is derived from C48v rtn through a dropping resistor. the turn-on sequence starts by pulling the ss pin up. the voltage at the ss pin is converted to a current, i gate(up) , pulling the gate up. when the pass fet starts to turn on and charge the load capacitor, the inrush current flowing through the fet is a function of the capacitor at ramp (c r ), the load capacitor (c l ) and the ramp current (i ramp ) that flows from the ramp pin to c r : i inrush = i ramp ? c l c r i ramp and i gate(up) are approximately proportional to the ss pin voltage and are limited to 20a and 11.5a, respectively when ss reaches its clamping voltage (2.56v). the acl amplifier is used for overcurrent and short-circuit protection. it monitors the load current through the sense pin voltage and a sense resistor r s . in an overcurrent condition, the acl amplifier limits the current to 50mv/ r s by pulling down gate in an active servo loop. after a 530s timeout, the acl amplifier turns off the pass fet. in the event of a catastrophic short circuit, when v sense crosses 250mv, a fast response comparator immediately pulls the gate pin down. the drain and the gate voltages are monitored to de - termine if power is available for the load. two power good signals are sequenced on the pg pin (first power good signal) and the pgio pin (second power good signal), each with a debounce delay that is twice the start-up delay. the pgio pin can also be used as a general purpose input or output. the pgi pin serves as a watchdog to monitor the output of the dc/dc module. if the module output fails to come up, the ltc4261/ltc4261-2 shut down. the tmr pin generates delays for initial start-up, auto- retry following a fault, power good outputs and pgi check. the logic circuits a re powered by an internally generated 5v supply (available on the intv cc pin). prior to turning on the pass fet, both v in and intv cc voltages must ex - ceed their undervoltage lockout thresholds. in addition, the control inputs uvh, uvl, ov , en, on and pgi are monitored by comparators. the fet is held off until all start-up conditions are met. a 10-bit analog-to-digital converter (adc) is included in the ltc4261/ltc4261-2. the adc measures sense resistor voltage as well as voltage at the adin2/ov (ssop/qfn) and adin pins. the results are stored in on-board registers. an i 2 c interface is provided to read the adc data registers. it also allows the host to poll the device and determine if a fault has occurred. if the alert line is used as an interrupt, the host can respond to a fault in real time. the sda line is divided into sdai (input) and sdao (output) to facili - tate opto coupling with the system host. two three-state pins, adr0 and adr1, are used to decode eight device addresses. the inter face can also be configured through the adr0 and adr1 pins for a single-wire broadcast mode, sending adc data and faults status through the sdao pin to the host without clocking the scl line. this single-wire, one-way communication simplifies system design by eliminating two optocouplers on scl and sdai that are required by an i 2 c interface. operation ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
13 the ltc4261/ltc4261-2 are ideally suited for C48v distributed power systems and advancedtca systems. a basic 200w application circuit using the ltc4261 is shown in figure 1. a more complete application circuit with advancedtca connections is shown in figure 2. input power supply power for the ltc4261/ltc4261-2 is derived from the C48v rtn through an external current limiting resistor (r in ) to the v in pin. an internal shunt regulator clamps + fltin pgi scl sdai sdao alert pg adin 8 9 10 11 19 20 26 2 25 24 22 1 6 5 4 3 27 pwrgd1 23 uvl uvh adin2 ov ss tmr en on adr1 adro ramp drain gate ltc4261cgn v in intv cc v ee sense r d 1m r in 4 1k in series 1/4w each r3 453k 1% ?48v rtn ?48v input uv = 38.5v uv release at 43v ov release at 71v ov = 72.3v r2 16.9k 1% r1 11.8k 1% c r 10nf 100v 5% c f 33nf c tmr 47nf c ss 220nf c vcc 0.1f c in 1f c uv 100nf c g 47nf r s 0.008 1% r g 10 q1 irf1310ns r11 402k 1% r10 10k 1% r f 1k 13 14 15 16 18 c l 330f 100v 21 7 module2 on 42612 f01 v in + v in ? module1 on v in + v in ? v out pgio 28 pwrgd2 figure 1. C48v/200w hot swap controller using ltc4261 with current, input voltage and v ds monitoring (5.6a current limit, 0.66a inrush) figure 2a. 200w advancedtca hot swap controller with input/output monitoring and power good watchdog using l tc4261 in i 2 c mode (part one) 8 9 10 11 19 20 26 2 25 24 r d 1m r h 604 1% r3 412k 1% uv turn off = 34.2v uv release = 37.5v ov turn off = 74.8v ov release = 73.2v r2 19.1k 1% r14 100k r11 100k r10 100k rtn a rtn b enable a enable b ?48v a ?48v b r13 10k r12 10k mbrm5100 10a 10a r15 100k q10 2n5401 r1 10.5k 1% r16 100k c r 10nf 100v 5% c f 33nf c tmr 330nf c ss 330nf c uv 100nf 1n4148 2 c g 47nf r s 0.008 5% r g 10 q1 irf1310ns r f 1k 13 14 15 16 18 42612 f02a c en 1f hzs5c1 mbrm5100 q9 2n5401 7a ltc4354 plug-in card 7a backplane a b uvl uvh adin2 ov ss tmr en on adr1 adr0 ramp drain gate ltc4261cgn v ee v ee sense applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
14 22 1 6 5 28 27 4 3 v ee r6 100k r in 8 240 in series 1/4w each c vcc 0.1f v ee c in 1f moc207 21 7 23 r8 7.5k r7a 10k r7b 10k r9 5.1k r7 100k r24 5.1k r23 1k r22 1k r17 100k 1% q11 2n5401 output sense q12 2n5401 r19 2.49k 1% v ee v ee v out v out v out r20 2.49k 1% r18 100k 1% r4 20k r21 1k 5v lucent fltr100v10 v in + ?48v rtn output v in ? case v out + v out ? micro- controller v dd gnd scl sda alert mbrm5100 c l 4000f 100v 0v transient resevoir capacitor rst lucent jw050a1-e v in + v in ? v ee q5 moc207 on/off case ltc2900 supply monitor v dd rst gnd v out + v out ? r l 343 7 2.4k, 0805 each 28.7w + q8 a b anode v cc q3 hcpl-0300 gnd cathode r l v out anode v cc q4 q6 q7 42612 f02b 5v ps9113 ps9113 6n139 cathode v o v o v cc gnd anode cathode v o v cc anode cathode gnd gnd fltin pgi scl sdai pgio pg sdao alert ltc4261cgn v in intv cc adin figure 2b. 200w advancedtca hot swap controller with input/output monitoring and power good watchdog using ltc4261 in i 2 c mode (part two) the voltage at v in to 11.2v (v z ) and provides power to the gate driver. the data converter and logic control circuits are powered by an internal linear regulator that derives 5v from the 11.2v supply. the 5v output is available at the intv cc pin for driving external circuits (up to 20ma load current). bypass capacitors of 1f and 0.1f are recommended at v in and intv cc , respectively. r in should be chosen to accommodate the maximum supply current requirement of the ltc4261/ltc4261-2 (5ma) plus the supply current required by any external devices driven by the v in and intv cc pins at the minimum intended operation voltage. r in v 48v(min) C v z(max) i in(max) + i external the maximum power dissipation in the resistor is: p max = v 48v(max) C v z(min) ( ) 2 r in if the power dissipation is too high for a single resistor, use multiple resistors in series or supply external loads from a separate npn buffer as illustrated in figure 3. initial start-up and inrush control several conditions must be satisfied before the fet turn-on sequence is started. first the voltage at v in must exceed its 9v undervoltage lockout level. next the internal supply intv cc must cross its 4.25v undervoltage lockout level. this generates a 100s to 160s power-on-reset pulse during which the fault register bits are cleared and the control register bits are set or cleared as described in the register section. after the power-on-reset pulse, the voltages at the uvh, uvl and ov pins must satisfy uvh > 2.56v, uvl > 2.291v and ov < 1.77v to indicate that the input power is within the acceptable range and the en pin must be pulled low. all the above conditions must be satisfied throughout the duration of the start-up debounce delay that is set by an external capacitor (c tmr ) connected to the tmr pin. c tmr is charged with a pull-up current of applications information rtn 100 bcp56 v in or intv cc 10.5v or 4.3v 42612 f03 figure 3. npn buffer relieves r in of excessive dissipation when supplying external loads ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
15 10a until the voltage at tmr reaches 2.56v. c tmr is then quickly discharged with a 12ma current. the initial delay expires when tmr is brought below 75mv. the duration of the start-up delay is given by: t d = 256ms ? c tmr 1f if any of the above conditions is violated before the start-up delay expires, c tmr is quickly discharged and the turn-on sequence is restarted. after all the conditions are validated throughout the start-up delay, the on pin is then checked. if it is high, the fet will be turned on. otherwise, the fet will be turned on when the on pin is raised high or the fet on bit d3 in the control register is set to 1 through the i 2 c interface. the fet turn-on sequence follows by charging an external capacitor at the ss pin (c ss ) with a 10a pull-up current and the voltage at ss (v ss ) is converted to a current (i gate(up) ) of 11.5a v ss /2.56v for gate pull-up. when the gate reaches the fet threshold voltage, the inrush current starts to flow through the fet and a current (i ramp ) of 20a v ss /2.56v flows out of the ramp pin and through an external capacitor (c r ) connected between ramp and v out . the ss voltage is clamped to 2.56v, which cor - responds to i gate(up) = 11.5a and i ramp = 20a. the ramp pin voltage is regulated at 1.1v and the ramp rate of v out determines the inrush current: i inrush = 20a ? c l c r the ramp rate of v ss determines di/dt of the inrush current: di inrush dt = 20a ? c l c r ? 1f 256ms ? c ss if c ss is absent, an internal circuit pulls the ss pin from 0v to 2.56v in about 220s. when v out is ramped down to v ee , i gate returns to the gate pin and pulls the gate up to v gateh . figure 4 illustrates the start-up sequence of the ltc4261/ l tc4261 - 2. during board insertion and input power step, an internal clamp turns on to hold the ramp pin low. capacitor c f and resistor r f suppress the noise at the ramp pin. for proper operation, r f ? c r should not exceed 50s. the recommended value of c f is 3 ? c r . power good monitors when v ds of the pass transistor falls below 1.77v and gate pulls above v z C 1.2v, an internal power good signal is latched and a series of three delay cycles are started as shown in figure 4. when the first delay cycle with a duration of 2t d expires, the pg pin pulls low as a power good signal to turn on the first module. when the second delay cycle (2t d ) expires, the pgio pin pulls low as a power good signal to turn on the second module. the third delay cycle with a duration of 4t d is for pgi check. before the third delay cycle expires, the pgi pin must be pulled low by an external supply monitor (such as the ltc2900 in figure 2) to keep the fet on. otherwise, the fet is turned off and the power bad fault (pbad) is logged in the fault register. the 2t d timer delay is obtained by charging c tmr with a 5a current and discharging c tmr with a 12ma current when tmr reaches 2.56v. for the 4t d timer delay, the charging and discharging currents of c tmr are both 5a. the power good signals at pg and pgio are reset in all fet turn-off conditions except the overvoltage fault. turn-off sequence and auto-retry in any of the following conditions, the fet is turned off by pulling down gate with a 110ma current, and c ss and c tmr are discharged with 12ma currents. 1. the on pin is low or the on bit in the control reg - ister is set to 0. 2. the en pin is high. 3. the voltage at uvl is lower than 2.291v and the volt - age at uvh is lower than 2.56v (undervoltage fault). 4. the voltage at ov is higher than 1.77v (overvoltage fault). 5. the voltage at v in is lower than 9v (v in undervoltage lockout). applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
16 6. the voltage at intv cc is lower than 4.25v (intv cc undervoltage lockout). 7. v sense > 50mv and the condition lasts longer than 530s (overcurrent fault). 8. the pgi pin is high when the pgi check timer expires (power bad fault). for conditions 1, 2, 5, 6, after the condition is cleared, the ltc4261/ltc4261-2 will automatically enter the fet turn-on sequence as previously described. for any of the fault conditions 3, 4, 7, 8, the fet off mode is programmable by the corresponding auto-retry bit in the control register. if the auto-retry bit is set to 0, the fet is latched off upon the fault condition. if the auto-retry bit is set to 1, after the fault condition is cleared, a delay timer is started. after the timer expires, the fet enters the auto-retry mode and gate is pulled up. the auto-retry delay following the undervoltage fault or the power bad fault has a duration of t d . the auto- retry delay following the overcurrent fault has a duration of 4t d for extra cooling time. the auto-retry following the overvoltage fault does not have a delay. the auto-retry control bits and their defaults at power up are listed in table 6. note that the ltc4261 defaults to latch-off while the ltc4261-2 defaults to auto-retry following the over - current fault. figure 4. ltc4261 turn-on sequence applications information rtn_v ee tmr uvh 1x start-up delay ss gate v out sense pg pgio pgi internal pwrgd 2x v z ? 1.2v 1.77v pwrgd1 delay 2x pwrgd2 delay 4x pgi check delay 50mv inrush load 1 latched pwrgd1 ready load 1 + load 2 pwrgd2 ready normal pgi power bad 42612 f04 ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
17 en and on figure 5 shows a logic diagram for en and on as they relate to gate, alert and internal registers a4, a7, b4, c4 and d3. also affecting gate is the status of uv, ov and several other fault conditions. the en and on pins have 0.8v to 2v logic thresholds relative to v ee with a maximum input leakage current of 2a. register bit a4 indicates the present state of en, and b4 is set high whenever en changes state. rising and falling edges at the on pin set and clear fet-on control bit, d3. another path allows a falling edge at en to latch a high state at the on pin (such as when on is permanently pulled high) into d3 after a time delay. both b4 and d3 can be set or cleared directly by i 2 c, and both are cleared low whenever intv cc drops below its uvlo threshold. the condition of the gate pin output is controlled by register bit a7, which is the and of a4, d3 and the ab - sence of uv, ov and other faults. overcurrent protection and overcurrent fault the ltc4261/l tc4261-2 feature two levels of protec - tion from short-circuit and overcurrent conditions. load current is monitored by the sense pin and resistor r s . there are two distinct thresholds for the voltage at sense: 50mv for engaging the active current limit loop and starting a 530s circuit breaker timer and 250mv for a fast gate pull-down to limit peak current in the event of a catastrophic short circuit or an input step. in an overcurrent condition, when the voltage drop across r s exceeds 50mv, the current limit loop is engaged and an internal 530s circuit breaker timer is started. the current limit loop servos the gate to maintain a constant output current of 50mv/r s . when the circuit breaker timer expires, the fet is turned off by pulling gate down with a 110ma current, the capacitors at ss and tmr are discharged and the power good signals are reset. at this time, the overcurrent present bit a2 and the overcurrent fault bit b2 are set, and the circuit breaker timer is reset. after the fet is turned off, the overcurrent present bit a2 is cleared. if the overcurrent auto-retry bit d2 has been set, the fet will turn on again automatically after a cooling time of 4t d . otherwise, the fet will remain off until the overcurrent fault bit b2 is reset. when the over - current fault bit is reset (see resetting faults), the fet is allowed to turn on again after a delay of 4t d . the 4t d cooling time associated with the overcurrent fault will not be interrupted by any other fault condition. see figure 6 for operation of ltc4261/ltc4261-2 under overcurrent condition followed by auto-retry. figure 5. logic block diagram of en and on pins applications information r/w i 2 c clr q s r r/w clr intv cc uvlo intv cc uvlo absence of uv/ov and other faults q s clr q s 1 t d timer delay edge detector state-change detector en on b4 c4 alert* gate on alert 42612 f05 read any register *b4 ??c4 is one of seven conditions that can generate an alert output. see table 5 i 2 c alert response a4 a7 d3 ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
18 figure 6. overcurrent fault and auto-retry in the case of a low impedance short circuit on the load side or an input step during battery replacement, current overshoot is inevitable. a fast sense comparator with a threshold of 250mv detects the overshoot and immedi - ately pulls gate low. once the sense voltage drops to 50mv , the current limit loop takes over and ser vos the current as previously described. if the short-circuit con - dition lasts longer than 530s, the fet is shut down and the overcurrent fault is registered. in the case of an input step, after an internal clamp pulls the ramp pin down to 1.1v, the inrush control circuit takes over and the current limit loop is disengaged before the circuit breaker timer expires. from this point on, the device works as in the initial start-up: v out is ramped down at the rate set by i ramp and c r followed by gate pull-up. the power good signals on the pg and pgio pins, the tmr pin, and the ss pin are not interrupted through the input step sequence. the waveform in figure 7 shows how the ltc4261/l tc4261-2 responds to an input step. note that the current limit threshold should be set suffciently high to accommodate the sum of the load current and the inrush current to avoid engagement of the current limit loop in the event of an input step. the maximum value of the inrush current is given by: i inrush 0.8 ? 45mv r s C i load where the 0.8 factor is used as a worst case margin com - bined with the minumum threshold (45mv). the active current limit cir cuit is compensated using the capacitor c g with a series resistor r g (10w) connected between gate and v ee , as shown in figure 1. the sug- gested value for c g is 50nf. this value should work for most pass transistors (q1). overvoltage fault an overvoltage fault occurs when the ov pin rises above its 1.77v threshold. this shuts off the pass transistor immediately, sets the overvoltage present bit a0 and the overvoltage fault bit b0, and pulls the ss pin down. note that the power good signals are not affected by the overvoltage fault. if the ov pin subsequently falls back below the threshold, the pass transistor will be allowed to turn on again immediately (without delay) unless the applications information tmr ss gate v out sense pg pgio oc cooling delay pwrgd1 delay 4x 2x v z ? 1.2v 1.77v inrush pwrgd2 delay 2x 50mv 530s 42612 f06 ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
19 overvoltage auto-retry has been disabled by clearing reg - ister bit d0. under voltage comparator and under voltage fault the ltc4261/ltc4261-2 provide two undervoltage pins, uvh and uvl, for adjustable uv threshold and hyster - esis. the uvh and uvl pins have the following accurate thresholds: for uvh rising, v uvh(th) = 2.56v, turn on for uvl falling, v uvl(th) = 2.291v, turn off both uvh and uvl pins have a minimum hysteresis of dv uv (15mv typical). in either a rising or a falling input supply, the undervoltage comparator works in such a way that both the uvh and the uvl pins have to cross their thresholds for the comparator output to change state. the uvh, uvl, and ov threshold ratio is designed to match the standard telecom operating range of 43v to 71v and uv hysteresis of 4.5v when uvh and uvl are tied together as in figure 1, where the built-in uv hyster - esis referred to the uvl pin is: dv uv(hyst) = v uvh(th) C v uvl(th) = 0.269v using r1 = 11.8k, r2 = 16.9k and r3 = 453k as in figure 1 gives a typical operating range of 43.0v to 70.7v, with an undervoltage shutdown threshold of 38.5v and an overvoltage shutdown threshold of 72.3v. the uv hysteresis can be adjusted by separating the uvh and the uvl pins with a resistor r h (figure 8). to increase the uv hysteresis, the uvl tap should be placed above the uvh tap as in figure 8a. to reduce the uv hys - teresis, place the uvl tap under the uvh tap as in figure 8b. uv hysteresis referred to the uvl pin is given by: for v uvl v uvh , d v uvl(hyst) = d v uv(hyst) + 2.56v ? r h r1 + r2 or for v uvl < v uvh , d v uvl(hyst) = d v uv(hyst) C 2.56v ? r h r1 + r2 + r h for v uvl < v uvh , the minimum uv hysteresis allowed is the minimum hysteresis at uvh and uvl: dv uv = 15mv when r h(max) = 0.11 ? (r1 + r2) the design of the ltc4261/ltc4261-2 protects the uv comparator from chattering even when r h is larger than r h(max) . an undervoltage fault occurs when the uvl pin falls below 2.291v and the uvh pin falls below 2.56v C dv uv . this activates the fet turn-off and sets the undervoltage figure 7. C36v to C72v step response applications information rtn ? v ee tmr ss gate v out sense pg pgio 36v 0v 2.56v v gateh load load 0v 0v 42612 f07 50mv load + inrush fet v th 72v ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
20 figure 8. adjustment of undervoltage thresholds for larger (8a) or smaller (8b) hysteresis present bit a1 and the undervoltage fault bit b1. the power good signals at pg and pgio are also reset. the undervoltage present bit a1 is cleared when the uvh pin rises above 2.56v and the uvl pin rises above 2.291v + dv uv . after a delay of t d , the fet will turn on again unless the undervoltage auto-retry has been dis - abled by clearing bit d1. when power is applied to the device, if uvl is below the 2.291v threshold and uvh is below 2.56v C d v uv after intv cc crosses its undervoltage lock out threshold (4.25v), an undervoltage fault will be logged in the fault register. because of the compromises of selecting from a table of discrete resistor values (1% resistors in 2% increments, 0.1% resistors in 1% increments), best possible ov and uv accuracy is achieved using separate dividers for each pin. this increases the total number of resistors from three or four to as many as six, but maximizes accuracy, greatly simplifes calculations and facilitates running changes to accommodate multiple standards or custom - ization without any board changes. t o improve noise immunity , put the resistive divider to the uv and ov pins close to the chip and keep traces to rtn and v ee short. a 0.1f capacitor from the uvh or uvl pin (and ov pin through resistor r2) to v ee helps reject supply noise. fet short fault a fet short fault will be reported if the data converter mea - sures a current sense voltage greater than or equal to 2mv while the fet is turned off. this condition sets the fet short present bit a5 and the fet short fault bit b5. power bad fault after the fet is turned on and the power good outputs pull pg and pgio low , a delay timer with duration of 4t d is started and the level of the pgi pin is checked (figure 3). if the pgi pin is pulled below its 1.4v threshold before the pgi check timer expires, the fet will remain on. otherwise, the fet is immediately turned off, the power good signals are reset and the power bad present bit a3 and the power bad fault bit b3 are set. after the fet is turned off, the power bad present bit a3 will be cleared. if the pgi pin is subsequently pulled low, the fet will remain off unless the power bad auto-retry has been en - abled by setting bit d4 or the power bad fault bit b3 is cleared. in either of those two conditions, the fet will turn on again following a delay of t d and the pgi pin is checked again as described above. external fault monitors the fltin pin (ssop only) and the pgio pin, when con - fgured as general purpose input, allow monitoring of ex - ternal fault conditions such as broken fuses. if fltin is pulled below its 1.4v threshold, bit b7 in the f aul t reg - ister is set. an associated alert bit, c7, is also available in the aler t register . when the pgio pin is confgured as general purpose input, if the voltage at pgio is above 1.25v, both bit a6 in the status register and bit b6 in the fault register are set, though there is no alert bit as - sociated with this fault. the external fault conditions do not directly affect the ga te control functions. fault alerts when any of the fault bits in f ault register b is set, an optional bus alert can be generated by setting the appropri - ate bit in the alert register c. this allows only selected faults to generate alerts. at power -up the default state is not to alert on faults. if an alert is enabled, the corresponding applications information r3 453k 1% uvl turn-on = 46v turn-off = 38.5v hysteresis = 7.5v ?48v rtn (8a) v ee v ee r h 1.91k 1% uvh r2 15k 1% r1 11.8k 1% 0v r3 453k 1% uvh turn-on = 43v turn-off = 41.2v hysteresis = 1.8v ?48v rtn (8b) r h 1.91k 1% uvl r2 15k 1% r1 11.8k 1% 0v 42612 f08 ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
21 fault will cause the alert pin to pull low. after the bus master controller broadcasts the alert response address, the ltc4261/ltc4261-2 will respond with its address on the sda line and release alert as shown in figure 14. if there is a collision between two ltc4261s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. the alert line will also be released if the device is addressed by the bus master. once the alert signal has been released for one fault, it will not be pulled low again until the fault register indicates a different fault has occurred, or the original fault is cleared and it occurs again. note that this means repeated or continuing faults will not generate alerts until the associated fault register bit has been cleared. resetting faults faults are reset with any of the following conditions. first, writing zeros to the fault register b will clear the associated fault bits. second, the entire fault register is cleared when either the on pin or bit d3 goes from high to low, or if intv cc falls below its 4.25v undervolt - age lockout. pulling the uvl pin below its 1.21v reset threshold also clears the entire fault register. when the uvl pin is brought back above 1.21v but below 2.291v, the undervoltage fault bit b1 is set if the uvh pin is below 2.56v. this can be avoided by holding the uvh pin above 2.56v while toggling the uvl pin to reset faults. finally, when en is brought from high to low, all fault bits except bit b4 are cleared. the bit b4 that indicates an en change of state will be set. fault bits with associated conditions that are still pres - ent (as indicated in the status register a) cannot be cleared. the f aul t register will not be cleared when auto-retrying. when auto-retry is disabled, the existence of b0 (overvoltage), b1 (undervoltage), b2 (overcurrent) or b3 (power bad) fault keeps the fet off. after the fault bit is cleared and a delay of t d (for b0, b1 and b3) or 4t d (for b4) expires, the fet will turn on again. note that if the overvoltage fault bit b0 is cleared by writing a zero through i 2 c, the fet is allowed to turn on without a de- lay. if auto-retry is enabled, then a high value in a0, a1, a2 or a3 will hold the fet off and the f aul t register is ignored. subsequently, when the a0, a1, a2 and a3 bits are cleared, the fet is allowed to turn on again. turning the ltc4261/ltc4261-2 on and off many methods of on/off control are possible using the on, en , uv/ov, fltin or pgio pins along with the i 2 c port. the en pin works well with logic inputs or foat - ing switch contacts; i 2 c control is intended for systems where the board operates only under command of a cen - tral control processor and the on pin is useful with sig - nals referenced to rtn, as are the uv (uvh, uvl) and ov pins. pgio and fl tin control nothing directly, but are useful for i 2 c monitoring of connection sense or other important signals. on/off control is possible with or without i 2 c interven - tion. further, the ltc4261/ltc4261-2 may reside on either the removable board or on the backplane. even when operating autonomously , the i 2 c port can still ex - ercise control over the gate output, although depending on how they are connected, en and on could subse - quently override conditions set by i 2 c. uv, ov and other fault conditions seize control as needed to turn off the gate output, regardless of the state of en, on or the i 2 c port. figure 9 shows fve confgurations of on/off control of the ltc4261/ltc4261-2. determining factors in selecting a pin confguration for autonomous operation are the polarity and voltage of the controlling signal. optical isolation. figure 9a shows an opto-isolator driv - ing the on pin. rising and falling edges at the on pin turn the ga te output on and off. if on is already high when power is applied, ga te is delayed one t d period. the status of on can be examined or overridden through the i 2 c port at register bit d3. this circuit works in both backplane and board resident applications. logic control. figure 9b shows an application using log - ic signal control. again, the on pin is used as an input; all remarks made concerning opto-isolator control apply here as well. applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
22 ejector switch or loop-through connection sense. floating switch contacts or a connection sense loop also work well with the on pin, replacing the phototransistor in figure 9a. if an insertion debounce delay is desired, use the en pin as shown in figure 9c. like figures 9a and 9b, this circuit works on either side of the backplane connector. short pin to rtn . figure 9d uses the uv divider string to detect board insertion. this method works equally well in both backplane and board resident applications. advancedtca style control . figure 2 shows an atca application using en as the interface to the ltc4261. register bit a4 allows the i 2 c port to monitor the status of en and by setting c4 high, bit b4 can generate an alert to instantly report any changes in the state of en. i 2 c only control . to lock out en and on, use the con - fguration shown in figure 9e and control the gate pin with register bit d3. the cir cuit defaults off at power up. t o default on, connect the on pin to intv cc . either fltin or pgio can be used as an input to monitor a connection sense or other control signal. pgio is confgured as an input by setting register bits d6 and d7 high; its input state is stored at location b6. fltin is always an input whose state is available from register bit b7. fltin gen - erates an alert if c7 is set high. data converter the ltc4261/ltc4261-2 incorporates a 10-bit d ana - log-to-digital converter (adc) that continuously moni- tors three different voltages at (in the sequence of) sense, adin2/ov (ssop/qfn) and adin. the d ar - chitecture inherently averages signal noise during the measurement period. the voltage between the sense pin and v ee is monitored with a 64mv full scale and 62.5v resolution, and the data is stored in registers e and f. the adin and the adin2/ov pins are monitored with a 2.56v full scale and 2.5mv resolution. the data for the adin2/ov pin is stored in registers g and h. the data for the adin pin is stored in registers i and j. the results in registers e, f, g, h, i and j are updated at a frequency of 7.3hz. setting control register bit d5 invokes a test mode that halts updating of these registers so that they can be written to and read from for software testing. by invoking the test mode right before reading the adc data registers, the 10-bit data separated in two registers are synchronized. the adin and adin2 pins can be used to monitor input and output voltages of the hot swap controller as shown in figures 1 and 2. figure 9. on/off control of the ltc4261 applications information intv cc ltc4261 (9a) opto-isolator control 5v on 47k 1k en ?48v v ee intv cc ltc4261 (9c) contact debounce delay upon insertion for use with an ejector switch or loop-through style connection sense en 100k loop or switch 10nf 1m on ?48v v ee intv cc ltc4261 (9b) logic control on en ?48v v ee intv cc i 2 c 42612 f09 ltc4261 (9e) i 2 c-only control on en sdao sdai scl default on default off ?48v v ee intv cc ltc4261 (9d) short pin connection sense to rtn on en uvl uvh 28.7k ?48v input ?48v rtn v ee 453k ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
23 configuring the pgio pin table 6 describes the possible states of the pgio pin us - ing the control register bits d6 and d7. at power-up the default state is for the pgio pin to pull low when the second power good signal is ready . other uses for the pgio pin are to go high impedence when the sec - ond power good is ready , a general purpose output and a general purpose input. when the pgio pin is confgured as a general purpose output, the status of bit c6 is sent out to the pin. when it is confgured as a general pur - pose input, if the input voltage at pgio is higher than 1.25v , both bit a6 in the st atus register and bit b6 in the fault register are set. if the input voltage at pgio subsequently drops below 1.25v, bit a6 is cleared. bit b6 can be cleared by resetting the fault register as de - scribed previously. design example as a design example, consider the 200w application with c l = 330f as shown in figure 1. the operating voltage range is from 43v to 71v with a uv turn-off threshold of 38.5v. the design fow starts with calculating the maximum in - put current: i max = 200w 36v = 5.6a where 36v is the minimum input voltage. the selection of the sense resistor, r s , is determined by the minimum current limit threshold and maximum input current: r s = d v sense(min) i max = 45mv 5.6a = 8m w the inrush current is set to 0.66a using c r : c r = c l ? i ramp i inrush = 330f ? 20a 0.66a = 10nf the value of r f and c f are chosen to 1k and 33nf as discussed previously. the fet is selected to handle the maximum power dissi - pation during start-up or an input step. the latter usually results in a larger power due to summation of the inrush current charging c l and the load current. for a 36v input step, the total p 2 t in the fet is approximated by: p 2 t = 36v ? i max ( ) 2 ? t 3 where t is the time it takes to charge up c l : t = c l ? 36v i inrush = 330f ? 36v 0.66a = 18m s which gives a p 2 t value of 244w 2 s. now the p 2 t given by the soa (safe operating area) curves of candidate fets must be higher than 244w 2 s. the soa curves of the irf1310ns provide for 5a at 50v (250w) for 10ms, which gives a p 2 t value of 625w 2 s and satisfes the requirement. sizing r1, r2 and r3 for the required uv and ov thresh - old voltages: v uv(rising) = 43v, v uv(falling) = 38.5v, (using v uvh(th) = 2.56v and v uvh(th) = 2.291v) v ov(rising) = 72.3v, v ov(falling) = 70.7v (using v ov(th) = 1.77v rising and 1.7325v falling) layout considerations to achieve accurate current sensing, a kelvin connection is recommended (figure 10). the minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. using 0.03" per amp or wider is recommended. note that 1oz copper ex - hibits a sheet resistance of about 530w/square. small resistances add up quickly in high current applications. the v ee pin of the ltc4261 should be connected to a separate plane that is different from the main C48v in - put plane. to improve noise immunity, as shown in figure? 10, the v ee connections of all capacitors, resistive dividers, opto-isolators and i 2 c common must be made directly to the local v ee plane, not the C48v input plane. applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
24 i 2 c interface the ltc4261/ltc4261-2 feature an i 2 c interface to pro - vide access to the adc data registers and four other regis - ters for monitoring and control of the pass fet. figure 11 shows a general data transfer format using the i 2 c. the ltc4261/ltc4261-2 are read-write slave devices and support smbus bus read byte, write byte, read word and write word commands. the second word in a read word command will be identical to the frst word. the second word in a write word command is ignored. the data for - mats for these commands are shown in figures 12 to 15. using opto-isolators with sda the ltc4261/l tc4261-2 split the sda line into sdai (in - put) and sdao (output) for convenience of opto-coupling with the host. if opto-isolators are not used then tie sdai and sdao together to form a normal sda line. when us - ing opto-isolators, connect the sdai pin to the output of the incoming opto-isolator and connect the sdao pin to the input of the outgoing opto-isolator (see figure 2). if the sdai and sdao on the master controller are not tied together, the ack bit of sdao must be returned back to sdai. if the alert line is used as an interrupt for the host to respond to a fault in real time, connect the alert pin to an opto-isolator in a way similar to that for the sdao pin as shown in figure 2. figure 11. data transfer over i 2 c or smbus figure 12. ltc4261 serial bus sda write byte protocol figure 13. ltc4261 serial bus sda write word protocol figure 14. ltc4261 serial bus sda read byte protocol figure 15. ltc4261 serial bus sda read word protocol applications information scl sda start condition stop condition address r/ w ack data ack data ack 1 - 7 8 9 42612 f11 a6 - a0 b7 - b0 b7 - b0 1 - 7 8 9 1 - 7 8 9 p s s address 0 0 1 a3:a0 42612 f12 from master to slave from slave to master a: acknowledge (low) a : not acknowledge (high) r: read bit (high) w: write bit (low) s: start condition p: stop condition command d ata x x x x b3:b0 0 w 0 0 0b7:b0 a a a p s address 0 0 1 a3:a0 command d ata d ata x x x x b3:b0 0 w 0 0 0 0 42612 f13 x x x x x x x x b7:b0 a a a a p s address 0 0 1 a3:a0 0 0 1 a3:a0 1 0 command s address r a b7:b0 1 d ata x x x x b3:b0 0 w 0 0 42612 f14 a a a p s address 0 0 1 a3:a0 0 0 1 a3:a0 1 0 command s address r a b7:b0 1 d ata x x x x b3:b0 0 w 0 0 42612 f15 a 0 a b7:b0 d ata a a p mosfet to sense pin ?48v input plane v ee plane ltc4261 v ee pin all capacitors all resistive dividers all opto-isolators i 2 c common d g s r s vias 42612 f10 figure 10. layout example of v ee plane, C48v input plane and sense resistor connection ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
25 start and stop conditions when the bus is idle, both scl and sda must be high. a bus master signals the beginning of a transmission with a start condition by transiting sda from high to low while scl is high. when the master has fnished com - municating with the slave, it issues a stop condition by transiting sda from low to high while scl is high. the bus is then free for another transmission. stuck-bus reset the ltc4261/ltc4261-2 i 2 c interface features a stuck- bus reset timer. the low conditions of the scl and the sdai pins are ored to start the timer. the timer is reset when both scl and sdai are pulled high. if the scl pin or the sdai pin is held low for over 66ms, the stuck-bus timer will expire and the internal i 2 c state machine will be reset to allow normal communication after the stuck- low condition is cleared. when the scl pin and the sdai pin are held low alternatively, if the ored low period of scl and sdai exceeds 66ms before the timer reset con - dition (both scl and sdai are high) occurs, the stuck- bus timer will expire and the i 2 c state machine is reset. i 2 c device addressing any of eight distinct i 2 c bus addresses are selectable us - ing the three-state pins adr0 and adr1, as shown in t able 1. note that the confguration of adr0 = l and adr1 = h is used to enable the single-wire broadcasting mode. for the eight i 2 c bus addresses, address bits b6, b5 and b4 are confgured to (001) and the least signifcant bit b0 is the r/w bit. in addition, the ltc4261/ltc4261-2 will respond to two special addresses. address (0011 111) is a mass write used to write to all ltc4261/ltc4261-2s, regardless of their individual address settings. address (0001 100) is the smbus alert response address. if the ltc4261/ltc4261-2 are pulling low on the alert pin, it will acknowledge this address using the smbus alert response protocol. acknowledge the acknowledge signal is used for handshaking be - tween the transmitter and the receiver to indicate that the last byte of data was received. the transmitter always re - leases the sda line during the acknowledge clock pulse. when the slave is the receiver, it must pull down the sda line so that it remains low during this pulse to acknowl - edge receipt of the data. if the slave fails to acknowl - edge by leaving sda high, then the master can abort the transmission by generating a stop condition. when the master is receiving data from the slave, the master must pull down the sda line during the clock pulse to indicate receipt of the data. after the last byte has been received the master will leave the sda line high (not acknowledge) and issue a stop condition to terminate the transmission. write protocol the master begins communication with a st ar t con - dition followed by the seven bit slave address and the r/w bit set to zero. the addressed l tc4261/l tc4261-2 acknowledge this and then the master sends a command byte which indicates which internal register the master wishes to write. the ltc4261/ltc4261-2 acknowledge this and then latch the lower four bits of the command byte into its internal register address pointer. the master then delivers the data byte and the ltc4261/ltc4261-2 acknowledge once more and latch the data into its inter - nal register. the transmission is ended when the master sends a stop condition. if the master continues sending a second data byte, as in a write word command, the second data byte will be acknowledged by the l tc4261/ ltc4261-2 but ignored. read protocol the master begins a read operation with a start con - dition followed by the seven bit slave address and the r/w bit set to zero. the addressed l tc4261/l tc4261-2 acknowledge this and then the master sends a command byte that indicates which internal register the master wishes to read. the ltc4261/ltc4261-2 acknowledge this and then latch the lower four bits of the command byte into its internal register address pointer. the mas - ter then sends a repeated start condition followed by the same seven bit address with the r/ w bit now set to one. the ltc4261/ltc4261-2 acknowledge and send the contents of the requested register. the transmission is ended when the master sends a stop condition. if the applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
26 master acknowledges the transmitted data byte, as in a read word command, the ltc4261/ltc4261-2 will re - peat the requested register as the second data byte. note that the register address pointer is not cleared at the end of the transaction. thus the receive byte protocol can be used to repeatedly read a specifc register . alert response protocol the l tc4261/ltc4261-2 implement the smbus alert response protocol as shown in figure 16. if enabled to do so through the alert register c, the ltc4261/ ltc4261-2 will respond to faults by pulling the alert pin low. multiple ltc4261/ltc4261-2s can share a com - mon aler t line and the protocol allows a master to de - termine which l tc4261/ltc4261-2s are pulling the line low . the master begins by sending a st art bit followed by the special alert response address (0001 100)b with the r/w bit set to one. any ltc4261/ltc4261-2 that is pulling its alert pin low will acknowledge and begin sending back its individual slave address. figure 16. ltc4261 serial bus sda alert response protocol applications information this means repeated or continuing faults will not gener - ate alerts until the associated fault register bit has been cleared. single-wire broadcast mode the l tc4261/ltc4261-2 provides a single-wire broadcast mode in which selected register data are sent out to the sdao pin without clocking the scl line (figure 17). the single-wire broadcast mode is enabled by setting the adr1 pin high and the adr0 pin low (the i 2 c interface is disabled). at the end of each conversion of the three adc channels, a stream of eighteen bits are broadcasted to sdao with a serial data rate of 15.3khz 20% in a format as illustrated in figure 18. the data bits are encoded with an internal clock in a way similar to manchester encoding that can be easily decoded by a microcontroller or fpga. each data bit consists of a noninverting phase and an inverting phase. during the conversion of each adc chan - nel, sdao is idle at high. at the end of the conversion, the sdao pulls low. the st art bit indicates the beginning of data broadcasting and is used along with the dummy bit (dmy) to measure the internal clock cycle (i.e., the serial data rate). following the dmy bit are two channel code bits ch1 and ch0 labeling the adc channel (see table 10). ten data bits of the adc channel (adc9-0) and three fault register bits (b2, b1 and b0) are then sent out. a parity bit (prty) ends each data stream. after that the sdao line enters the idle mode with sdao pulled high. the following data reception procedure is recommended: 0. wait for int v cc rising edge. 1. wait for sdao falling edge. 2. the first falling edge could be a glitch, so check again after a delay of 10s. if back to high, wait again. if still low, it is the st art bit. 3. use the following low-to-high and high-to-low transis - tions to measure 1/2 of the internal clock cycle. s alert response address 0 0 0 1 1 0 0 device address 0 0 1 a3:a0 0 1 1 r 0 42612 f16 a a p an arbitration scheme ensures that the ltc4261/ ltc4261-2 with the lowest address will have priority; all others will abort their response. the successful re - sponder will then release its alert pin while any others will continue to hold their aler t pins low. polling may also be used to search for any ltc4261/ltc4261-2 that have detected faults. any ltc4261/ltc4261-2 pulling its alert pin low will also release it if it is individually ad - dressed during a read or write transaction. the aler t signal will not be pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
27 figure 17. single-wire broadcast mode figure 18. single-wire broadcast data format 4. wait for the second low-to-high transistion (middle of dmy bit). 5. w ait 3/4 of a clock cycle. 6. sample bit ch1, wait for transistion. 7. wait 3/4 of a clock cycle. 8. sample bit ch0, wait for transistion. 9. wait 3/4 of a clock cycle. 10. sample adc9, wait for transistion. 11. continue until all bits are read. applications information the above procedure can be ported to a microcontroller or used to design a state machine in fpga. code should have timeouts in case an edge is missed. abort the read if it takes more than double the typical time (1.2ms) for all 18 bits to be clocked out. a typical application circuit with the ltc4261/ltc4261-2 in the broadcast mode is illustrated in figure 19, where input voltage, v ds of the fet and v sense are monitored. register addresses and contents the register addresses and contents are summerized in table 1 and table 2. the function of each register bit is detailed in tables 3 to 9. sdai scl sdao adr1 adr0 ltc4261 v in intv cc v ee 6 0.51k in series 1/4w each ?48v rtn ?48v input 0.1f 1f 7.5k 42612 f17 v dd 5v d in v cc gnd anode cathode r l hcpl-0300 v out micro- controller internal clk data sdao start start dmy ch1 ch0 oc ov prty 4261 f18 uv adc9 .. .. .. adc0 ch1 ch1 ch0 ch0 0c 0c uv uv ov ov adc9 adc0 adc9 adc0 prty prty ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
28 table 1. ltc4261 device addressing description hex device address binary device address ltc4261 address pins h 6 5 4 3 2 1 0 r/ w adr1 adr0 mass write 3e 0 0 1 1 1 1 1 0 x x alert response 19 0 0 0 1 1 0 0 1 x x 0 20 0 0 1 0 0 0 0 x l l 1 22 0 0 1 0 0 0 1 x l nc 2 24 0 0 1 0 0 1 0 x h nc 3 26 0 0 1 0 0 1 1 x l h 4 28 0 0 1 0 1 0 0 x nc l 5 2a 0 0 1 0 1 0 1 x nc nc 6 2c 0 0 1 0 1 1 0 x h h 7 2e 0 0 1 0 1 1 1 x nc h 8 single-wire broadcast mode h l h = tie to inv cc ; l = tie to v ee ; nc = no connect, open; x = dont care table 2. ltc4261 register address and contents register address* register name read/write descrip tion 00h st atus (a) r system status information 01h fault (b) r/w fault log and pgio input 02h alert (c) r/w controls whether the alert pin is pulled low after a fault is logged in the fault register 03h control (d) r/w controls whether the part retries after faults, set the on/off switch state 04h sense (e) r/w** adc current sense voltage data (8 msbs) 05h sense (f) r/w** adc current sense voltage data (2 lsbs) 06h adin2/ov (g) r/w** adc adin2/ov (ssop/qfn) voltage data (8 msbs) 07h adin2/ov (h) r/w** adc adin2/ov (ssop/qfn) voltage data (2 lsbs) 08h adin (i) r/w** adc adin voltage data (8 msbs) 09h adin (j) r/w** adc adin voltage data (2 lsbs) *register address msbs b7-b4 are ignored. **writable if bit d5 set. applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
29 table 3. status register a (00h)read only bit name operation a7 fet on indicates state of fet; 1 = fet on, 0 = fet off a6 pgio input indicates state of the pgio pin when configured to general purpose input: 1 = pgio high, 0 = pgio low a5 fet short indicates potential fet short if current sense voltage exceeds 2mv while fet is off; 1 = fet is shorted, 0 = fet is not shorted a4 en indicates state of the en pin; 1 = en pin high, 0 = en pin low a3 power bad indicates power is bad when pgi is high at the end of the pgi check timer; 1 = pgi high, 0 = pgi low a2 overcurrent indicates overcurrent condition; 1 = overcurrent, 0 = not overcurrent a1 undervoltage indicates input undervoltage when both uvh and uvl are low; 1 = uvh and uvl low, 0 = uvh or uvl high a0 overvoltage indicates input overvoltage when ov is high; 1 = ov high, 0 = ov low table 4. fault register b (01h)read/write bit name operation b7 external fault occurred latched to 1 if fltin goes low; 1 = fltin low state detected, 0 = fltin has not been low b6 pgio input high occurred latched to 1 if the pgio pin goes high when configured to general purpose input; 1 = pgio high detected, 0 = pgio has been low b5 fet short fault occurred indicates potential fet short was detected when measured current sense v oltage exceeded 2mv while fet was off; 1 = fet short fault occurred, 0 = no fet short fault b4 en changed state indicates that a board was inserted or extracted when en changed state; 1 = en changed state, 0 = en unchanged b3 power bad fault occurred indicates power was bad when pgi was high at the end of the pgi check timer; 1 = power bad fault occurred, 0 = no power bad fault b2 over current fault occurred indicates over current fault occurred; 1 = overcurrent fault occurred, 0 = no overcurrent fault b1 undervoltage fault occurred indicates input undervoltage fault occurred when both uvh and uvl went low; 1 = undervoltage fault occurred, 0 = no undervoltage fault b0 over voltage fault occurred indicates input over voltage fault occurred when ov was high; 1 = overvoltage fault occurred, 0 = no overvoltage fault table 5. alert register c (02h)read/write bit name operation c7 external fault alert enables alert for external fault when fltin was low; 1 = enable alert, 0 = disable alert (default) c6 pgio output output data bit to pgio pin when configured as output. defaults to 0 c5 fet short alert enables alert for fet short fault; 1 = enable alert, 0 = disable alert (default) c4 en state change alert enables alert when en changed state; 1 = enable alert, 0 disable alert (default) c3 power bad alert enables alert for power bad fault; 1 = enable alert, 0 disable alert (default) c2 overcurrent alert enables alert for overcurrent fault; 1 = enable alert, 0 disable alert (default) c1 undervoltage alert enables alert for undervoltage fault; 1 = enable alert, 0 disable alert (default) c0 overvoltage alert enables alert for overvoltage fault; 1 = enable alert, 0 disable alert (default) applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
30 table 6. control register d (03h)read/write bit name operation d7:6 pgio configure configures behavior of pgio pin function d6 d7 pgio pin power good (default) 0 0 open drain power good 0 1 open drain general purpose output 1 0 pgio = c6 general purpose input 1 1 pgio = hi-z d5 test mode enable test mode halts adc operation and enables writes to adc registers; 1 = enable test mode, 0 = disable test mode (default) d4 power bad auto-retry enables auto-retr y after a power bad fault; 1 = retr y enabled, 0 = retry disabled (default) d3 fet on control turns fet on and off; 1 = turn fet on, 0 = turn fet off. defaults to on pin state at end of start-up debounce delay d2 overcurrent auto-retry enables auto-retr y after an over current fault; 1 = retry enabled (default, ltc4261-2), 0 = retry disabled (default, ltc4261) d1 undervoltage auto-retr y enables auto-retry after an undervoltage fault; 1 = retry enabled (default), 0 = retry disabled d0 overvoltage auto-retry enables auto-retr y after an over voltage fault; 1 = retry enabled (default), 0 = retry disabled table 7. sense registers e (04h) and f (o5h)read/write bit name operation e7:0, f7:6 sense voltage data 10-bit data of current sense voltage with 62.5v lsb and 64mv full scale f5:0 reserved always returns 0, not writable table 8. adin2/ov registers g (06h) and h (o7h)read/write bit name operation g7:0, h7:6 adin2/ov voltage data 10-bit data of adin2/ov (ssop/qfn) voltage with 2.5mv lsb and 2.56v full scale h5:0 reserved always returns 0, not writable table 9. adin registers i (08h) and j (o9h)read/write bit name operation i7:0, j7:6 adin voltage data 10-bit data of adin voltage with 2.5mv lsb and 2.56v full scale j5:0 reserved always returns 0, not writable table 10. adc channel labeling for single-wire broadcast mode ch1 ch0 adc channel 0 0 sense voltage 0 1 adin2/ov (ssop/qfn) voltage 1 0 adin voltage applications information ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
31 typical application package description using the ltc4261 and a thermistor to monitor temperature v in ltc4261cgn sdao sdai scl adin 100k at 25c 1% vishay ntcs0402e3104*ht 30.1k 1% 10k 1% t (c) = 38.05 (v adin (v) ? 0.1458), 20c < t < 60c 1f 42612 ta02 ?48v rtn ?48v input i 2 c 6 0.51k in series 1/4w each v ee please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. .386 ? .393* (9.804 ? 9.982) gn28 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 202122232425262728 19 18 17 13 14 16 15 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b) ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
32 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 23 24 1 2 bottom view?exposed pad 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd24) qfn 0506 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 2.00 ref 3.00 ref 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 2.00 ref 3.00 ref 3.65 0.10 3.65 0.05 ufd package 24-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1696 rev a) ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
33 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 9/11 change to electrical characteristics gate turn-off current update to typical performance characteristics graph g06 update to pin functions sdai (pin 5/pin 2) description update to block diagram text changes to operations section added figure 3 update to figure 4 text changes to applications information update to typical applications figure 17 3 6 9 11 12 14 16 14, 17, 18, 22, 24 34 d 6/14 separated v ee connection of ltc4261 and related components from C48v input plane in circuit figures added patent numbers changed delay conditions to gate open from c gate = 1pf layout considerations section: added paragraph and figure 10 on separating local v ee plane from -48v input plane 1, 13, 20, 22, 27, 31, 34 1 3 23, 24 (revision history begins at rev c) ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261
34 ? linear technology corporation 2005 lt 0614 rev d ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4261 part number description comments lt1640ah/lt1640al negative high voltage hot swap controllers in so-8 negative high voltage supplies from C10v to C80v ltc1921 dual C48v supply and fuse monitor uv/ov monitor, C10v to C80v operation, msop package lt4250l/lt4250h C48v hot swap controllers in so-8 active current limiting, supplies from C18v to C80v ltc4251/ltc4251-1 C48v hot swap controllers in sot-23 fast active current limiting, supplies from C15v ltc4252-1/ltc4252-2 ltc4252a-1/ltc4252a-2 C48v hot swap controllers in ms8 fast active current limiting, supplies from C15v , 1% uv /ov (ltc4252a) ltc4253 C48v hot swap controller with sequencer fast current limiting with three sequenced power good outputs, supplies from C15v l tc4260 positive high voltage hot swap controller with i 2 c and adc, supplies from 8.5v to 80v ltc4354 negative voltage diode-or controller and monitor controls two n-channel mosfets, 1.2s turn-off, 80v operation figure 19. application circuit of the ltc4261 in single-wire broadcast mode typical applications related parts sdai scl sdao adin uvl uvh adin2 ov adr1 adr0 gate drain ramp ltc4261cgn v in intv cc on v ee tmr ss en sense r in 6 0.51k in series 1/4w each r3 432k 1% ?48v rtn ?48v input r2 15.8k 1% r1 11.5k 1% c vcc 0.1f c tmr 47nf c ss 220nf c g 47nf c f 33nf c r 10nf 100v 5% r g 10 r d 1m c in 1f r s 0.02 1% v out q1 irf1310ns r6 10k 1% r7 402k 1% c l 330f 100v 4261 f19 v dd 5v d in micro- controller gnd v cc anode r4 7.5k cathode r l hcpl-0300 v out r f 1k ltc4261/ltc4261-2 42612fd for more information www.linear.com/ltc4261

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