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pm applications ? ? distributed power architectures ? ? intermediate bus voltage applications ? ? servers and storage applications ? ? network equipment typical unit features ? ? small package: 12.2 x 12.2 x 8.0 mm (0.48 x 0.48 x 0.315 in) ? ? 0.6 v - 5 v output voltage range ? ? high ef? ciency, typ. 95.4% at 12vin, 5vout and 50% load ? ? con? guration control and monitoring via pmbus? ? ? adaptive compensation of pwm control loop & fast loop transient response ? ? synchonization input & phase spreading/interleaving ? ? voltage tracking & voltage margining ? ? mtbf 24 mh ? ? for narrow board pitch applications (15 mm/0.6 in) ? ? pre-bias start-up & shut down ? ? monotonic & soft start power up ? ? input under voltage shutdown; otp, output ovp, ocp ? ? remote control & power good ? ? differential sense pins ? ? voltage setting via pin-strap or pmbus? ? ? advanced con? gurable via graphical user interface ? ? iso 9001/14001 certi? ed supplier ? ? highly automated manufacturing ensures quality product overview the OKDL-T/12-w12 is a high ef? ciency, digital point-of-load (pol) dc-dc power converter capable of delivering 12a/60w. designed for a minimal footprint, the high power-density lga module measures just 12.2 x 12.2 x 8.0 mm (0.48 x 0.48 x 0.315 in). pmbus? compatibility allows monitor- ing and con? guration of critical system- level performance requirements. apart from standard pol performance and safety features like ovp, ocp, otp, and uvlo, these digital converters have advanced features: adaptive compen- sation of pwm control loop, fast loop transient response, synchronization, and phase spreading. these converters are ideal for use in telecommunica- tions, networking, and distributed power applications. part number structure OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 1 of 31 www.murata-ps.com www.murata-ps.com/support trimmable output voltage range 0.6 - 5vdc - t lga package l digital non-isolated pol okd c - rohs hazardous substance compliance c = rohs-6 (does not claim eu rohs exemption 7b C lead in solder) maximum rated output current in amps / 12 input voltage range 4.5-14vdc w12 - xxx - software con? guration digits (001 is positive turn-on logic) (002 is negative turn-on logic)* *special quantity order is required; contact murata power solutions for moq and lead times.
characteristics min typ max unit t p1 operating temperature (see thermal consideration section) -40 120 c t s storage temperature -40 125 c v i input voltage (see operating information section for input and output voltage relations) -0.3 18 v logic i/o voltage ctrl, sa0, sa1, salert, scl, sda, vset, sync, pg, cs_vtrk -0.3 4 v ground voltage differential -s, pref, gnd -0.3 0.3 v analog pin voltage vo, +s -0.3 5.5 v absolute maximum ratings stress in excess of absolute maximum ratings may cause permanent damage. absolute maximum ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits in the electrical speci? cation. if exposed to stress above these limits, function and performance may degrade in an unspeci? ed manner. con? guration file this product is designed with a digital control circuit. the control circuit uses a con? guration ? le which determines the functionality and performance of the product. the electrical speci? cation table shows parameter values of functionality and performance with the default con? guration ? le, unless otherwise speci? ed. the default con? guration ? le is designed to ? t most application needs with focus on high ef? ciency. if different characteristics are required it is pos- sible to change the con? guration ? le to optimize certain performance characteristics. in this technical speci? cation examples are included to show the possibilities with digital control. see operating information section for information about trade offs when optimizing certain key performance characteristics. fundamental circuit diagram vout vin controller and digital interface ctrl sda scl salert cs_vtrk pref gnd c i c o +sense -sense pgood sa0 sync vset sa1 general and safety conditions min typ max unit safety designed for ul/iec/en 60950 1 calculated mtbf telcordia sr-332, issue 2 method 1 24 mhrs OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 2 of 31 www.murata-ps.com/support ordering guide model number output OKDL-T/12-w12-001-c 0.6-5.0 v, 12 a/ 60 w
electrical speci? cations t p1 = -30 to +95c, v i = 4.5 to 14 v, v i > v o + 1.0 v typical values given at: t p1 = +25c, v i = 12.0 v, max i o , unless otherwise speci? ed under conditions. default con? guration ? le, 190 10-cda 102 0370/001. v o de? ned by pin strap. external c in = 47 f ceramic + 270 f/10 m electrolytic, c out = 3x100 f + 0.1 f ceramic. see operating information section for selection of capacitor types. sense pins are connected to the output pins. characteristics conditions min typ max unit v i input voltage 4.5 14 v v o output voltage without pin strap 0v output voltage adjustment range 0.60 5.0 v output voltage adjustment including pmbus margining 0.50 5.25 v output voltage set-point resolution 1.2 mv output voltage accuracy including line, load, temp -1 1 % v o internal resistance +s/-s to vout/gnd 47 +s bias current 50 a -s bias current -35 a line regulation i o = max i o v o = 0.6 v 1 mv v o = 1.2 v 2 v o = 1.8 v 3 v o = 3.3 v 4 v o = 5.0 v 7 load regulation i o = 0 - 100% v o = 0.6 v 1 mv v o = 1.2 v 1 v o = 1.8 v 1 v o = 3.3 v 2 v o = 5.0 v 2 v oac output ripple & noise (up to 20 mhz) v o = 0.6 v 10 mvp-p v o = 1.2 v 10 v o = 1.8 v 11 v o = 3.3 v 19 v o = 5.0 v 25 i o output current 012a i s static input current at max i o v o = 0.6 v 0.7 a v o = 1.2 v 1.3 v o = 1.8 v 2.0 v o = 3.3 v 3.5 v o = 5.0 v 5.2 i lim current limit threshold 15 17 a i sc short circuit current rms, hiccup mode, v o = 3.3 v, 4 m short 3a ? ef? ciency 50% of max i o v o = 0.6 v 78.8 % v o = 1.2 v 87.5 v o = 1.8 v 90.8 v o = 3.3 v 94.1 v o = 5.0 v 95.4 i o = max i o v o = 0.6 v 81.3 % v o = 1.2 v 89.0 v o = 1.8 v 91.8 v o = 3.3 v 94.6 v o = 5.0 v 95.8 p d power dissipation at max i o v o = 0.6 v 1.66 w v o = 1.2 v 1.78 v o = 1.8 v 1.93 v o = 3.3 v 2.24 v o = 5.0 v 2.63 p li input idling power i o = 0 v o = 0.6 v 0.70 w v o = 1.2 v 0.70 v o = 1.8 v 0.71 v o = 3.3 v 0.80 v o = 5.0 v 0.92 p ctrl input standby power turned off with ctrl-pin 0.25 w OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 3 of 31 www.murata-ps.com/support
characteristics conditions min typ max unit c i internal input capacitance v i = 0 v 47 f c o internal output capacitance v o = 0 v 47 f v o = 3.3 v 24 v o = 5.0 v 15 c out total output capacitance effective capacitance note 1 55 f v tr1 load transient peak voltage deviation load step 25-75-25% of max?i o , di/dt = 1.5 a/s c o =3x100 f + 270 f v o = 3.3 v 60 mv t tr1 load transient recovery time 25 s f sw switching frequency 600 khz switching frequency range pmbus con? gurable frequency_switch note 2 300-1000 khz switching frequency set-point accuracy -10 5 10 % external sync duty cycle 40 60 % input clock frequency drift tolerance external clock source -10 10 % input under voltage lockout (hardware controlled) threshold, v uvlo rising edge 3.8 4.1 4.4 v hysteresis 0.24 v input over voltage lockout (hardware controlled) threshold, v ovlo input rising 14.3 15.2 16 v input turn-on voltage threshold 4.35 v threshold range pmbus con? gurable vin_on 0-14.7 v input turn-off voltage threshold 3.8 v threshold range pmbus con? gurable vin_off 0-14.7 v input under/over voltage protection, iuvp/ iovp iuvp threshold 4.1 v iuvp threshold range pmbus con? gurable vin_uv_fault_limit 0-14.7 v iovp threshold 14.4 v iovp threshold range pmbus con? gurable vin_ov_fault_limit 0-14.7 v set point accuracy -150 150 mv fault response vin_uv_fault_response vin_ov_fault_response shutdown, make continuous restarts at 700 ms interval (hiccup). note 3 output voltage over/under voltage protection, ovp/uvp uvp threshold 85 % v o uvp threshold range pmbus con? gurable vout_uv_fault_limit 0-100 % v o ovp threshold 115 % v o ovp threshold range pmbus con? gurable vout_ov_fault_limit 100-115 % v o fault response vout_uv_fault_response vout_ov_fault_response shutdown, make continuous restarts at 700 ms interval (hiccup). note 3 over current protection, ocp ocp threshold set value 16 a ocp threshold range pmbus con? gurable iout_oc_fault_limit 0-18 a fault response iout_oc_fault_response shutdown, make continuous restarts at 700 ms interval (hiccup). note 3. over temperature protection, otp otp threshold note 4 120 c otp threshold range pmbus con? gurable ot_fault_limit -40+120 c otp hysteresis pmbus con? gurable 15 c fault response ot_fault_response shutdown, make continuous restarts at 700 ms interval (hiccup). note 3 over temperature shutdown (hardware controlled) threshold note 4 150 c hysteresis 20 c accuracy 20 c OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 4 of 31 www.murata-ps.com/support
characteristics conditions min typ max unit v ol logic output low signal level scl, sda, sync, salert, pg sink/source current = 4 ma 0.4 v v oh logic output high signal level 2.8 v i ol logic output low sink current 4ma i oh logic output high source current 4ma v il logic input low threshold scl, sda, ctrl, sync 0.8 v v ih logic input high threshold 2 v i il_ctrl logic input low sink current ctrl 0.5 ma i i_leak logic leakage current scl, sda, sync, salert, pg 10 ua f smb smbus operating frequency 400 khz t buf smbus bus free time stop bit to start bit see section smbus C timing 1.3 s t set smbus sda setup time from scl 100 ns t hold smbus sda hold time from scl 300 ns smbus start/stop condition setup/hold time from scl 600 ns t low scl low period 1.3 s t high scl high period 0.6 s initialization time from v i > v uvlo to ready to be enabled 23 ms soft-start on delay time note 5 delay duration 10 ms delay duration range pmbus con? gurable ton_delay 1-145 ms delay set resolution 0.6 ms delay set accuracy ton_delay value sent versus read- back 0.5 x delay set resolution ms delay accuracy actual delay duration versus ton_de- lay read-back 0.8 ms soft-start rise time (0-100% of v o ) note 5 ramp duration 10 ms ramp duration range pmbus con? gurable ton_rise 1 - (255 x ramp set resolution) ms ramp set resolution varies with v o 0.4 1 ms ramp set accuracy ton_rise value sent versus read-back 0.5 x ramp set resolution ms ramp time accuracy actual ramp duration versus ton_rise read-back 10 s compensation calibration signal duration 5ms signal level v o = 0.6 v 3.5 % v o v o = 1.2 C 3.3 v 2.5 v o = 5.0 v 2 power good , pg pg threshold rising 90 % v o falling 85 % v o tracking mode see section voltage tracking 450 mv pg thresholds range (non-tracking only) pmbus con? gurable power_good_on power_good_off 0 100 % v o pg delay enabled compensation calibration (default) from v o reaching target to pg assertion 11 ms tracking mode see section voltage tracking 20 ms pg delay disabled compensation calibration from v o reaching pg rising threshold to pg assertion 0ms tracking mode see section voltage tracking 20 ms tracking input voltage range cs_vtrk pin note 6 0 1.2 v tracking accuracy -100 100 mv OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 5 of 31 www.murata-ps.com/support
note 1. value refers to total (internal + external) effective output capacitance. capacitance derating with vo typical for ceramic capacitors (bias characteristics) and temperature variations must be considered for the external capacitor(s). see section external output capacitors. note 2. a switching frequency close to 475 khz should not be used since this frequency represents a boundary of two operational modes of the product. there are con? guration changes to consider when changing the switching frequency, see section switching frequency. note 3.the restart interval is con? gurable between 100ms and 700ms in 100ms steps. severe overcurrent faults occurring with vo > 2.5v may result in a restart interval of 1200 ms instead of the con? gured value. see operating conditions for other fault response alternatives. note 4. temperature measured internally at temperature position p3. see section over temperature protection. note 5. same speci? cation applies for soft-stop and toff_delay/toff_fall if enabled. the internal ramp and delay generators can only achieve certain discrete timing values. a written ton/off_delay or ton/off_rise value will be rounded to the closest achievable value, thus a command read-back provides the actual set value. see section soft-start and soft-stop. note 6.larger tracking input range is provided by external resistor divider, see section voltage tracking. note 7. at vo > 3.5v and vo / vi in the approximate range 55-70% there may be an additional current monitoring inaccuracy on the negative side up to -1 a. characteristics conditions min typ max unit monitoring accuracy input voltage read_vin 3 % vi output voltage read_vout 1 % v o output current read_iout note 7 tp 1 = 0-95 c, v i = 4.5-14 v, i o > 5 a 8.5 % i o tp 1 = 0-95 c, v i = 4.5-14 v, i o < 5 a 0.4 a temperature read_ temperature_1 note 4 -5 5 c duty cycle read_duty_cycle duty cycle < 10% -3 3 % duty cycle > 10% -1 0.5 1 % OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 6 of 31 www.murata-ps.com/support
power dissipation typical characteristics , v o = 0.6 v default configuration, t p1 = +25c efficiency efficiency vs. load current and input voltage. dissipated power vs. load current and input voltage. output current derating current limit characteristics output voltage vs. load current and input voltage. available load current vs. ambient air temperature and airflow at v i = 12 v. see section thermal consideration. output ripple and noise transient response fundamental output voltage ripple at v i = 12 v, c o = 3x100 f, i o = 12 a. scale: 5 mv/div, 1 s/div, 20 mhz bandwidth. see section output ripple and noise. 50 55 60 65 70 75 80 85 90 02 8 6 41012 [a] [%] v i 4.5 v 5 v 12 v 14 v 0.0 0.5 1.0 1.5 2.0 2.5 0468 21012 output voltage response to load current step change (3?9?3 a) at v i = 12 v, c o = 3x100 f + 270 f/10m ? . default compensation settings. scale: 50 mv/div, 5 a/div, 50 s/div. [w] [a] v i 4.5 v 5 v 12 v 14 v 0 2 4 6 8 10 12 85 90 95 100 105 [a] [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0.00 0.15 0.30 0.45 0.60 0.75 12 13 14 15 16 [v] 17 [a] v i 4.5 v 5 v 12 v 14 v OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 7 of 31 www.murata-ps.com/support
power dissipation typical characteristics , v o = 1.2 v default configuration, t p1 = +25c efficiency efficiency vs. load current and input voltage. dissipated power vs. load current and input voltage. output current derating current limit characteristics output voltage vs. load current and input voltage. available load current vs. ambient air temperature and airflow at v i = 12 v. see section thermal consideration. output ripple and noise transient response fundamental output voltage ripple at v i = 12 v, c o = 3x100 f, i o = 12 a. scale: 5 mv/div, 1 s/div, 20 mhz bandwidth. see section output ripple and noise. 55 60 65 70 75 80 85 90 95 02 8 6 41012 [%] [a] v i 4.5 v 5 v 12 v 14 v 0.0 0.5 1.0 1.5 2.0 4 2 0 2.5 68 output voltage response to load current step change (3?9?3 a) at v i = 12 v, c o = 3x100 f + 270 f/10m ? . default compensation settings. scale: 50 mv/div, 5 a/div, 50 s/div. 10 12 [w] [a] v i 4.5 v 5 v 12 v 14 v 0 2 4 6 8 10 12 85 90 95 100 [a] 105 [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0.00 0.30 0.60 0.90 1.20 1.50 12 13 14 15 16 17 [v] [a] v i 4.5 v 5 v 12 v 14 v OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 8 of 31 www.murata-ps.com/support
power dissipation typical characteristics , v o = 1.8 v default configuration, t p1 = +25c efficiency efficiency vs. load current and input voltage. output current derating dissipated power vs. load current and input voltage. current limit characteristics output voltage vs. load current and input voltage. available load current vs. ambient air temperature and airflow at v i = 12 v. see section thermal consideration. output ripple and noise transient response fundamental output voltage ripple at v i = 12 v, c o = 3x100 f, i o = 12 a. scale: 5 mv/div, 1 s/div, 20 mhz bandwidth. see section output ripple and noise. 60 65 70 75 80 85 90 95 02 100 4681012 [%] [a] v i 4.5 v 5 v 12 v 14 v 0.0 0.5 1.0 1.5 2.0 output voltage response to load current step change (3?9?3 a) at v i = 12 v, c o = 3x100 f + 270 f/10m ? . default compensation settings. scale: 50 mv/div, 5 a/div, 50 s/div. 2.5 08 6 4 21012 [w] [a] v i 4.5 v 5 v 12 v 14 v 0 2 4 6 8 10 12 85 95 90 100 [a] 105 [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0.0 0.4 0.8 1.2 1.6 2.0 12 13 14 15 16 17 [v] [a] v i 4.5 v 5 v 12 v 14 v OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 9 of 31 www.murata-ps.com/support
power dissipation typical characteristics , v o = 3.3 v default configuration, t p1 = +25c efficiency efficiency vs. load current and input voltage. dissipated power vs. load current and input voltage. output current derating current limit characteristics output voltage vs. load current and input voltage. available load current vs. ambient air temperature and airflow at v i = 12 v. see section thermal consideration. output ripple and noise transient response fundamental output voltage ripple at v i = 12 v, c o = 3x100 f, i o = 12 a. scale: 5 mv/div, 1 s/div, 20 mhz bandwidth. see section output ripple and noise. 70 75 80 85 90 95 100 2 06 4 8 10 12 [%] [a] v i 4.5 v 5 v 12 v 14 v 0.0 0.5 1.0 1.5 2.0 2.5 08 246 10 output voltage response to load current step change (3?9?3 a) at v i = 12 v, c o = 3x100 f + 270 f/10m ? . default compensation settings. scale: 50 mv/div, 5 a/div, 50 s/div. 12 [w] [a] v i 4.5 v 5 v 12 v 14 v 0 2 4 6 8 10 12 85 90 95 100 [a] 105 [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0.0 0.6 1.2 1.8 2.4 3.0 12 3.6 13 14 15 16 17 [v] [a] v i 4.5 v 5 v 12 v 14 v OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 10 of 31 www.murata-ps.com/support
power dissipation typical characteristics , v o = 5.0 v default configuration, t p1 = +25c efficiency efficiency vs. load current and input voltage. dissipated power vs. load current and input voltage. output current derating current limit characteristics output voltage vs. load current and input voltage. available load current vs. ambient air temperature and airflow at v i = 12 v. see section thermal consideration. output ripple and noise transient response fundamental output voltage ripple at v i = 12 v, c o = 3x100 f, i o = 12 a. scale: 5 mv/div, 1 s/div, 20 mhz bandwidth. see section output ripple and noise. 70 75 80 85 90 95 100 2 06 4810 [%] 12 [a] v i 6 v 9.6 v 12 v 14 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 024681012 output voltage response to load current step change (3?9?3 a) at v i = 12 v, c o = 3x100 f + 270 f/10m ? . default compensation settings. scale: 50 mv/div, 5 a/div, 50 s/div. [a] [w] v i 6 v 9.6 v 12 v 14 v 0 2 4 6 8 10 12 80 85 90 95 [a] 100 [c] 3.0 m/s 2.0 m/s 1.0 m/s 0.5 m/s nat. conv. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 12 13 14 15 16 17 [v] [a] v i 6 v 9.6 v 12 v 14 v OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 11 of 31 www.murata-ps.com/support
typical characteristics default configuration, t p1 = +25c, v o = 3.3 v start-up by input source shut-down by input source start-up enabled by applying v i . ton_delay = ton_rise = 10 ms (default). v i = 12 v, i o = max i o, pg pulled up to v o . scale: 10 or 2 v/div, 10 ms/div. start-up by ctrl signal shutdown by ctrl signal shut-down by removing v i . v i = 12 v, i o = max i o, pg pulled up to v o . scale: 10 or 2 v/div, 1 ms/div. start-up enabled by ctrl signal. ton_delay = ton_rise = 10 ms (default). v i = 12 v, i o = max i o, pg pulled up to v o . scale: 2 v/div, 10 ms/div. v i v o pg ctrl shut-down by ctrl signal. v i = 12 v, i o = max i o, pg pulled up to v o . scale: 2 v/div, 1 ms/div. v o pg v i v o pg ctrl v o pg OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 12 of 31 www.murata-ps.com/support
emc speci? cation conducted emi is measured according to the test set-up below. the fundamental switching frequency is 600 khz. layout recommendations the radiated emi performance of the product will depend on the pwb layout and ground layer design. it is also important to consider the stand- off of the product. if a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. a ground layer will increase the stray capacitance in the pwb and improve the high frequency emc performance. output ripple and noise output ripple and noise is measured according to ? gure below. a 50 mm conductor works as a small inductor forming together with the two capacitances a damped ? lter. the digital compensation of the product is designed to automatically provide stability, accurate line and load regulation and good transient performance for a wide range of operating conditions (switching frequency, input voltage, output voltage, output capacitance). inherent from the implementation and normal to the product there will be some low-frequency noise or wander at the output, in addition to the fundamen- tal switching frequency output ripple. the total output ripple and noise is maintained at a low level. conducted emi input terminal value (typical for default con? guration) emi without ? lter test set-up conducted emission, power lead c1 rf current probe 1khz ? 50mhz analyzer to spectrum dut load resistive battery supply 800mm c1 = 10uf / 600vdc feed- thru rf capacitor 200mm 50mm output ripple and noise test set-up vout s s gnd ceramic capacitor 0.1 f tantalum capacitor 10 f load 50 mm conductor 50 mm conductor bnc-contact to oscilloscope c o example of low frequency noise at the output v i =12 v, v o =3.3 v, i o =12 a, c o =3x100 f,10 mv/div, 50 s/div OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 13 of 31 www.murata-ps.com/support
operating information power management overview this product is equipped with a pmbus? interface. the product incorporates a wide range of readable and con? gurable power man- agement features that are simple to implement with a minimum of external components. additionally, the product includes protection features that continuously safeguard the load from damage due to unexpected system faults. a fault is also shown as an alert on the salert pin. the product is delivered with a default con? guration suitable for a wide range of operation in terms of input voltage, output voltage, and load. the con? guration is stored in an internal non-volatile memory (nvm). all power management functions can be recon? gured using the pmbus? interface. please contact your local murata power solutions representative for design support of custom con? gura- tions or appropriate sw tools for design and download of your own con? gurations. input under voltage lockout, uvlo the product provides a non-con? gurable under voltage lockout (uvlo) circuit that monitors the internal supply of the converter. below a cer- tain input voltage level the internal supply will be too low for proper operation and the product will be in under voltage lockout, not switch- ing or responding to the ctrl pin or to pmbus? commands. input over voltage lockout, ovlo the product provides a non-con? gurable over voltage lockout (ovlo) circuit that will shut down the product when the input voltage rises above a certain level. the product will not switch, respond to the ctrl pin or to pmbus? commands when being in over voltage lockout. input turn-on and turn-off voltage the product monitors the input voltage and will turn-on and turn-off the output at con? gured levels (assuming the product is enabled by ctrl pin or pmbus?). the default turn-on input voltage level is 4.35 v whereas the corresponding turn-off input voltage level is 3.8 v. the turn-on and turn-off levels may be recon? gured using the pmbus? commands vin_on and vin_off. input under voltage protection (iuvp) the product monitors the input voltage continously and will respond as con? gured when the input voltage falls below the con? gured threshold level. the product can respond in a number of ways as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by an output voltage shutdown if the fault still exists. 3. immediate and de? nite shutdown of output voltage until the fault is cleared by pmbus? or the output voltage is re-enabled. 4. immediate shutdown of output voltage while the fault is present. operation resumes and the output is enabled when the fault condi- tion no longer exists. the default response is 4. the iuvp function can be recon? g- ured using the pmbus? commands vin_uv_fault_limit and vin_uv_fault_response. input over voltage protection (iovp) the product monitors the input voltage continously and will respond as con? gured when the input voltage rises above the con? gured threshold level. refer to section input under voltage protection for response con? guration options and default setting. input and output impedance the impedance of both the input source and the load will interact with the impedance of the product. it is important that the input source has low characteristic impedance. if the input voltage source contains signi? cant inductance, the addition of a capacitor with low esr at the input of the product will ensure stable operation. external input capacitors the input ripple rms current in a buck converter can be estimated to eq. 1. where is the output load current and is the duty cycle. the maxi mum load ripple current becomes . the ripple current is divided into three parts, i.e., currents in the input source, external input capacitor, and internal input capacitor. how the current is divided depends on the impedance of the input source, esr and capacitance values in the capacitors. for most applications non-tantalum capacitors are preferred due to the robustness of such capacitors to accommodate high inrush currents of systems being powered from very low impedance sources. it is recommended to use a combination of ceramic capacitors and low-esr electrolytic/polymer bulk capacitors. the low esr of ceramic capacitors effectively limits the input ripple voltage level, while the bulk capacitance minimizes deviations in the input voltage at large load transients. it is recommended to use at least 47 uf of ceramic input capaci- tance. at duty cycles between 25% and 75% where the input ripple current increases (see eq. 1), additional ceramic capacitance will help to keep the input ripple voltage low. the required bulk capacitance depends on the impedance of the input source and the load tran- sient levels at the output. in general a low-esr bulk capacitor of at least 100 uf is recommended. the larger the duty cycle is, the larger impact an output load step will have on the input side, thus the larger bulk capacitance is required to limit the input voltage deviation. if several products are connected in a phase spreading setup the amount of input capacitance per product can be reduced. input capacitors must be placed closely and with low impedance connections to the vin and gnd pins in order to be effective. external output capacitors the output capacitor requirement depends on two considerations; output ripple voltage and load transient response. to achieve low load inputrms 1 , load i d 2 load i d d ii OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 14 of 31 www.murata-ps.com/support
capacitance is required. the limit of cout_low must be followed in order to guarantee stability. note that eq. 2 and eq. 3 and the chart above refer to the total capacitance at the output, thus including both the capacitance internal to the product and the external capacitance applied in the application. the internal output capacitance is listed in the electrical characteris- tics table. note also that eq. 2 and eq. 3 and the chart refers to the effective capacitance, not taking into account the capacitance derating that applies for ceramic capacitors with increased voltage or temperature variations. in cases where the external output ? lter includes an inductor (form- ing a pi ? lter) according to the picture below, the following must be considered. in order for the compensation calibration (see next sections) to give a reliable result, the following condition should be ful? lled: where flc_ext is the resonance frequency of the external ? lter and fsw is the switching frequency. if there are multiple pi ? lters in paral- lel on the output, giving a more complex transfer function with several resonance peaks, each of the peaks should be above fsw/10. if this condition is not ful? lled it is recommended to disable com- pensation calibration and set flc manually in comp_model (see next sections). please contact your murata power solutions sales representative for further support. for the okdl products, it is recommended that the remote sense connections are made at a point before the external inductor, as illus- trated in the drawing above. dynamic loop compensation (dlc) the typical design of regulated power converters includes a con- trol function with a feedback loop that can be closed using either analog or digital circuits. the feedback loop is required to provide a stable output voltage, but should be optimized for the output ? lter to maintain output voltage regulation during transient conditions such as sudden changes in output current and/or input voltage. digitally controlled converters allow one to optimize loop parameters without the need to change components on the board, however, optimization ripple voltage, the output capacitor bank must have a low esr value, which is achieved with ceramic output capacitors. a small output voltage deviation during load transients is achieved by using a larger amount of capacitance. designs with smaller load transients can use fewer capacitors and designs with more dynamic load content will require more load capacitors to achieve a small output deviation. improved transient response can also be achieved by adjusting the settings of the control loop of the product (see section compensation implementation). it is recommended to locate low esr ceramic and low esr electro- lytic/polymer capacitors as close to the load as possible, using several capacitors in parallel to lower the effective esr. it is important to use low resistance and low inductance pcb layouts and cabling in order for capacitance to be effective. the control loop of the product is optimized to operate with low- esr output capacitors and is capable of achieving a fast loop transient response with a reduced amount of capacitance. the effective output capacitance is recommended to be in the range [cout_low, cout_ high] according to equations eq. 2 and eq. 3 below, where fsw is the switching frequency. the compensation implementation of the product is optimized for this range. eq. 2. eq. 3. the product permits a large range of output capacitance, thus capacitance above cout_high is acceptable. this capability is impor- tant in applications where the output capacitance may be unknown or not well controlled or in applications where a large amount of output 2 7 _ 2.6 0 1 sw low out f c ? 2 7 _ 6 10 1 sw high out f c ? effective total output capacitance limits vs switching frequency. 10 100 1000 10000 300 400 500 600 700 800 900 1000 [ f] [khz] permissible recommended unstable external output ? lter with inductor (pi ? lter). vout s s gnd okdl load c o l ext c ext 10 2 1 _ sw t x et x e ext lc f f ! s l c OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 15 of 31 www.murata-ps.com/support
user. note however, as soon as the output voltage is disabled, the flc value in comp_model will revert back to the corresponding value stored in user nvm. therefore, user values of comp_model should be written to nvm, or, if written to ram only, be written before each time the output voltage is enabled. comp_model should only be changed in ram while the output voltage is disabled. by setting bit 2 in adaptive_mode a store_user_all command will automatically be performed after the next calibration, effectively storing the measured flc value in comp_model 15:0 in nvm as the flc value for subsequent ramp-ups. the table below shows an example of improvement in transient response due to the compensation calibration, compared to using the flc_default value. non-calibrated compensation calibrated compensation voltage deviation 53 mv 34 mv recovery time 50 s 30 s the pmbus? command adaptive_mode provides the user differ- ent options for compensation calibration: 1. calibration is performed once after each ramp-up (default). (adap- tive_mode = 0x024b). 2. calibration is performed once after ? rst ramp-up after input volt- age is applied (adaptive_mode = 0x124b). 3. calibration is performed continuously after ramp-up at ~800 ms interval (adaptive_mode = 0x034b). 4. calibration is disabled (adaptive_mode = 0x004b). the flc value stored in bits 15:0 in comp_model will be applied. 5. calibration is performed continuously in response to a pmbus? command. controlled by setting/clearing bit 8 in adaptive_mode during operation. compensation may be set more or less aggressive by adjusting the feedback gain factor, controlled by the pmbus? command feed- back_effort. this parameter is proportional to the open loop gain of the system. increasing the gain, i.e the control effort, will reduce the voltage deviation at load transients, at the expense of somewhat increased jitter and noise on the output. users also have access to can still be challenging because the key parameters of the output ? lter include parasitic impedances in the pcb and the often distrib- uted ? lter components themselves. dynamic loop compensation has been developed to solve the problem of compensation for a converter with a dif? cult to de? ne output ? lter. this task is achieved by utilization of algorithms that can characterize an arbitrary output ? lter based on behavior of the output voltage in response to a disturbance initiated by the algorithm, or occurring due to the changes in operating conditions, and automati- cally adjust feedback loop parameters to match the output ? lter. details of the algorithm that is used to characterize an output ? lter and the different operational modes can be found in the following sections. compensation implementation unlike pid-based digital power regulators the product uses a state- space model based algorithm that is valid for both the small- and large-signal response and accounts for duty-cycle saturation effects. this eliminates the need for users to determine and set thresholds for transitioning from linear to nonlinear modes. these capabilities result in fast loop transient response and the possibility of reducing the number of output capacitors. compensation calibration is when the resonance frequency flc of the output stage is measured. the flc value is used to automati- cally control the compensation. during ramp-up of the output voltage, robust and low bandwidth default compensation settings are used based on the default flc value assigned by bits 15:0 in pmbus? command comp_model. if the switching frequency is changed the default flc should be adjusted according to eq. 4 to maintain robust settings. eq. 4. it is possible for the user to write any flc value in comp_model to be used during ramp-up. this is useful in cases where improved dynamic performance is needed during ramp-up. user assignment of flc in comp_model is also needed when calibration is disabled, since in such case the flc value used during ramp-up will continue to be used when ramp-up has ? nished. when calibration is enabled (default), an ac low amplitude meas- urement signal is applied on the output immediately after ramp-up has ? nished. see electrical characteristics table for a speci? cation of this measurement signal. during calibration the resonant frequency flc of the power stage is measured. from the result an internal non- linear model is constructed to optimize the bandwidth and transient response of the product. pole locations of the closed system are automatically selected based on switching frequency, measured flc and the output voltage level. after each performed calibration, bits 15:0 in comp_model are updated with measured flc, thus this value can be read out by the 32 _ sw default lc f f load transient performance non-calibrated compensation with flc_default vs. calibrated compensation. vi=12 v, vo=1.2 v, co = 3x100 f + 270f/10m, load step 3-9-3 a, 1 a/us. time output voltage compensation calibration OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 16 of 31 www.murata-ps.com/support
remote sense the product has remote sense that can be used to compensate for voltage drops between the output and the point of load. the sense traces should be located close to the pwb ground layer to reduce noise susceptibility. due to derating of internal output capacitance the voltage drop should be kept below vdropmax = (5.25 C vout) / 2. a large voltage drop will impact the electrical performance of the regulator. if the remote sense is not needed +s must be connected to vout and ?s must be connected to gnd. output voltage control to control the output voltage the product features both a remote control input through the ctrl pin and a pmbus? enable function by the command operation. it is also possible to con? gure the output to be always on. by default the output is controlled by the ctrl pin only. the output voltage control can be recon? gured using the pmbus? command on_off_config. remote control the product is equipped with a remote control function, i.e., the ctrl pin. the remote control can be connected to either the primary negative input connection (gnd) or an external voltage (vext). see absolute maximum rating for maximum voltage level allowed at the ctrl pin. the ctrl function allows the product to be turned on/off by an external device like a semiconductor or mechanical switch. the ctrl pin has an internal 6.8 k pull-up resistor to 3.3 v. the external device must provide a minimum required sink current to guarantee a voltage not higher than the logic low threshold level (see the pmbus? command zetap, which corresponds to the damping ratio of the closed loop system. by default the product uses 0.5 as the feedback gain factor and 1.5 for damping ratio, to target a system bandwidth of 10% of the switching frequency. in some operating conditions at low output voltages, it is possible to enhance the recovery time at load release by enabling negative duty cycle by pmbus? command loop_config. the graphs below exemplify the impact on load transient perfor- mance when adjusting the feedback gain factor, the damping ratio and the negative duty cycle feature. v i =12 v, v o =1.2 v, load step 3-9-3 a,1 a/us. 20 30 40 50 60 70 0.20.30.40.50.60.70.80.91.0 [mv] feedback_effort co=3x100 f+270 f/10m ? co=3x100 f voltage deviation vs. feedback_effort setting. recovery time to within 1% of vo vs. zetap setting. v i =12 v, v o =1.2 v, c o = 3x100 f + 270 f/10m ? , load step 3-9-3 a,1 a/us. 15.0 18.0 21.0 24.0 27.0 30.0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 [us] zetap load release response at enabled/disabled negative duty cycle at low output voltage. v i =12 v, v o =0.6 v, c o = 3x100 f + 270 f/10m ? , load step 3-9-3 a,1 a/us. feedback_effort = 0.8, zetap = 1.5. scale: 20 mv/div, 5 a/div, 10 s/div. enabled disabled ctrl gnd vext OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 17 of 31 www.murata-ps.com/support
default, but the margin limits can be recon? gured using the pmbus? commands vout_margin_low, vout_margin_high. margining is activated by the command operation. output voltage trim the actual output voltage can be trimmed to optimize performance of a speci? c load by setting a non-zero value for pmbus? command vout_trim. the value of vout_trim is summed with vout_com- mand, allowing for multiple products to be commanded to a common nominal value, but with slight adjustments per load. output voltage range limitation the output voltage is by default limited to the least of 5.5 v or 110% of the nominal output voltage, where the nominal output voltage is de? ned by pin-strap or by vout_command in non-volatile memory (see section initialization procedure). this protects the load from an over voltage due to an accidentally written wrong vout_command. the limitation applies to the regulated output voltage, rather than the internal value of vout_command. the output voltage limit can be recon? gured using the pmbus? command vout_max. output over voltage protection (ovp) the product includes over voltage limiting circuitry for protection of the load. the default ovp limit is 15% above the nominal output volt- age. the product can be con? gured to respond in different ways to the output voltage exceeding the ovp limit: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by an output voltage shutdown if the fault still exists. 3. immediate and de? nite shutdown of output voltage until the fault is cleared by pmbus? or the output voltage is re-enabled. 4. immediate shutdown of output voltage while the fault is present. operation resumes and the output is enabled when the fault condi- tion no longer exists. the default response is 4. the ovp limit and fault response can be recon? gured using the pmbus? commands vout_ov_fault_limit and vout_ov_fault_response. output under voltage protection (uvp) the product includes output under voltage limiting circuitry for protection of the load. the default uvp limit is 15% below the nominal output voltage. refer to section output over voltage protection for response con? guration options and default setting. power good pg (power good) is an active high open drain output used to indicate when the product is ready to provide regulated output voltage to the load. during startup and during a fault condition, pg is held low. by default, pg is asserted high after the output has ramped to a voltage above 90% of the nominal voltage and a successful compen- sation calibration has completed. electrical characteristics). when the ctrl pin is left open, the voltage generated on the ctrl pin is 3.3 v. by default the product provides positive logic rc and will turn on when the ctrl pin is left open and turn off when the ctrl pin is applied to gnd. it is possible to con? gure negative logic instead by using the pmbus? command on_off_config. if the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the ctrl pin. output voltage adjust using pin-strap resistor using an external pin-strap resis- tor, rset, the output voltage can be set in the range 0.6 v to 5.0 v at 16 different levels shown in the table below. the resistor should be applied between the vset pin and the pref pin. rset also sets the maximum output voltage; see section output voltage range limitation. the resistor is sensed only at the applica- tion of input voltage. changing the resistor value during normal opera- tion will not change the output voltage. the input voltage must be at least 1 v larger than the output voltage in order to deliver the correct output voltage. see ordering information for output voltage range. the following table shows recommended resistor values for rset. maximum 1% tolerance resistors are required. output voltage adjust using pmbus? the output voltage set by pin-strap can be overridden using the pmbus? command vout_command. see electrical speci? cation for adjustment range. voltage margining up/down using the pmbus? interface it is possible to adjust the output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its speci? ed supply voltage range. this provides a convenient method for dynami- cally testing the operation of the load circuit over its supply margin or range. it can also be used to verify the function of supply voltage supervisors. margin limits of the nominal output voltage 5% are vset r set pref v out [v] r set [k] v out [v] r set [k] 0.60 5.11 1.05 17.8 0.70 6.19 1.10 21.5 0.75 7.15 1.20 26.1 0.80 8.25 1.50 31.6 0.85 9.53 1.80 38.3 0.90 11.0 2.50 44.2 0.95 12.7 3.30 51.1 1.00 14.7 5.00 59.0 OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 18 of 31 www.murata-ps.com/support
by default, pg is deasserted if the output voltage falls below 85% of the nominal voltage. these limits may be changed using the pmbus? commands power_good_on and power_good_off. the pg output is not de? ned during ramp up of the input voltage due to the initialization of the product. over current protection (ocp) the product includes robust current limiting circuitry for protection at continuous overload. after ramp-up is complete the product can detect an output overload/short condition. the following ocp response options are available: 1. continue operating without interruption (this could result in perma- nent damage to the product). 2. immediate and de? nite shutdown of output voltage until the fault is cleared by pmbus? or the output voltage is re-enabled. 3. immediate shutdown of output voltage followed by continous restart attempts of the output voltage with a preset interval (hiccup mode). the default response from an over current fault is 3. note that delayed shutdown is not supported. the load distribution should be designed for the maximum output short circuit current speci? ed. the ocp limit and response can be recon? gured using the pmbus? com- mands iout_oc_fault_limit and iout_oc_fault_response. if option 2 above is to be used, the ton_max_fault_response setting should match the setting of iout_oc_fault_response in order to make sure that no restart attempts occur. switching frequency the default switching frequency yields optimal performance. the switching frequency can be re-con? gured in a certain range using the pmbus? command frequency_switch. refer to electrical speci? - cation for default switching frequency and range. if changing the switching frequency more than +/-10% from the default value, the following should be considered to maintain reliable operation: ? ? the default flc value in comp_model should be adjusted, see section compensation implementation. ? ? adjustment of the ? xeddtr and ? xeddtf values in deadtime_gctrl may be required, for higher switching frequencies in particular. changing the switching frequency will affect ef? ciency/power dis- sipation, load transient response and output ripple. synchronization the product may be synchronized with an external clock to eliminate beat noise on the input and output voltage lines by connecting the clock source to the sync pin. synchronization can also be utilized for phase spreading, described in section phase spreading. the clock frequency of the external clock source must be stable prior to enabling the output voltage. further, the pmbus? command frequency_switch must be set to a value close to the frequency of the external clock prior to enabling the output voltage, in order to set the internal controller in proper operational mode. the product automatically checks for a clock signal on the sync pin when input power is applied and when the output is enabled. if no incoming clock signal is present, the product will use the internal oscillator at the con? gued switching frequency. in the event of a loss of the external clock signal during normal operation, the product will automatically switch to the internal oscillator and switch at a frequency close to the original sync input frequency. phase spreading when multiple products share a common dc input supply, spreading of the switching clock phase between the products can be utilized. this dramatically reduces input capacitance requirements and ef? - ciency losses, since the peak current drawn from the input supply is effectively spread out over the whole switch period. this requires that the products are synchronized. the phase offset is measured from the rising edge of the applied external clock to the center of the pwm pulse as illustrated below. by default the phase offset is controlled by the de? ned pmbus? address (see section pmbus? interface) according to the table below. this provides a way to con? gure phase spreading with up to eight dif- ferent phase positions without using a pmbus? command. illustration of phase offset. sync clock pwm pulse (v o /v i =0.33) phase offset = 120 set pmbus address phase offset xxxx000b 0 xxxx001b 60 xxxx010b 120 xxxx011b 180 xxxx100b 240 xxxx101b 300 xxxx110b 90 xxxx111b 270 OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 19 of 31 www.murata-ps.com/support
the default phase offset can be overridden by using the standard pmbus? command interleave. the phase offset can then be de? ned as interleave_order is in the range 0-15. number_in_group is in the range 0-15 where a value of 0 means 16. the set resolution for the phase offset is 360 / 128 2.8. giving the pmbus? command interleave a value of 0x0000 will revert back to the default address controlled phase offset. murata power solutions provides software tools for convenient con? guration of optimized phase spreading, allowing the amount of input capacitance to be signi? cantly reduced. initialization procedure the product follows an internal initialization procedure after power is applied to the vin pin (refer to ? gure below): 1. self test and memory check. 2. the address pin-strap resistors are measured and the associated pmbus? address is de? ned. 3. the output voltage pin-strap resistor is measured. the associated output voltage level will be loaded into operational ram memory, unless an overriding pmbus? command vout_command has been explicitly written and stored in the user non-volatile memory (indicated by bit 0 in command strap_disable). 4. values stored in the user non-volatile memory (nvm) are loaded into operational ram memory. for pmbus? commands listed in the table below, loaded values will be based on the output voltage level loaded in step 3 above, unless the commands have been explicitly written and stored in the user nvm. 5. check for external clock signal at the sync pin and wait for lock if used. once this procedure is completed and the initialization time has passed (see electrical speci? cation), the output voltage is ready to be enabled and the pmbus? interface can be used. note the following implications of the initialization procedure: ? ? if the rset pin-strap resistance is changed, input voltage will have to be cycled before the output voltage level is affected. ? ? if vout_command is changed and stored to user nvm, input voltage will have to be cycled before the output voltage related commands in the table below are re-scaled according to the new output voltage level. see section pmbus? interface for more information about the non-volatile memories (nvm) of the product. soft-start and soft-stop the soft-start and soft-stop control functionality allows the output voltage to ramp-up and ramp-down with de? ned timing with respect to the control of the output. this can be used to control inrush current and manage supply sequencing of multiple controllers. the rise time is the time taken for the output to ramp to its target voltage while the fall time is the time taken for the output to ramp down from its regulation voltage to less than 10% of that value. the on delay time sets a delay from when the output is enabled until the output voltage starts to ramp up. the off delay time sets a delay from when the output is disabled until the output voltage starts to ramp down. soft-stop is disabled by default but may be enabled through the pmbus? command on_off_config. the delay and ramp times can be recon? gured using the pmbus? commands ton_delay, ton_rise, toff_delay and toff_fall. the internal delay generator can only achieve certain discrete timing values. a written ton_delay/toff_delay value will be rounded to the closest achievable value, thus a ton_delay/off_ delay read will provide the actual set value. the internal ramp generator can only achieve certain discrete timing values for a given combination of switch frequency, output volt- age level, set ramp time and trim data. these values are close, but not group in number order interleave offset phase __ _ _()0 6 3 u qq loading of nominal output voltage level user nvm vout_command pmbus interface vout_command ram vout_command vm strap_disable[0]=1? no pin-strap vout rset yes write read strap_disable[0]=1 vout related pmbus command loaded value unless explicitly written + stored to user nvm. power_good_on 0.90 x loaded vout level power_good_off 0.85 x loaded vout level vout_max 1.10 x loaded vout level vout_margin_high 1.05 x loaded vout level vout_margin_low 0.95 x loaded vout level vout_ov_fault_limit 1.15 x loaded vout level vout_uv_fault_limit 0.85 x loaded vout level illustration of soft-start and soft-stop output control v out on delay time rise time fall time off delay time OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 20 of 31 www.murata-ps.com/support
exactly the same, when any of the relevant parameters are altered. a written ton_rise/toff_fall value will be rounded to the closest achievable value, thus a ton_rise/toff_fall read will provide the actual set value. refer to electrical speci? cation for default on delay time and rise time and the con? gurability ranges and resolutions. the speci? cation provided for soft-start applies also for soft-stop, if enabled. output voltage sequencing a group of products may be con? gured to power up in a predeter- mined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another. multi-product sequencing can be achieved by con? guring the start delay and rise time of each device through the pmbus? interface and by connecting the ctrl pin of each product to a common enable signal. pre-bias startup capability pre-bias startup often occurs in complex digital systems when current from another power source is fed back through a dual-supply logic component, such as fpgas or asics. the product incorporates syn- chronous recti? ers, but will not sink current during startup, or turn off, or whenever a fault shuts down the product in a pre-bias condition. when the output is enabled the product checks the output for the presence of pre-bias voltage. if the pre-bias voltage is above the output overvoltage threshold the product will not attempt soft-start. if the pre- bias voltage is less than 200 mv the soft-start is performed assuming no pre-bias. if the pre-bias voltage is above 200 mv but below target output voltage, the product ramps up the output voltage from the pre- bias voltage to the target regulation as shown in the ? gure below. voltage tracking the product supports tracking of the output from a master voltage applied to the cs_vtrk pin. to select the tracking mode, a resistance 4.22 k must be connected between the vset and pref pins. the tracking ratio used is controlled by an internal feedback divider rdiv and an external resistive voltage divider (r1, r2) which is placed from the supply being tracked to gnd pins. in tracking mode the output voltage is regulated to the lower of: eq. 5 or the output voltage de? ned by the pmbus? command vout_command. rdiv is automatically selected based on the value of vout_com- mand as shown in the table below. if vout_command is not de? ned by the user, it will default to 5.25 v with rdiv= 0.20272. for best tracking accuracy it is recommended that once the product is powered up, the vout_command should not be changed so as to cause a change to the operational rdiv. if such a change in vout_ command is required, the user should save the new value to user non-volatile memory (using store_user_all command) and recycle the input voltage to set a new rdiv operational value. to simplify resistor selection it is recommended to ? x r1 at 10 k and use the following equation to determine r2: eq. 6 illustration of output voltage sequencing time voltage v out1 v out2 illustration of pre-bias startup time soft-start ramp time voltage v track (master) r2 cs_vtrk vout vset pref okdl gnd r1 r set r set ? 4.22 k ? v out (slave) rdiv max 1.2v tracking mode con? guration 2 1 r 1 r rdiv v v track out u r vout_command [v] rdiv < 0.99 0.99547 0.99 to < 1.12 0.88222 1.12 to < 1.28 0.76897 1.28 to < 1.50 0.65572 1.50 to < 1.82 0.54247 1.82 to < 2.29 0.42922 2.29 to < 3.12 0.31597 3.12 to < 5.25 0.20272 vout_command not user de? ned => 5.25 0.20272 ? ? ? 1 ? u 1 out track v rdiv v r 2( k : ) = r 1 u OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 21 of 31 www.murata-ps.com/support
r2 must be chosen so that the cs_vtrk input does not exceed 1.2 v. as seen in eq. 5, if the resistor-divider ratio from r1//r2 is chosen such that it is equal to the operational rdiv, the output voltage follows the tracking voltage coincidentally. for all other cases, the output volt- age follows a ratiometric tracking. these two modes of tracking are further described below. 1. coincident tracking. output voltage is ramped at the same rate as the vtrack voltage. to achieve coincident tracking the desired output voltage should be set by the pmbus? command vout_command. r2 should be set so that r2 = r1 / rdiv C r1. the output will stop ramping when the vout_command level is reached. since the voltage at the cs_vtrk pin must be below 1.2 v, coincident tracking will not be possible in all cases. a higher r2 value may be required, giving a ratiometric tracking instead. example: external vtrack = 3.3 v target vout = 2.5 v r1 = 10 k vout_command = 2.5 v => rdiv = 0.31597 r2 = 10 / 0.31597C 10 = 21.6 k 2. ratiometric tracking. output voltage is ramped at a rate that is a percentage of the vtrack voltage. to achieve ratiometric tracking, r2 should be set according to eq. 6 with vout being the desired output voltage. the pmbus? command vout_command should be set equal to or higher than the output voltage given by eq. 5, or not being set at all giving the default vout_command value 5.25 v. since the target voltage level is decided by the r1//r2 divider there will be a small regulation inaccuracy due to the tolerance of the resistors. note also that vout will be higher than vtrack if r1 / (r1 + r2) > rdiv. example: external vtrack = 3.3 v target vout = 1.3 v vout_command not set => rdiv = 0.20272 r1 = 10 k eq. 7 => during voltage tracking compensation calibration is triggered when the output voltage is above 450 mv and stable within a 100 mv window for two consecutive measurements at 10 ms intervals. when calibration is complete, the power good (pg) output is asserted. the pg output remains asserted until the output voltage falls below 450 mv, as veri? ed at 10 ms intervals. for this reason, the pg output may remain high for as much as 10 ms after the output voltage has fallen below 450 mv. when voltage tracking is enabled the output over voltage protection limit is set 12% above vout_command as default. this limit may be recon? gured using the pmbus? command vout_ov_fault_limit. output under voltage protection is not functional in tracking mode. soft-start parameters ton_delay and ton_rise are not functional in tracking mode and will be set to their minimum values to prevent interference with tracking. toff_delay and toff_fall can be used if soft-stop is enabled. in such case the output voltage will follow the least of the output levels given by the soft-stop parameters and the tracking equations. thermal consideration general the product is designed to operate in different thermal environments and suf? cient cooling must be provided to ensure reliable operation. cooling is achieved mainly by conduction, from the pins to the host board, and convection, which is dependent on the air? ow across the product. increased air? ow enhances the cooling of the product. the output current derating graph found in the output section for each model provides the available output current vs. ambient air temperature and air velocity at speci? ed vi. the product is tested on a 254 x 254 mm, 35 m (1 oz), test board mounted vertically in a wind tunnel with a cross-section of 608 x 203 mm. the test board has 8 layers. proper cooling of the product can be veri? ed by measuring the temperature at positions p1, p2 and p3. the temperature at these positions should not exceed the max values provided in the table below. note that the max value is the absolute maximum rating (non destruction) and that the electrical output data is guaranteed up to tp1 +95c. coincident voltage tracking time r1 / (r1 + r2) = rdiv voltage v track v out vout_ command ratiometric voltage tracking ti me r1 / (r1 + r2) < rdiv voltage v track v out 2 1 r r rdiv v track u = ? ? ? ? ? ? ? ? ? = k r 115 1 3 . 1 20272 . 0 3 . 3 10 2 OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 22 of 31 www.murata-ps.com/support
de? nition of product operating temperature the product operating temperature is used to monitor the temperature of the product. proper thermal conditions can be veri? ed by measur- ing the temperature at positions p1, p2 and p3. the temperature at these position (tp1,tp2, tp3) should not exceed the maximum temperatures in the table below. the number of measurement points may vary with different thermal design and topology. * a guard band of 5 c is applied to the maximum recorded compo- nent temperatures when calculating output current derating curves. ** see section alternative thermal veri? cation. de? nition of reference temperature tp1 the reference temperature is used to monitor the temperature limits of the product. temperature above maximum tp1, measured at the reference point p1 is not allowed and may cause degradation or permanent damage to the product. tp1 is also used to de? ne the temperature range for normal operating conditions. tp1 is de? ned by the design and used to guarantee safety margins, proper operation and high reliability of the product. alternative thermal veri? cation since it is dif? cult to access positions p1 and p3 of the product, measuring the temperature at only position p2 is an alternative method to verify proper thermal conditions. if measuring only tp2 the maximum temperature of p2 must be lowered since in some operat- ing conditions tp1 will be higher than tp2. using a temperature limit of 115c for tp2 will make sure that the temperatures at all points p1, p2 and p3 stay below their maximum limits. over temperature protection (otp) the internal temperature of the product is continously monitored at position p3. when the internal temperature rises above the con? gured threshold level the product will respond as con? gured. the product can respond in a number of ways as follows: 1. continue operating without interruption (this could result in perma- nent damage to the product). 2. continue operating for a given delay period, followed by an output voltage shutdown if the fault still exists. 3. immediate and de? nite shutdown of output voltage until the fault is cleared by pmbus? or the output voltage is re-enabled. 4. immediate shutdown of output voltage while the fault is present. operation resumes and the output is enabled when the fault condi- tion no longer exists. default response is 4. the otp protection uses hysteresis so that the fault exists until the temperature has fallen to a certain level (ot_ warn_limit) below the fault threshold. the default otp threshold and hysteresis are speci? ed in electrical characteristics. the otp limit, hysteresis and response can be recon? gured using the pmbus? commands ot_fault_limit, ot_warn_limit and ot_fault_response. the product also incorporates a non-con? gurable hard-coded thermal shutdown associated with the temperature monitored at position p3 to ensure long-term ? ash-memory integrity. see electrical characteristics. connections the table below gives a brief description of the functionality of each pin. a more detailed description can be found in the different subsec- tions of the operating information section. position description max temperature p1 t3, fet reference point 125c * p2 l1, inductor 125c * (115c **) p3 n1, control circuit 115c * temperature positions and air ? ow direction. top view. air flow p1 p3 p2 pin layout, bottom view. OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 23 of 31 www.murata-ps.com/support
pin designation function 1a, 1b, 2a, 2b, 2c, 2d vout output voltage 3a, 3b, 4a, 4b, 5a, 5b gnd power ground 5c, 6a, 6b, 6c vin input voltage 1c +s positive sense. connect to output voltage close to the load 1d -s negative sense. connect to power ground close to the load. 1e pg power good output. asserted high when the product is ready to provide regulated output voltage to the load. open drain. see section power good. 1f sa0 pmbus? address pin strap. used with external resistors to assign a unique pmbus? address to the product. see section pmbus? interface. 3e sa1 2f vset output voltage pin strap. used with external resistor to set the nominal output voltage or to select track- ing mode. see section output voltage adjust using pin-strap resistor. 3f pref pin-strap reference. ground reference for pin-strap resistors. 6d ctrl remote control. can be used to enable/disable the output voltage of the product. see section remote control. 2e sync external switching frequency synchronization input. see section synchronization. 5f salert pmbus? alert. asserted low when any of the con- ? gured protection mechanisms indicate a fault. 6e sda pmbus? data. data signal for pmbus? communi- cation. see section pmbus? interface. 6f scl pmbus? clock. clock for pmbus? communication. see section pmbus? interface. 4f cs_vtrk voltage tracking input. allows for tracking of output voltage to an external voltage. see section voltage tracking. in normal operation when tracking is not used, this pin must be connected to pref. 4e rsvd reserved. connect to pref. 5d, 5e nc no connection unused pins unused pins should be connected according to the table below. note that connection of cs_vtrk to pref is required for normal standalone operation. vset should always have a pin strap resistor. typical application circuit pcb layout consideration the radiated emi performance of the product will depend on the pcb layout and ground layer design. if a ground layer is used, it should be connected to the output of the product and the equipment ground or chassis. a ground layer will increase the stray capacitance in the pcb and improve the high frequency emc performance. further layout recommendations are listed below. ? ? the pin strap resistors, rset, and rsa0/rsa1 should be placed as close to the product as possible to minimize loops that may pick up noise. ? ? avoid current carrying planes under the pin strap resistors and the pm- bus? signals. ? ? the capacitors ci should be placed as close to the input pins as possible. ? ? the capacitors co should be placed close to the load. ? ? the point of output voltage sense should be downstream of co according to ? gure below. ? ? care should be taken in the routing of the connections from the sensed output voltage to the s+ and sC terminals. these sensing connections should be routed as a differential pair, preferably between ground planes which are not carrying high currents. the routing should avoid areas of high electric or magnetic ? elds. ? ? if possible use planes on several layers to carry vi, vo and gnd. there should be a large number of vias close to the vin, vout and gnd pads in order to lower input and output impedances and improve heat spreading between the product and the host board. unused pin connection cs_vtrk pref. required for normal operation ctrl open (pin has internal pull-up) rsvd pref or pulled down to pref sync pref or pulled down to pref sa0 pref or open sa1 pref or open sda pull-up resistor to voltage > 2 v scl pull-up resistor to voltage > 2 v pg open salert open typical standalone operation with pmbus communication. vin vout +s -s ctrl pg sa0 sa1 vset pref salert scl cs_vtrk sda sync rsvd gnd v out l o a d v in c o c i r sa0 r sa1 r set 3 x r pu = 2.2 k ? 2.7-3.6 v salert scl sda dgnd OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 24 of 31 www.murata-ps.com/support
pmbus? interface this product provides a pmbus? digital interface that enables the user to con? gure many aspects of the device operation as well as to monitor the input and output voltages, output current and device temperature. the product can be used with any standard two-wire i2c or smbus host device. in addition, the product is compatible with pmbus? version 1.1 and includes an salert line to help mitigate bandwidth limitations related to continuous fault monitoring. the pmbus? signals, scl, sda and salert require passive pull-up resistors as stated in the smbus speci? cation. pull-up resistors are required to guarantee the rise time as follows: where rp is the pull-up resistor value and cp is the bus loading. the maximum allowed bus load is 400 pf. the pull-up resistor should be tied to an external supply voltage in range from 2.7-3.6 v, which should be present prior to or during power-up. if the proper power supply is not available, voltage dividers may be applied. note that in this case, the resistance in the equation above corresponds to parallel connection of the resistors forming the voltage divider. monitoring via pmbus? it is possible to monitor a wide variety of parameters through the pmbus? interface. fault conditions can be monitored using the salert pin, which will be asserted when any number of pre-con? g- ured fault or warning conditions occur. it is also possible to continu- ously monitor one or more of the power conversion parameters including but not limited to the following: ? ? input voltage (read_vin) ? ? output voltage (read_vout) ? ? output current (read_iout) ? ? internal junction temperature (read_temperature_1) ? ? switching frequency (read_frequency) ? ? duty cycle (read_duty_cycle) reading set parameters to clearly display the true performance of the product, pmbus? command reads of set levels, limits and timing parameters will return the internally used values. for this reason, due to rounding or internal representation in the controller of the product, there may be a differ- ence between written and read value of a pmbus? command. this applies to pmbus? commands of type linear or voutlinear. when verifying write transactions, tolerances according to the table below can be used. pmbus? command read back accuracy comp_model 0 vin_on 0.1 v vin_off vin_uv_fault_limit vin_ov_fault_limit iout_oc_fault_limit 0.1 a ton_delay 0.3 ms toff_delay ton_rise 0.4 ms toff_fall vout_command 0.001 v vout_max vout_margin_high vout_margin_low vout_transition_rate 0.5 v vout_ov_fault_limit 0.01 v vout_uv_fault_limit power_good_on power_good_off non-volatile memory (nvm) the product incorporates two non-volatile memory areas for storage of the supported pmbus? commands; the default nvm and the user nvm. the default nvm is pre-loaded with murata power solutions factory default values. the default nvm is write-protected and can be used to restore the murata power solutions factory default values through the command restore_default_all. the restore_default_all command will load a nominal output level of 0 v. therefore, after a restore_default_all command is sent, the input voltage must be cycled in order to load correct output voltage level according to vset pin-strap resistor (see section startup procedure). the user nvm is pre-loaded with murata power solutions factory default values. the user nvm is writable and open for customization. the values in the user nvm are loaded during initialization whereaf- ter commands can be changed through the pmbus? interface. the store_user_all command will store the changed parameters to the user nvm. layout guidelines v o +s scl sda sync load -s c i c o gnd v i r sa0, r set, r sa1 v i r s a 0 , r se s c l s d a s y n c et , r s a 1 gnd c r pp p s w 1 d OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 25 of 31 www.murata-ps.com/support
rsa1 [k] 4.22 5.11 6.19 7.15 8.25 9.53 11.0 12.7 14.7 17.8 21.5 26.1 31.6 38.3 44.2 51.1 59.0 68.1 86.6 115 rsa0 [k] 140 169 205 237 274 4.22 0x0a 0x22 0x3a 0x52 0x6a 5.11 0x0b 0x23 0x3b 0x53 0x6b 6.19 0x0c 0x24 0x3c 0x54 0x6c 7.15 0x0d 0x25 0x3d 0x55 0x6d 8.25 0x0e 0x26 0x3e 0x56 0x6e 9.53 0x0f 0x27 0x3f 0x57 0x6f 11.0 0x10 0x28 0x40 0x58 0x70 12.7 0x11 0x29 0x41 0x59 0x71 14.7 0x12 0x2a 0x42 0x5a 0x72 17.8 0x13 0x2b 0x43 0x5b 0x73 21.5 0x14 0x2c 0x44 0x5c 0x74 26.1 0x15 0x2d 0x45 0x5d 0x75 31.6 0x16 0x2e 0x46 0x5e 0x76 38.3 0x17 0x2f 0x47 0x5f 0x77 44.2 0x18 0x30 0x48 0x60 0x78 51.1 0x19 0x31 0x49 0x61 0x79 59.0 0x1a 0x32 0x4a 0x62 0x7a 68.1 0x1b 0x33 0x4b 0x63 0x7b 86.6 0x1c 0x34 0x4c 0x64 0x7c 115 0x1d 0x35 0x4d 0x65 0x7d 140 0x1e 0x36 0x4e 0x66 0x7e 169 0x1f 0x37 0x4f 0x67 0x7f 205 0x20 0x38 0x50 0x68 0x7f 237 0x21 0x39 0x51 0x69 0x7f optional pmbus? addressing the user may leave sa0/sa1 open or shorted to pref. shorting sa0/sa1 to pref corresponds to rsa0/rsa1 4.22 k in the address table above. leaving sa0/sa1 open corresponds to rsa0/rsa1 274 k in the address table above. reserved addresses addresses listed in the table below are reserved or assigned accord- ing to the smbus speci? cation and may not be usable. refer to the smbus speci? cation for further information. protecting commands the user may write-protect speci? c pmbus? commands in the user nvm by following the steps below. 1. enter the default password 0x0000 through the command user_ passwd. after the correct password is entered, security_level will read back 0x01 instead of default 0x00. 2. if desired, de? ne a new password by writing it to the user_lock command. 3. de? ne which commands should be locked by using the 256 bit command user_conf. setting bit x will write-protect the pmbus? command with code x. 4. send command store_user_all. 5. cycle the input voltage. software tools for design and production murata power solutions provides software tools for con? guration and monitoring of this product via the pmbus? interface. for more information please contact your local murata power solu- tions sales representative. pmbus? addressing the pmbus? address should be con? gured with resistors connected between the sa0/sa1 pins and the pref pin, as shown in the table and ? gure below. note that ? ve different values of rsa1 produce the same address. recommended resistor values for hard-wiring pmbus? addresses are shown in the table. 1% tolerance resistors are required. the con? gurable pmbus? addresses range from 0x0a to 0x7f. in total 118 device address combinations are provided. user nvm murata factory default customizable ram default nvm write-protected restore_default_all write read pmbus interface restore_user_all store_user_all initialization murata factory default schematic of connection of address resistor. sa0 sa1 pref r sa1 r sa0 OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 26 of 31 www.murata-ps.com/support
pmbus? command delay after write before additional command store_user_all 500 ms store_default_all deadtime_gctrl user_conf 350 ms manuf_conf restore_user_all 10 ms restore_default_all frequency_switch vout_droop 0.5 ms iout_cal_gain adaptive_mode feedback_effort loop_config comp_model zetap pmbus? commands the product is pmbus? compliant. the following table lists all the implemented pmbus? read commands. for more detailed informa- tion see pmbus? power system management protocol speci? cation; part i C general requirements, transport and electrical interface and pmbus? power system management protocol; part ii C command language. designation code impl* standard pmbus? commands control commands page 00h no operation 01h yes on_off_config 02h yes write_protect 10h yes output commands capability (read only) 19h yes vout_mode (read only) 20h yes vout_command 21h yes vout_trim 22h yes vout_cal_offset 23h yes vout_max 24h yes vout_margin_high 25h yes vout_margin_low 26h yes vout_transition_rate 27h yes vout_droop 28h yes max_duty 32h no frequency_switch 33h yes vin_on 35h yes vin_off 36h yes iout_cal_gain 38h yes iout_cal_offset 39h yes vout_scale_loop 29h no vout_scale_monitor 2ah no coefficients 30h no fault limit commands power_good_on 5eh yes power_good_off 5fh yes vout_ov_fault_limit 40h yes vout_ov_warn_limit 42h no address comment 0x00 general call address / start byte 0x01 cbus address 0x02 address reserved for different bus format 0x03 - 0x07 reserved for future use 0x08 smbus host 0x09 - 0x0b assigned for smart battery 0x0c smbus alert response address 0x28 reserved for access.bus host 0x2c - 0x2d reserved by previous versions of the smbus speci? cation 0x37 reserved for access.bus default address 0x40 - 0x44 reserved by previous versions of the smbus speci? cation 0x48 - 0x4b unrestricted addresses 0x61 smbus device default address 0x78 - 0x7b 10-bit slave addressing 0x7c - 0x7f reserved for future use i2c/smbus C timing the setup time, tset, is the time data, sda, must be stable before the rising edge of the clock signal, scl. the hold time thold, is the time data, sda, must be stable after the falling edge of the clock signal, scl. if these times are violated incorrect data may be captured or meta-stability may occur and the bus communication may fail. all standard smbus protocols must be followed, including clock stretch- ing. refer to the smbus speci? cation, for smbus electrical and timing requirements. the bus-free time (time between stop and start packet) accord- ing to electrical speci? cation must be followed. the product supports pec (packet error checking) according to the smbus speci? cation. in operation cases according to the list below the products control- ler will be executing processor-intensive tasks and may not respond to pmbus? commands. ? ? during the presence of an overcurrent fault. ? ? just after the output voltage has been enabled. it is recommended to wait until pg is asserted (or the equivalent time) before sending commands. ? ? when sending subsequent commands to the same unit it is recommended to insert additional delays after write transactions according to the table below. setup and hold times timing diagram OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 27 of 31 www.murata-ps.com/support
designation code impl* phase_control f0h no identi? cation commands pmbus_revision 98h yes mfr_id 99h yes mfr_model 9ah yes mfr_revision 9bh yes mfr_location 9ch yes mfr_date 9dh yes mfr_serial 9eh yes ic_device_id adh yes ic_device_rev aeh yes supervisory commands store_default_all 11h yes restore_default_all 12h yes store_user_all 15h yes restore_user_all 16h yes product speci? c commands adaptive_mode d0h yes feedback_effort d3h yes loop_config d5h yes test_mode d9h yes comp_model dbh yes strap_disable dch yes manuf_conf e0h yes manuf_lock e1h yes manuf_passwd e2h yes user_conf e3h yes user_lock e4h yes user_passwd e5h yes security_level e6h yes deadtime_gctrl e7h yes zetap e8h yes *impl stands for implemented. designation code impl* vout_uv_warn_limit 43h no vout_uv_fault_limit 44h yes iout_oc_fault_limit 46h yes iout_oc_lv_fault_limit 48h no iout_oc_warn_limit 4ah no iout_uc_fault_limit 4bh no ot_fault_limit 4fh yes ot_warn_limit 51h yes ut_warn_limit 52h no ut_fault_limit 53h no vin_ov_fault_limit 55h yes vin_ov_warn_limit 57h no vin_uv_warn_limit 58h no vin_uv_fault_limit 59h yes fault response commands vout_ov_fault_response 41h yes vout_uv_fault_response 45h yes ot_fault_response 50h yes ut_fault_response 54h no vin_ov_fault_response 56h yes vin_uv_fault_response 5ah yes iout_oc_fault_response 47h yes iout_oc_lv_fault_response 49h no iout_uc_fault_response 4ch no ton_max_fault_response 63h yes time setting commands ton_delay 60h yes ton_rise 61h yes toff_delay 64h yes toff_fall 65h yes ton_max_fault_limit 62h yes status commands (read only) clear_faults 03h yes status_byte 78h yes status_word 79h yes status_vout 7ah yes status_iout 7bh yes status_input 7ch yes status_temperature 7dh yes status_cml 7eh yes status_mfr_specific 80h yes monitor commands (read only) read_vin 88h yes read_iin 89h no read_vout 8bh yes read_iout 8ch yes read_temperature_1 8dh yes read_temperature_2 8eh yes read_fan_speed_1 90h no read_duty_cycle 94h yes read_frequency 95h yes read_pout 96h no read_pin 97h no group commands interleave 37h yes OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 28 of 31 www.murata-ps.com/support
mechanical specifications OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 29 of 31 www.murata-ps.com/support
all solder joints is recommended to ensure a reliable solder joint. maximum product temperature requirements top of the product pcb near pin a2 or a5 is chosen as reference loca- tions for the maximum (peak) allowed product temperature (tp roduct ) since these will likely be the warmest part of the product during the re? ow process. snpb solder processes for snpb solder processes, the product is quali? ed for msl 1 accord- ing to ipc/jedec standard j std 020c. during re? ow tp roduct must not exceed 225 c at any time. pb-free solder processes for pb-free solder processes, the product is quali? ed for msl 3 according to ipc/jedec standard j-std-020c. during re? ow tp roduct must not exceed 260 c at any time. dry pack information surface mounted versions of the products are delivered in standard moisture barrier bags according to ipc/jedec standard j std 033 (handling, packing, shipping and use of moisture/re? ow sensitivity surface mount devices). using products in high temperature pb-free soldering processes requires dry pack storage and handling. in case the products have been stored in an uncontrolled environment and no longer can be considered dry, the modules must be baked according to j std 033. thermocoupler attachment surface mount assembly and repair the lga of the product require particular care during assembly since the lgas are hidden between the host board and the products pcb. special procedures are required for successful rework of these products. soldering information - surface mounting the surface mount product is intended for forced convection or vapor phase re? ow soldering in snpb or pb-free processes. the re? ow pro? le should be optimised to avoid excessive heating of the product. it is recommended to have a suf? ciently extended preheat time to ensure an even temperature across the host pcb and it is also recommended to minimize the time in re? ow. a no-clean ? ux is recommended to avoid entrapment of cleaning ? uids in cavities inside the product or between the product and the host board, since cleaning residues may affect long time reliability and isolation voltage. general reflow process specifications snpb eutectic pb-free average ramp-up (tproduct) 3c/s max 3c/s max typical solder melting (liquidus) temperature t l 183c 221c minimum re? ow time above tl 30 s 30 s minimum pin temperature t pin 210c 235c peak product temperature t product 225c 260c average ramp-down (t product ) 6c/s max 6c/s max maximum time 25c to peak 6 minutes 8 minutes minimum pin temperature recommendations pin number c1 or d1 are chosen as reference location for the mini- mum pin temperature recommendation since these will likely be the coolest solder joint during the re? ow process. snpb solder processes for snpb solder processes, a pin temperature (tpin) in excess of the solder melting temperature, (tl, 183c for sn63pb37) for more than 30 seconds and a peak temperature of 210c is recommended to ensure a reliable solder joint. for dry packed products only: depending on the type of solder paste and ? ux system used on the host board, up to a recommended maximum temperature of 245c could be used, if the products are kept in a controlled environment (dry pack handling and storage) prior to assembly. lead-free (pb-free) solder processes for pb-free solder processes, a pin temperature (tpin) in excess of the solder melting temperature (tl, 217 to 221c for snagcu solder alloys) for more than 30 seconds and a peak temperature of 235c on t product maximum t pin minimum time n i p profile product profile t l time in reflow time in preheat / soak zone time 25c to peak temperature pin c1 or d1 for measurement of minimum pin (solder joint) temperature tpin top of pwb near pin a2 or a5 for measurement of maximum product temperature, tproduct OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 30 of 31 www.murata-ps.com/support
assembly automatic pick and place equipment should be used to mount the product on the host board. the use of a vision system, utiliz- ing the ? ducials on the bottom side of the product, will ensure adequate accuracy. manual mounting of solder bump products is not recommended. this module is not recommended for assembly on the bottom side of a customer board. if such an assembly is attempted, components may fall off the module during the second re? ow process. repair for a successful repair (removal and replacement) of a lga product, a dedicated rework system should be used. the rework system should preferably utilize a re? ow station and a bottom side heater might also be needed for the operation. the product is an open frame design with a pick up surface on a large central component (in this case the choke). this pick up surface can be used for removal of the module provided that it is glued against module pcb before removal to prevent it from separating from the module pcb. delivery package information the products are delivered in antistatic carrier tape (eia 481 standard). carrier tape specifications material ps, antistatic surface resistance < 107 ohm/square bakeability the tape is not bakable tape width, w 24 mm [0.94 inch] pocket pitch, p1 20 mm [0.79 inch] pocket depth, k0 8.6 mm [0.339 inch] reel diameter 330 mm [13 inch] reel capacity 280 products /reel reel weight 1160 g/full reel round sprocket OKDL-T/12-w12-xxx-c 12a digital pol dc-dc converter series mdc_OKDL-T/12-w12-xxx-c.a02 page 31 of 31 www.murata-ps.com/support murata power solutions, inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to cha nge without notice. ? 2016 murata power solutions, inc. murata power solutions, inc. 11 cabot boulevard, mans? eld, ma 02048-1151 u.s.a. iso 9001 and 14001 registered this product is subject to the following operating requirements and the life and safety critical application sales policy: refer to: http://www.murata-ps.com/requirements/

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