1 ps8872h 09/26/08 features ? one high-speed pci-express lane ? adjustable transmiter de-emphasis & amplitude ? adjustable receiver equalization ? one spread spectrum reference clock buffer output ? input signal level detect and output squelch ? 100 differential cml i/o?s ? low power (100mw per channel) ? stand-by mode ? power down state ? v dd operating range: 1.8v 0.1v ? packaging (pb-free & green): ? 36-pad tqfn (zf36) description pericom semiconductor?s pi2eqx4401d is a low power, pci-express compliant signal re-driver. the device provides programmable equalization, ampli cation, and de-emphasis by using 4 select bits, sel[0:3], to optimize performance over a variety of physical mediums by reducing inter-symbol interference. pi2eqx4401d supports two 100 differential cml data i/o?s between the protocol asic to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user?s platform. the integrated equalization circuitry provides exibility with signal integrity of the pci-express signal before the re-driver. whereas the integrated de-emphasis circuitry provides exibility with signal integrity of the pci-express signal after the re- driver. a low-level input signal detection and output squelch function is provided for both channels. each channel operates fully independantly. when a channel is enabled (en_x=1) and operating, that channel's input signal level (on xl+/-) determines whether the output is enabled. if the input level of the channel falls below the active threshold level (vth-) then the output driver switches off, and the pin is pulled to vdd via a high impedance resistor. in addition to providing signal re-conditioning, pericom?s pi2eqx4401d also provides power management stand-by mode operated by a bus enable pin. a differential clock buffer is provided for test and other system requirements. this clock function is not used by the data channels. pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal detect feature 08-0241
2 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature block diagram pin description v dd ai+ ai- gnd av dd v dd b 0 + b 0 - gnd v dd v dd a 0 + a 0 - gnd agnd v dd bi+ bi- gnd iref sig_a sig_b sel0_a sel1_a sel2_a sel3_a en_a en_b out- out+ sel3_b sel2_b sel1_b sel0_b clk in- clk in+ 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 gnd xl+ cml lvcmos sig_x xo+ xo- cml limiting amp equalizer sel[0:1] clkin- clkin+ out0- out0+ sel[2]_x sel buffer clk iref xl+ 08-0241
3 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature pin description pin # pin name i/o description 1, 6, 10, 23, 28 v dd pwr 1.8v supply voltage 2 ai+ i positive cml input channel a with internal 50 pull down during normal operation (en_a=1). when en_a=0, this pin is high-impedance. 3 ai- i negative cml input channel a with internal 50 pull down during normal operation (en_a=1). when en_a=0, this pin is high-impedance. 4, 9, 20, 25 gnd pwr supply ground 22 bi+ i positive cml input channel b with internal 50 pull down during normal operation (en_b=1). when en_b=0, this pin is high-impedance. 21 bi- i negative cml input channel b with internal 50 pull down during normal operation (en_b=1). when en_b=0, this pin is high-impedance. 34, 33 sel[0:1]_a i selection pins for equalizer (see ampli er con guration table) w/ 50k internal pull up 13, 14 sel[0:1]_b i 32 sel[2]_a i selection pins for ampli er (see ampli er con guration table) w/ 50k internal pull up 15 sel[2]_b i 31 sel[3]_a i selection pins for de-emphasis (see de-emphasis con guration table) w/ 50k internal pull up 16 sel[3]_b i 27 ao+ o positive cml output channel a internal 50 pull up during normal opera- tion and 2k pull up otherwise. 26 ao- o negative cml output channel a with internal 50 pull up during normal operation and 2k pull up otherwise. 7 bo+ o positive cml output channel b with internal 50 pull up during normal operation and 2k pull up otherwise. 8 bo- o negative cmloutput channel b with internal 50 pull up during normal operation and 2k pull up otherwise. 30, 29 en_[a,b] i en_[a:b] is the enable pin. a lvcmos high provides normal operation. a lvcmos low selects a low power down mode. 12 clkin- i differential input reference clock. if clock buffer is not used, then both clkin+, clkin- should be pulled high to vdd. 11 clkin+ i 17, 18 out+, out- o differential reference clock output 5 avdd pwr 1.8v analog supply voltage 24 agnd pwr analog ground 19 iref o external 475 resistor connection to set the differential output current. if the clock buffer is not used, then iref should be unconnected (open). 36, 35 sig_a, sig_b o sig detector output for channel a-b. provides a lvcmos high output when an input signal greater than the threshold is detected 08-0241
4 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature storage temperature ........................................................ ?65c to +150c supply voltage to ground potential ................................... ?0.5v to +2.5v dc sig voltage ..........................................................?0.5v to v dd +0.5v current output ................................................................-25ma to +25ma power dissipation continous ......................................................... 500mw operating temperature .............................................................. 0 to +70c output swing control sel2_[a:b] swing 01 x 1 1.2x equalizer selection sel0_[a:b] sel1_[a:b] compliance channel 0 0 no equalization 0 1 [0:2.5db] @ 1.25 ghz 1 0 [2.5:4.5db] @ 1.25 ghz 1 1 [4.5:6.5db] @ 1.25 ghz output de-emphasis adjustment sel3_[a:b] de-emphasis 0 0db 1 -3.5db note: stresses greater than those listed under max i mum rat- ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. exposure to absolute max i mum rating con di tions for ex- tended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) note: 1. design target speci cation. absolute values will be based on characterization. 08-0241
5 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature ac/dc electrical characteristics (v dd = 1.8 0.1v) symbol parameter conditions min. typ. max. units ps supply power en = lvcmos low 0.1 w en = lvcmos high 0.6 latency from input to output 2.0 ns cml receiver input rl rx return loss 50 mhz to 1.25 ghz 12 db v rx-diffp-p differential input peak-to- peak voltage 0.175 1.200 v v rx-cm-acp ac peak common mode input voltage 150 mv v th- signal detection threshold en_x=high 120 175 mv z rx-diff-dc dc differential input impedance 80 100 120 z rx-dc dc input impedance 40 50 60 equalization j rs residual jitter total jitter (2) 0.3 ulp-p deterministic jitter 0.2 j rm random jitter see note 2 1.5 psrms notes 1. k28.7 pattern is applied differentially at point a as shown in figure 1. 2. total jitter does not include the signal source jitter. total jitter (tj) = (14.1 rj + dj) where rj is random rms jitter and dj is maximum deterministic jitter. signal source is a k28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and k28.7 (00 11111000) or equivalent for random jitter test. residual jitter is that which remains after equalizing media-induced losses of the environment of figure 1 or its equivalent. the deterministic jitter at point b must be from media-induced loss, and not from clock source modulation. jitter is measured at 0v at point c of figure 1. figure 1. test condition referenced in the electrical characteristic table pericom pi2eqx4401a signal source sma connector in out a sma connector bc fr4 30 in 08-0241
6 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature ac/dc electrical characteristics (t a = 0 to 70?c) symbol parameter conditions min. typ. max. units cml transmitter output (100 differential) v diffp output voltage swing differential swing | v tx-d+ - v tx-d- | 400 650 mvp-p v tx-c common-mode voltage | v tx-d+ + v tx-d- | / 2 v dd - 0.3 t f , t r transition time 20% to 80% (3) 150 ps z out output resistance single ended 40 50 60 z tx-diff-dc dc differential tx impedance 80 100 120 c tx ac coupling capacitor 75 200 nf v tx-diffp-p differential peak-to-peak ouput voltage v tx-diffp-p = 2 * | v tx-d+ - v tx-d- | 0.8 1.3 v lvcmos control pins v ih input high voltage 0.65 v dd v dd v v il input low voltage 0.35 v dd i ih input high current 250 a i il input low current 500 notes 3. using k28.7 (00 11111000) patern) 4. ac speci cations are guaranteed by design and characterization 08-0241
7 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature ac switching characteristics for clock buffer (v dd = 1.8 0.1v, av dd = 1.8 0.1v) symbol parameters min max. units notes t rise / t fall rise and fall time (measured between 0.175v to 0.525v) 125 525 ps 1 t rise / t fall rise and fall time variation 75 1 v high voltage high including overshoot 660 900 mv 1 v low voltage low including undershoot -200 1 v cross absolute crossing point voltages 200 550 1 v cross total variation of vcross over all edges 250 1 t dc duty cycle (input duty cycle = 50%) 45 55 % 2 notes: 1. measurement taken from single ended waveform. 2. measurement taken from differential waveform. 3. test con guration is r s = 33.2 , rp = 49.9 , and 2pf. con guration test load board termination figure 2. con guration test load board termination note: 1. tla and tlb are 3? transmission lines. rs 33 5% rs 33 5% rp 49.9 1% 475 1% rp 49.9 1% 2pf 5% 2pf 5% clock# clock tla tlb clkbuf 08-0241
8 ps8872h 09/26/08 pi2eqx4401d 2.5gbps x1 lane serial pci-express repeater/equalizer with clock buffer & signal defect feature packaging mechanical: 36-pad tqfn (zf36) description: 36-contact, very thin fine pitch quad flat no-lead (tqfn) package code: zf36 document control #: pd-2023 revision: b notes: 1) all dimensions are in millimeters, angles in degrees 2) bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 3) ref jedec: mo-220i/wjhd 4) thermal via diameter. recommended 0.2~0.33mm 5) thermal pitch. recommended 1.27mm date: 4/28/06 ordering information ordering number package code package description PI2EQX4401DZFE zf pb-free and green 36-pad tqfn notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com 08-0241
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