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rev: 1.00b 12/2002 1/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. bytesafe is a trademark of giga semiconductor, inc. (gsi technology). gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) 512k x 18, 256k x 32, 256k x 36 9mb sync burst srams 250 mhz ? 133 mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 100-pin tqfp & 165-bump bga commercial temp industrial temp features ? ieee 1149.1 jtag-compatible boundary scan ? 2.5 v or 3.3 v +10%/?10% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? byte write (bw ) and/or global write (gw ) operation ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec-standard packages functional description applications the gs88118b(t/d)/gs88132b(d)/gs88136b(t/d) is a 9,437,184-bit high performance synchronous sram with a 2- bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. controls addresses, data i/os, chip enable (e1 , e2), address burst control inputs (adsp , adsc , adv ) and write control inputs (bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable (g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order (lbo ) input. the burst function need not be used . new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output register can be controlled by the user via the ft mode pin (pin 14). holding the ft mode pin low places the ram in flow th rough mode, causing output data to bypass the data output register. holding ft high places the ram in pipeline m ode, activating the rising-edge- triggered data output register. scd pipelined reads the gs88118b(t/d)/gs88132b(d)/gs88136b(t/d) is a scd (single cycle deselect) pipelined synchronous sram. dcd (dual cycle deselect) versio ns are also available. scd srams pipeline deselect commands one stage less than read commands. scd rams begin turning off their outputs immediately after the deselect command has been captured in the input registers. byte write and global write byte write operation is performed by using byte write enable (bw ) input combined with one or more individual byte write signals (bx ). in addition, global write (gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs88118b(t/d)/gs88132b(d)/gs88136b(t/d) operates on a 2.5 v or 3.3 v power supply. all input are 3.3 v and 2.5 v compatible. separate output power (v ddq ) pins are used to decouple output noise from the internal circuits and are 3.3 v and 2.5 v compatible. -250 -225 -200 -166 -150 -133 unit pipeline 3-1-1-1 t kq tcycle 2.5 4.0 2.7 4.4 3.0 5.0 3.4 6.0 3.8 6.7 4.0 7.5 ns ns 3.3 v curr (x18) curr (x32/x36) 280 330 255 300 230 270 200 230 185 215 165 190 ma ma 2.5 v curr (x18) curr (x32/x36) 275 320 250 295 230 265 195 225 180 210 165 185 ma ma flow through 2-1-1-1 t kq tcycle 5.5 5.5 6.0 6.0 6.5 6.5 7.0 7.0 7.5 7.5 8.5 8.5 ns ns 3.3 v curr (x18) curr (x32/x36) 175 200 165 190 160 180 150 170 145 165 135 150 ma ma 2.5 v curr (x18) curr (x32/x36) 175 200 165 190 160 180 150 170 145 165 135 150 ma ma
rev: 1.00b 12/2002 2/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) gs88118b 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 ft v dd nc v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss nc v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 tms tdi v ss v dd tdo tck a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 nc nc b b b a a 17 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 512k x 18 top view dq a9 a 18 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.00b 12/2002 3/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) gs88136b 100-pin tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 ft v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 v ss v dd a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 b d b c b b b a a 17 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 256k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 tms tdi tdo tck
rev: 1.00b 12/2002 4/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) tqfp pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a 2 ? a 17 i address inputs a 18 i address input dq a1 ? dq a9 dq b1 ? dq b9 dq c1 ? dq c9 dq d1 ? dq d9 i/o data input and output pins nc ? no connect bw ibyte write ? writes all enabled bytes; active low b a , b b, b c , b d i byte write enable for dq a , dq b data i/os; active low ck i clock input signal; active high gw i global write enable ? writes all bytes; active low e 1 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low zz i sleep mode control; active high tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
rev: 1.00b 12/2002 5/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) 165 bump bga?x18 commom i/o?top view (package d) 12345 6 7891011 anc ae1 bb nc e3 bw adsc adv a a18 a bnc ae2ncba ck gw g adsp anc b cncnc v ddq v ss v ss v ss v ss v ss v ddq nc dqa c dnc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa d enc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa e fnc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa f gnc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa g hft mcl nc v dd v ss v ss v ss v dd nc nc zz h j dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc j k dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k l dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l m dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m n dqb nc v ddq v ss nc nc nc v ss v ddq nc nc n pncnc a atdi a1 tdo a a a a17 p rlbo nc a atms a0 tck a a a ar 11 x 15 bump bga?13mm x 15 mm body?1.0 mm bump pitch
rev: 1.00b 12/2002 6/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) 165 bump bga?x32 common i/o?top view (package d) 12345 6 7891011 anc ae1 bc bb e3 bw adsc adv a nc a bnc ae2bd ba ck gw g adsp anc b cncnc v ddq v ss v ss v ss v ss v ss v ddq nc nc c d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb d e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g hft mcl nc v dd v ss v ss v ss v dd nc zq zz h j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa j k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m nncnc v ddq v ss nc nc nc v ss v ddq nc nc n pncnc a atdi a1 tdo a a a a17 p rlbo nc a atms a0 tck a a a ar 11 x 15 bump bga?13mm x 15 mm body?1.0 mm bump pitch
rev: 1.00b 12/2002 7/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) 165 bump bga?x36 common i/o?top view (package d) 12345 6 7891011 anc ae1 bc bb e3 bw adsc adv a nc a bnc ae2bd ba ck gw g adsp anc b c dqc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqb c d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb d e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g hft mcl nc v dd v ss v ss v ss v dd nc nc zz h j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa j k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m n dqd nc v ddq v ss nc nc nc v ss v ddq nc dqa n pncnc a atdi a1 tdo a a a a17 p rlbo nc a atms a0 tck a a a ar 11 x 15 bump bga?13mm x 15 mm body?1.0 mm bump pitch
rev: 1.00b 12/2002 8/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) gs88118/32/36bd 165-bu mp bga pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs an i address inputs a 17, a 18 i address input dq a1 ?dq a9 dq b1 ?dq b9 dq c1 ?dq c9 dq d1 ?dq d9 i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low nc ? no connect ck i clock input signal; active high bw i byte write?writes all enabled bytes; active low gw i global write enable?writes all bytes; active low e 1 i chip enable; active low e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active l0w adsc , adsp i address strobe (processor, cache controller); active low zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock mcl ? must connect low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
rev: 1.00b 12/2002 9/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) gs88118b(t/d)/gs88132b(d)/gs 88136b(t/d) block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0 ? an lbo adv ck adsc adsp gw bw e 1 ft g zz power down control memory array 36 36 4 a qd dqx1 ? dqx9 nc parity nc parity encode compare 36 4 36 36 4 32 note: only x36 version shown for simplicity. 1 36 36 dq register 4 b a b b b c b d
rev: 1.00b 12/2002 10/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) note: there arepull-up devices on the ft pin and a pull-down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences bpr 1999.05.18 mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb linear burst sequence n ote: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.00b 12/2002 11/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) byte wr ite truth table note: 1. all byte outputs are active in read cycles regar dless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x36 version. function gw bw b a b b b c b d notes read h h x x x x 1 read hlhhhh1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all byteshlllll2, 3, 4 write all byteslxxxxx
rev: 1.00b 12/2002 12/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) synchronous truth table operation address used state diagram key 5 e 1 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x l x x high-z read cycle, begin burst external r l l x x x q read cycle, begin burst external r l h l x f q write cycle, begin burst external w l h l x t d read cycle, continue burst next cr x h h l f q read cycle, continue burst next cr h x h l f q write cycle, continue burst next cw x h h l t d write cycle, continue burst next cw h x h l t d read cycle, suspend burst current x h h h f q read cycle, suspend burst current h x h h f q write cycle, suspend burst current x h h h t d write cycle, suspend burst current h x h h t d notes: 1. x = don?t care, h = high, l = low 2. w = t (true) and f (false) is defined in the byte write truth table preceding. 3. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 4. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 5. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 6. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
rev: 1.00b 12/2002 13/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr simplified state diagram notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assume s active use of only the enable (e1 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs, and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs, and assumes adsp is tied high and adv is tied low.
rev: 1.00b 12/2002 14/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw simplified state diagram with g notes: 1. the diagram shows supported (tes ted) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in gray tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
rev: 1.00b 12/2002 15/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an exte nded period of tim e, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c
rev: 1.00b 12/2002 16/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 2.0 ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v1 v ddq i/o input high voltage v ihq 0.6*v dd ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v.
rev: 1.00b 12/2002 17/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) note: these parameters are sample tested. notes: 1. junction temperature is a function of sr am power dissipation, package thermal resi stance, mounting board temperature, ambient . temper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ? 40 25 85 c2 note: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf input/output capacitance c i/o v out = 0 v 67pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r ja 24 c/w 1,2 junction to case (top) ? r jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.00b 12/2002 18/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
rev: 1.00b 12/2002 19/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) operating currents notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario. parameter test conditions mode symbol -250 -225 -200 -166 -150 -133 unit 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current 3.3 v device selected; all other inputs v ih o r v il output open (x32 x36) pipeline i dd i ddq 290 40 300 40 265 35 275 35 240 30 250 30 205 25 215 25 190 25 200 25 170 20 180 20 ma flow through i dd i ddq 180 20 190 20 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 150 10 ma (x18) pipeline i dd i ddq 260 20 270 20 235 20 245 20 215 15 225 15 185 15 195 15 170 15 180 15 155 10 165 10 ma flow through i dd i ddq 165 10 175 10 155 10 165 10 150 10 160 10 140 10 150 10 135 10 145 10 125 10 135 10 ma operating current 2.5 v device selected; all other inputs v ih o r v il output open (x32/ x36) pipeline i dd i ddq 290 30 300 30 265 30 275 30 240 25 250 25 205 20 215 20 190 20 200 20 170 15 180 15 ma flow through i dd i ddq 180 20 190 20 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 150 10 ma (x18) pipeline i dd i ddq 260 15 270 15 235 15 245 15 215 15 225 15 185 10 195 10 170 10 180 10 155 10 165 10 ma flow through i dd i ddq 165 10 175 10 155 10 165 10 150 10 160 10 140 10 150 10 135 10 145 10 125 10 135 10 ma standby current zz v dd ? 0.2 v ? pipeline i sb 40 50 40 50 40 50 40 50 40 50 40 50 ma flow through i sb 40 50 40 50 40 50 40 50 40 50 40 50 ma deselect current device deselected; all other inputs v ih or v il ? pipeline i dd 85 90 80 85 75 80 64 70 60 65 50 55 ma flow through i dd 60 65 60 65 50 55 50 55 50 55 45 50 ma
rev: 1.00b 12/2002 20/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above. parameter symbol -250 -225 -200 -166 -150 -133 unit min max min max min max min max min max min max pipeline clock cycle time tkc 4.0 ? 4.4 ? 5.0 ? 6.0 ? 6.7 ? 7.5 ? ns clock to output valid tkq ? 2.5 ? 2.7 ? 3.0 ? 3.4 ? 3.8 ? 4.0 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.2 ? 1.3 ? 1.4 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.2 ? 0.3 ? 0.4 ? 0.5 ? 0.5 ? 0.5 ? ns flow through clock cycle time tkc 5.5 ? 6.0 ? 6.5 ? 7.0 ? 7.5 ? 8.5 ? ns clock to output valid tkq ? 5.5 ? 6.0 ? 6.5 ? 7.0 ? 7.5 ? 8.5 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? 1.5 ? 1.7 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.7 ? 2 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns g to output valid toe ? 2.5 ? 2.7 ? 3.2 ? 3.5 ? 3.8 ? 4.0 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 2.7 ? 3.0 ? 3.0 ? 3.0 ? 3.0 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? 20 ? ns
rev: 1.00b 12/2002 21/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) pipeline mode timing begin read a cont cont deselect write b read c read c+1 read c+2 read c+3 cont deselect tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts burst read burst read single write tkc tkc tkl tkl tkh single write single read tkh single read q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) abc deselected with e1 e1 masks adsp e2 and e3 only sampled with adsp and adsc adsc initiated read ck adsp adsc adv a0?an gw bw b a?b d e1 e2 e3 g dqa?dqd
rev: 1.00b 12/2002 22/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) flow through mode timing begin read a cont cont1 write b read c read c+1 read c+2 read c+3 read c cont2 deselect tkqx thz tkq tlz th ts tohz toe th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsc adsc initiated read deselected with e1 fixed high ck adsp adsc adv a0?an gw bw b a?b d e1 e2 e3 g dqa?dqd
rev: 1.00b 12/2002 23/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates norma lly after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exit ing sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. application tips single and dual cycle deselect scd devices (like this one) force the use of ?dummy read cycles? (read cycles that ar e launched normally bu t that are ended wit h the output drivers inactive) in a fully sy nchronous environment. dumm y read cycles waste performance but their use usually assures there will be no bus c ontention in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care mu st be exercised to avoid excessive bus contention. jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with ieee standard 1149. 1-1990, a serial boundary scan interface standard (commonly referred to as jtag) . the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v ddq . ck adsp adsc th tkh tkl tkc ts zz tzzr tzzh tzzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze sleep mode timing diagram ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
rev: 1.00b 12/2002 24/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are selected (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap registers is a serial shift register that captures serial input data on th e rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is se lected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructio ns that are executed by the tap controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in th e scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of th e rams i/o ring when the controller is in jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset aut omaticly at power-up.
rev: 1.00b 12/2002 25/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the c ode is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. tap controller instruction set overview there are two classes of instructions defi ned in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 xxxx0000000000001000000110110011 x18 xxxx0000000000001010000110110011 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.00b 12/2002 26/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occur s when the tap controller is moved to the shift-dr state. this allo ws the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instru c- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bo undary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state i dentified in the boundary scan chain table at the end of this section of the dat asheet. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring conten ts while the input buffers are in transition (i.e. in a metast able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set- up plus hold time (tts plus tth). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan r egister. moving the controlle r to shift- select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1
rev: 1.00b 12/2002 27/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) dr state then places the boundary scan register between t he tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruct ion register is loaded with al l logic 0s. the extest command does not block or override the ram?s input pins; therefore, the ram?s in ternal state is still determined by its input pins. typically, the boundary scan register is loaded with the desired pa ttern of data with the sample/preload command. then the exte st command is used to output the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling e dge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest co mmand. when the extest instruction is sele cted, the sate of all the ram?s input and i/o pins, as well as the default va lues at scan register locations not associated with a pin, a re transferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ra m?s output pins drive out the value of the boundary scan register location with wh ich each output pin is associated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in sh ift-dr mode. the idcode instruction is t he default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register , all ram outputs are forced to an inactive drive state (high- z) and the bound- ary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.00b 12/2002 28/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v dd2 v1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 11ua4 test port output high voltage v ohj 1.7 ? v5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
rev: 1.00b 12/2002 29/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) jtag port timing diagram jtag port ac electrical characteristics boundary scan (bsdl files) for information regarding the boundary scan chain, or to obta in bsdl files for this part, please contact our applications engineering department at: apps@gsitechnology.com . parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.00b 12/2002 30/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) tqfp package drawing d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch 0.65 l foot length 0.45 0.60 0.75 l1 lead length 1.00 y coplanarity 0.10 lead angle 0 7
rev: 1.00b 12/2002 31/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) package dimensions?165- bump fpbga (package d) a b c d e f g h i j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.07 150.07 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.50 (165x) c seating plane 0.15 c 0.25~0.40 1.20 max. 0.450.05 0.25 c (0.26)
rev: 1.00b 12/2002 32/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) ordering information for gs i synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 512k x 18 gs88118bt-250 pipeline/flow through tqfp 250/5.5 c 512k x 18 gs88118bt-225 pipeline/flow through tqfp 225/6 c 512k x 18 gs88118bt-200 pipeline/flow through tqfp 200/6.5 c 512k x 18 gs88118bt-166 pipeline/flow through tqfp 166/7 c 512k x 18 gs88118bt-150 pipeline/flow through tqfp 150/7.5 c 512k x 18 gs88118bt-133 pipeline/flow through tqfp 133/8.5 c 256k x 36 gs88136bt-250 pipeline/flow through tqfp 250/5.5 c 256k x 36 gs88136bt-225 pipeline/flow through tqfp 225/6 c 256k x 36 gs88136bt-200 pipeline/flow through tqfp 200/6.5 c 256k x 36 gs88136bt-166 pipeline/flow through tqfp 166/7 c 256k x 36 gs88136bt-150 pipeline/flow through tqfp 150/7.5 c 256k x 36 gs88136bt-133 pipeline/flow through tqfp 133/8.5 c 512k x 18 gs88118bt-250i pipeline/flow through tqfp 250/5.5 i 512k x 18 gs88118bt-225i pipeline/flow through tqfp 225/6 i 512k x 18 gs88118bt-200i pipeline/flow through tqfp 200/6.5 i 512k x 18 gs88118bt-166i pipeline/flow through tqfp 166/7 i 512k x 18 gs88118bt-150i pipeline/flow through tqfp 150/7.5 i 512k x 18 gs88118bt-133i pipeline/flow through tqfp 133/8.5 i 256k x 36 gs88136bt-250i pipeline/flow through tqfp 250/5.5 i 256k x 36 gs88136bt-225i pipeline/flow through tqfp 225/6 i 256k x 36 gs88136bt-200i pipeline/flow through tqfp 200/6.5 i 256k x 36 gs88136bt-166i pipeline/flow through tqfp 166/7 i 256k x 36 gs88136bt-150i pipeline/flow through tqfp 150/7.5 i 256k x 36 gs88136bt-133i pipeline/flow through tqfp 133/8.5 i 512k x 18 gs88118bd-250 pipeline/flow through 165 bga 250/5.5 c 512k x 18 gs88118bd-225 pipeline/flow through 165 bga 225/6 c 512k x 18 gs88118bd-200 pipeline/flow through 165 bga 200/6.5 c 512k x 18 gs88118bd-166 pipeline/flow through 165 bga 166/7 c 512k x 18 gs88118bd-150 pipeline/flow through 165 bga 150/7.5 c 512k x 18 gs88118bd-133 pipeline/flow through 165 bga 133/8.5 c notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs88118bt- 150it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00b 12/2002 33/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) 256k x 32 gs88132bd-250 pipeline/flow through 165 bga 250/5.5 c 256k x 32 gs88132bd-225 pipeline/flow through 165 bga 225/6 c 256k x 32 gs88132bd-200 pipeline/flow through 165 bga 200/6.5 c 256k x 32 gs88132bd-166 pipeline/flow through 165 bga 166/7 c 256k x 32 gs88132bd-150 pipeline/flow through 165 bga 150/7.5 c 256k x 32 gs88132bd-133 pipeline/flow through 165 bga 133/8.5 c 256k x 36 gs88136bd-250 pipeline/flow through 165 bga 250/5.5 c 256k x 36 gs88136bd-225 pipeline/flow through 165 bga 225/6 c 256k x 36 gs88136bd-200 pipeline/flow through 165 bga 200/6.5 c 256k x 36 gs88136bd-166 pipeline/flow through 165 bga 166/7 c 256k x 36 gs88136bd-150 pipeline/flow through 165 bga 150/7.5 c 256k x 36 gs88136bd-133 pipeline/flow through 165 bga 133/8.5 c 512k x 18 gs88118bd-250i pipeline/flow through 165 bga 250/5.5 i 512k x 18 gs88118bd-225i pipeline/flow through 165 bga 225/6 i 512k x 18 gs88118bd-200i pipeline/flow through 165 bga 200/6.5 i 512k x 18 gs88118bd-166i pipeline/flow through 165 bga 166/7 i 512k x 18 gs88118bd-150i pipeline/flow through 165 bga 150/7.5 i 512k x 18 gs88118bd-133i pipeline/flow through 165 bga 133/8.5 i 256k x 32 gs88132bd-250i pipeline/flow through 165 bga 250/5.5 i 256k x 32 gs88132bd-225i pipeline/flow through 165 bga 225/6 i 256k x 32 gs88132bd-200i pipeline/flow through 165 bga 200/6.5 i 256k x 32 gs88132bd-166i pipeline/flow through 165 bga 166/7 i 256k x 32 gs88132bd-150i pipeline/flow through 165 bga 150/7.5 i 256k x 32 gs88132bd-133i pipeline/flow through 165 bga 133/8.5 i 256k x 36 gs88136bd-250i pipeline/flow through 165 bga 250/5.5 i 256k x 36 gs88136bd-225i pipeline/flow through 165 bga 225/6 i 256k x 36 GS88136BD-200I pipeline/flow through 165 bga 200/6.5 i 256k x 36 gs88136bd-166i pipeline/flow through 165 bga 166/7 i 256k x 36 gs88136bd-150i pipeline/flow through 165 bga 150/7.5 i 256k x 36 gs88136bd-133i pipeline/flow through 165 bga 133/8.5 i org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs88118bt- 150it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.00b 12/2002 34/34 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs88118b(t/d)/gs8813 2b(d)/gs88136b(t/d) 9mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 88118b_r1 ? creation of new datasheet

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