View ST10F273M-4QR3_8428589.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. september 2013 doc id 13453 rev 4 1/186 1 st10f273m 16-bit mcu with 512 kbyte flas h memory and 36 kbyte ram datasheet ? production data features high performance 16-bit cpu with dsp functions ? 50ns instruction cycle time at 40 mhz max cpu clock ? multiply/accumulate unit (mac) 16 x 16-bit multiplication, 40 -bit accumulator ? enhanced boolean bit manipulations ? single-cycle context switching support memory organization ? 512 kbyte on-chip flash memory single voltage with erase/program controller (full performance, 32-bit fetch) ? 100 k erasing/programming cycles ? up to 16 mbyte linear address space for code and data (5 mbytes with can or i 2 c) ? 2 kbyte on-chip internal ram (iram) ? 34 kbyte on-chip extension ram (xram) ? programmable external bus configuration and characteristics for different address ranges ? 5 programmable chip-select signals ? hold-acknowledge bus arbitration support interrupt ? 8-channel peripheral event controller for single cycle interrupt driven data transfer ? 16-priority-level interrupt system with 56 sources, sampling rate down to 25ns timers ? 2 multifunctional general purpose timer units with 5 timers two 16-channel capture / compare units 4-channel pwm unit + 4-channel xpwm 24-channel a/d converter ? 16-channel 10-bit, accuracy +/-2 lsb ? 8-channel 10-bit, accuracy +/-5 lsb ? 4.85s minimum conversion time serial channels ? 2 synch. / asynch. serial channels ? 2 high-speed synchronous channels ?i 2 c standard interface 2 can 2.0b interfaces operating on 1 or 2 can buses (64 or 2x32 messages, c-can version) fail-safe protection ? programmable watchdog timer ? oscillator watchdog on-chip bootstrap loader clock generation ? on-chip pll and 4 to 12 mhz oscillator ? direct or prescaled clock input real time clock and 32 khz on-chip oscillator up to 111 general purpose i/o lines ? individually programmable as input, output or special function ? programmable threshold (hysteresis) idle, power down and standby modes single voltage supply: 5 v 10% (embedded regulator for 1.8 v core supply) temperature range: -40c to 125c pqfp144 (28 x 28 x 3.4mm) (plastic quad flat package) lqfp144 (20 x 20 x 1.4mm) (low profile quad flat package) www.st.com
contents st10f273m 2/186 doc id 13453 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 special characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.1 x-peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 improved supply ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 internal flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.2 module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 flash control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.1 flash control register 0 low (fcr0l) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.2 flash control register 0 high (fcr0h) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.3 flash control register 1 low (fcr1l) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4.4 flash control register 1 high (fcr1h) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.5 flash data register 0 low (fdr0l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4.6 flash data register 0 high (fdr0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.4.7 flash data register 1 low (fdr1l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.8 flash data register 1 high (fdr1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.9 flash address register low (farl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4.10 flash address register high (farh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4.11 flash error register (fer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4.12 xflash interface control dummy register (xficr) . . . . . . . . . . . . . . . . . 40 5.5 protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.5.1 protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
st10f273m contents doc id 13453 rev 4 3/186 5.5.2 flash non-volatile write protection i register low (fnvwpirl) . . . . . . . 41 5.5.3 flash non-volatile write protection i register high (fnvwpirh) . . . . . . 42 5.5.4 flash non-volatile write protection i register low mirror (fnvwpirl-m) 42 5.5.5 flash non-volatile write protection i register high mirror (fvwpirh-m) 42 5.5.6 flash non-volatile access protection register 0 (fnvapr0) . . . . . . . . . 43 5.5.7 flash non-volatile access protection register 1 low (fnvapr1l) . . . . . 43 5.5.8 flash non-volatile access protection register 1 high (fnvapr1h) . . . . 44 5.5.9 access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.10 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.5.11 temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6 write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.7 write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1 selection among user-code, standard or selective bootstrap . . . . . . . . . . 49 6.2 standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 alternate and selective boot mode (abm and sbm) . . . . . . . . . . . . . . . . 50 6.3.1 activation of the abm and sbm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.2 user mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.3 selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 multiplier-accumulator unit (mac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3 mac co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1 x-peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2 exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10 capture / compare (capcom) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11 general purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.1 gpt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
contents st10f273m 4/186 doc id 13453 rev 4 11.2 gpt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12 pwm modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.2 i/o?s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.2.1 open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.2.2 input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.3 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15 serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.1 asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 74 15.2 ascx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.3 ascx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15.4 high speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 75 16 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17 can modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.1 configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.2 can bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.2.1 single can bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.2.2 multiple can bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17.2.3 parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 19 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 20 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 20.1 input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 20.2 asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 20.3 synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
st10f273m contents doc id 13453 rev 4 5/186 20.4 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 20.5 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 20.6 bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 20.7 reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 20.8 reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 20.9 reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 21 power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21.2.1 protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 21.2.2 interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 21.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 21.3.1 entering standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 21.3.2 exiting standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 21.3.3 real time clock and standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 21.3.4 power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 22 programmable output clo ck divider . . . . . . . . . . . . . . . . . . . . . . . . . . 114 23 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 23.1 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 23.2 x-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 23.3 flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 23.4 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 24 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 24.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 24.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 24.3 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 24.4 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 24.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 24.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 24.7 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 24.7.1 conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
contents st10f273m 6/186 doc id 13453 rev 4 24.7.2 a/d conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 24.7.3 total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 24.7.4 analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 24.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 24.8.1 test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 24.8.2 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 24.8.3 clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 24.8.4 prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 24.8.5 direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 24.8.6 oscillator watchdog (owd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 24.8.7 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 24.8.8 voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 24.8.9 pll jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 24.8.10 pll lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 24.8.11 main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 24.8.12 32 khz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 24.8.13 external clock drive xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 24.8.14 memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 24.8.15 external memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 24.8.16 multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 24.8.17 demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 24.8.18 clkout and ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 24.8.19 external bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 24.8.20 high-speed synchronous serial interface (ssc) timing . . . . . . . . . . . . 177 25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 25.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 25.2 pqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 25.3 lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 26 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 27 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
st10f273m list of tables doc id 13453 rev 4 7/186 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2. summary of iflash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 3. flash module address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4. flash module sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5. flash module sectorization (write operations, or roms1 = ?1?) . . . . . . . . . . . . . . . . . . . . . 29 table 6. flash control registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. fcr0l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. fcr0h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. fcr1l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. fcr1h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11. bank (bxs) and sectors (bxfy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. fdr0l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13. fdr0h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. fdr1l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. fdr1h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16. farl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. farh register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. fer register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19. xflash interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. fnvwpirl register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. fnvwprih register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. fnvapr0 register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 23. fnvapr1l register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24. fnvapr1h register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 25. summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 26. flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. st10f273m boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 table 28. standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. mac instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 30. interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 31. x-interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 32. trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 33. compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 34. capcom timer input frequencies, resolutions and periods at 40 mhz . . . . . . . . . . . . . . . 63 table 35. gpt1 timer input frequencies, resolutions and periods at 40 mhz. . . . . . . . . . . . . . . . . . . 64 table 36. gpt2 timer input frequencies, resolutions and periods at 40 mhz. . . . . . . . . . . . . . . . . . . 66 table 37. pwm unit frequencies and resolutions at 40 mhz cpu clock . . . . . . . . . . . . . . . . . . . . . . 68 table 38. asc asynchronous baudrates by reload value and deviation errors . . . . . . . . . . . . . . . . . 74 table 39. asc synchronous baudrates by reload value and deviation errors . . . . . . . . . . . . . . . . . . 75 table 40. ssc synchronous baudrate and reload values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 41. wdtrel reload value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 42. reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 43. reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 44. port0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 107 table 45. power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 46. list of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 47. list of xbus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 48. list of flash control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
list of tables st10f273m 8/186 doc id 13453 rev 4 table 49. idmanuf register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 50. idchip register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 51. idmem register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 52. idprog register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 53. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 54. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 55. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 56. package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 57. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 58. flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 59. flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 60. a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 61. a/d converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 62. on-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 63. internal pll divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 64. pll characteristics (v dd = 5v 10%, v ss =0v, t a = -40c to +125c) . . . . . . . . . . . . 157 table 65. main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 66. main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 67. 32 khz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 68. minimum values of negative resistance (module) for 32 khz oscillator . . . . . . . . . . . . . . 159 table 69. external clock drive xtal1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 70. memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 71. multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 72. demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 73. clkout and ready timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 74. external bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 75. ssc master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 76. ssc slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 77. pqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 78. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 79. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 80. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
st10f273m list of figures doc id 13453 rev 4 9/186 list of figures figure 1. st10f273m logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. st10f273m memory mapping (xadrs3 = 800bh - reset value) . . . . . . . . . . . . . . . . . . . 25 figure 5. st10f273m memory mapping (xadrs3 = e009h - user programmed value) . . . . . . . . . 26 figure 6. flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7. write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 8. cpu block diagram (mac unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 9. mac unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 10. x-interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 11. block diagram of gpt1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 12. block diagram of gpt2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 13. block diagram of pwm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 14. connection to single can bus via separate can transceivers . . . . . . . . . . . . . . . . . . . . . 79 figure 15. connection to single can bus via common can transceivers. . . . . . . . . . . . . . . . . . . . . . 79 figure 16. connection to two different can buses (for example for gateway application) . . . . . . . . . 80 figure 17. connection to one can bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 80 figure 18. asynchronous power-on reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 19. asynchronous power-on reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 20. asynchronous hardware reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 21. asynchronous hardware reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 22. synchronous short / long hard ware reset (ea = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 23. synchronous short / long hard ware reset (ea = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 24. synchronous long hardware reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 25. synchronous long hardware reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 26. sw / wdt unidirectional reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 27. sw / wdt unidirectional reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 28. sw / wdt bidirectional reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 29. sw / wdt bidirectional reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 30. sw / wdt bidirectional reset (ea = 0) follo wed by a hw reset . . . . . . . . . . . . . . . . 101 figure 31. minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 32. system reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 33. internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 34. example of software or watchdog bidirectional reset (ea = 1) . . . . . . . . . . . . . . . . . . . . . 104 figure 35. example of software or watchdog bidirectional reset (ea = 0) . . . . . . . . . . . . . . . . . . . . . 105 figure 36. port0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 37. external rc circuitry on rpd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 38. port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 39. supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . 137 figure 40. a/d conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 41. a/d converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 42. charge-sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 43. anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 44. input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 45. float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 46. generation mechanisms for the cpu clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 47. st10f273m pll jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 48. crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
list of figures st10f273m 10/186 doc id 13453 rev 4 figure 49. 32 khz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 50. external clock drive xtal1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 51. external memory cycle: multiplexed bus, with/ without read/ write delay, normal ale. . . 163 figure 52. external memory cycle: multiplexed bus, with/ without read/ write delay, extended ale. 164 figure 53. external memory cycle: multiplexed bu s, with/ without read/ wr ite delay, normal ale, read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 54. external memory cycle: multiplexed bus, with/ without read/ write delay, extended ale, read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 55. external memory cycle: demultiplexed bus, with/ without read/ write delay, normal ale. 169 figure 56. external memory cycle: demultiplexed bus, with/ without read/ write delay, extended ale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 57. external memory cycle: demultiplexed bus, with/ without read/ write delay, normal ale, read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 58. external memory cycle: demultiplexed bus, without read/ write delay, extended ale, read/ write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 59. clkout and ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 60. external bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 figure 61. external bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 figure 62. ssc master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 63. ssc slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 64. pqfp144 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1 figure 65. lqfp144 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 83
st10f273m introduction doc id 13453 rev 4 11/186 1 introduction 1.1 description the st10f273m device is a new derivative of the stmicroelectronics ? st10 family of 16-bit single-chip cmos microcontrollers. the st10f273m combines high cpu performance (up to 20 million instructions per second) with high peripheral functionalit y and enhanced i/o capabilities. it also provides on-chip high-speed single voltage flash memory, on-c hip high-speed ram, and clock generation via pll. the st10f273m is processed in 0.18mm cmos technology. the mcu core and the logic is supplied with a 5v to 1.8v on-chip voltage regulator. the part is supplied with a single 5v supply and i/os work at 5v. the st10f273m is an optimized version of the st10f273e, upward compatible with the following set of differences: maximum cpu frequency is 40 mhz a single bank of iflash has been implemented but the programming interface has been kept compatible with the st10f273e identification registers: the idmem register reflects the flash type difference and allows to differentiate the two devices by software improved emc behavior thanks to the introduction of an internal rc filter on the 5v for the ballast transistors the clock to the x-peripherals is gated: x-pe ripheral not used will not get the clock in order to reduce the power consumption. 1.2 special characteristics 1.2.1 x-peripheral clock gating this new feature have been implemented on the st10f273m: once the einit instruction has been executed, only the x-peripheral s enabled in the xpercon register will be clocked. the new feature allows to reduce the power consumption and also should improve the emissions as it avoids to propagate us eless clock signals across the device. 1.2.2 improved supply ring an rc filter has been introduced in the 5v power supply ring of the ballast transistor. in addition, the supply rings for the internal voltage regulators and the ios have been split. these two modifications should improve the behavior of the device regarding conducted emissions.
introduction st10f273m 12/186 doc id 13453 rev 4 figure 1. st10f273m logic symbol ;7$/ 567,1 ;7$/ 567287 10, ($ 9 67%< 5($'< $/( 5' :5 :5/ 3ruw elw 3ruw el w 3ruw el w 3ruw e lw 3ruw e lw 3ruw e lw 3ruw e lw 9 '' 9 66 3ruw el w 3ruw el w 9 $5() 9 $*1' 67)0 9 ;7$/ ;7$/ 53' ("1($'5
st10f273m pin data doc id 13453 rev 4 13/186 2 pin data figure 2. pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p6.0 / cs0 p6.1 / cs1 p6.2 / cs2 p6.3 / cs3 p6.4 / cs4 p6.5 / hold / sclk1 p6.6 / hlda / mtsr1 p6.7 / breq / mrst1 p8.0 / xpout0 / cc16io p8.1 / xpout1 / cc17io p8.2 / xpout2 / cc18io p8.3 / xpout3 / cc19io p8.4 / cc20io p8.5 / cc21io p8.6 / rxd1 / cc22io p8.7 / txd1 / cc23io vdd vss p7.0 / pout0 p7.1 / pout1 p7.2 / pout2 p7.3 / pout3 p7.4 / cc28io p7.5 / cc29io p7.6 / cc30io p7.7 / cc31io p5.0 / an0 p5.1 / an1 p5.2 / an2 p5.3 / an3 p5.4 / an4 p5.5 / an5 p5.6 / an6 p5.7 / an7 p5.8 / an8 p5.9 / an9 p0h.0 / ad8 p0l.7 / ad7 p0l.6 / ad6 p0l.5 / ad5 p0l.4 / ad4 p0l.3 / ad3 p0l.2 / ad2 p0l.1 / ad1 p0l.0 / ad0 ea / vstby ale ready wr /wrl rd vss vdd p4.7 / a23 / can2_txd / sda p4.6 / a22 / can1_txd / can2_txd p4.5 / a21 / can1_rxd / can2_rxd p4.4 / a20 / can2_rxd / scl p4.3 / a19 p4.2 / a18 p4.1 / a17 p4.0 / a16 rpd vss vdd p3.15 / clkout p3.13 / sclk0 p3.12 / bhe / wrh p3.11 / rxd0 p3.10 / txd0 p3.9 / mtsr0 p3.8 / mrst0 p3.7 / t2in p3.6 / t3in varef vagnd p5.10 / an10 / t6eud p5.11 / an11 / t5eud p5.12 / an12 / t6in p5.13 / an13 / t5in p5.14 / an14 / t4eud p5.15 / an15 / t2eud vss vdd p2.0 / cc0io p2.1 / cc1io p2.2 / cc2io p2.3 / cc3io p2.4 / cc4io p2.5 / cc5io p2.6 / cc6io p2.7 / cc7io vss v18 p2.8 / cc8io / ex0in p2.9 / cc9io / ex1in p2.10 / cc10io / ex2in p2.11 / cc11io / ex3in p2.12 / cc12io / ex4in p2.13 / cc13io / ex5in p2.14 / cc14io / ex6in p2.15 / cc15io / ex7in / t7in p3.0 / t0in p3.1 / t6out p3.2 / capin p3.3 / t3out p3.4 / t3eud p3.5 / t4in vss vdd xtal4 xtal3 nmi rstout rstin vss xtal1 xtal2 vdd p1h.7 / a15 / cc27i p1h.6 / a14 / cc26i p1h.5 / a13 / cc25i p1h.4 / a12 / cc24i p1h.3 / a11 p1h.2 / a10 p1h.1 / a9 p1h.0 / a8 vss vdd p1l.7 / a7 / an23 p1l.6 / a6 / an22 p1l.5 / a5 / an21 p1l.4 / a4 / an20 p1l.3 / a3 / an19 p1l.2 / a2 / an18 p1l.1 / a1 / an17 p1l.0 / a0 / an16 p0h.7 / ad15 p0h.6 / ad14 p0h.5 / ad13 p0h.4 / ad12 p0h.3 / ad11 p0h.2 / ad10 p0h.1 / ad9 vss vdd st10f273m
pin data st10f273m 14/186 doc id 13453 rev 4 table 1. pin description symbol pin type function p6.0 - p6.7 1 - 8 i/o 8-bit bidirectional i/o port, bit-wise prog rammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 6 outputs ca n be configured as push-pull or open drain drivers. the input threshold of po rt 6 is selectable (ttl or cmos). the following port 6 pins have alternate functions: 1op6.0cs0 chip select 0 output ... ... ... ... ... 5op6.4cs4 chip select 4 output 6 ip6.5hold external master hold request input i/o sclk1 ssc1: master clock output / slave clock input 7 o p6.6 hlda hold acknowledge output i/o mtsr1 ssc1: master-transmi tter / slave-receiver o/i 8 op6.7 breq bus request output i/o mrst1 ssc1: master-receiver / slave-transmitter i/o p8.0 - p8.7 9-16 i/o 8-bit bidirectional i/o port, bit-wise prog rammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 8 outputs ca n be configured as push-pull or open drain drivers. the input threshold of port 8 is selectable (ttl or cmos). the following port 8 pins have alternate functions: 9 i/o p8.0 cc16io capcom2: cc16 c apture input / compare output o xpwm0 pwm1: channel 0 output ... ... ... ... ... 12 i/o p8.3 cc19io capcom2: cc19 c apture input / compare output o xpwm0 pwm1: channel 3 output 13 i/o p8.4 cc20io capcom2: cc20 c apture input / compare output 14 i/o p8.5 cc21io capcom2: cc21 c apture input / compare output 15 i/o p8.6 cc22io capcom2: cc22 c apture input / compare output i/o rxd1 asc1: data input (asynch ronous) or i/o (synchronous) 16 i/o p8.7 cc23io capcom2: cc23 c apture input / compare output o txd1 asc1: clock / data output (asynchronous/synchronous)
st10f273m pin data doc id 13453 rev 4 15/186 p7.0 - p7.7 19-26 i/o 8-bit bidirectional i/o port, bit-wise prog rammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 7 outputs ca n be configured as push-pull or open drain drivers. the input threshold of port 7 is selectable (ttl or cmos). the following port 7 pins have alternate functions: 19 o p7.0 pout0 pwm0: channel 0 output ... ... ... ... ... 22 o p7.3 pout3 pwm0: channel 3 output 23 i/o p7.4 cc28io capcom2: cc28 c apture input / compare output ... ... ... ... ... 26 i/o p7.7 cc31io capcom2: cc31 c apture input / compare output p5.0 - p5.9 p5.10 - p5.15 27-36 39-44 i i 16-bit input-only port with schmitt-trigge r characteristics. the pins of port 5 can be the analog input channels (up to 16) for the a/d converter, where p5.x equals anx (analog input channel x), or they ar e timer inputs. the input threshold of port 5 is selectable (ttl or cmos). the following port 5 pins have alternate functions: 39 i p5.10 t6eud gpt2: timer t6 external up/down control input 40 i p5.11 t5eud gpt2: timer t5 external up/down control input 41 i p5.12 t6in gpt2: timer t6 count input 42 i p5.13 t5in gpt2: timer t5 count input 43 i p5.14 t4eud gpt1: timer t4 external up/down control input 44 i p5.15 t2eud gpt1: timer t2 external up/down control input p2.0 - p2.7 p2.8 - p2.15 47-54 57-64 i/o 16-bit bidirectional i/o port, bit-wise pr ogrammable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 2 ou tputs can be configured as push-pull or open drain drivers. the input threshold of port 2 is selectable (ttl or cmos). the following port 2 pins have alternate functions: 47 i/o p2.0 cc0io capcom: cc0 capture input/compare output ... ... ... ... ... 54 i/o p2.7 cc7io capcom: cc7 capture input/compare output 57 i/o p2.8 cc8io capcom: cc8 capture input/compare output i ex0in fast external interrupt 0 input ... ... ... ... ... 64 i/o p2.15 cc15io capcom: cc15 capture input/compare output i ex7in fast external interrupt 7 input i t7in capcom2: timer t7 count input table 1. pin description (continued) symbol pin type function
pin data st10f273m 16/186 doc id 13453 rev 4 p3.0 - p3.5 p3.6 - p3.13, p3.15 65-70, 73-80, 81 i/o i/o i/o 15-bit (p3.14 is missing) bidirectional i/o port, bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port 3 outputs can be configured as push-pull or open drain driv ers. the input threshold of port 3 is selectable (ttl or cmos). the following port 3 pins have alternate functions: 65 i p3.0 t0in capcom1: timer t0 count input 66 o p3.1 t6out gpt2: timer t6 toggle latch output 67 i p3.2 capin gpt2: register caprel capture input 68 o p3.3 t3out gpt1: timer t3 toggle latch output 69 i p3.4 t3eud gpt1: timer t3 external up/down control input 70 i p3.5 t4in gpt1; timer t4 input for count/gate/reload/capture 73 i p3.6 t3in gpt1: timer t3 count/gate input 74 i p3.7 t2in gpt1: timer t2 input for count/gate/reload / capture 75 i/o p3.8 mrst0 ssc0: master-receiver/slave-transmitter i/o 76 i/o p3.9 mtsr0 ssc0: master-transmitter/slave-receiver o/i 77 o p3.10 txd0 asc0: clock / data output (asynchronous/synchronous) 78 i/o p3.11 rxd0 asc0: data input (a synchronous) or i/o (synchronous) 79 o p3.12 bhe external memory high byte enable signal wrh external memory high byte write strobe 80 i/o p3.13 sclk0 ssc0: master clock output / slave clock input 81 o p3.15 clkout system clock output (programmable divider on cpu clock) table 1. pin description (continued) symbol pin type function
st10f273m pin data doc id 13453 rev 4 17/186 p4.0 ?p4.7 85-92 i/o port 4 is an 8-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. the input threshold is selectable (ttl or cmos). port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open drain drivers. in case of an external bus configuration, port 4 can be used to output the segment address lines: 85 o p4.0 a16 segment address line 86 o p4.1 a17 segment address line 87 o p4.2 a18 segment address line 88 o p4.3 a19 segment address line 89 o p4.4 a20 segment address line i can2_rxd can2: receive data input i/o scl i 2 c interface: serial clock 90 o p4.5 a21 segment address line i can1_rxd can1: receive data input i can2_rxd can2: receive data input 91 o p4.6 a22 segment address line o can1_txd can1: transmit data output o can2_txd can2: transmit data output 92 o p4.7 a23 most significant segment address line o can2_txd can2: transmit data output i/o sda i 2 c interface: serial data rd 95 o external memory read strobe. rd is activated for every external instruction or data read access. wr /wrl 96 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in the syscon register for mode selection. ready/ ready 97 i ready input. the active level is programmable. when the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitst ate cycles until the pin returns to the selected active level. ale 98 o address latch enable output. in case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. table 1. pin description (continued) symbol pin type function
pin data st10f273m 18/186 doc id 13453 rev 4 ea / v stby 99 i external access enable pin. a low level applied to this pin during and after reset forces the st10f273m to start the program from the external memory space. a high level forces st10f273m to start in the internal memory space. this pin is also used (when standby mode is entered, that is st10f273m under reset and main v dd turned off) to bias the 32 khz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8v supply for the rtc module (when not disabled) and to retain data inside the standby portion of the xram (16 kbyte). it can range from 4.5 to 5.5v (6v for a reduced amount of time during the device life, 4.0v when rtc and 32 khz on-chip oscillator amplifier are turned off). in running mode, this pin can be tied low during reset without affecting 32 khz oscillator, rtc and xram activities, since the presence of a stable v dd guarantees the proper biasing of all those modules. p0l.0 -p0l.7, p0h.0 p0h.1 - p0h.7 100-107, 108, 111-117 i/o two 8-bit bidirectional i/o ports p0l and p0h, bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. the input threshold of port 0 is selectable (ttl or cmos). in case of an external bus configuratio n, port0 serves as the address (a) and as the address / data (ad) bus in mult iplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes multiplexed bus modes p1l.0 - p1l.7 p1h.0 - p1h.7 118-125 128-135 i/o two 8-bit bidirectional i/o ports p1l and p1h, bit-wise programmable for input or output via direction bit. programming an i/o pin as input forces the corresponding output driver to high impedance state. port1 is used as the 16- bit address bus (a) in demultiplexed bus modes: if at least busconx is configured such the demultiplexed mode is selected, the pis of port1 are not available for general purpose i/o function. the input threshold of port 1 is selectable (ttl or cmos). the pins of p1l also serve as the additional (up to 8) analog input channels for the a/d converter, where p1l.x equals any (analog input channel y, where y = x + 16). this additional function have higher priority on demultiplexed bus function. the following port1 pins have alternate functions: 132 i p1h.4 cc24io capcom2: cc24 capture input 133 i p1h.5 cc25io capcom2: cc25 capture input 134 i p1h.6 cc26io capcom2: cc26 capture input 135 i p1h.7 cc27io capcom2: cc27 capture input table 1. pin description (continued) symbol pin type function data path width 8-bit 16-bit p0l.0 ? p0l.7: d0 ? d7 d0 - d7 p0h.0 ? p0h.7: i/o d8 - d15 data path width 8-bit 16-bit p0l.0 ? p0l.7: ad0 ? ad7 ad0 - ad7 p0h.0 ? p0h.7: a 8 ? a15 a d8 - ad15
st10f273m pin data doc id 13453 rev 4 19/186 xtal1 138 i xtal1 main oscillator amplifier circuit and/or external clock input. xtal2 137 o xtal2 main oscillator amplifier circuit output. to clock the device from an external source, drive xtal1 while leaving xtal2 unconnected. minimum and maximum high / low and rise / fall times specified in the ac characteristics must be observed. xtal3 143 i xtal3 32 khz oscillator amplifier circuit input xtal4 144 o xtal4 32 khz oscillator amplifier circuit output when 32 khz oscillator amplifier is not used, to avoid spurious consumption, xtal3 shall be tied to ground while xtal4 shall be left open. besides, bit off32 in rtccon register shall be set. 32 khz oscillator can only be driven by an external crystal, and not by a different clock source. rstin 140 i reset input with cmos schmitt- trigger characteristics. a low level at this pin for a specified duration while the oscillator is running resets the st10f273m. an internal pull-up resistor permits power-on reset using only a capacitor connected to v ss . in bidirectional reset mode (enabled by setting bit bdrsten in syscon register), the rstin line is pulled low for the duration of the internal reset sequence. rstout 141 o internal reset indication output. this pin is driven to a low level during hardware, software or watchdog timer reset. rstout remains low until the einit (end of initialization) in struction is executed. nmi 142 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. if bit pwdcfg = ?0? in syscon register, when the pwrdn (power down) instru ction is executed, the nmi pin must be low in order to force the st10f273m to go into power down mode. if nmi is high and pwdcfg = ?0?, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. v aref 37 - a/d converter reference voltage and analog supply v agnd 38 - a/d converter reference and analog ground rpd 84 - timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection. v dd 17, 46, 72,82,93, 109, 126, 136 - digital supply voltage = + 5v during normal operation, idle and power down modes. it can be turned off when standby ram mode is selected. v ss 18,45, 55,71, 83,94, 110, 127, 139 - digital ground v 18 56 - 1.8v decoupling pin: a decoupling capacit or (typical value of 10nf, max 100nf) must be connected between this pin and nearest v ss pin. table 1. pin description (continued) symbol pin type function
functional description st10f273m 20/186 doc id 13453 rev 4 3 functional description the architecture of the st10f273m combines advantages of both risc and cisc processors and an advanced peripheral subsystem. the block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the st10f273m. figure 3. block diagram ([whuqdoexv frqwuroohu elw$'& *37 *37 $6& %5* %5* 66& 3:0 &$3&2 0 &$3&2 0 3ruw 3ruw 3ruw 3ruw 3ruw &38fruhdqg0$&xqlw ;&$1 ;66& ;$6& ;&$1 ;,& ;5 $0 . ;5$0 . . 67%< 3 (& ,)odvk . 3(& ,qwhuuxswfrqwuroohu 3ruw 3ruw 3ruw :dwfkgrj ,5$0 . ;57& 2vfloodwru 3// 99 yrowdjh uhjxodwru 3ruw n+] rvflood wru ;3:0 ("1($'5
st10f273m memory organization doc id 13453 rev 4 21/186 4 memory organization the memory space of the st10f273m is configured in a unified memory architecture. code memory, data memory, registers and i/o ports are organized within the same linear address space of 16 mbytes. the entire memory space can be accessed bytewise or wordwise. particular portions of the on-chip memory have additionally been made directly bit addressable. iflash : 512 kbytes of on-chip flash memory implemented as a unique bank (bank0). bank0 is divided in 12 blocks (b0f0...b0f11). note: read-while-write operations are not allowed: write commands must be executed from a non iflash memory area (on-chip ram or external memory). when bootstrap mode is selected, the test-flash block b0tf (4 kbytes) appears at address 00?0000h: refer to the device user manual for more details on the memory mapping in bootstrap mode . the summary of address range for iflash is the following: note: a single flash bank is implemented on the st10f273m compared to the st10f273e. the last two sectors (b0f10 and b0f11) can be seen as the bank1 of the st10f273e in order to maintain the compatibility with the existing flash programming drivers. for this, the control and status bit of the blocks b0f10 and b0f11 have been duplicated to be usable as blocks b1f0 and b1f1 of the st10f273e. xflash / flash control registers: address range 0e?0000h-0e?ffffh is reserved for the flash control register and other internal service memory space used by the flash program/erase controller. xflashen bit in xpercon register must be set to access the flash control register. note that when flash control registers are not accessible, no program/erase operations are possible. the flash control registers are accessed in 16-bit demultiplexed bus-mode without read/write delay. byte and word accesses are allowed. table 2. summary of iflash address range blocks user mode size (bytes) b0tf not visible 4 k b0f0 00?0000h - 00?1fffh 8 k b0f1 00?2000h - 00?3fffh 8 k b0f2 00?4000h - 00?5fffh 8 k b0f3 00?6000h - 00?7fffh 8 k b0f4 01?8000h - 01?ffffh 32 k b0f5 02?0000h - 02?ffffh 64 k b0f6 03?0000h - 03?ffffh 64 k b0f7 04?0000h - 04?ffffh 64 k b0f8 05?0000h - 05?ffffh 64 k b0f9 06?0000h - 06?ffffh 64 k b1f0 / b0f10 (1) 07?0000h - 07?ffffh 64 k b1f1 / b0f11 (1) 08?0000h - 08?ffffh 64 k
memory organization st10f273m 22/186 doc id 13453 rev 4 iram : 2 kbytes of on-chip internal ram (dual-port) is provided as a storage for data, system stack, general purpose register banks a nd code. a register bank is 16 wordwide (r0 to r15) and / or bytewide (rl0, rh0, ?, rl7, rh7) general purpose registers group. xram : 34 kbytes of on-chip extension ram (singl e port xram) is provided as a storage for data, user stack and code. the xram is divided into two areas, the first 2 kbytes named xram1 and the second 32 kbytes named xram2, connected to the internal xbus and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (50ns access at 40 mhz cpu clock). by te and word accesses are allowed. the xram1 address range is 00?e000h - 00?e7ffh if xpen (b it 2 of syscon register), and xram1en (bit 2 of xpercon register) are set. if xram1en or xpen is clear ed, then any access in th e address range 00?e000h - 00?e7ffh will be direct ed to external memory interface, using the busconx register corresponding to address matching addrselx register. the xram2 address range is f?0000h - f?7ffffh if xpen (bit 2 of sysc on register), and xram2en (bit 3 of xpercon register) are set. if bit xpen is cleared, then any access in the address range programmed for xram2 will be directed to external memory interface, using the busconx register corresponding to address matching addrselx register. the 16 kbytes lower portion of the xram2 (address range f?0000h - f?3ffffh) represents also the standby ram, which can be maintained biased through ea /v stby pin when the main supply v dd is turned off. as the xram appears like external memory, it cannot be used as system stack or as register banks. the xram is not provided for single bit storage and therefore is not bit addressable. sfr/esfr: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function register (sfr) areas. sfrs are wordwide registers which are used to control and to monitor the function of the different on-chip units. can1 : address range 00?ef00h - 00?efffh is reserved for the can1 module access. the can1 is enabled by setting xpen bit 2 of th e syscon register and by setting can1en bit 0 of the xpercon register. a ccesses to the can module us e demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two wait states give an access time of 100ns at 40 mhz cpu clock. no tri-state wait states are used. can2 : address range 00?ee00h - 00?eeffh is reserved for the can2 module access. the can2 is enabled by setting xpen bit 2 of th e syscon register and by setting can2en bit 1 of the new xpercon register. accesses to the can module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two wait states give an access time of 100ns at 40 mhz cpu clock. no tri-state wait states are used. note: if one or the two can modules are used, port 4 cannot be programmed to output all eight segment address lines. thus, only four segment address lines can be used, reducing the external memory space to 5 mbytes (1 mbyte per cs line). rtc : address range 00?ed00h - 00?edffh is reserved for the rtc module access. the rtc is enabled by setting xpen bit 2 of th e syscon register and bit 4 of the xpercon register. accesses to the rtc module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two waitstat es give an access time of 100ns at 40 mhz cpu clock. no tristate waitstate is used.
st10f273m memory organization doc id 13453 rev 4 23/186 pwm1 : address range 00?ec00h - 00?ecffh is reserved for the pwm1 module access. the pwm1 is enabled by sett ing xpen bit 2 of the syscon register and bit 6 of the xpercon register. accesses to the pwm1 mo dule use demultiplexed addresses and a 16- bit data bus (only word accesses are possible). two waitstates give an access time of 100ns at 40 mhz cpu clock. no tristate waitstat e is used. only word access is allowed. asc1 : address range 00?e900h - 00?e9ffh is reserved for the asc1 module access. the asc1 is enabled by setting xpen bit 2 of t he syscon register and bit 7 of the xpercon register. accesses to the asc1 module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two waitstat es give an access time of 100ns at 40 mhz cpu clock. no tristate waitstate is used. ssc1 : address range 00?e800h - 00?e8ffh is reserved for the ssc1 module access. the ssc1 is enabled by setting xpen bit 2 of t he syscon register and bit 8 of the xpercon register. accesses to the ssc1 module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two waitstat es give an access time of 100ns at 40 mhz cpu clock. no tristate waitstate is used. i2c : address range 00?ea00h - 00?eaffh is reserved for the i2c module access. the i2c is enabled by setting xpen bit 2 of the syscon register and bit 9 of the xpercon register. accesses to the i2c module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two waitstates give an access time of 100ns at 40 mhz cpu clock. no tristate waitstate is used. x-miscellaneous: address range 00?eb00h - 00?ebffh is reserved for the access to a set of xbus additional features. they are enab led by setting xpen bit 2 of the syscon register and bit 10 of the xpercon register. accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). two waitstates give an access time of 100ns at 40 mhz cpu clock. no tristate waitstate is used. the following set of features are provided: clkout programmable divider xbus interrupt management registers adc multiplexing on p1l register port1l digital disable register for extra adc channels can2 multiplexing on p4.5/p4.6 can1-2 main clock prescaler main voltage regulator disable for power-down mode ttl / cmos threshold selection for port0, port1 and port5 in order to meet the needs of designs where more memory is required than is provided on chip, up to 16 mbytes of external memory can be connected to the microcontroller. visibility of xbus peripherals in order to keep the st10f273m compatible with the st10f168 / st10f269, the xbus peripherals can be selected to be visible on the external address / data bus. different bits for x-peripheral enabling in xpercon register must be set. if these bits are cleared before the global enabling with xpen bit in syscon register , the corresponding a ddress space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. refer to chapter 23: register set on page 115 .
memory organization st10f273m 24/186 doc id 13453 rev 4 xpercon and x-peripheral clock gating as already mentioned, the xpercon register must be programmed to enable the single xbus modules separately. the xpercon is a read/write esfr register. the new feature of clock gating has been implemented by means of this register: once the einit instruction has been executed, all the peripherals (except rams and xmisc) not enabled in the xpercon register are not be clocked. the clock gating can reduce power consumption and improve emi when the user does not use all x-peripherals. note: when the clock has been gated in the disabled peripherals , no reset will be raised once the einit instruction has been executed.
st10f273m memory organization doc id 13453 rev 4 25/186 figure 4. st10f273m memory mapping (xadrs3 = 800bh - reset value) ext. mem b0f3 ext. mem reserved b3f1 (xflash) (xflash) b2f2 xssc xasc xi2c xpwm xi2c xasc xssc ff ffff 00 0000 16 mb 255 0 code data page 1023 0 data page 1 3 5 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 07 ffff 06 0000 05 ffff 04 0000 03 ffff 02 0000 01 ffff 00 0000 b0f4 b0f5 b0f8 b0f11 00 c000 00 ffff xcan1 esfr sfr i-ram reserved ext. memory 00 dfff 00 e000 00 e7ff 00 e800 00 fdff 00 fe00 00 f1ff 00 f200 00 f5ff 00 f600 8k 256 512 1k 2k 512 data page 3 (segment 0) - 16kbyte 256 xcan2 9 20 21 22 23 0a 0000 09 ffff 08 0000 11 24 25 26 27 0c 0000 0b ffff 13 28 29 30 31 0e 0000 0d ffff 15 32 33 34 35 0f ffff 00 f000 xcan1 xcan2 00 efff 00 f000 00 eeff 00 ef00 00 edff 00 ee00 00 eaff 00 eb00 256 256 256 256 00 e7ff 00 e800 xram1 2k 14 0f 0000 0e ffff 12 0d 0000 0c ffff 10 0b 0000 0a ffff 8 6 4 05 0000 04 ffff 07 0000 06 ffff 09 0000 08 ffff 2 03 0000 02 ffff 0 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 b0f6 b0f9 b0f10 b2f1 b0f7 01 0000 00 ffff xram2 32k b3f0 code segment 64 65 66 67 64 65 66 67 16 17 10 0000 10 ffff 11 0000 11 ffff flash + xram - 1mbyte flash xrtc 00 efff (xflash) (xflash) 256 256 256 xrtc 256 256 00 e8ff 00 e900 00 e9ff 00 ea00 (standby) 256 00 ecff 00 ed00 256 256 xpwm 256 256 00 ebff 00 ec00 xmiscellaneous xmiscellaneous x-peripherals (2kbyte) segment xadrs3 = 800bh (512k - default) reserved b2f0 (xflash) reserved reserved reserved reserved 64k address area defined by xadrs3 by default after reset (b1f0) (b1f1) control registers b0f2 b0f1 b0f0
memory organization st10f273m 26/186 doc id 13453 rev 4 figure 5. st10f273m memory mapping (xadrs3 = e009h - user programmed value ) xssc xasc xi2c xpwm xi2c xasc xssc ff ffff 00 0000 16 mb 255 0 code data page 1023 0 data page 1 3 5 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 07 ffff 06 0000 05 ffff 04 0000 03 ffff 02 0000 01 ffff 00 0000 b0f4 b0f5 b0f8 b0f11 00 c000 00 ffff xcan1 esfr sfr i-ram reserved ext. memory 00 dfff 00 e000 00 e7ff 00 e800 00 fdff 00 fe00 00 f1ff 00 f200 00 f5ff 00 f600 8k 256 512 1k 2k 512 data page 3 (segment 0) - 16kbyte 256 xcan2 9 20 21 22 23 0a 0000 09 ffff 08 0000 11 24 25 26 27 0c 0000 0b ffff 13 28 29 30 31 0e 0000 0d ffff 15 32 33 34 35 0f ffff 00 f000 xcan1 xcan2 00 efff 00 f000 00 eeff 00 ef00 00 edff 00 ee00 00 eaff 00 eb00 256 256 256 256 00 e7ff 00 e800 xram1 2k 14 0f 0000 0e ffff 12 0d 0000 0c ffff 10 0b 0000 0a ffff 8 6 4 05 0000 04 ffff 07 0000 06 ffff 09 0000 08 ffff 2 03 0000 02 ffff 0 0 b0f3 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 b0f6 b0f9 b0f10 b0f7 01 0000 00 ffff xram2 32k code segment 64 65 66 67 64 65 66 67 16 17 10 0000 10 ffff 11 0000 11 ffff flash + xram - 1mbyte flash xrtc 00 efff 256 256 256 xrtc 256 256 00 e8ff 00 e900 00 e9ff 00 ea00 (standby) 256 00 ecff 00 ed00 256 256 xpwm 256 256 00 ebff 00 ec00 xmiscellaneous xmiscellaneous x-peripherals (2kbyte) segment xadrs3 = e009h reserved 64k address area defined by xadrs3 after reprogramming note: e009h defines a 128k wide window starting from 0e?0000h (b1f0) (b1f1) control registers 32k ext memory b0f2 b0f1 b0f0 ext mem ext mem
st10f273m internal flash memory doc id 13453 rev 4 27/186 5 internal flash memory 5.1 overview the on-chip flash is composed of one matrix module of one bank of 512 kbytes, named bank0, that can be read and modified. this module is called iflash because it is on the st10 internal bus. figure 6. flash structure the programming operations of the flash are managed by an embedded flash program/erase controller (fpec). the high voltages needed for program/erase operations are generated internally. the data bus is 32-bit wide for fetch accesses to iflash. read/write accesses to iflash control registers area are 16-bit wide. 5.2 functional description 5.2.1 structure ta bl e 3 below shows the address space reserved for the flash module. 5.2.2 module structure the iflash module is composed of a bank (bank 0) of 512 kbytes of program memory divided in 12 sectors (b0f0...b0f11). bank 0 also contains a reserved sector named test- flash. %dqn.e\wh surjudpphpru\ +9dqg5hi jhqhudwru 3urjudphudvh frqwuroohu ,%86lqwhuidfh .e\wh7hvw)odvk ;%86lqwhuidfh ,)odvk &rqw uro6hfwl rq )odvkfrqwuro uhjlvwhuv ("1($'5 table 3. flash module address space description addresses size iflash sectors 0x00 0000 to 0x08 ffff 512 kbytes registers and flash internal reserved area 0x0e 0000 to 0x0e ffff 64 kbytes
internal flash memory st10f273m 28/186 doc id 13453 rev 4 the addresses from 0x0e 0000 to 0x0e ffff are reserved for the control register interface and other internal service memory space used by the flash program/erase controller. the following tables show the memory mapping of the flash when it is accessed in read mode ( table 4: flash module sectorization (read operations) ), and when accessed in write or erase mode ( table 5: flash module sectorization (write operations, or roms1 = ?1?) ). note: with this second mapping, the first four sectors are remapped into code segment 1 (same as obtained setting bit roms1 in syscon register). table 4. flash module sectorization (read operations) bank description addresses size (bytes) b0 bank 0 flash 0 (b0f0) 0x00 0000 - 0x00 1fff 8 k bank 0 flash 1 (b0f1) 0x00 2000 - 0x00 3fff 8 k bank 0 flash 2 (b0f2) 0x00 4000 - 0x00 5fff 8 k bank 0 flash 3 (b0f3) 0x00 6000 - 0x00 7fff 8 k bank 0 flash 4 (b0f4) 0x01 8000 - 0x01 ffff 32 k bank 0 flash 5 (b0f5) 0x02 0000 - 0x02 ffff 64 k bank 0 flash 6 (b0f6) 0x03 0000 - 0x03 ffff 64 k bank 0 flash 7 (b0f7) 0x04 0000 - 0x04 ffff 64 k bank 0 flash 8 (b0f8) 0x05 0000 - 0x05 ffff 64 k bank 0 flash 9 (b0f9) 0x06 0000 - 0x06 ffff 64 k bank 0 flash 10 (b0f10 / b1f0) (1) 1. a single bank is implemented but the last two sector s can be seen as a bank 1 in order to maintain compatibility with the flash programming routi nes developed for the st10f273e (based on st10f276e). this means that the control and status flags for t he blocks b0f10 and b0f11 are duplicated to also be accessible as blocks b1f0 and b1f1. 0x07 0000 - 0x07 ffff 64 k bank 0 flash 11 (b0f11 / b1f1) (1) 0x08 0000 - 0x08 ffff 64 k
st10f273m internal flash memory doc id 13453 rev 4 29/186 ta bl e 5 above refers to the configuration when bit roms1 of syscon register is set. when bootstrap mode is entered: test-flash is seen and available fo r code fetches (address 0x00 0000) user iflash is only availabl e for read and write accesses write accesses must be made with addresses starting in segment 1 from 0x01 0000, whatever roms1 bit in syscon value read accesses are made in segment 0 or in segment 1 depending of roms1 value. in bootstrap mode, by default roms1 = 0, so the first 32 kbytes of iflash are mapped in segment 0. example 1: in default configuration, to program address 0, the user must put the value 0x01 0000 in the farl and farh registers but to verify the content of the address 0, a read to 0x00 0000 must be performed. the next ta bl e 6 shows the control register interface composition: this set of registers can be addressed by the cpu . table 5. flash module sectorization (write operations, or roms1 = ?1?) bank description addresses size (bytes) b0 bank 0 test-flash (b0tf) 0x00 0000 - 0x00 0fff 4 k bank 0 flash 0 (b0f0) 0x01 0000 - 0x01 1fff 8 k bank 0 flash 1 (b0f1) 0x01 2000 - 0x01 3fff 8 k bank 0 flash 2 (b0f2) 0x01 4000 - 0x01 5fff 8 k bank 0 flash 3 (b0f3) 0x01 6000 - 0x01 7fff 32 k bank 0 flash 4 (b0f4) 0x01 8000 - 0x01 ffff 64 k bank 0 flash 5 (b0f5) 0x02 0000 - 0x02 ffff 64 k bank 0 flash 6 (b0f6) 0x03 0000 - 0x03 ffff 64 k bank 0 flash 7 (b0f7) 0x04 0000 - 0x04 ffff 64 k bank 0 flash 8 (b0f8) 0x05 0000 - 0x05 ffff 64 k bank 0 flash 9 (b0f9) 0x06 0000 - 0x06 ffff 64 k bank 0 flash 10 (b0f10 / b1f0) (1) 1. a single bank is implemented but the last two sector s can be seen as a bank 1 in order to maintain compatibility with the flash programming routi nes developed for the st10f273e (based on st10f276e). this means that the control and status flags for t he blocks b0f10 and b0f11 are duplicated to also be accessible as blocks b1f0 and b1f1. 0x07 0000 - 0x07 ffff 64 k bank 0 flash 11 (b0f11 / b1f1) (1) 0x08 0000 - 0x08 ffff 8 k
internal flash memory st10f273m 30/186 doc id 13453 rev 4 note: fvwpir-mirror is a mirror of the fvwpir to maintain software compatibility with the st10f273e in the handling of the last two blocks b0f10/b1f0 and b0f11/b1f1. xficr is a dummy register that can be re ad and written (for compatibility with the st10f273e) but its content has no effect on the xbus timings. 5.2.3 low power mode the flash module is automatically switc hed off executing pw rdn instruction. the consumption is drastically reduced, but exiting this state can require a long time (t pd ). recovery time from power-down mode for the flash modules is anyway shorter than the main oscillator start-up time. to avoid any problem in restarting to fetch code from the flash, it is important to size properly the external circuit on rpd pin. note: pwrdn instruction must not be executed while a flash program/erase operation is in progress. 5.3 write operation the flash module has a single register interface mapped in the xbus memory space 0x0e 0000 - 0x0e 0015. all the operations are enabled through four 16-bit control registers: flash control register 1-0 high/low (fcr1h/l-fcr0h/l). eight other 16-bit registers are used to store flash address and data for program operations (farh/l and fdr1h/l- fdr0h/l) and write operation error flags (fer). all registers are accessible with 8- and 16-bit instructions (since they are mapped on the xbus). note: to have access to the flash control regist ers used for program/erasing operations, bit 5 (xflashen) in xpercon re gister must be set. table 6. flash control registers summary name description addresses size bus size fcr1 - 0 flash control registers 1 - 0 high & low 0x0e 0000 - 0x0e 0007 8 byte 16-bit (xbus) fdr1 - 0 flash data registers 1 - 0 high & low 0x0e 0008 - 0x0e 000f 8 byte far flash address registers 0x0e 0010 - 0x0e 0013 4 byte fer flash error register 0x0e 0014 - 0x0e 0015 2 byte fvwpir-mirror flash non-volatile protection i registers mirrored 0x0e dfb0 - 0x0e dfb3 4 byte fvwpir flash volatile protection i registers 0x0e dfb4 - 0x0e dfb7 4 byte fvapr0 flash volatile access protection register 0 0x0e dfb8 - 0x0e dfb9 2 byte fvapr1 flash non-volatile access protection register 1 0x0e dfbc - 0x0e dfbf 4 byte xficr xflash interface control register (dummy register) 0x0e e000 - 0x0e e001 2 byte
st10f273m internal flash memory doc id 13453 rev 4 31/186 caution: during a flash write operation any attempt to read the iflash will outp ut the invalid data 009bh (corresponding, for code fetch, to the software trap 009bh). this means that the iflash is not fetchable when a programming operation is active: the write operation commands must be executed from another memory (one of the on-chip rams or some external memory). warning: during a write operation, when bit lock of fcr0 is set, it is forbidden to write into the flash control registers. power supply drop if during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to read mode. at following power-on, the interrupted flash write operation must be repeated. 5.4 flash control re gisters description 5.4.1 flash control register 0 low (fcr0l) the flash control register 0 low (fcr0l), together with the flash control register 0 high (fcr0h), is used to enable and to monitor all the write operations on the iflash. the user has no access in write mode to the test-flash (b0tf). more over, the test-flash block is seen by the user in bootstrap mode only. fcr0l (0x0e 0000) fcr reset value: 0000h 1514131211109876543210 reserved dbsy 1 bsy 0 lock reserved bsy nvr res - rororo - ro - table 7. fcr0l register description bit name function 15:7 - reserved. these bits must be left to their reset value (0). 6 dbsy1 dummy bank1 busy it is a replication of the bsy0 bit: it is set whenever a write operation is on-going. this bit is emulating the bsy1 bit of the st10f273e device. when write operations are on going on b0f10 and/or b0f11 blocks of the st10f273m, this bit will be set in order to indicate that their equivalent b1f0 or b1f1 in the st10f273e are busy.
internal flash memory st10f273m 32/186 doc id 13453 rev 4 5 bsy0 bank0 busy this bits indicate that a write operation is running in the bank0. it is automatically set when bit wms is set. when this bit is set every read access to the bank0 will output invalid data (software trap 009bh), while every write access will be ignored. at the end of the write oper ation or during a program or erase suspend this bit is automatically reset and flash bank returns to read mode. after a program or erase resume this bit is automatically set again. 4lock flash registers access locked when this bit is set, it means that the access to the flash control registers fcr0h/-fcr1h/l, fdr0h/l- fdr1h/l, farh/l and fer is locked by the fpec: any read access to the registers will output invalid data (software trap 009bh) and any write access will be ineffective. lock bit is automatically set when the flash bit wms is set. this is the only bit the user can always a ccess to detect the status of the flash: once it is found low, the rest of fcr0l and all the other flash registers are accessible by the user as well. note that fer content can be read when lock is low, but its content is updated only when also bsyx bits are reset. 3:2 - reserved. these bits must be left to their reset value (0). 1bsynvr busy of non-volatile registers this bit indicate that a write operation is running in the corresponding on ?non- volatile registers?. they are automatically set when bit wms is set. when this bit is set every read access to the iflash will output the value 009bh (software trap), while every write access to the iflash w ill be ignored. at the end of the write operation or during a program suspend this bit is automatically reset and the iflash returns to read mode. after a prog ram this bit is auto matically set again. 0 - reserved. this bit must be left to its reset value (0). table 7. fcr0l register description (continued) bit name function
st10f273m internal flash memory doc id 13453 rev 4 33/186 5.4.2 flash control register 0 high (fcr0h) the flash control register 0 high (fcr0h) together with the flash control register 0 low (fcr0l) is used to enable and to monitor all the write operations on the iflash. the user has no access in write mode to the test-flash (b0tf). more over, the test-flash block is seen by the user in bootstrap mode only. fcr0h (0x0e 0002) fcr reset value: 0000h 1514131211109876543210 wms susp wpg dwpg ser reserved spr ds mod reserved rs rw rw rw rw - rw rw - table 8. fcr0h register description bit name function 15 wms write mode start this bit must be set to start every write operation in the flash module. at the end of the write operation or during a suspend, this bit is automatically reset. to resume a suspended operation, this bit must be set again. it is forbidden to set this bit if bit err of fer is high (the operation is not accepted). it is also forbidden to start a new write (program or erase) operation (by setting wms high) when bit susp of fcr0 is high. resetting this bit by software has no effect. 14 susp suspend this bit must be set to suspend the current program (word or double word) or sector erase operation in order to read data in another part of the flash. the suspend operation resets the bank0 to no rmal read mode (automatically resetting bits bsyx). when in program suspend, the flash module accepts only the following operations: read and program resume. when in erase suspend the module accepts only the following operations: read, erase resume. to resume a suspended operation, the wms bit must be set again, together with the selection bit corresponding to the operation to resume (wpg, dwpg, ser). (1) 13 wpg word program this bit must be set to select the word (32 bits) program operation in the flash module. the word program operation allows to program 0s in place of 1s. the flash address to be programmed must be written in the farh/l registers, while the flash data to be programmed must be written in the fdr0h/l registers before starting the execution by setting bit wms. wpg bit is automatically reset at the end of the word program operation. 12 dwpg double word program this bit must be set to select the double word (64 bits) program operation in the flash module. the double word program operation allows to program 0s in place of 1s. the flash address in which to program (aligned with even words) must be written in the farh/l registers, while the two flash data words to be programmed must be written in the fd r0h/l registers (even word) and fdr1h/l registers (odd word) before starting the execution by setting bit wms. dwpg bit is automatically reset at the end of the double word program operation.
internal flash memory st10f273m 34/186 doc id 13453 rev 4 11 ser sector erase this bit must be set to select the se ctor erase operation . the sector erase operation allows to erase all the flash locations to value 0xffff. from 1 to all of bank0?s sectors (excluding test-flash) can be selected to be erased through bits bxfy of fcr1h/l registers bef ore starting the execution by setting bit wms. it is not necessary to preprogram the sectors to 0, because this is done automatically. ser bit is automatically reset at th e end of the sector erase operation. 10:9 - reserved. this bit must be left to their reset value (0). 8 spr set protection this bit must be set to select the set protection operation. the set protection operation allows to program 0s in place of 1s in the flash non-volatile protection registers. the flash address in which to program must be written in the farh/l registers, while the flash data to be programmed must be written in the fdr0h/l before starting the execution by setting bit wms. a sequence error is flagged by bit seqer of fer if the address written in farh/l is not in the range 0x0e dfb0- 0x0e dfbf. spr bit is automatically reset at th e end of the set protection operation. 7dsmod dummy select module this is a dummy smod bit that is main taining software compatibility with the st10f273e where it must be set before every write operation to the iflash. it has no effect in the st10f273m. 6:0 - reserved. these bits must be kept to their reset value (0). 1. it is forbidden to start a new write operation with bit susp already set. table 8. fcr0h register description (continued) bit name function
st10f273m internal flash memory doc id 13453 rev 4 35/186 5.4.3 flash control register 1 low (fcr1l) the flash control register 1 low (fcr1l), together with flash control register 1 high (fcr1h), is used to select the sectors to erase or during any write operation, to monitor the status of each sector and bank. fcr1l (0x0e 0004) fcr reset value: 0000h 1514131211109876543210 reserved b0f 11 b0f 10 b0f 9 b0f 8 b0f 7 b0f 6 b0f 5 b0f 4 b0f 3 b0f 2 b0f 1 b0f 0 - rsrsrsrsrsrsrsrsrsrsrsrs table 9. fcr1l register description bit name function 15:12 - reserved. these bits must be kept to their default value (0). 11:10 b0f11 b0f10 bank0 iflash sector 11:10 status these bits are a copy of bits b0f10 and b0f11 in fcr1h. it is possible use these bits as well as the bits b0f10/b1f0 and b0f11/b1f1 in fcr1h. to preserve compatibility with the st10f 273e, these bits must be left at their default value ?0? and the fcr1h register must be used. 9:0 b0f9 ... b0f0 bank 0 iflash sector 9:0 status these bits must be set during a sector erase operation to select the sectors to erase in bank 0. besides, during any erase operation, these bits are automatically set and give the status of the first 10 sectors of bank 0 (b0f9- b0f0). the meaning of b0fy bit for sector y of bank 0 is given by ta b l e 1 1 : bank (bxs) and sectors (bxfy) status bits meaning . these bits are automatically reset at the end of a writ e operation if no errors are detected.
internal flash memory st10f273m 36/186 doc id 13453 rev 4 5.4.4 flash control register 1 high (fcr1h) the flash control register 1 high (fcr1h), together with flash control register 1 low (fcr1l), is used to select the sectors to erase or during any write operation, to monitor the status of each sector and bank. fcr1h (0x0e 0006) fcr reset value: 0000h 151413121110 9 8 765432 1 0 reserved db1s b0s reserved b0f11 /b1f1 b0f10 /b1f0 - rs rs - rs rs table 10. fcr1h register description bit name function 15:10 - reserved. these bits must be kept to their default value (0). 9db1s dummy bank1 status this is a replication of b0s bit. in order to maintain compatibility with the st10f273e where operations on the last 2 sectors were flagged in this position. 8b0s bank0 status during any erase operation, this bit is automatically modified and gives the status of the bank 0. the meaning of b0s bit is given in the next table 11: bank (bxs) and sectors (bxfy) status bits meaning . this bit is automatically reset at the end of a erase operation if no errors are detected. 7:2 - reserved. these bits must be kept to their default value (0). 1:0 b0f10/b1f0 b0f11/b1f1 bank0 iflash sector 11:10 status / bank1 iflash sector 1:0 status these bits must be set during a sector erase operation to select the last 2 sectors of bank0. besides, during any erase operation, these bits are automatically set and give the status of the last two sectors of bank0 (b0f11-b0f10). the meaning of b0fy bit for sector y of bank 0 is given by the next table 11: bank (bxs) and sectors (bxfy) status bits meaning . these bits are automatically reset at th e end of a write operation if no errors are detected. note: these bits can also be seen as selecting the two sectors of bank1 for compatibility with the st10f273e. table 11. bank (bxs) and sectors (bxfy) status bits meaning operation bxs = 1 meaning bxfy = 1 meaning erase suspend 1 - erase error erase error in sector y 0 1 erase suspended in bank x erase suspended in sector y of bank x 0 0 don?t care don?t care
st10f273m internal flash memory doc id 13453 rev 4 37/186 5.4.5 flash data register 0 low (fdr0l) during program operations, the flash address registers (farh/l) are used to store the flash address in which to program and the flash data registers (fdr1h/l-fdr0h/l) are used to store the flash data to program. 5.4.6 flash data register 0 high (fdr0h) fdr0l (0x0e 0008) fcr reset value: ffffh 1514131211109876543210 din 15 din 14 din 13 din 12 din 11 din 10 din 9 din 8 din 7 din 6 din 5 din 4 din 3 din 2 din 1 din 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 12. fdr0l register description bit name function 15:0 din[15:0] data input 15:0 these bits must be written with the data to program in flash during the following operations: word program (32-bit), double word program (64-bit) and set protection. fdr0h (0x0e 000a) fcr reset value: ffffh 1514131211109876543210 din 31 din 30 din 29 din 28 din 27 din 26 din 25 din 24 din 23 din 22 din 21 din 20 din 19 din 18 din 17 din 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 13. fdr0h register description bit name function 15:0 din[31:16] data input 31:16 these bits must be written with the data to program in flash during the following operations: word program (32-bit), double word program (64-bit) and set protection.
internal flash memory st10f273m 38/186 doc id 13453 rev 4 5.4.7 flash data register 1 low (fdr1l) 5.4.8 flash data register 1 high (fdr1h) 5.4.9 flash address re gister low (farl) fdr1l (0x0e 000c) fcr reset value: ffffh 1514131211109876543210 din15 din14 din13 din12 din11 din10 din9 di n8 din7 din6 din5 din4 din3 din2 din1 din0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 14. fdr1l register description bit name function 15:0 din[15:0] data input 15:0 these bits must be written with the data to program in flash during the following operations: double word program (64-bit) and set protection. fdr1h (0x0e 000e) fcr reset value: ffffh 1514131211109876543210 din31 din30 din29 din28 din27 din26 din25 din24 din23 din22 din21 din20 din19 din18 din17 din16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 15. fdr1h register description bit name function 15:0 din[31:16] data input 31:16 these bits must be written with the data to program in flash during the following operations: double word program (64-bit) and set protection. farl (0x0e 0010) fcr reset value: 0000h 1514131211109876543210 add15 add14 add13 add12 add11 add10 add9 add8 add7 add6 add5 add4 add3 add2 reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw - table 16. farl register description bit name function 15:2 add[15:2] address 15:2 these bits must be written with the ad dress of the flash location to program during the following operations: word program (32-bit) and double word program (64-bit). in double word program bit add2 must be written to ?0?. 1:0 - reserved. these bits must be kept to their default value (0).
st10f273m internal flash memory doc id 13453 rev 4 39/186 5.4.10 flash address register high (farh) 5.4.11 flash error register (fer) the flash error register, as well as all the other flash registers, can be read only once the lock bit of register fcr0l is low. nevertheless, the fer content is updated after completion of the flash operation, that is, when bsyx bits are rese t. therefore, the fer content can only be read once the lock and bsyx bits are cleared. farh (0x0e 0012) fcr reset value: 0000h 1514131211109876543210 reserved add 20 add 19 add 18 add 17 add 16 -rwrwrwrwrw table 17. farh register description bit name function 4:0 add20 ... add16 address 20:16 these bits must be written with the addr ess of the flash location to program during the following operations: word program and double word program. 15:5 - reserved. these bits must be kept to their default value (0). fer (0xe 0014h) fcr reset value: 0000h 1514131211109876543210 reserved wpf reser seqer reserved 10er pger erer err - rc rc rc - rc rc rc rc table 18. fer register bits bit name function 15:9 - reserved. these bits must be kept to their default value (0). 8wpf write protection flag this bit is automatically set when trying to program or erase in a sector write protected. in case of multiple sector erase, the not protected sectors are erased, while the protected sectors are not erased and bit wpf is set. this bit must be cleared by software. 7 reser resume error this bit is automatically set when a suspended program or erase operation is not resumed correctly due to a protocol error. in this case the suspended operation is aborted. this bit must be cleared by software. 6 seqer sequence error this bit is automatically set when the control registers (fcr1h/l-fcr0h/l, farh/l, fdr1h/l-fdr0h/l) are not corre ctly filled to execute a valid write operation. in this case no write operation is executed. this bit must be cleared by software. 5:4 - reserved. these bits must be kept to their default value (0).
internal flash memory st10f273m 40/186 doc id 13453 rev 4 5.4.12 xflash interface cont rol dummy register (xficr) 5.5 protection strategy the protection bits are stored in non-volatile flash cells that are read once at reset and stored in five volatile register s. before they are read from the non-volatile cells, all the available protections are forced active during reset. 310er 1 over 0 error this bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the protection bits). this error is not due to a failure of the flash cell, but only flags that the desired data has not been written. this bit must be cleared by software. 2pger program error this bit is automatically set when a program error occurs during a flash write operation. this error is due to a real failure of a flash cell, that can no more be programmed. the word where this error occurred must be discarded. this bit must be cleared by software. 1erer erase error this bit is automatically set when an erase error occurs during a flash write operation. this error is due to a real failure of a flash cell, that can no more be erased. this kind of error is fatal and the sector where it occurred must be discarded. this bit must be cleared by software. 0err write error this bit is automatically set when an error occurs during a flash write operation or when a bad write operation setup is done. once the error has been discovered and understood, err bit must be cleared by software. table 18. fer register bits (continued) bit name function xficr (0x0e e0000) fcr reset value: 0007h 1514131211109876543210 reserved ws3 ws2 ws1 ws0 -rwrwrwrw table 19. xflash interface control register bit name function 3:0 ws3...ws0 dummy wait states 3:0 in the st10f273e, these bits were us ed to configure the number of wait- states to access the xflash. as there is no xflash on the root part number 1, these bits have no effect. this register is implemented for so ftware compatibility with the st10f273e. 15:4 - reserved. these bits must be kept to their default value (0).
st10f273m internal flash memory doc id 13453 rev 4 41/186 note: the protection bits in the non-volatile registers are programmable one time and this programing is permanent. temporary unprot ection will be handled with their volatile equivalent. the protections can be programmed using the set protection operation (see section 5.4: flash control registers description ) that must be executed from the on-chip rams or from external memories. two kind of protections are available: write protections to avoid unwanted writings access protections to avoid piracy the next sections show the different level of protections and highlight the architecture limitations. 5.5.1 protection registers the five non-volatile protection registers are one-time programmable for the user. two registers, fvwpirl and fvwpirh, are used to store the write protection fuses for each sector iflash module. the other three registers (fnvapr0 and fnvapr1l/h) are used to store the access protection fuses. note: on-going protection oper ations are flagged with bsynvr , bit 1 of fcr0l register. 5.5.2 flash non-volatile write pr otection i register low (fnvwpirl) fnvwpirl (0x0e dfb4) nvr delivery value: ffffh 1514131211109876543210 reserved w0p 11 w0p 10 w0p 9 w0p 8 w0p 7 w0p 6 w0p 5 w0p 4 w0p 3 w0p 2 w0p 1 w0p 0 - ro rorwrwrwrwrwrwrwrwrwrw table 20. fnvwpirl register bits bit name function 15:12 - reserved. these bits must be left to their default value ?1? when programming pvwpirl. 11:10 w0p11 w0p10 read-only for write protection bank0 sectors 11 and 10 these bits must be left to their default value ?1? when programming fvwpirl (they can not be used to set write protection on sectors b0f11 and b0f10). after a protection command, these bits wil l reflect the value of bit 0 and 1 of fvwpirh register (w0p11 and w0p10). 9:0 w0p9 ... w0p0 write protection bank 0 / sectors 9-0 these bits, if programmed at 0, disabl e any write access to the sectors of bank 0 (iflash).
internal flash memory st10f273m 42/186 doc id 13453 rev 4 5.5.3 flash non-volatile write pr otection i register high (fnvwpirh) 5.5.4 flash non-volatile write protecti on i register low mirror (fnvwpirl-m) this register is mirroring the register at fvwpirl (address 0x0e dfb4). it is intended to maintain software compat ibility with the st10f273e. in applications ported from a st10f273e, fvwpirl-m register (address 0x0e dfb0) must be used to maintain the existing flash drivers. in applications ported from a st10f272x, fvwpirl register (address 0x0e dfb4) must be used to maintain existing drivers. 5.5.5 flash non-volatile write protect ion i register high mirror (fvwpirh-m) this register is mirroring the register at fv wpirh (address 0x0e dfb6). it is intended to maintain software compat ibility with the st10f273e. in applications ported from a st10f273e, fvwpirh-m register (address 0x0e dfb2) must be used to maintain the existing flash drivers. in applications ported from a st10f272x, fvwpirh register (address 0x0e dfb6) must be used to maintain existing drivers. fnvwpirh (0x0e dfb6) nvr delivery value: ffffh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved w0p11- w1p1 w0p10- w1p0 -rwrw table 21. fnvwprih register bits bit name function 15:2 - reserved. these bits must be left to their default value ?1?. 1:0 w0p11/w1p1 w0p10/w1p0 write protection bank0 - sectors 11:10 / write protection bank1 - sectors 1:0 these bits, if programmed at 0, disable any write access to the selected sectors. fnvwpirl-m (0x0e dfb0) n vr delivery value: ffffh 1514131211109876543210 reserved w0p 11 w0p 10 w0p 9 w0p 8 w0p 7 w0p 6 w0p 5 w0p 4 w0p 3 w0p 2 w0p 1 w0p 0 - ro rorwrwrwrwrwrwrwrwrwrw fvwpirh-m (0x0e dfb2 nvr delivery value: ffffh 151413121110987654321 0 reserved w0p11- w1p1 w0p10- w1p0 -rwrw
st10f273m internal flash memory doc id 13453 rev 4 43/186 5.5.6 flash non-volatile access pr otection register 0 (fnvapr0) 5.5.7 flash non-volatile access prot ection register 1 low (fnvapr1l) fnvapr0 (0x0e dfb8) nvr delivery value: acffh 1514131211109876543210 reserved dbgp accp -rwrw table 22. fnvapr0 register bits bit name description 15:2 - reserved. these bits must be left to their default value. 1dbgp debug protection this bit, if erased at 1, allows to bypass all the protections using the debug features through the test interface. if programmed at 0, on the contrary, all the debug features, the test interface and all the flash test modes are disabled. even stmicroelectronics will not be able to access the device to run any eventual failure analysis. 0 accp access protection this bit, if programmed at 0, disables any access (read/write) to data mapped inside iflash module address space, unle ss the current instruction is fetched from iflash. fnvapr1l (0x0e dfbc) nvr delivery value: ffffh 1514131211109876543210 pds15 pds14 pds13 pds12 pds11 pds10 pds9 pds8 pds7 pds6 pds5 pds4 pds3 pds2 pds1 pds0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 23. fnvapr1l register bits bit name function 15:0 pds15 ... pds0 protections disable15-0 if bit pdsx is programmed at 0 and bit penx is erased at 1, the action of bit accp is disabled. bit pds0 can be prog rammed at 0 only if both bits dbgp and accp have already been programmed at 0. bit pdsx can be programmed at 0 only if bit penx-1 has already been programmed at 0.
internal flash memory st10f273m 44/186 doc id 13453 rev 4 5.5.8 flash non- volatile access protection register 1 high ( fnvapr1h ) 5.5.9 access protection the iflash module has one level of access protection (access to data both in reading and writing): if bit accp of fnvapr0 is programmed at 0, the iflash module becomes access protected, meaning data in the iflash module can be read only if the current execution is from the iflash module itself. protection can be permanently disabled by programming bit pds0 of fnvapr1h (user operation before returning parts to stmicroelectronics for analysis). protection can be permanently enabled again by programming bit pen0 of fnvapr1l. the action to disable and enable again access protections in a permanent way can be executed a maximum of 16 times. trying to write into the access protected flash from internal ram or external memories will be unsuccessful. trying to read into the access protected flash from internal ram or external memories will output a dummy data (software trap 009bh). when the flash module is protected in access, data access through pec of a peripheral is also forbidden. to read/write data in pec mode from/to a protected bank, it is necessary to first temporarily unprotect the flash module. the following table summarizes all possible access protection levels: in particular, it shows what is possible and not possible to do when fetching from a memory (see fetch location column) supposing all possible access protections are enabled. fnvapr1h (0x0e dfbe) nvr delivery value: ffffh 1514131211109876543210 pen15 pen14 pen13 pen12 pen11 pen10 pen9 pen8 pen7 pen6 pen5 pen4 pen3 pen2 pen1 pen0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 24. fnvapr1h register bits bit name function 15:0 pen15 ... pen0 protections enable 15-0 if bit penx is programmed at 0 and bit pdsx +1 is erased at 1, the action of bit accp is enabled again. bit penx can be programmed at 0 only if bit pdsx has already been programmed at 0. table 25. summary of access protection level fetch location read iflash / jump to iflash read xram or external memory / jump to xram or external memory read flash registers write flash registers fetching from iflash yes / yes yes / yes yes yes fetching from iram no / yes yes / yes yes no fetching from xram no / yes yes / yes yes no fetching from external memory n o / ye s ye s / ye s ye s n o
st10f273m internal flash memory doc id 13453 rev 4 45/186 5.5.10 write protection the flash modules have one level of write protections: each sector can be software write protected by programming at 0 the related bit wypx in fnvwpirl/h register. 5.5.11 temporary unprotection bits wypx of fnvwpirl/h can be temporarily unprotected by executing the set protection operation and writing 1 into these bits. bit accp can be temporarily unprotected by executing the set protection operation and writing are executed from iflash. to restore the write access protection bits it is necessary to reset the microcontroller or to execute a set protection operation and write 0 into the desired bits. in reality, when a temporary unprotection operation is executed, the corresponding volatile register is written to 1, while the non-volatile registers bits previously written to 0 (for a protection set operation), will co ntinue to maintain the 0. for this reason, the user software must be in charge to track the current protection status (for instance using a specific ram area), it is not possible to deduce it by reading the non-volatile register content (a temporary unprotection cannot be detected). 5.6 write operation examples in the following, examples for each kind of flash write operation are presented. the examples are showing the sequence of instructions needed to start an operation. write operations should be followed by a status check (fer register). note: after a write operation has started, the flash control registers are not accessible for a short time. the lock bit, bit 4 of fcr0l register, must be polled in order to know when the flash control registers can be accessed again (lock = ?1?: no access to flash control registers). write operation on ibus registers is 16 bits wide. word program example: 32-bit word program of data 0xaaaaaaaa at address 0x025554 fcr0h |= 0x2000; /*set wpg in fcr0h*/ farl = 0x5554; /*load add in farl*/ farh = 0x0002; /*load add in farh*/ fdr0l = 0xaaaa; /*load data in fdr0l*/ fdr0h = 0xaaaa; /*load data in fdr0h*/ fcr0h |= 0x8000; /*operation start*/ double word program example: double word program (64-bit) of data 0x55aa55aa at address 0x035558 and data 0xaa55aa55 at address 0x03555c. fcr0h |= 0x1000; /*set dwpg in fcr0h*/ farl = 0x5558; /*load add in farl*/ farh = 0x0003; /*load add in farh*/ fdr0l = 0x55aa; /*load data in fdr0l*/
internal flash memory st10f273m 46/186 doc id 13453 rev 4 fdr0h = 0x55aa; /*load data in fdr0h*/ fdr1l = 0xaa55; /*load data in fdr1l*/ fdr1h = 0xaa55; /*load data in fdr1h*/ fcr0h |= 0x8000; /*operation start*/ double word program is always performed on the double word aligned on an even word: bit add2 of farl is ignored. sector erase example: sector erase of sectors b0f1 and b0f0 of bank 0. fcr0h |= 0x0800; /*set ser in fcr0h*/ fcr1l |= 0x0003; /*set b0f1, b0f0*/ fcr0h |= 0x8000; /*operation start*/ suspend and resume word program, double word program, and sector erase operations can be suspended in the following way: fcr0h |= 0x4000; /*set susp in fcr0h*/ then the operation can be resumed in the following way: fcr0h |= 0x0800; /*set ser in fcr0h*/ fcr0h |= 0x8000; /*operation resume*/ before resuming a suspended erase, fcr1h/fcr1l must be read to check if the erase is already completed (fcr1h = fcr1l = 0x0000 if erase is complete). original setup of select operation bits in fcr0h/l must be restored before the operation resume, otherwise the operation is aborted an d bit reser of fer is set. set protection example 1: enable write protection of sectors b0f3-0 of bank 0. fcr0h |= 0x0100; /*set spr in fcr0h*/ farl = 0xdfb4; /*load add of register fnvwpir in farl*/ farh = 0x000e; /*load add of register fnvwpir in farh*/ fdr0l = 0xfff0; /*load data in fdr0l*/ fdr0h = 0xffff; /*load data in fdr0h*/ fcr0h |= 0x8000; /*operation start*/ example 2: enable access and debug protection. fcr0h |= 0x0100; /*set spr in fcr0h*/ farl = 0xdfb8; /*load add of register fnvapr0 in farl*/ farh = 0x000e; /*load add of register fnvapr0 in farh*/ fdr0l = 0xfffc; /*load data in fdr0l*/ fcr0h |= 0x8000; /*operation start*/ example 3: disable in a permanent way access and debug protection. fcr0h |= 0x0100; /*set spr in fcr0h*/ fcr0h |= 0x0100; /*set spr in fcr0h*/ farl = 0xdfbc; /*load add of register fnvapr1l in farl*/ farh = 0x000e; /*load add of register fnvapr1l in farh*/
st10f273m internal flash memory doc id 13453 rev 4 47/186 fdr0l = 0xfffe; /*load data in fdr0l for clearing pds0*/ fcr0h |= 0x8000; /*operation start*/ example 4: enable again in a permanent way access and debug protection, after having disabled them. fcr0h|= 0x0100; /*set spr in fcr0h*/ farl = 0xdfbc; /*load add register fnvapr1h in farl*/ farh = 0x000e; /*load add register fnvapr1h in farh*/ fdr0h = 0xfffe; /*load data in fdr0h to clear pen0*/ fcr0h|= 0x8000; /*operation start*/ disable and re-enable of access and debug protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times.
internal flash memory st10f273m 48/186 doc id 13453 rev 4 5.7 write operation summary in general, each write operation is started through a sequence of three steps: 1. the first instruction is used to select the desired operation by setting its corresponding selection bit in the fl ash control register 0. 2. the second step is the definition of the address and data for programming or the sectors to erase. 3. the last instruction is used to start the write operation, by setting the start bit wms in the fcr0. this last instruction must not be executed from flash. once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. available flash module write operatio ns are summarized in the following ta b l e 2 6 . figure 7 shows the complete flow needed for a write operation. figure 7. write operation control flow table 26. flash write operations operation select bit address and data start bit word program (32-bit) wpg farl/farh fdr0l/fdr0h wms double word program (64-bit) dwpg farl/farh fdr0l/fdr0h fdr1l/fdr1h sector erase ser fcr1l/fcr1h set protection spr fdr0l/fdr0h program/erase suspend susp none none 6wduw:ulwh2shudwlrq )&5//2&. " 1r <h v :ulwh2shudwlrqilqlvkhg" &khfnuhodwhgexv\elw 1r <h v &khfn(uuru6wdwxv 1rhuuru 3urfhhgzlwkdssolfdwlrq (uuru (uurukdqgohu 5hvwduwrshudwlrq ("1($'5
st10f273m bootstrap loader doc id 13453 rev 4 49/186 6 bootstrap loader the st10f273m implements boot capabilities in order to: support bootstrap via uart or bootstrap via can for the standard bootstrap support a selective bootstrap loader, to manage the bootstrap sequence in a different way 6.1 selection among u ser-code, standard or selective bootstrap the boot modes are triggered with a special combination set on port0l[5...4]. those signals, as other configuration signals, are latched on the rising edge of rstin pin. decoding of reset configuration (p0l.5 = 1, p0l.4 = 1) selects the normal mode (also called user mode) and selects the user flash to be mapped from address 00?0000h. decoding of reset configuration (p0l.5 = 1, p0l.4 = 0) selects st10 standard bootstrap mode (test-flash is active and overlaps us er flash for code fetches from address 00'0000h; user flash is active and available for read accesses). decoding of reset configuration (p0l.5 = 0, p0l.4 = 1) activates additional verifications to select which bootstrap software to execute: ? if the user mode signature in the user flash is programmed correctly, then a software reset sequence is selected and the user code is executed; ? if the user mode signature is not progra mmed correctly in the user flash, then the user key location is read again. its value determines which communication channel will be enabled for bootstrapping. . 6.2 standard bootstrap loader after entering the standard bsl mode and the respective initialization, the st10f273m scans the rxd0 line and the can1_rxd line to receive either a valid dominant bit from the can interface or a start condition from the uart line. start condition on uart rxd: st10f273m starts standard bootstrap loader. this bootstrap loader is identical to that of other st10 devices (example: st10f269, st10f168). valid dominant bit on can1 rxd: st10f273m start bootstrapping via can1. caution: as both uart_rxd and can1_rxd lines are polled to detect a start of communication, ensure a stable level on the unused channel by adding a pull-up resistor. table 27. st10f273m boot mode selection p0.5 p0.4 st10 decoding 11 user mode: user flash mapped at 00?0000h 10 standard bootstrap loader: user flash mapped from 00?0000h, code fetches redirected to test-flash at 00?0000h 01 selective boot mode: user flash mapped from 00?0000h, code fetches redirected to test-flash at 00?0000h (dif ferent sequence execution compared to standard bootstrap loader) 00reserved
bootstrap loader st10f273m 50/186 doc id 13453 rev 4 6.3 alternate and selective boot mode (abm and sbm) 6.3.1 activation of the abm and sbm alternate boot is activated with the combination ?01? on port0l[5..4] at the rising edge of rstin . 6.3.2 user mode signature integrity check the behavior of the selective boot mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature. this requires that users who use selective boot have reserved and programmed the flash memory locations. 6.3.3 selective boot mode when the user signature is not correct, instead of executing the standard bootstrap loader (triggered by p0l.4 low at reset), additional check is made. depending on the value at the user key location, the following behavior occurs: a jump is performed to the standard bootstrap loader only uart is enabled for bootstrapping only can1 is enabled for bootstrapping the device enters an infinite loop
st10f273m central processing unit (cpu) doc id 13453 rev 4 51/186 7 central processing unit (cpu) the cpu includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedicated sfrs. additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. most of the st10f273m?s instructions can be executed in one instruction cycle which requires 50ns at 40 mhz cpu clock. for example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. the jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. the cpu uses a bank of 16 word registers to run the current context. this bank of general purpose registers (gpr) is physically stored within the on-chip internal ram (iram) area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 2048 bytes is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. figure 8. cpu block diagram (mac unit not included) ,qwhuqdo 5$ 0 .%\wh *hqhudo 3xusrvh 5hjlvwhuv 5 5 0'+ 0' / %duuho6kliw 0xo'ly+: %lw0dvn*hq $/8 %lw &3 63 67 .29 67.8 1 ([hf8qlw ,qvwu3wu 6wdjh 3lsholqh 36: 6<6&2 1 %86&21 %8 6&21 %8 6&21 %8 6&21 %86&21 $''56(/ $''56( / $''56( / $''56( / 'dwd 3j3wuv &rgh6hj3wu &3 8 .%\wh )odvk phpru\ %dq n q %dqn l %dqn ("1($'5
central processing unit (cpu) st10f273m 52/186 doc id 13453 rev 4 7.1 multiplier-accumulator unit (mac) the mac co-processor is a specia lized co-processor added to the st10 cpu core in order to improve the performances of the st10 family in signal processing algorithms. the standard st 10 cpu has been modified to include new addressing capabilities which enable the cpu to supply the new co-processor with up to 2 operands per instruction cycle. this new co-processor (so-called mac) contai ns a fast multiply-accumulate unit and a repeat unit. the co-processor instructions extend the st10 cpu instruction set with multiply, multiply- accumulate, 32-bit signed arithmetic operations. figure 9. mac unit architecture 2shudqg 2shudqg &rqwuro8qlw 5hshdw8qlw 67&38 ,qwhuuxsw &rqwuroohu 06: 05: 0$+ 0$/ 0&: )odjv 0$( 0x[ elw/hiw5ljkw 6kliwhu 0x[ 0x[ 6ljq([whqg [ &rqfdwhqdwlrq vljqhgxqvljqhg 0xowlsolhu elw6ljqhg$ulwkphwlf8qlw k k k 6fdohu % $ *353rlqwhuv ,'; 3rlqwhu ,'; 3rlqwhu 45*352iivhw5hjlvwhu 45*352iivhw5hjlvwhu 4;,';2iivhw5hjlvwhu 4;,';2iivhw5hjlvwhu ("1($'5
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st10f273m central processing unit (cpu) doc id 13453 rev 4 53/186 7.2 instruction set summary ta bl e 2 8 lists the instructions of the st10f273m. the detailed description of each instruction can be found in the st10 family programming manual . table 28. standard instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-/16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement dire ct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indir ect/relative if condition is met 4 jmps jump absolute to a code segment 4
central processing unit (cpu) st10f273m 54/186 doc id 13453 rev 4 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative s ubroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power-down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout-pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 28. standard instruction set summary (continued) mnemonic description bytes
st10f273m central processing unit (cpu) doc id 13453 rev 4 55/186 7.3 mac co-processor sp ecific instructions ta bl e 2 9 lists the mac instructions of the st10f273m. the detailed description of each instruction can be found in the st10 family programming manual . note that all mac instructions are encoded on 4 bytes. table 29. mac instruction set summary mnemonic description coabs absolute value of the accumulator coadd(2) addition coashr(rnd) accumulator arithmetic shift right & optional round cocmp compare accumulator with operands coload(-,2) load accumulator with operands comac(r,u,s,-,rnd) (un)signed/(un)signed multiply-accumulate & optional round comacm(r)(u,s,-,rnd) (un)signed/(un)signed multiply-a ccumulate with parallel data move & optional round comax / comin maximum / minimum of operands and accumulator comov memory to memory move comul(u,s,-,rnd) (un)signed/(un)si gned multiply & optional round coneg(rnd) negate accumulator & optional round conop no-operation cornd round accumulator coshl / coshr accumulator logical shift left / right costore store a mac unit register cosub(2,r) subtraction
external bus controller st10f273m 56/186 doc id 13453 rev 4 8 external bus controller all of the external memory accesses are performed by the on-chip external bus controller. the ebc can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed in demultiplexed bus modes addresses are output on port1 and data is input / output on port0 or p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input / output. timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. up to four independent address windows may be defined (using register pairs addrselx / busconx) to access different res ources and bus characteristics. these address windows are arranged hierar chically where buscon4 overrides buscon3 and buscon2 overrides buscon1. all accesses to locations not covered by these four address windows are controlled by buscon0. up to five external cs signals (four windows plus default) can be generated in order to save external glue logic. access to very slow memories is supported by a ?ready? function. a hold / hlda protocol is available for bus arbitration which shares external resources with other bus masters. the bus arbitration is enabled by setting bit hlden in register psw. after setting hlden once, pins p6.7...p6.5 (breq , hlda , hold ) are automatically controlled by the ebc. in master mode (default after reset) the hlda pin is an output. by setting bit dp6.7 to ?1? the slave mode is selected where pin hlda is switched to input. this directly connects the slave controller to another master controller without glue logic. for applications which require less external memory space, the address space can be restricted to 1 mbyte, 256 kbytes or to 64 kbytes. port 4 outputs all eight address lines if an address space of 16 mbytes is used, otherwise four, two or no address lines. chip select timing can be made programmable. by default (after reset), the csx lines change half a cpu clock cycle after the rising edge of ale. with the cscfg bit set in the syscon register the csx lines change with the rising edge of ale. the active level of the ready pin can be set by bit rdypol in the busconx registers. when the ready function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit rdypol in the associated buscon register.
st10f273m interrupt system doc id 13453 rev 4 57/186 9 interrupt system the interrupt response time for internal program execution is from 125ns to 300ns at 40 mhz cpu clock. the st10f273m architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. any of these interrupt requests can be serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source or destination pointer. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited to perform the transmission or the reception of blocks of data. the st10f273m has eight pec channels, each of them offe rs such fast interrupt-driv en data transfer capabilities. an interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. once starting to be processed by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). fast external interrupts may also have interrupt sources selected from other peripherals; for example the canx controller receive signals (canx_rxd) and i 2 c serial clock signal can be used to interrupt the system. ta bl e 3 0 shows all the available st10f273m interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. table 30. interrupt sources source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number capcom register 0 cc0ir cc0ie cc0int 00?0040h 10h capcom register 1 cc1ir cc1ie cc1int 00?0044h 11h capcom register 2 cc2ir cc2ie cc2int 00?0048h 12h capcom register 3 cc3ir cc3ie cc3int 00?004ch 13h capcom register 4 cc4ir cc4ie cc4int 00?0050h 14h capcom register 5 cc5ir cc5ie cc5int 00?0054h 15h
interrupt system st10f273m 58/186 doc id 13453 rev 4 capcom register 6 cc6ir cc6ie cc6int 00?0058h 16h capcom register 7 cc7ir cc7ie cc7int 00?005ch 17h capcom register 8 cc8ir cc8ie cc8int 00?0060h 18h capcom register 9 cc9ir cc9ie cc9int 00?0064h 19h capcom register 10 cc10ir cc10ie cc10int 00?0068h 1ah capcom register 11 cc11ir cc11ie cc11int 00?006ch 1bh capcom register 12 cc12ir cc12ie cc12int 00?0070h 1ch capcom register 13 cc13ir cc13ie cc13int 00?0074h 1dh capcom register 14 cc14ir cc14ie cc14int 00?0078h 1eh capcom register 15 cc15ir cc15ie cc15int 00?007ch 1fh capcom register 16 cc16ir cc16ie cc16int 00?00c0h 30h capcom register 17 cc17ir cc17ie cc17int 00?00c4h 31h capcom register 18 cc18ir cc18ie cc18int 00?00c8h 32h capcom register 19 cc19ir cc19ie cc19int 00?00cch 33h capcom register 20 cc20ir cc20ie cc20int 00?00d0h 34h capcom register 21 cc21ir cc21ie cc21int 00?00d4h 35h capcom register 22 cc22ir cc22ie cc22int 00?00d8h 36h capcom register 23 cc23ir cc23ie cc23int 00?00dch 37h capcom register 24 cc24ir cc24ie cc24int 00?00e0h 38h capcom register 25 cc25ir cc25ie cc25int 00?00e4h 39h capcom register 26 cc26ir cc26ie cc26int 00?00e8h 3ah capcom register 27 cc27ir cc27ie cc27int 00?00ech 3bh capcom register 28 cc28ir cc28ie cc28int 00?00f0h 3ch capcom register 29 cc29ir cc29ie cc29int 00?0110h 44h capcom register 30 cc30ir cc30ie cc30int 00?0114h 45h capcom register 31 cc31ir cc31ie cc31int 00?0118h 46h capcom timer 0 t0ir t0ie t0int 00?0080h 20h capcom timer 1 t1ir t1ie t1int 00?0084h 21h capcom timer 7 t7ir t7ie t7int 00?00f4h 3dh capcom timer 8 t8ir t8ie t8int 00?00f8h 3eh gpt1timer 2 t2ir t2ie t2int 00?0088h 22h gpt1 timer 3 t3ir t3ie t3int 00?008ch 23h gpt1 timer 4 t4ir t4ie t4int 00?0090h 24h gpt2timer 5 t5ir t5ie t5int 00?0094h 25h table 30. interrupt sources (continued) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number
st10f273m interrupt system doc id 13453 rev 4 59/186 hardware traps are exceptions or error conditions that arise during run-time. they cause immediate non-maskable system reaction simila r to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). a hardware trap will interrup t any other program execution except when another higher prioritized trap service is in progress. hardware trap services cannot not be interrupted by a standard interrupt or by pec interrupts. 9.1 x-peripheral interrupt the limited number of x-bus interrupt lines of the present st10 architecture, imposes some constraints on the implementation of the new functionality. in particular, the additional x- peripherals ssc1, asc1, i 2 c, pwm1 and rtc need some resources to implement interrupt and pec transfer capabilities. for this reas on, a multiplexed structure for the interrupt management is proposed. in the next figure 10 , the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four x-interrupt available vectors (xp0int, xp1int, xp2int and xp3int). it is based on a set of 16-bit registers xirxsel (x = 0,1,2,3), divided in two portions each: byte high xirxsel[15:8] interrupt enable bits byte low xirxsel[7:0] interrupt flag bits gpt2 timer 6 t6ir t6ie t6int 00?0098h 26h gpt2 caprel register crir crie crint 00?009ch 27h a/d conversion complete adcir adcie adcint 00?00a0h 28h a/d overrun error adeir adeie adeint 00?00a4h 29h asc0 transmit s0tir s0tie s0tint 00?00a8h 2ah asc0 transmit buffer s0tbir s0tbie s0tbint 00?011ch 47h asc0 receive s0rir s0rie s0rint 00?00ach 2bh asc0 error s0eir s0eie s0eint 00?00b0h 2ch ssc transmit sctir sctie sctint 00?00b4h 2dh ssc receive scrir scrie scrint 00?00b8h 2eh ssc error sceir sceie sceint 00?00bch 2fh pwm channel 0...3 pwmir pwmie pwmint 00?00fch 3fh see section 9.1 xp0ir xp0ie xp0int 00?0100h 40h see section 9.1 xp1ir xp1ie xp1int 00?0104h 41h see section 9.1 xp2ir xp2ie xp2int 00?0108h 42h see section 9.1 xp3ir xp3ie xp3int 00?010ch 43h table 30. interrupt sources (continued) source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number
interrupt system st10f273m 60/186 doc id 13453 rev 4 when different sources submit an interrupt request, the enable bits (byte high of xirxsel register) define a mask which controls which sources will be associated with the unique available vector. if more than one source is enabled to issue the request, the service routine will have to take care to identify the real even t to be serviced. this can easily be done by checking the flag bits (byte low of xirxsel register). note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt reques t: a periodic polling of the flag bits may be implemented inside the user application. figure 10. x-interrupt basic structure ta bl e 3 1 summarizes the mapping of the different interrupt sources which shares the four x- interrupt vectors. table 31. x-interrupt detailed mapping interrupt source xp0i nt xp1int xp2int xp3int can1 interrupt x x can2 interrupt x x i2c receive x x x i2c transmit x x x i2c error x ssc1 receive x x x ssc1 transmit x x x ssc1 error x asc1 receive x x x asc1 transmit x x x asc1 transmit buffer x x x asc1 error x ;,5[6(/>@[ ;,5[6(/>@[ ;3[,&;3[,5[ ,76rxufh ,76rxufh ,76rxufh ,76rxufh ,76rxufh ,76rxufh ,76rxufh ,76rxufh (qdeoh>@ )odj>@ ("1($'5
st10f273m interrupt system doc id 13453 rev 4 61/186 9.2 exception and error traps list ta bl e 3 2 shows all of the possible exceptions or error conditions that can arise during run- time. pll unlock / owd x pwm1 channel 3...0 xx table 31. x-interrupt detailed mapping (continued) interrupt source xp0i nt xp1int xp2int xp3int table 32. trap priorities exception condition trap flag trap vector vector location trap number trap priority (1) 1. - all the class b traps have the same trap number ( and vector) and the same lower priority compared to the class a traps and to the resets. - each class a trap has a dedicated trap number (and vect or). they are prioritiz ed in the second priority level. - the resets have the highest priori ty level and the same trap number. - the psw.ilvl cpu priority is forced to the highes t level (15) when these exceptions are serviced. reset functions: hardware reset software reset watchdog timer overflow reset reset reset 00?0000h 00?0000h 00?0000h 00h 00h 00h iii iii iii class a hardware traps: non-maskable interrupt stack overflow stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00?0008h 00?0010h 00?0018h 02h 04h 06h ii ii ii class b hardware traps: undefined opcode mac interruption protected instruction fault illegal word operand access illegal instruction access illegal external bus access undopc mactrp prtflt illopa illina illbus btrap btrap btrap btrap btrap btrap 00?0028h 00?0028h 00?0028h 00?0028h 00?0028h 00?0028h 0ah 0ah 0ah 0ah 0ah 0ah i i i i i i reserved [002ch - 003ch] [0bh - 0fh] software traps trap instruction any 0000h ? 01fch in steps of 4h any [00h - 7fh] current cpu priority
capture / compare (capcom) units st10f273m 62/186 doc id 13453 rev 4 10 capture / compare (capcom) units the st10f273m has two 16-channel capcom units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 200ns at 40 mhz cpu clock. the capcom units are typically used to handl e high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw), digital to analog (d/a) conversion, software timing, or time recording relative to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. in addition, external count inputs for capcom timers t0 and t7 allow event scheduling for the capture/compare registers relative to external events. each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, respectively), and programmed for capture or compare functions. each of the 32 registers has one associated port pin which serv es as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. either a positive, a negative, or both a positi ve and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture / compare register, specific actions will be take n based on the selected compare mode. the input frequencies f tx , for the timer input selector tx, are determined as a function of the cpu clocks. the timer input frequencies, resolution and periods which result from the selected prescaler option in txi when using a 40 mhz cpu clock are listed in ta b l e 3 4 . the numbers for the timer periods are based on a reload value of 0000h. note that some numbers may be rounded off to three significant figures. table 33. compare modes compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; seve ral compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated
st10f273m capture / compare (capcom) units doc id 13453 rev 4 63/186 mode 3 pin set ?1? on match; pin reset ?0? on compare time overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. table 33. compare modes (continued) compare modes function table 34. capcom timer input frequencies, resolutions and periods at 40 mhz f cpu = 40 mhz timer input selection txi 000b 001b 010b 011b 100b 101b 110b 111b prescaler for f cpu 8 16 32 64 128 256 512 1024 input frequency 5 mhz 2.5 mhz 1.25 mhz 625 khz 312.5 khz 156.25 khz 78.125 khz 39.1 khz resolution 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s 25.6s period 13.1ms 26.2ms 52.4ms 104 .8ms 209.7ms 419.4ms 838.9ms 1.678s
general purpose timer unit st10f273m 64/186 doc id 13453 rev 4 11 general purpose timer unit the gpt unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gp t unit contains five 16-bit timers organized into two separate modules gpt1 and gpt2. each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 11.1 gpt1 each of the three timers t2, t3, t4 of the gpt1 module can be configured individually for one of four basic modes of operation: timer , gated timer , counter mode and incremental interface mode . in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler. in counter mode, the timer is clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the ?gate? level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. ta bl e 3 5 lists the timer input frequencies, resolution and periods for each prescaler option at 40 mhz cpu clock. in incremental interface mode, the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b by their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals so that the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has output toggle latches (txotl) which changes state on each timer over flow / underflow. the state of this latch may be output on port pins (txout) for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for high resolution of long duration measurements. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. table 35. gpt1 timer input frequencies, resolutions and periods at 40 mhz f cpu = 40 mhz timer input selection t2i / t3i / t4i 000b 001b 010b 011b 100b 101b 110b 111b prescaler factor 8 16 32 64 128 256 512 1024 input frequency 5 mhz 2.5 mhz 1.25 mhz 625 kh z 312.5 khz 156.25 khz 78.125 khz 39.1 khz resolution 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s 25.6s period maximum 13.1ms 26.2ms 52.4m s 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
st10f273m general purpose timer unit doc id 13453 rev 4 65/186 figure 11. block diagram of gpt1 q q q q q q 7(8' 7,1 &3 8forfn &38forfn &38forfn 7,1 7,1 7(8' 7(8' *3 7wlphu7 *37wlphu7 *37wlphu7 727/ 5hordg &dswxuh 8' 8' 5hordg &dswxuh ,qwhuuxsw uhtxhvw ,qwhuuxsw uhtx hvw ,qwhuuxsw uhtxhvw 7 287 8' 7 prgh frqwuro 7 prgh frqwuro 7 prgh frqwur o ("1($'5
general purpose timer unit st10f273m 66/186 doc id 13453 rev 4 11.2 gpt2 the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported via the output toggle latch (t6otl) of timer t6 which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, or it may be output on a port pin (t6out). the overflow / underflow of timer t6 can additionally be used to clock the capcom timers t0 or t1, and to cause a re load from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture procedure. this allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. the capture trigger (timer t5 to caprel) may also be generated upon transitions of gpt1 timer t3 inputs t3in and/or t3eud. this is advantageous when t3 operates in incremental interface mode. ta bl e 3 6 lists the timer input frequencies, resolution and periods for each prescaler option at 40 mhz cpu clock. table 36. gpt2 timer input frequencies, resolutions and periods at 40 mhz f cpu = 40 mhz timer input selection t5i / t6i 000b 001b 010b 011b 100b 101b 110b 111b prescaler factor 4 8 16 32 64 128 256 512 input frequency 10 mhz 5 mhz 2.5 mhz 1.25 mhz 625 khz 312.5 khz 156.25 khz 78.125 khz resolution 100ns 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms
st10f273m general purpose timer unit doc id 13453 rev 4 67/186 figure 12. block diagram of gpt2 q q q q 7(8' 7,1 &38&orfn &38&orfn 7,1 7(8' *377lphu7 *377lphu7 8' ,qwhuuxsw 5htxhvw 8' *37&$35(/ 77/ 7rjjoh)) 7287 &$3,1 5hordg ,qwhuuxsw 5htxhvw wr&$3&20 7lphuv &dswxuh &ohdu ,qwhuuxsw 5htxhvw ("1($'5 7 0rgh frqwuro 7 0r gh frqwuro
pwm modules st10f273m 68/186 doc id 13453 rev 4 12 pwm modules two pulse width modulation modules are available on st10f273m: standard pwm0 and xbus pwm1. they can generate up to four pwm output signals each, using edge-aligned or center-aligned pwm. in addition, the pwm modules can generate pwm burst signals and single shot outputs. ta b l e 3 7 shows the pwm frequencies for different resolutions. the level of the output signals is selectable and the pwm modules can generate interrupt requests. figure 13. block diagram of pwm module table 37. pwm unit frequencies and resolutions at 40 mhz cpu clock mode 0 resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 25ns 156.25 khz 39.1 khz 9.77 khz 2.44 hz 610 hz cpu clock/64 1.6s 2.44 khz 610 hz 152.6 hz 38.15 hz 9.54 hz mode 1 resolution 8-bit 10-bit 12-bit 14-bit 16-bit cpu clock/1 25ns 78.12 khz 19.53 khz 4.88 khz 1.22 khz 305.2 hz cpu clock/64 1.6s 1.22 khz 305.17hz 76.29 hz 19.07 hz 4.77 hz 33[3hulrg5hjlvwhu &rpsdudwru 37[ elw8s'rzq&rxqwhu 6kd grz5hjlvwhu 3:[3xovh:lgwk5hjlvwhu ,qsxw 5xq &rqwuro &orfn &orfn &rpsdudwru 8s'rzq &ohd u&rqwuro 0dwfk 2xwsxw&rqwuro 0dwfk :ulwh&rqwuro 8vhuuhdgdeohzulwhdeohuhjlvwhu (qdeoh 3287[ ("1($'5
st10f273m parallel ports doc id 13453 rev 4 69/186 13 parallel ports 13.1 introduction the st10f273m mcu provides up to 111 i/o lines with programmable features. these capabilities permit this mcu to be adapted to a wide range of applications. the st10f273m i/o lines are organized in nine groups: port 0 is a two time 8-bit port named p0l (low as less significant byte) and p0h (high as most significant byte) port 1 is a two time 8-bit port named p1l and p1h port 2 is a 16-bit port port 3 is a 15-bit port (p3.14 line is not implemented) port 4 is an 8-bit port port 5 is a 16-bit port input only port 6, port 7 and port 8 are 8-bit ports these ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. for example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using odpx registers. the input threshold levels are programmable (ttl/cmos) for all the ports. the logic level of a pin is clocked into the input latch once pe r state time, regardless whether the port is configured for input or output. the threshold is selected with picon and xpicon registers control bits. a write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. a read- modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. writing to a pin configured as an output (dpx.y = ?1?) causes the output latch and the pin to have the written value, since the output buffer is enabled. reading this pin returns the value of the output latch. a read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. i/o lines support an alternate function which is detailed in the following description of each port. 13.2 i/o?s special features 13.2.1 open drain mode some of the i/o ports of st10f273m support the open drain capability. this programmable feature may be used with an external pull-up resistor, in order to get an and wired logical function. this feature is implemented for ports p2, p3, p4, p6, p7 and p8 (see respective sections) and is controlled through the respective open drain control registers odpx.
parallel ports st10f273m 70/186 doc id 13453 rev 4 13.2.2 input threshold control the standard inputs of the st10f273m determine the status of input signals according to ttl levels. in order to accept and recognize noisy signals, cmos input thresholds can be selected instead of the standard ttl thresholds for all the pins. these cmos thresholds are defined above the ttl thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. the port input control registers picon and xpicon are used to select these thresholds for each byte of the indicated ports, this means the 8-bit ports p0l, p0h, p1l, p1h, p4, p7 and p8 are controlled by one bit each while ports p2, p3 and p5 are controlled by two bits each. all options for individual direction and output mode control are available for each pin, independent of the selected input threshold. 13.3 alternate port functions each port line has one associated programmable alternate input or output function. port0 and port1 may be used as address and data lines when accessing external memory. additionally, port1 provides: ? input capture lines ? 8 additional analog input channels to the a/d converter port 2, port 7 and port 8 are associated with the capture inputs or compare outputs of the capcom units and/or with the outputs of the pwm0 module, of the pwm1 module and of the asc1. port 2 is also used for fast external interrupt inputs and for timer 7 input. port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal bhe and the system clock output (clkout). port 4 outputs the additional segment address bit a23...a16 in systems where more than 64 kbytes of memory are to be access directly. in addition, can1, can2 and i 2 c lines are provided. port 5 is used as analog input channels of the a/d converter or as timer control signals. port 6 provides optional bus arbitration signals (breq , hlda , hold ) and chip select signals and the ssc1 lines. if the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (dpx.y = ?1?), except for some signals that are used directly after reset and are configured automatically. otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. the respective port latch should hold a ?1?, because its output is anded with the alternate output data (except for pwm output signals). if the alternate input function of a pin is used, the direction of the pin must be programmed for input (dpx.y = ?0?) if an external device is driving the pin. the input direction is the default after reset. if no external device is connected to the pin, however, the direction for this pin can also be set to output. in this case, the pin reflects the state of the port output latch. thus, the alternate input function reads the value stored in the port output latch. this can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. on most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin.
st10f273m parallel ports doc id 13453 rev 4 71/186 this is done by setting or clearing the direction control bit dpx.y of the pin before enabling the alternate function. there are port lines, however, where the direction of the port line is switched automatically. for instance, in the multiplexed external bus modes of port0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. obviously, this cannot be done through instructions. in these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. to determine the appropriate level of the port output latches, check how the alternate data output is combined with the respective port latch output. there is one basic structure for all port lines with only an alternate input function. port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. all port lines that are not used for these alte rnate functions may be used as general purpose i/o lines.
a/d converter st10f273m 72/186 doc id 13453 rev 4 14 a/d converter a 10-bit a/d converter with 24 multiplexed input channels and a sample and hold circuit is integrated on-chip. an automatic self-calibration adjusts the a/d converter module to process parameter variations at each reset event. the sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. the st10f273m has 16 + 8 multiplexed input channels on port 5 and port 1 respectively. the selection between port 5 and port 1 is made via a bit in an xbus register. refer to the user manual for a detailed description. a different accuracy is guaranteed (total unadjusted error) on port 5 and port 1 analog channels (with higher restrictions when overload conditions occur); in particular, port 5 channels are more accurate than the port 1 channels. refer to section 24: electrical characteristics for details. the a/d converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5lsb (2mv) impacting the global tue (tue depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 khz. of course, to reduce the effect of the input signal variation on the accuracy down to 0.05lsb, the maximum input frequency of the sine wave must be reduced to 800 hz. if a static signal is applied during the sampling phase, a series resistance shall not be greater than 20k (this taking into account eventual input leakage). it is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an rc filter is necessary, the external capacitance must be greater than 10nf to minimize the accuracy impact. overrun error detection / protection is controlled by the addat register. either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. for applications which require less than 16+8 analog input channels, the rning channel inputs can be used as digital input port pins. the a/d converter of the st10f273m supports different conversion modes: single channel single conversion : the analog level of the selected channel is sampled once and converted. the result of the conversion is stored in the addat register. single channel continuous conversion : the analog level of the selected channel is repeatedly sampled and converted. the result of the conversion is stored in the addat register. auto scan single conversion : the analog level of the selected channels are sampled once and converted. after each conversion the result is stored in the addat register. the data can be transferred to the ram by interrupt software management or using the powerful peripheral event controller (pec) data transfer. auto scan continuous conversion : the analog level of the selected channels are repeatedly sampled and converted. the result of the conversion is stored in the addat
st10f273m a/d converter doc id 13453 rev 4 73/186 register. the data can be transferred to the ram by interrupt software management or using the pec data transfer. wait for addat read mode : when using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the adwr bit of adcon control register must be activated. then, until the addat register is read, the new result is stored in a temporary buffer and the conversion is on hold. channel injection mode : when using continuous modes, a selected channel can be converted in between without changing the current operating mode. the 10-bit data of the conversion are stored in adres field of addat2. the current continuous mode remains active after the single conversion is completed. a full calibration sequence is performed after a reset. this full calibration lasts up to 40630 cpu clock cycles. during this time, the busy flag adbsy is set to indica te the operation. it compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. no conversion can be performed during this time: the bit adbsy shall be polled to verify when the calibration is over, and the module is able to start a conversion.
serial channels st10f273m 74/186 doc id 13453 rev 4 15 serial channels serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (asc0 and asc1) and two high-speed synchronous serial channel (ssc0 and ssc1). dedicated baudrate generators set up all standard baudrates without the requirement of oscillator tuning. for transm ission, reception and erroneous reception, separate interrupt vectors are provided for asc0 and ssc0 serial channel. a more complex mechanism of interrupt sources multiplexing is implemented for asc1 and ssc1 (xbus mapped). 15.1 asynchronous / sync hronous serial interfaces the asynchronous / synchronous serial interfaces (asc0 and asc1) provides serial communication between the st10f273m and other microcontrollers, microprocessors or external peripherals. 15.2 ascx in asynchronous mode in asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. parity framing and overrun error detection is provided to increase the reliability of data transfers. transmission and reception of data is double-buffered. full- duplex communication up to 1.25 mbaud (at 40 mhz of f cpu ) is supported in this mode. table 38. asc asynchronous baudrates by reload value and deviation errors s0brs = ?0?, f cpu = 40 mhz s0brs = ?1?, f cpu = 40 mhz baudrate (baud) deviation error reload value (hex) baudrate (baud) deviation error reload value (hex) 1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -7.0% 000a / 000b 112 000 +6.3% / -7.0% 0006 / 0007 56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000d / 000e 38 400 +1.7% / -1.4% 001f / 0020 38 400 +3.3% / -1.4% 0014 / 0015 19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002a / 002b 9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056 4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00ac / 00ad 2 400 +0.2% / 0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015a / 015b 1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02b5 / 02b6 600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056b / 056c 300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0ad8 / 0ad9 153 0.0% / 0.0% 1fe8 / 1fe9 102 0.0% / 0.0% 1fe8 / 1fe9
st10f273m serial channels doc id 13453 rev 4 75/186 note: the deviation errors given in the ta bl e 3 8 are rounded off. to avoid deviation errors use a baudrate crystal (providing a multiple of the asc0 sampling frequency). 15.3 ascx in synchronous mode in synchronous mode, data is transmitted or rece ived synchronously to a shift clock which is generated by the st10f273m. half-duplex communication up to 5 mbaud (at 40 mhz of f cpu ) is possible in this mode. note: the deviation errors given in the are rounded off. to avoid deviation errors use a baudrate crystal (providing a multiple of the asc0 sampling frequency). 15.4 high speed synchr onous serial interfaces the high-speed synchronous serial interfaces (ssc0 and ssc1) provides flexible high- speed serial communication between the st10f273m and other microcontrollers, microprocessors or external peripherals. the sscx supports full-duplex and half-duplex synchronous communication. the serial clock signal can be generated by the sscx itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data is double-buffered. a 16-bit baudrate generator provides the sscx with a separate serial clock signal. the serial channel sscx has its own dedicated 16-bit baudrate generator with 16-bit reload capability, a llowing baudrate generation independent from the timers. table 39. asc synchronous baudrates by reload value and deviation errors s0brs = ?0?, f cpu = 40 mhz s0brs = ?1?, f cpu = 40 mhz baudrate (baud) deviation error reload value (hex) baudrate (baud) deviation error reload value (hex) 5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -0.8% 002b / 002c 112 000 +2.6% / -0.8% 001c / 001d 56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003a / 003b 38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056 19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00ac / 00ad 9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015a / 015b 4 800 +0.1% / 0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02b5 / 02b6 2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / 0.0% 056b / 056c 1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0ad8 / 0ad9 900 0.0% / 0.0% 15b2 / 15b3 600 0.0% / 0.0% 15b2 / 15b3 612 0.0% / 0.0% 1fe8 / 1fe9 407 0.0% / 0.0% 1ffd / 1ffe
serial channels st10f273m 76/186 doc id 13453 rev 4 ta bl e 4 0 lists some possible baudrates against the required reload values and the resulting bit times for the 40 mhz cpu clock. the maximum is limited to 8 mbaud. table 40. ssc synchronous baudrate and reload values baudrate for f cpu = 40 mhz bit time reload value reserved - 0000h can be used only with f cpu = 32 mhz (or lower) - 0001h 6.6 mbaud 150ns 0002h 5 mbaud 200ns 0003h 2.5 mbaud 400ns 0007h 1 mbaud 1s 0013h 100 kbaud 10s 00c7h 10 kbaud 100s 07cfh 1 kbaud 1ms 4e1fh 306 baud 3.26ms ff4eh
st10f273m i2c interface doc id 13453 rev 4 77/186 16 i2c interface the integrated i 2 c bus module handles the transmission and reception of frames over the two-line sda/scl in accordance with the i 2 c bus specification. the i 2 c module can operate in slave mode, in master mode or in multi-master mode. it can receive and transmit data using 7-bit or 10-bit addressing. data can be transferred at speeds up to 400 kbit/s (both standard and fast i 2 c bus modes are supported). the module can generate three different types of interrupt: requests related to bus events, such as start or stop events, or arbitration lost requests related to data transmission requests related to data reception these requests are issued to the interrupt cont roller by three different lines, and identified as error, transmit, and re ceive interrupt lines. when the i 2 c module is enabled by setting bit xi2cen in xpercon register, pins p4.4 and p4.7 (where scl and sda are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. p4, dp4 and odp4 cannot influence the pin configuration. when the i 2 c cell is disabled (clearing bit xi2cen), p4.4 and p4.7 pins are standard i/ o controlled by p4, dp4 and odp4. the speed of the i 2 c interface can be selected between standard mode (0 to 100 khz) and fast i 2 c mode (100 to 400 khz).
can modules st10f273m 78/186 doc id 13453 rev 4 17 can modules the two integrated can modules (can1 and can2) are identical and handle the completely autonomous transmission and reception of can frames according to the can specification v2.0 part b (active). it is based on the c-can specification. each on-chip can module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. because of duplication of the can controllers, the following adjustments are to be considered: same internal register addresses of both can controllers, but with base addresses differing in address bit a8; separate chip select for each can module. refer to section 4: memory organization on page 21 . the can1 transmit line (can1_txd) is the alternate function of the port p4.6 pin and the receive line (can1_rxd) is the alternate function of the port p4.5 pin. the can2 transmit line (can2_txd) is the alternate function of the port p4.7 pin and the receive line (can2_rxd) is the alternate function of the port p4.4 pin. interrupt request lines of the can1 and can2 modules are connected to the xbus interrupt lines together with other x-peripherals sharing the four vectors. the can modules must be selected with corresponding canxen bit of xpercon register before the bit xpen of syscon register is set. the reset default configuration is: can1 enabled, can2 disabled. note: if one or both can modules is used, port 4 cannot be programmed to output all eight segment address lines. thus, only four segment address lines can be used, reducing the external memory space to 5 mbytes (1 mbyte per cs line). 17.1 configuration support it is possible that both can controllers are working on the same can bus, supporting together up to 64 message objects. in this configuration, both receive signals and both transmit signals are linked together when using the same can transceiver. this configuration is especially supported by providing open drain outputs for the can1_txd and can2_txd signals. the open drain function is controlled with the odp4 register for port p4: in this way it is possible to connect together p4.4 with p4.5 (receive lines) and p4.6 with p4.7 (transmit lines configured to be configured as open-drain). the user may also map internally both can modules on the same pins p4.5 and p4.6. in this way, p4.4 and p4.7 can be used either as general purpose i/o lines, or used for i 2 c interface. this is possible by setting bit canpar of the xmisc register. to access this register it is necessary to set bit xmiscen of the xpercon register and bit xpen of the syscon register. 17.2 can bus configurations depending on the application, can bus configuration may be one single bus with a single or multiple interfaces or a multip le bus with a single or multiple interfaces. the st10f273m can support both configurations.
st10f273m can modules doc id 13453 rev 4 79/186 17.2.1 single can bus the single can bus multiple interfaces conf iguration may be implemented using two can transceivers as shown in figure 14 . figure 14. connection to single can bus via separate can transceivers the st10f273m also supports single can bus multiple (dual) interfaces using the open drain option of the canx_txd output as shown in figure 15 . thanks to the or-wired connection, only one transceiver is required. in this case the design of the application must take in account the wire length and the noise environment. figure 15. connection to single can bus via common can transceivers &$1 5; 7; &$1b+ &$1b/ &$1exv &$1 5; 7; ;0,6&&$13$5 &$1 &$1 wudqvfh lyhu wudqvfhlyhu 3 3 3 3 ("1($'5 2' 2shq'udlq2xwsxw 9 &$1 &$1b+ &$1b/ &$1exv n: 2' wudqvfhlyhu ;0,6&&$13$5 &$1 5; 7; &$1 5; 7; 3 3 3 3 2' ("1($'5
can modules st10f273m 80/186 doc id 13453 rev 4 17.2.2 multiple can bus the st10f273m provides two can interfaces to support such kind of bus configuration as shown in figure 16 . figure 16. connecti on to two different can buses (for example for gateway application) 17.2.3 parallel mode in addition to previous configurations, a parallel mode is supported. this is shown in figure 17 . figure 17. connection to one can bus with internal parallel mode enabled 1. p4.4 and p4.7 when not used as can functions can be used as general purpose i/o while they cannot be used as external bus address lines. &$1b+ &$1b/ &$1 exv &$1b+ &$1b/ &$1 exv ;0,6&&$13$5 &$1 5; 7; &$1 5; 7; &$1 &$1 wudqvfhlyhu wudqvfhlyhu 3 3 3 3 ("1($'5 ;0,6&&$13$5 &$1 5; 7; 3 3 3 3 &$1 &$1b+ &$1b/ &$1exv wudqvfhlyhu &$1 5; 7; %rwk&$1hqdeohg ("1($'5
st10f273m real time clock doc id 13453 rev 4 81/186 18 real time clock the real time clock is an independent timer, in which the clock is derived directly from the clock oscillator on xtal1 (main oscillator) inpu t or xtal3 input (32 khz low-power oscillator) so that it can continue running even in idle or power-down modes (if so enabled). registers access is implemented onto the xbus. this module is designed with the following characteristics: generation of the current time and date for the system cyclic time based interrupt, on port2 externa l interrupts every ?rtc basic clock tick? and after n ?rtc basic clock ticks? ( n is programmable) if enabled 58-bit timer for long term measurement capability to exit the st10 chip from power-down mode (if pwdcfg of syscon set) after a programmed delay the real time clock is based on two main blocks of counters. the first block is a prescaler which generates a basic reference clock (for example, a 1 second period). this basic reference clock is provided by the 20-bit divider. this 20-bit counter is driven by an input clock derived from the on-chip cpu clock, predivided by a 1/64 fixed counter. this 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit prescaler register. the value of the 20-bit rtcp register determines the period of the basic reference clock. a timed interrupt request (rtcsi) may be sent on each basic reference clock period. the second block of the rtc is a 32-bit counter that may be initialized with the current system time. this counter is driven with the basic reference clock signal. in order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. the alarm register may be loaded with a reference date. an alarm interrupt request (rtcai), may be generated when the value of the counter matches the alarm register. the timed rtcsi and the alarm rtcai interrupt requests can trigger a fast external interrupt via the exisel register of port 2 and wake up the st10 chip when running power- down mode. using the rtcoff bit of the rtccon register, the user may switch off the clock oscillator when enteri ng the power-down mode. the last function implem ented in the rtc is to switch off the main on-chip oscillator and the 32 khz on chip oscillator if the st10 enters the power-down mode, so that the chip can be fully switched off (if rtc is disabled). at power-on, and after reset phase, if the presence of a 32 khz oscillation on xtal3 / xtal4 pins is detected, then the rtc counter is driven by this low frequency reference clock: when power-down mode is entered, the rtc can either be stopped or left running, and in both the cases the main oscillator is turned off, re ducing the power consumption of the device to the minimum required to keep on running the rtc counter and relative reference oscillator. this is also valid if st andby mode is entered (s witching off the main supply v dd ), since both the rtc and the low power oscillator (3 2 khz) are biased by the v stby . vice versa, when at power on and after reset, the 32 khz is not present, the main oscillator drives the rtc counter, and since it is powered by the main power supply, it cannot be maintained running in standby mode, while in power-down mode the main oscillator is maintained running to provide the reference to th e rtc module (if not disabled).
watchdog timer st10f273m 82/186 doc id 13453 rev 4 19 watchdog timer the watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. the watchdog timer is always enabled after a reset of the chip and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. therefore, the chip start-up procedure is always monitored. the software must be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. it pulls the rstout pin low in order to allow external hardware components to be reset. each of the different reset sources is indicated in the wdtcon register: watchdog timer reset in case of an overflow software reset in case of execution of the srst instruction short,long and power-on reset in case of hardware reset (and depending of reset pulse duration and rpd pin configuration) the indicated bits are cleared with the einit instruction. the source of the reset can be identified during the initialization phase. the watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. the high byte of the watchdog timer register can be set to a prespecified reload value (stored in wdtrel). each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. for security, rewrite wdtcon each time before the watchdog timer is serviced ta bl e 4 1 shows the watchdog time range for 40 mhz cpu clock. table 41. wdtrel reload value reload value in wdtrel prescaler for f cpu = 40 mhz 2 (wdtin = ?0?) 128 (wdtin = ?1?) ffh 12.8s 819.2s 00h 3.277ms 209.7ms
st10f273m system reset doc id 13453 rev 4 83/186 20 system reset system reset initializes the mcu in a predefined state. there are six ways to activate a reset state. the system start-up configuration is different for each case as shown in ta b l e 4 2 . the figures in the upcoming sections 20.2 , 20.3 , 20.5 and 20.6 use the following terminology: transparent = level of the pin affects the internal reset logic not transparent = level of the pin does not affect internal logic 20.1 input filter on the rstin input pin an on-chip rc filter is implemented. it is sized to filter all spikes shorter than 50ns. on the other hand, a valid pulse longer than 500ns is required for the st10 to recognize a reset command. in between 50ns and 500ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations. for this reason all minimum durations mentioned in this chapter for the different kinds of reset events must be carefully evaluated, taking into account the above requirements. in particular, for short hardware reset, wher e only 4 tcl is specified as minimum input reset pulse duration, the operating frequency is a key factor. examples: for a cpu clock of 40 mhz, 4 tcl is 50ns, so it would be filtered. in this case the minimum becomes the one imposed by the filter (that is 500ns). for a cpu clock of 4 mhz, 4 tcl is 500ns. in this case the minimum from the formula is coherent with the limi t imposed by the filter. table 42. reset event definition reset source flag rpd status conditions power-on reset ponr low power-on asynchronous hardware reset lhwr low t rstin > (1) 1. rstin pulse should be longer than 500ns (filter) and than settling time for configuration of port0. synchronous long hardware reset high t rstin > (1032 + 12)tcl + max(4 tcl, 500ns) synchronous short hardware reset shwr high t rstin > max(4 tcl, 500ns) t rstin (1032 + 12)tcl + max(4 tcl, 500ns) watchdog timer reset wdtr (2) 2. see next section 20.1 for more details on minimum reset pulse duration wdt overflow software reset swr (3) 3. the rpd status has no influence unless bidirectional reset is activated (bit bdrsten in syscon): rpd low inhibits the bidirectional reset on sw and wdt reset events, that is rstin is not activated (refer to sections 20.4 , 20.5 and 20.6 ). srst instruction execution
system reset st10f273m 84/186 doc id 13453 rev 4 20.2 asynchronous reset an asynchronous reset is triggered when rstin pin is pulled low while rpd pin is at low level. then the st10f273m is immediately (after the input filter delay) forced in reset default state. it pulls low rstout pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and i/o pin drivers to high-impedance, it pulls high port0 pins. note: if an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended. power-on reset the asynchronous reset must be used during the power-on of the device. depending on crystal or resonator frequency, the on-chip oscilla tor needs about 1ms to 10ms to stabilize (refer to section 24: electrical characteristics ), with an already stable v dd . the logic of the st10f273m does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. to ensure a proper reset sequence, the rstin pin and the rpd pin must be held at low level until the de vice clock signal is stabilized and the system configuration value on port0 is settled. at power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules. in particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8v for the core logic: this time is computed from when the external reference (v dd ) becomes stable (inside specification range, that is at least 4.5v). this is a constraint for the application hardware (external voltage regulator): the rstin pin assertion shall be extended to guarantee the volta ge regulator stabilization. a second constraint is imposed by the embedded flash. when booting from internal memory, starting from rstin releasing, it needs a maximum of 1ms for its initialization: before that, the internal reset (rst signal) is not released, so the cpu does not start code execution in internal memory. note: this is not true if external memory is used (pin ea held low during reset phase). in this case, once rstin pin is released, and after few cpu clock (filter delay plus 3...8 tcl), the internal reset signal rst is released as well, so the code execution can start immediately after. obviously, an eventual access to the data in internal flash is forbidden before its initialization phase is complete d: an eventual access during starting phase will return ffffh (just at the beginning), wh ile later 009bh (an illegal opc ode trap can be generated). at power-on, the rstin pin shall be tied low for a minimum time that includes also the start- up time of the main oscillator (t stup = 1ms for resonator, 10ms for crystal) and pll synchronization time (t psup = 200s): this means that if the internal flash is used, the rstin pin could be released before the main oscillator and pll are stable to recover some time in the start-up phase (flash initialization only needs stable v 18 , but does not need stable system clock since an inte rnal dedicated oscillator is used). warning: it is recommended to provide the external hardware with a current limitation circuitry. this is necessary to avoid permanent damage of the device during the power-on transient, when the capacitance on v 18 pin is charged. for the on-chip voltage regulator functionality 10nf is sufficient:
st10f273m system reset doc id 13453 rev 4 85/186 in any case, a maximum of 100nf on v 18 pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware). external current limitation is nevertheless also recommended to avoid risks of damage in case of a temporary short between v 18 and ground: the internal 1.8v drivers are sized to drive currents of several tens of amps, so the current must be limited by the external hardware. the limit of current is imposed by power dissipation considerations (refer to section 24: electrical characteristics ). in figures 18 and 19 asynchronous power-on timing diagrams are shown, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded iflash module when selected. caution: never power the device without keeping the rstin pin grounded: the device could enter into unpredictable states, risking also permanent damage.
system reset st10f273m 86/186 doc id 13453 rev 4 figure 18. asynchronous power-on reset (ea = 1) 567) 3>@ 3> @ wudqvsduhqw wudqvsduhqw 3>@ qrww qrwwudqvsduhqw )/$567 9 ;7$/ d 7&/ 567 d pv /dwfklqjsrlqwri3ruwiru v\v whpvwduwxsfrqiljxudwlrq 9 '' t pvirurqfkls95 (*vwdelol]dwlrq 53' ,%86&6 d pviruuhvrqdwrurvflood wlrq3//vwdelol]dwlrq d pvirufu\vwdorvflo odwlrq3//vwdelol]dwlrq 567,1 $iwhu)lowhu d qv t qv 7&/ 7&/ ,qwhuqdo qrww qrw w qrww ("1($'5
st10f273m system reset doc id 13453 rev 4 87/186 figure 19. asynchronous power-on reset (ea = 0) 1. 3 to 8 tcl depending on clock source selection hardware reset the asynchronous reset must be used to recover from catastrophic situations of the application. it may be triggered by the hardware of the application. internal hardware logic and application circuitry are described in reset circuitry chapter and figures 31 , 32 and 33 . it occurs when rstin is low and rpd is detected (or becomes) low as well. 567,1 3>@ 3>@ qrww wudqvsduhqw qrww 3>@ qrww qrw wudqvsduhqw 9 ;7$/ 7&/ 567 /dwfklqjsrlqwri3ruwiru v\vwhpvwduwxsfrqiljxudwlrq 9 '' t pvirurqfkls95(*vwdelol]dwlrq 53' $/( t pviruuhvrqdwrurvfloodwlrq3//vwdelol]dwlrq t pvirufu\vwdorvfloodwlrq3//vwdelol]dwlrq 567) d qv $iwhu)lowhu t qv 7&/ wudqvsduhqw 7&/ ("1($'5
system reset st10f273m 88/186 doc id 13453 rev 4 figure 20. asynchronous hardware reset (ea = 1) 1. longer than port0 settling time + pll synchroni zation (if needed, that is p0(15:13) changed). longer than 500ns to take into account of input filter on rstin pin. 567) 3>@ 3>@ wudqvsduhqw wu dqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw )/$567 d 7&/ 567 d pv /dwfklqjsrlqwri3ruwiru v\vwhpvwduwxsfrqiljxudwlrq 53' ,%86&6 qrwwudqvsduhqw qrw wudqvsduhqw $iwhu)lowhu 567,1 d qv t qv d qv t qv 7&/ lqwhuqdo 7&/ qrww qrww ("1($'5
st10f273m system reset doc id 13453 rev 4 89/186 figure 21. asynchronous hardware reset (ea = 0) 1. longer than port0 settling time + pll synchroni zation (if needed, that is p0(15:13) changed). longer than 500ns to take into account of input filter on rstin pin. 2. 3 to 8 tcl depending on clock source selection. exit from asynchronous reset state when the rstin pin is pulled high, the device restarts: as already mentioned, if internal flash is used, the restarting occurs after the embedded flash initialization routine is completed. the system configuration is latched from port0: ale, rd and wr /wrl pins are driven to their inactive level. the st10f273m starts program execution from memory location 00'0000h in code segmen t 0. this starting location will ty pically point to the general initialization routine. the timings of as ynchronous hardware reset sequence are summarized in figure 20 and figure 21 . 20.3 synchronous reset (warm reset) a synchronous reset is triggered when rstin pin is pulled low while rpd pin is at high level. in order to properly activate the internal reset logic of the device, the rstin pin must be held low, at least, during 4 tcl (two periods of cpu clock): refer also to section 20.1 for details on minimum reset pulse duration. the i/o pins are set to high impedance and rstout pin is driven low. after rstin level is detected, a short duration of a maximum of 12 tcl (six periods of cpu clock) elapses, du ring which pending internal hold states are cancelled and the current internal access cycle if any is completed. external bus cycle is aborted. the internal pull-down of rstin pin is activated if bit bdrsten of syscon 567) 3>@ 3> @ wudqvsduhqw qrww wudqvsduhqw qrww 3>@ qrww qr wwudqvsduhqw 7&/ 56 7 /dwfklqjsrlqwri3ruwiru v\v whpvwduwxsfrqiljxudwlrq 53' $/( qrwwudqvsduhqw qrwwudqvsduhqw $iwhu)lowhu 567, 1 d qv t qv d qv t qv 7&/ 7&/ ("1($'5
system reset st10f273m 90/186 doc id 13453 rev 4 register was previously set by software. note that this bit is always cleared on power-on or after a reset sequence. short and long synchronous reset once the first maximum 16 tcl are elapsed (4+12tcl), the internal reset sequence starts. it is 1024 tcl cycles long: at the end of it, and after other 8tcl the level of rstin is sampled (after the filter, see rstf in the drawings): if it is al ready at high level, only short reset is flagged (refer to chapter 19 for details on reset flags); if it is recognized still low, the long reset is flagged as well. the major difference between long and short reset is that during the long reset, also p0(15:13) become transparent, so it is possible to change the clock options. warning: in case of a short pulse on rstin pin, and when bidirectional reset is enable d, the rstin pin is held low by the internal circuitry. at the end of the 1024 tcl cycles, the rtsin pin is released, but due to the presence of the input analog filter the internal input reset signal (rstf in the drawings) is released later (from 50 to 500 ns). this delay is in parallel with the additional 8 tcl, at the end of which the internal input reset line (rstf ) is sampled, to decide if the reset event is short or long. in particular: if 8 tcl > 500ns (f cpu < 8 mhz), the reset event is always recognized as short if 8 tcl < 500ns (f cpu > 8 mhz), the reset event could be recognized either as short or long, depending on the real filter delay (between 50 and 500ns) and the cpu frequency (rstf sampled high means short reset, rstf sampled low means long reset). note that in case a long reset is recognized, once the 8 tcl are elapsed, the p0(15:13) pins becomes transparent, so the system clock can be reconfigured. the port returns not transparent 3-4tcl after the internal rstf signal becomes high. the same behavior just described, occurs also when unidirectional reset is selected and rstin pin is held low till the end of the intern al sequence (exactly 1024tcl + max 16 tcl) and released exactly at that time. note: when running with cpu frequency lower than 40 mhz, the minimum valid reset pulse to be recognized by the cpu (4 tcl) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a cpu reset (shorter than 4 tcl): this would generate a flash reset but not a system reset. in this condition, the flash answers always with ffffh, which leads to an ille gal opcode and cons equently a trap event is generated. exit from synchronous reset state the reset sequence is extended until rstin level becomes high. besi des, it is internally prolonged by the flash initialization when ea = 1 (internal memory selected). then, the code execution restarts. the system configuration is latched from port0, and ale, rd and wr /wrl pins are driven to their inactive level. the st10f273m starts program execution from memory location 00'0000h in code segment 0. this star ting location will typically point to the general initialization routine. timing of synchronous reset sequence are summarized in figure 22 and figure 23 where a short reset event is shown, with particular emphasis on the fact that it can degenerate into long reset: the two figures show the behavior when
st10f273m system reset doc id 13453 rev 4 91/186 booting from internal or external memory respectively. figure 24 and figure 25 report the timing of a typical synchronous long reset, again when booting from internal or external memory. synchronous reset and rpd pin whenever the rstin pin is pulled low (by external hardware or as a consequence of a bidirectional reset), the rpd internal weak pull-down is activated. the external capacitance (if any) on rpd pin is slowly discharged through the internal weak pull-down. if the voltage level on rpd pin reaches the input low threshold (around 2.5v), the reset event becomes immediately asynchronous. in case of hardware reset (short or long) the situation goes immediately to the one illustrated in figure 20 . there is no effect if rpd comes again above the input threshold: the asynchronous reset is completed coherently. to grant the normal completion of a synchronous reset, the value of the capacitance shall be big enough to maintain the voltage on rpd pin sufficient high along the duration of the internal reset sequence. for a software or watchdog reset events, an active synchronous reset is completed regardless of the rpd status. it is important to highlight that the signal that makes rpd status transparent under reset is the internal rstf (after the noise filter).
system reset st10f273m 92/186 doc id 13453 rev 4 figure 22. synchronous short / long hardware reset (ea = 1) 1. rstin assertion can be released there. refer also to section 21.1 for details on minimum pulse duration. 2. if during the reset condition (rstin low), rpd volta ge drops below the threshold voltage (about 2.5v for 5v operation), the asynchronous rese t is then immediately entered. 3. rstin pin is pulled low if bit bdrsten (bit 3 of syscon register) was previously set by software. bit bdrsten is cleared after reset. 4. minimum rstin low pulse duration shall also be l onger than 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1 ). 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw )/$567 567 d pv 7&/ d 7&/ 9 53' !9$v\qfkurqrxv5hvhwqrwhqwhuhg ?$'lvfkdujh 53' 567287 $wwklvwlph567) lvvdpsohg+,*+ru/2: vrlwlv6+257ru/21*uhvhw $iwhu)lowhu 567,1 7&/ d 7&/ d 7&/ d qv t qv d qv t qv d qv t qv ,%86&6 7&/ ,qwhuqdo 7&/ qrww ("1($'5
st10f273m system reset doc id 13453 rev 4 93/186 figure 23. synchronous short / long hardware reset (ea = 0) 1. rstin assertion can be released there. refer also to section 21.1 for details on minimum pulse duration. 2. if during the reset condition (rstin low), rpd volta ge drops below the threshold voltage (about 2.5v for 5v operation), the asynchronous rese t is then immediately entered. 3. 3 to 8 tcl depending on clock source selection. 4. rstin pin is pulled low if bit bdrsten (bit 3 of syscon register) was previously set by software. bit bdrsten is cleared after reset. 5. minimum rstin low pulse duration shall also be l onger than 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1 ). 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhqw qrww 3>@ qrww qrw wudqvsduhqw 567 7&/ 7&/ 953'!9$v\q fkurqrxv5hvhwqrwhqwhuhg ?$'lvfkdujh 53' 567287 $wwklvwlph567)l vvdpsohg+,*+ru/2: vr lwlv6+257ru/21*uhvhw $iwhu)lowhu 56 7,1 7&/ d 7&/ d 7&/ d qv t qv d qv t qv d qv t qv $ /( 7&/ 7&/ qrww ("1($'5
system reset st10f273m 94/186 doc id 13453 rev 4 figure 24. synchronous long hardware reset (ea = 1) 1. if during the reset condition (rstin low), rpd voltage drops below the threshold voltage (about 2.5v for 5v operation), the asynchronous reset is then imm ediately entered. even if rpd returns above the threshold, the reset is defin itely taken as asynchronous. 2. minimum rstin low pulse duration shall also be longer th an 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1 ). 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhqw qrww 3>@ qrww qrw wudqvsduhqw )/$567 567 d pv 7&/ d 7&/ 9 53' !9$v\qfkurqrxvuhvhw ?$'lvfkdujh 53 ' 567287 $wwklvwlph567) lvvdpsohg/2: vr lwlvghilqlwho\/21*uhvhw $iwhu)lowhu 567,1 7&/ d 7&/ d 7&/ d qv t qv d qv t qv d qv t qv ,%86&6 7&/ qrww wudqvsduhqw qrww 7&/ ,qwhuqdo qrwhqwhuhg ("1($'5
st10f273m system reset doc id 13453 rev 4 95/186 figure 25. synchronous long hardware reset (ea = 0) 1. if during the reset condition (rstin low), rpd voltage drops below the threshold voltage (about 2.5v for 5v operation), the asynchronous re set is then immediately entered. 2. minimum rstin low pulse duration shall also be longer th an 500ns to guarantee the pulse is not masked by the internal filter (refer to section 21.1 ). 3. 3 to 8 tcl depending on clock source selection. 20.4 software reset a software reset sequence can be triggered at any time by the protected srst (software reset) instruction. this instruction can be deliberately executed within a program, for example, to leave bootstrap loader mode, or on a hardware trap that reveals system failure. on execution of the srst instruction, the internal reset sequence is started. the microcontroller behavior is the same as for a synchronous short reset, except that only bits p0.12...p0.8 are latched at the end of the reset sequence, while previously latched, bits p0.7...p0.2 are cleared (that is written at ?1?). a software reset is always taken as synchronous: there is no influence on software reset behavior with rpd status. in case bidirectional reset is selected, a software reset event pulls rstin pin low: this occurs only if rpd is high; if rpd is low, rstin pin is not pulled low even though bidirect ional reset is selected. 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw 567 7&/ 7&/ 9 53' !9$v\qfkurqrxvuhvhwqrwhqwhuhg ?$'lvfkdujh 53 ' 567287 $wwklvwlph567) lvvdpsohg/2: vr lwlv/21*uhvhw $iwhu)lowhu 567,1 7&/ 7&/ 7&/ d qv t qv d qv t qv d qv t qv $ /( 7&/ qrww wudqvsduhqw 7&/ ("1($'5
system reset st10f273m 96/186 doc id 13453 rev 4 refer to the next figure 26 and figure 27 for unidirectional sw reset timing, and to figure 28 , figure 29 and figure 30 for bidirectional. 20.5 watchdog timer reset when the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will over flow and trigger the reset sequence. unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use ready , or if ready is sampled active (low) after the programmed wait states. when ready is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. then the internal reset sequence is started. bit p0.12...p0.8 are latched at the end of the reset sequence and bit p0.7...p0.2 are cleared (that is written at ?1?). a watchdog reset is always taken as synchronous: there is no influence on watchdog reset behavior with rpd status. in case bidirectional reset is selected, a watchdog reset event pulls rstin pin low: this occurs only if rpd is high; if rpd is low, rstin pin is not pulled low even though bidirect ional reset is selected. refer to the next figure 26 and figure 27 for unidirectional sw reset timing, and to figure 28 , figure 29 and figure 30 for bidirectional. figure 26. sw / wdt unidirectional reset (ea = 1) 3>@ qrwwudqvsduhqw 3>@ wudqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw 567 7&/ 567287 567,1 ,%86&6 7&/ 3>@ qrwwudqvsduhqw )/$567 d pv ,qwhuqdo d 7&/ ("1($'5
st10f273m system reset doc id 13453 rev 4 97/186 figure 27. sw / wdt unidirectional reset (ea = 0) 20.6 bidirectional reset as shown in the previous sections, the rstout pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). rstout pin stays active low beyond the end of the initialization routine, until the protected einit instruct ion (end of initializ ation) is completed. the bidirectional reset function is useful when external devices require a reset signal but cannot be connected to rstout pin, because rstout signal lasts during initialization. it is, for instance, the case of external memo ry running initialization routine before the execution of einit instruction. bidirectional reset function is enabled by setting bit 3 (bdrsten) in syscon register. it only can be enabled during the initialization ro utine, before einit in struction is completed. when enabled, the open drain of the rstin pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). at the end of the internal reset sequence the pull down is released and: after a short synchro nous bidirectional hardware reset, if rstf is sampled low eight tcl periods after the internal reset sequence completion (refer to figure 22 and figure 23 ), the short reset becomes a long reset. on the contrary, if rstf is sampled high the device simply exits reset state. after a software or watchdog bidirectional reset, the device exits from reset. if rstf remains still low for at least four tcl peri ods (minimum time to recognize a short hardware reset) after the reset exiting (refer to figure 28 and figure 29 ), the software 3>@ qrwwudqvsduhqw 3>@ wudqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw 567 7&/ 567287 567,1 $/( 7&/ 3>@ qrwwudqvsduhqw ("1($'5
system reset st10f273m 98/186 doc id 13453 rev 4 or watchdog reset become a short hardware reset. on the contrary, if rstf remains low for less than 4 tcl, the device simply exits reset state. the bidirectional reset is not effective in ca se rpd is held low, when a software or watchdog reset event occurs. on the contrary, if a software or watchdog bidirectional reset event is active and rpd becomes low, the rstin pin is immediately released, while the internal reset sequence is completed regardless of rpd status change (1024 tcl). note: the bidirectional reset function is disabled by any reset sequence (bit bdrsten of syscon is cleared). to be activated again it must be enabled during the initialization routine. wdtcon flags similarly to what already highlighted in the previous section when discussing about short reset and the degeneration into long reset, similar situations may occur when bidirectional reset is enabled. the presence of the internal filter on rstin pin introduces a delay: when rstin is released, the internal signal after the filter (see rstf in the drawings) is delayed, so it remains still active (low) for a while. it means that depending on the internal clock speed, a short reset may be recognized as a long reset: the wdtcon flags are set accordingly. besides, when either software or watchdog bidirectional reset events occur, again when the rstin pin is released (at the end of the internal reset sequence), the rstf internal signal (after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8tcl after the completion of the internal sequence, the level of rstf signal is sampled, and if recognized still low a hardware reset sequence starts, and wdtcon will flag this last event, masking the previous one (software or watchdog reset). typically, a short hardware reset is recognized, unless the rstin pin (and consequently internal signal rstf ) is sufficiently held low by the external hardware to inject a long hardware reset. after this occurrence, the init ialization routine is not able to recognize a software or watchdog bidirectional reset event, since a different source is flagged inside wdtcon register. this phenomenon does not o ccur when internal flash is selected during reset (ea = 1), since the initialization of the flash itself extend the internal reset duration well beyond the filter delay. the next figure 28 , figure 29 and figure 30 summarize the timing for software and watchdog timer bidirectional reset events: in particular figure 30 shows the degeneration into hardware reset.
st10f273m system reset doc id 13453 rev 4 99/186 figure 28. sw / wdt bi directional reset (ea =1) 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhq w qrww 3>@ qrww qr wwudqvsduhq w 567 7&/ 567287 $iwhu)lowhu 567,1 d qv t qv d qv t qv ,%86&6 7&/ )/$567 d pv d 7&/ ,qwhuqdo 3>@ qrwwudqvsduhqw ("1($'5
system reset st10f273m 100/186 doc id 13453 rev 4 figure 29. sw / wdt bi directional reset (ea = 0) 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw 567 7&/ 567287 $wwklvwlph567) lvvdpsohg+,*+ vr6:ru:'75hvhwlviodjjhglq:'7&21 $iwhu)lowhu 567,1 d qv t qv d qv t qv $/( 7&/ 3>@ qrwwudqvsduhqw ("1($'5
st10f273m system reset doc id 13453 rev 4 101/186 figure 30. sw / wdt bi directional reset (ea = 0) followed by a hw reset 20.7 reset circuitry internal reset circuitry is described in figure 33 . the rstin pin provides an internal pull-up resistor of 50k to 250k (the minimum reset time must be calculated using the lowest value). it also provides a programmable (bdrsten bit of syscon register) pull-down to output internal reset state signal (s ynchronous reset, watchdog timer reset or software reset). this bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to rstout pin. this is the case of an external memory runn ing codes before einit (e nd of initialization) instruction is executed. rstout pin is pulled high only when einit is executed. the rpd pin provides an internal weak pull-down resistor which discharges external capacitor at a typical rate of 200a. if bit pw dcfg of syscon register is set, an internal pull-up resistor is activated at the end of th e reset sequence. this pull-up will charge any capacitor connected on rpd pin. the simplest way to reset the st10f273m is to insert a capacitor c1 between rstin pin and v ss , and a capacitor between rpd pin and v ss (c0) with a pull-up resistor r0 between rpd pin and v dd . the input rstin provides an internal pull-up device equalling a resistor of 50k to 250k (the minimum reset time must be determ ined by the lowest value). select c1 3>@ qrwwudqvsduhqw 567) 3>@ wudqvsduhqw qrww 3>@ qrww qrwwudqvsduhqw 567 7&/ 567287 $wwklvwlph567) lvvdpsohg/2: vr+:5hvhwlvhqwhuhg $iwhu)lowhu 567,1 d qv t qv $/( 7&/ d qv t qv 3>@ qrwwudqvsduhqw ("1($'5
system reset st10f273m 102/186 doc id 13453 rev 4 that produce a sufficient discha rge time to permit the internal or external oscillator and / or internal pll and the on-chip voltage regulator to stabilize. to ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long peri od of time to stabilize, an as ynchronous hardware reset is required during power-up. for this reason, it is recommended to connect the external r0-c0 circuit shown in figure 31 to the rpd pin. on power-up, the logical low level on rpd pin forces an asynchronous hardware reset when rstin is asserted low. the external pull-up r0 will then charge the capacitor c0. note that an internal pull- down device on rpd pin is turned on when rstin pin is low, and causes the external capacitor (c0) to begin discharging at a typical rate of 100-200a. with this mechanism, after power-up reset, short low pulses applied on rstin produce synchronous hardware reset. if rstin is asserted longer than the time needed for c0 to be discharged by the internal pull-down device, then the device is forced in an asynchronous reset. this mechanism insures recovery from very catastrophic failure. figure 31. minimum external reset circuitry the minimum reset circuit of figure 31 is not adequate when the rstin pin is driven from the st10f273m itself during software or watchdog triggered resets, because of the capacitor c1 that will keep the voltage on rstin pin above v il after the end of the internal reset sequence, and thus will trigger an asynchronous reset sequence. figure 32 shows an example of a reset circuit. in this example, r1-c1 external circuit is only used to generate power-up or manual reset, and r0-c0 circuit on rpd is used for power-up reset and to exit from power-down mode. diode d1 creates a wired-or gate connection to the reset pin and may be replaced by open-collector schmitt trigger buffer. diode d2 provides a faster cycle time for repetitive power-on resets. r2 is an optional pull-up for faster recovery and correct biasing of ttl open collector drivers. 567287 53' 567, 1 & d+dugzduh 9 && & 5 e)rusrzhuxs dqglqwhuuxswleoh srzhugrzq ([whuqdokdugzduh uhvhw pr gh uhvhw 67)0 ("1($'5
st10f273m system reset doc id 13453 rev 4 103/186 figure 32. system reset circuit figure 33. internal (simplified) reset circuitry 53' 567, 1 9 '' & 5 ([whuqdokdugzduh 9 '' 5 & 5 ' ' rg ([whuqdo uhvhwvrxufh 2shqgudlqlqyhuwhu 9 '' 67)0 ("1($'5 567287 (,1,7,qvwuxfwlrq 7uljjhu &ou &orfn 5hvhw6wdwh 0dfklqh ,qwhuqdo 5hvhw 6ljqdo 5hvhw6htxhqfh &38&orfn&\fohv 65 67lqvwuxfwlrq zdwfkgrjryhuiorz 567,1 9 && %'567(1 9 && 53' :hdnsxoogrzq a p $ )urpwr([lw 3rzhugrzq &lufxlw $v\qfkurqrxv 5hvhw &ou 4 6hw ("1($'5
system reset st10f273m 104/186 doc id 13453 rev 4 20.8 reset application examples the next two timing diagrams ( figure 34 and figure 35 ) provide additional examples of bidirectional internal reset events (software and watchdog) including in particular the external capacitances charge and di scharge transients (refer also to figure 32 for the external circuit scheme). figure 34. example of software or watchdog bidirectional reset (ea = 1) 9,/ 9,+ 567287 567,1 567) lghdo 7ilowhu567 qv 7&/xv pv&fkdujh 7ilowhu567 qv 53' 9,/ 567 :'7&21 >@ (,1,7 k & k k 3>@ 7&/ 3>@ 3>@ 3>@ /dwfklqjsrlqw /dwfklqjsrlqw /dwfklqjsrlqw /dwfklqjsrlqw qrw wudqvsduhqw qrwwudqvsduhqw qrwwudqvsduhqw qrw wudqvsduhqw qrw wudqvsduhqw qrwwudqvsduhqw qrw wudqvsduhqw qrwwudqvsduhqw wudqvsduhqw wudqvsduhqw wudqvsduhqw 7&/ 7&/ &k ("1($'5
st10f273m system reset doc id 13453 rev 4 105/186 figure 35. example of software or watchdog bidirectional reset (ea = 0) 9,/ 9,+ 567287 567,1 567) lghdo 7ilowhu567 qv 7&/xv pv&fkdujh 7ilowhu567 qv 53' 9,/ 567 :'7&21 >@ (,1,7 k & k k 3>@ 7&/ 3>@ 3>@ 3>@ /dwfklqjsrlqw /dwfklqjsrlqw /dwfklqjsrlqw /dwfklqjsrlqw qrw wudqvsduhqw qrwwudqvsduhqw qrwwudqvsduhqw qrw wudqvsduhqw qrw wudqvsduhqw qrwwudqvsduhqw qrw wudqvsduhqw qrwwudqvsduhqw wudqvsduhqw wudqvsduhqw wudqvsduhqw 7&/ 7&/ &k ("1($'5
system reset st10f273m 106/186 doc id 13453 rev 4 20.9 reset summary the following table summarizes the different reset events. table 43. reset event event rpd ea bidir synch. asynch. rstin wdtcon flags min max ponr lhwr shwr swr wdtr power-on reset 0 0 n asynch. 1 ms (vreg) 1.2 ms (reson. + pll) 10.2 ms (crystal + pll) - 11110 0 1 n asynch. 1ms (vreg) - 1 1 1 1 0 1 x x forbidden xxy - hardware reset (asynchronous) 0 0 n asynch. 500ns - 0 1 1 1 0 0 1 n asynch. 500ns - 0 1 1 1 0 0 0 y asynch. 500ns - 0 1 1 1 0 0 1 y asynch. 500ns - 0 1 1 1 0 short hardware reset (synchronous) (1) 1 0 n synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 1 1 n synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 1 0 y synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 activated by internal logic for 1024 tcl 1 1 y synch. max (4 tcl, 500ns) 1032 + 12 tcl + max(4 tcl, 500ns) 00110 activated by internal logic for 1024 tcl long hardware reset (synchronous) 1 0 n synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 1 1 n synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 1 0 y synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 activated by internal logic only for 1024 tcl 1 1 y synch. 1032 + 12 tcl + max(4 tcl, 500ns) - 01110 activated by internal logic only for 1024 tcl
st10f273m system reset doc id 13453 rev 4 107/186 the start-up configurations and some system features are selected on reset sequences as described in ta b l e 4 4 and figure 36 . ta bl e 4 4 describes the system configuration latched on port0 in the six different reset modes. figure 36 summarizes the state of bits of port0 latched in rp0h, syscon, buscon0 registers. software reset (2) x 0 n synch. not activated 0 0 0 1 0 x 0 n synch. not activated 0 0 0 1 0 0 1 y synch. not activated 0 0 0 1 0 1 1 y synch. activated by internal logic for 1024 tcl 0 0 0 1 0 watchdog reset (2) x 0 n synch. not activated 0 0 0 1 1 x 0 n synch. not activated 0 0 0 1 1 0 1 y synch. not activated 0 0 0 1 1 1 1 y synch. activated by internal logic for 1024 tcl 0 0 0 1 1 1. it can degenerate into a long hardware reset and consequently differently flagged (see section 20.3 for details). 2. when bidirectional is active (and with rpd = 0), it can be followed by a short hardware reset and consequently differently flagged (see section 20.6 for details). table 43. reset event (continued) event rpd ea bidir synch. asynch. rstin wdtcon flags min max ponr lhwr shwr swr wdtr table 44. port0 latched configuration for the different reset events x: pin is sampled -: pin is not sampled port0 clock options segment address lines chip selects wr configuration bus type reserved bsl reserved reserved adapt mode emu mode sample event p0h.7 p0h.6 p0h.5 p0h.4 p0h.3 p0h.2 p0h.1 p0h.0 p0l.7 p0l.6 p0l.5 p0l.4 p0l.3 p0l.2 p0l.1 p0l.0 software reset ---xxxxxxx------ watchdog reset ---xxxxxxx------ synchronous short hardware reset - - - x x x x x x x x x x x x x synchronous long hardware reset xxxxxxxxxxxxxxxx asynchronous hardware reset xxxxxxxxxxxxxxxx asynchronous power-on reset xxxxxxxxxxxxxxxx
system reset st10f273m 108/186 doc id 13453 rev 4 figure 36. port0 bits latched into the different registers after reset / / / / / / + + + + / / + + + + (08 $'3 :5 & &6 6(/ 6$/6 (/ %867< 3 53 + &o rfn 3ruw /rjlf 3ruw /rjlf 6< 6&21 %86&21 ,qwhuqdo&rqwuro/rjlf &/.&) * 3/ 3/ %<7',6 :5& )* 3257 %rrwvwuds/rdghu *hq hudwru &/.&) * 6$/6 (/ &66 ( /:5 & %6/ 5hv ($ 967%< 52 0 (1 3/ %86 $&7 $/( &7/ %7< 3 ("1($'5
st10f273m power reduction modes doc id 13453 rev 4 109/186 21 power reduction modes three different power reduction modes with different levels of power reduction have been implemented in the st10f273m. in idle mode only the cpu is stopped, while peripherals still operate. in power-down mode both the cpu and peripherals ar e stopped. in standby mode the main power supply (v dd ) can be turned off while a portion of the internal ram remains powered via v stby dedicated power pin. idle and power-down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections. standby mode is entered by simply removing v dd , holding the mcu under reset state. note: all external bus actions are completed before idle or power-down mode is entered. however, idle or power-down mode is not entered if ready is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 21.1 idle mode idle mode is entered by running the idle protected instruction. the cpu operation is stopped and the peripherals still run. idle mode is terminated by any interrupt request. whether or not the interrupt is serviced, the instruction following the idle instruction will be executed after the re turn from interrupt (reti) instruction, and the cpu then resumes the normal program. 21.2 power-down mode power-down mode starts by running the pwrdn protected instruction. the internal clock is stopped and all mcu parts including the watchdog timer are on hold. the only exception could be the real time clock if programmed accordingly in conjuction with selecting one of the two oscillator circuits (either the main or the 32 khz on-chip oscillator). if the real time clock module is used when the device is in power-down mode, a reference clock is needed. in this case, two possible configurations may be selected by the user application according to the desired level of power reduction: a 32 khz crystal is connected to the on-chi p low-power oscillator (pins xtal3 / xtal4) and running. in this case the main oscillator is stopped when power-down mode is entered, while the real time clock continues counting using a 32 khz clock signal as reference. the pr esence of a running low-power osc illator is detected after the power- on: this clock is immediately assumed (if present, or as soon as it is detected) as reference for the real time clock counter an d it will be maintained indefinitely (unless specifically disabled via software). only the main oscillator is running (xtal1 / xtal2 pins). in this case the main oscillator is not stopped when power-down is entered, and the real time clock continues counting using the main oscillator clock signal as reference. there are two different operating power-down modes: protected mode and interruptible mode.
power reduction modes st10f273m 110/186 doc id 13453 rev 4 before entering power-down mode (by executing the instruction pwrdn), bit vregoff in the xmisc register must be set. note: leaving the main voltage regulator active during power-down may lead to unexpected behavior (example: cpu wake-up) and power consumption higher than what is specified. 21.2.1 protected power-down mode this mode is selected when pwdcfg (bit 5) of syscon regist er is cleared. the protected power-down mode is only activated if the nmi pin is pulled low when executing pwrdn instruction (this means that the pwrd instruction belongs to the nmi software routine). this mode is only deactivated with an external hardware reset on rstin pin. 21.2.2 interruptible power-down mode this mode is selected when pwdcfg (b it 5) of syscon register is set. the interruptible power-down mode is only activated if all the enabled fast external interrupt pins are in their inactive level. this mode is deactivated with an external reset applied to rstin pin or with an interrupt request applied to one of the fast external interrupt pins, or with an interrupt generated by the real time clock, or with an interrupt generated by the activity on can?s and i 2 c module interfaces. to allow the internal pll and clock to stabilize, the rstin pin must be held low according the recommendations described in section 20: system reset on page 83 . an external rc circuit must be connected to rpd pin, as shown in the figure 37 . figure 37. external rc circuitry on rpd pin to exit power-down mode with an external interrupt, an exxin (x = 7...0) pin has to be asserted for at least 40ns. 21.3 standby mode in standby mode, it is possible to turn off the main v dd provided that v stby is available through the dedicated pin of the st10f273m. to enter standby mode it is mandatory to held the device under reset: once the device is under reset, the ram is disabled (see xram2en bit of xpercon register), and its digital interface is frozen in order to avoid any kind of data corruption. a dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65v in standby mode) to bias all those circuits that shall remain 53' 9 '' & 5 n : plqlpxp ?) 7\slfdo 67)0 ("1($'5
st10f273m power reduction modes doc id 13453 rev 4 111/186 active: the portion of xram (16 kbytes for st10f273m), the rtc counters and 32 khz on- chip oscillator amplifier. in normal running mode (that is, when main v dd is on) the v stby pin can be tied to v ss during reset to exercise the ea functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with v stby (see in particular the 32 khz oscillator used in conjunction with real time clock module), is granted by the active main v dd . it must be noted that standby mode can generate problems associated with the usage of different power supplies in cmos systems; particular attention must be paid when the st10f273m i/o lines are interfaced with other external cmos integrated circuits: if v dd of st10f273m becomes (for example, in standby mode) lower than the output level forced by the i/o lines of these external integrated circuits, the st10f273m could be directly powered through the inherent diode existing on st10f273m output driver circuitry. the same is valid for st10f273m interfaced to active/inactive communication buses during standby mode: current injection can be generated through the inherent diode. furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the st10f273m device). the device standby mode current (i stby ) may vary while v dd to v stby (and vice versa) transition occurs: some current flows between v dd and v stby pins. system noise on both v dd and v stby can contribute to increase this phenomenon. 21.3.1 entering standby mode as already stated, to enter standby mode the xram2en bit in the xpercon register must be cleared: this allows the ram interface to be frozen immediately, avoiding any data corruption. as a consequence of a reset event, the ram power supply is switched to the internal low-voltage supply v 18sb (derived from v stby through the low-power voltage regulator). the ram interface remains frozen until the bit xram2en is set again by software initialization routine (at next exit from main v dd power-on reset sequence). since v 18 is falling down (as a consequence of v dd turning off), it can happen that the xram2en bit is no longer able to guarantee its content (logic ?0?), being the xpercon register powered by internal v 18 . this does not generate any problem, because the standby mode switching dedicated circuit continues to confirm the ram interface freezing, irrespective the xram2en bit content; xram 2en bit status is considered again when internal v 18 comes back over internal standby reference v 18sb . if internal v 18 becomes lower than internal standby reference (v 18sb ) of about 0.3 to 0.45v with bit xram2en set, the ram supply switching circuit is not active: in case of a temporary drop on internal v 18 voltage versus internal v 18sb during normal code execution, no spurious standby mode s witching can occur (the ram is not frozen and can still be accessed). the st10f273m core module, generating the ram control signals, is powered by internal v 18 supply; during turning off transient these control signals follow the v 18 , while ram is switched to v 18sb internal reference. it could happen that a high level of ram write strobe from st10f273m core (active low signal) is low enough to be recognized as a logic ?0? by the ram interface (due to v 18 lower than v 18sb ): the bus status could contain a valid address for the ram and an unwanted data corruption could occur. for this reason, an extra interface, powered by the switched supply, is used to prevent the ram from this kind of potential corruption mechanism.
power reduction modes st10f273m 112/186 doc id 13453 rev 4 warning: during power-off phase, it is important that the external hardware maintains a stable ground level on rstin pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. 21.3.2 exiting standby mode after the system has entered the standby mode, the procedure to exit this mode consists of a standard power-on sequence, with the only difference that the ram is already powered through v 18sb internal reference (derived from v stby pin external voltage). it is recommended to held th e device under reset (rstin pin forced low) until external v dd voltage pin is stable. even though, at the very beginning of the power-on phase, the device is maintained under reset by the inte rnal low voltage detector circuit (implemented inside the main vo ltage regulator) till the internal v 18 becomes higher than about 1.0v, there is no guaranty that the device stays under reset status if rstin is at high level during power ramp up. so, it is important the external hardware is able to guarantee a stable ground level on rstin along the power-on phase, without any temporary glitch. the external hardware shall be responsible to drive low the rstin pin until the v dd is stable, even though the internal lvd is active. once the internal reset signal goes low, the ra m (still frozen) power supply is switched to the main v 18 . at this time, everything becomes stable, and the execution of the initialization routines can start: xram2en bit can be set, enabling the ram. 21.3.3 real time cl ock and standby mode when standby mode is entered (turning off the main supply v dd ), the real time clock counting can be maintained running in case the on-chip 32 khz o scillator is used to provide the reference to the counter. this is not possible if th e main oscillator is used as reference for the counter: being the ma in oscillator powered by v dd , once this is switched off, the oscillator is stopped. 21.3.4 power reduction modes summary the different power reduction modes are summarized in the following ta b l e 4 5 .
st10f273m power reduction modes doc id 13453 rev 4 113/186 table 45. power reduction modes summary mode v dd v stby cpu peripherals rtc main osc 32 khz osc stby xram xram idle on on off on off run off biased biased on on off on on run on biased biased power-down on on off off off off off biased biased on on off off on on off biased biased on on off off on off on biased biased standby off on off off off off off biased off off on off off on off on biased off
programmable output clock divider st10f273m 114/186 doc id 13453 rev 4 22 programmable output clock divider a specific register mapped on the xbus allows to choose the division factor on the clkout signal (p3.15). this register is mapped on x-miscellaneous memory address range. when clkout function is enabled by setting bit clken of register syscon, by default the cpu clock is output on p3. 15. setting bit xmiscen of regi ster xpercon and bit xpen of register syscon, it is possible to program the clock prescaling factor: in this way on p3.15 a prescaled value of the cpu clock can be output. when clkout function is not enabled (bit clken of register syscon cleared), p3.15 does not output any clock signal, even though xclkoutdiv register is programmed.
st10f273m register set doc id 13453 rev 4 115/186 23 register set this section summarizes all registers implemented in the st10f273m, ordered by name. 23.1 special function registers the following table lists all sfrs which are implemented in the st10f273m in alphabetical order. bit-addressable sfrs are marked with the letter ? b ? in column ?name?. sfrs within the extended sfr-space (esfrs) are marked with the letter ? e ? in column ?physical address?. table 46. list of special function registers name physical address 8-bit address description reset value adcic b ff98h cch a/d converter end of conversion interrupt control register - - 00h adcon b ffa0h d0h a/d converter control register 0000h addat fea0h 50h a/d converter result register 0000h addat2 f0a0h e 50h a/d converter 2 result register 0000h addrsel1 fe18h 0ch address select register 1 0000h addrsel2 fe1ah 0dh address select register 2 0000h addrsel3 fe1ch 0eh address select register 3 0000h addrsel4 fe1eh 0fh address select register 4 0000h adeic b ff9ah cdh a/d converter overrun error interrupt control register - - 00h buscon0 b ff0ch 86h bus configuration register 0 0xx0h buscon1 b ff14h 8ah bus configuration register 1 0000h buscon2 b ff16h 8bh bus configuration register 2 0000h buscon3 b ff18h 8ch bus configuration register 3 0000h buscon4 b ff1ah 8dh bus configuration register 4 0000h caprel fe4ah 25h gpt2 capture/reload register 0000h cc0 fe80h 40h capcom register 0 0000h cc0ic b ff78h bch capcom register 0 interrupt control register - - 00h cc1 fe82h 41h capcom register 1 0000h cc1ic b ff7ah bdh capcom register 1 interrupt control register - - 00h cc2 fe84h 42h capcom register 2 0000h cc2ic b ff7ch beh capcom register 2 interrupt control register - - 00h cc3 fe86h 43h capcom register 3 0000h cc3ic b ff7eh bfh capcom register 3 interrupt control register - - 00h
register set st10f273m 116/186 doc id 13453 rev 4 cc4 fe88h 44h capcom register 4 0000h cc4ic b ff80h c0h capcom register 4 interrupt control register - - 00h cc5 fe8ah 45h capcom register 5 0000h cc5ic b ff82h c1h capcom register 5 interrupt control register - - 00h cc6 fe8ch 46h capcom register 6 0000h cc6ic b ff84h c2h capcom register 6 interrupt control register - - 00h cc7 fe8eh 47h capcom register 7 0000h cc7ic b ff86h c3h capcom register 7 interrupt control register - - 00h cc8 fe90h 48h capcom register 8 0000h cc8ic b ff88h c4h capcom register 8 interrupt control register - - 00h cc9 fe92h 49h capcom register 9 0000h cc9ic b ff8ah c5h capcom register 9 interrupt control register - - 00h cc10 fe94h 4ah capcom register 10 0000h cc10ic b ff8ch c6h capcom register 10 interrupt control register - - 00h cc11 fe96h 4bh capcom register 11 0000h cc11ic b ff8eh c7h capcom register 11 interrupt control register - - 00h cc12 fe98h 4ch capcom register 12 0000h cc12ic b ff90h c8h capcom register 12 interrupt control register - - 00h cc13 fe9ah 4dh capcom register 13 0000h cc13ic b ff92h c9h capcom register 13 interrupt control register - - 00h cc14 fe9ch 4eh capcom register 14 0000h cc14ic b ff94h cah capcom register 14 interrupt control register - - 00h cc15 fe9eh 4fh capcom register 15 0000h cc15ic b ff96h cbh capcom register 15 interrupt control register - - 00h cc16 fe60h 30h capcom register 16 0000h cc16ic b f160h e b0h capcom register 16 interrupt control register - - 00h cc17 fe62h 31h capcom register 17 0000h cc17ic b f162h e b1h capcom register 17 interrupt control register - - 00h cc18 fe64h 32h capcom register 18 0000h cc18ic b f164h e b2h capcom register 18 interrupt control register - - 00h cc19 fe66h 33h capcom register 19 0000h cc19ic b f166h e b3h capcom register 19 interrupt control register - - 00h cc20 fe68h 34h capcom register 20 0000h cc20ic b f168h e b4h capcom register 20 interrupt control register - - 00h table 46. list of special function registers (continued) name physical address 8-bit address description reset value
st10f273m register set doc id 13453 rev 4 117/186 cc4 fe88h 44h capcom register 4 0000h cc4ic b ff80h c0h capcom register 4 interrupt control register - - 00h cc5 fe8ah 45h capcom register 5 0000h cc5ic b ff82h c1h capcom register 5 interrupt control register - - 00h cc6 fe8ch 46h capcom register 6 0000h cc6ic b ff84h c2h capcom register 6 interrupt control register - - 00h cc7 fe8eh 47h capcom register 7 0000h cc7ic b ff86h c3h capcom register 7 interrupt control register - - 00h cc8 fe90h 48h capcom register 8 0000h cc8ic b ff88h c4h capcom register 8 interrupt control register - - 00h cc9 fe92h 49h capcom register 9 0000h cc9ic b ff8ah c5h capcom register 9 interrupt control register - - 00h cc10 fe94h 4ah capcom register 10 0000h cc10ic b ff8ch c6h capcom register 10 interrupt control register - - 00h cc11 fe96h 4bh capcom register 11 0000h cc11ic b ff8eh c7h capcom register 11 interrupt control register - - 00h cc12 fe98h 4ch capcom register 12 0000h cc12ic b ff90h c8h capcom register 12 interrupt control register - - 00h cc13 fe9ah 4dh capcom register 13 0000h cc13ic b ff92h c9h capcom register 13 interrupt control register - - 00h cc14 fe9ch 4eh capcom register 14 0000h cc14ic b ff94h cah capcom register 14 interrupt control register - - 00h cc15 fe9eh 4fh capcom register 15 0000h cc15ic b ff96h cbh capcom register 15 interrupt control register - - 00h cc16 fe60h 30h capcom register 16 0000h cc16ic b f160h e b0h capcom register 16 interrupt control register - - 00h cc17 fe62h 31h capcom register 17 0000h cc17ic b f162h e b1h capcom register 17 interrupt control register - - 00h cc18 fe64h 32h capcom register 18 0000h cc18ic b f164h e b2h capcom register 18 interrupt control register - - 00h cc19 fe66h 33h capcom register 19 0000h cc19ic b f166h e b3h capcom register 19 interrupt control register - - 00h cc20 fe68h 34h capcom register 20 0000h cc20ic b f168h e b4h capcom register 20 interrupt control register - - 00h table 46. list of special function registers (continued) name physical address 8-bit address description reset value
register set st10f273m 118/186 doc id 13453 rev 4 cc21 fe6ah 35h capcom register 21 0000h cc21ic b f16ah e b5h capcom register 21 interrupt control register - - 00h cc22 fe6ch 36h capcom register 22 0000h cc22ic b f16ch e b6h capcom register 22 interrupt control register - - 00h cc23 fe6eh 37h capcom register 23 0000h cc23ic b f16eh e b7h capcom register 23 interrupt control register - - 00h cc24 fe70h 38h capcom register 24 0000h cc24ic b f170h e b8h capcom register 24 interrupt control register - - 00h cc25 fe72h 39h capcom register 25 0000h cc25ic b f172h e b9h capcom register 25 interrupt control register - - 00h cc26 fe74h 3ah capcom register 26 0000h cc26ic b f174h e bah capcom register 26 interrupt control register - - 00h cc27 fe76h 3bh capcom register 27 0000h cc27ic b f176h e bbh capcom register 27 interrupt control register - - 00h cc28 fe78h 3ch capcom register 28 0000h cc28ic b f178h e bch capcom register 28 interrupt control register - - 00h cc29 fe7ah 3dh capcom register 29 0000h cc29ic b f184h e c2h capcom register 29 interrupt control register - - 00h cc30 fe7ch 3eh capcom register 30 0000h cc30ic b f18ch e c6h capcom register 30 interrupt control register - - 00h cc31 fe7eh 3fh capcom register 31 0000h cc31ic b f194h e cah capcom register 31 interrupt control register - - 00h ccm0 b ff52h a9h capcom mode control register 0 0000h ccm1 b ff54h aah capcom mode control register 1 0000h ccm2 b ff56h abh capcom mode control register 2 0000h ccm3 b ff58h ach capcom mode control register 3 0000h ccm4 b ff22h 91h capcom mode control register 4 0000h ccm5 b ff24h 92h capcom mode control register 5 0000h ccm6 b ff26h 93h capcom mode control register 6 0000h ccm7 b ff28h 94h capcom mode control register 7 0000h cp fe10h 08h cpu context pointer register fc00h cric b ff6ah b5h gpt2 caprel interrupt control register - - 00h csp fe08h 04h cpu code segment pointer register (read only) 0000h dp0l b f100h e 80h p0l direction control register - - 00h table 46. list of special function registers (continued) name physical address 8-bit address description reset value
st10f273m register set doc id 13453 rev 4 119/186 dp0h b f102h e 81h p0h direction control register - - 00h dp1l b f104h e 82h p1l direction control register - - 00h dp1h b f106h e 83h p1h direction control register - - 00h dp2 b ffc2h e1h port 2 direction control register 0000h dp3 b ffc6h e3h port 3 direct ion control register 0000h dp4 b ffcah e5h port 4 direction control register - - 00h dp6 b ffceh e7h port 6 direction control register - - 00h dp7 b ffd2h e9h port 7 direction control register - - 00h dp8 b ffd6h ebh port 8 direction control register - - 00h dpp0 fe00h 00h cpu data page pointer 0 register (10-bit) 0000h dpp1 fe02h 01h cpu data page pointer 1 register (10-bit) 0001h dpp2 fe04h 02h cpu data page pointer 2 register (10-bit) 0002h dpp3 fe06h 03h cpu data page pointer 3 register (10-bit) 0003h emucon fe0ah 05h emulation control register - - xxh exicon b f1c0h e e0h external interrupt control register 0000h exisel b f1dah e edh external interrupt source selection register 0000h idchip f07ch e 3eh device identifier register (n is the device revision) 111nh idmanuf f07eh e 3fh manufactur er identifier register 0403h idmem f07ah e 3dh on-chip memory identifier register 2080h idprog f078h e 3ch programming voltage identifier register 0040h idx0 b ff08h 84h mac unit address pointer 0 0000h idx1 b ff0ah 85h mac unit address pointer 1 0000h mah fe5eh 2fh mac unit accumulator - high word 0000h mal fe5ch 2eh mac unit accumulator - low word 0000h mcw b ffdch eeh mac unit control word 0000h mdc b ff0eh 87h cpu multiply divide control register 0000h mdh fe0ch 06h cpu multiply divide register ? high word 0000h mdl fe0eh 07h cpu multiply divide register ? low word 0000h mrw b ffdah edh mac unit repeat word 0000h msw b ffdeh efh mac unit status word 0200h odp2 b f1c2h e e1h port 2 open drain control register 0000h odp3 b f1c6h e e3h port 3 open drain control register 0000h odp4 b f1cah e e5h port 4 open drain control register - - 00h odp6 b f1ceh e e7h port 6 open drain control register - - 00h table 46. list of special function registers (continued) name physical address 8-bit address description reset value
register set st10f273m 120/186 doc id 13453 rev 4 odp7 b f1d2h e e9h port 7 open drain control register - - 00h odp8 b f1d6h e ebh port 8 open drain control register - - 00h ones b ff1eh 8fh constant value 1?s register (read only) ffffh p0l b ff00h 80h port0 low register (lower half of port0) - - 00h p0h b ff02h 81h port0 high register (upper half of port0) - - 00h p1l b ff04h 82h port1 low register (lower half of port1) - - 00h p1h b ff06h 83h port1 high register (upper half of port1) - - 00h p2 b ffc0h e0h port 2 register 0000h p3 b ffc4h e2h port 3 register 0000h p4 b ffc8h e4h port 4 register (8-bit) - - 00h p5 b ffa2h d1h port 5 register (read only) xxxxh p6 b ffcch e6h port 6 register (8-bit) - - 00h p7 b ffd0h e8h port 7 register (8-bit) - - 00h p8 b ffd4h eah port 8 register (8-bit) - - 00h p5didis b ffa4h d2h port 5 digital disable register 0000h pecc0 fec0h 60h pec channel 0 control register 0000h pecc1 fec2h 61h pec channel 1 control register 0000h pecc2 fec4h 62h pec channel 2 control register 0000h pecc3 fec6h 63h pec channel 3 control register 0000h pecc4 fec8h 64h pec channel 4 control register 0000h pecc5 fecah 65h pec channel 5 control register 0000h pecc6 fecch 66h pec channel 6 control register 0000h pecc7 feceh 67h pec channel 7 control register 0000h picon b f1c4h e e2h port input threshold control register - - 00h pp0 f038h e 1ch pwm module period register 0 0000h pp1 f03ah e 1dh pwm module period register 1 0000h pp2 f03ch e 1eh pwm module period register 2 0000h pp3 f03eh e 1fh pwm module period register 3 0000h psw b ff10h 88h cpu program status word 0000h pt0 f030h e 18h pwm module up/down counter 0 0000h pt1 f032h e 19h pwm module up/down counter 1 0000h pt2 f034h e 1ah pwm module up/down counter 2 0000h pt3 f036h e 1bh pwm module up/down counter 3 0000h pw0 fe30h 18h pwm module pulse width register 0 0000h table 46. list of special function registers (continued) name physical address 8-bit address description reset value
st10f273m register set doc id 13453 rev 4 121/186 pw1 fe32h 19h pwm module pulse width register 1 0000h pw2 fe34h 1ah pwm module pulse width register 2 0000h pw3 fe36h 1bh pwm module pulse width register 3 0000h pwmcon0 b ff30h 98h pwm module control register 0 0000h pwmcon1 b ff32h 99h pwm module control register 1 0000h pwmic b f17eh e bfh pwm module interrupt control register - - 00h qr0 f004h e 02h mac unit offset register r0 0000h qr1 f006h e 03h mac unit offset register r1 0000h qx0 f000h e 00h mac unit offset register x0 0000h qx1 f002h e 01h mac unit offset register x1 0000h rp0h b f108h e 84h system start-up configuration register (read only) - - xxh s0bg feb4h 5ah serial channel 0 baudrate generator reload register 0000h s0con b ffb0h d8h serial channel 0 control register 0000h s0eic b ff70h b8h serial channel 0 error interrupt control register - - 00h s0rbuf feb2h 59h serial channel 0 receive buffer register (read only) - - xxh s0ric b ff6eh b7h serial channel 0 receive interrupt control register - - 00h s0tbic b f19ch e ceh serial channel 0 transmit buffer interrupt control reg. - - 00h s0tbuf feb0h 58h serial channel 0 transmit buffer register (write only) 0000h s0tic b ff6ch b6h serial channel 0 transmit interrupt control register - - 00h sp fe12h 09h cpu system stack pointer register fc00h sscbr f0b4h e 5ah ssc baudrate register 0000h ssccon b ffb2h d9h ssc control register 0000h ssceic b ff76h bbh ssc e rror interrupt control register - - 00h sscrb f0b2h e 59h ssc receive buffer (read only) xxxxh sscric b ff74h bah ssc receive interrupt control register - - 00h ssctb f0b0h e 58h ssc transmit buffer (write only) 0000h ssctic b ff72h b9h ssc transmit interrupt control register - - 00h stkov fe14h 0ah cpu stack overflow pointer register fa00h stkun fe16h 0bh cpu stack underflow pointer register fc00h syscon b ff12h 89h cpu system c onfiguration r egister 0xx0h (1) t0 fe50h 28h capcom timer 0 register 0000h t01con b ff50h a8h capcom timer 0 and timer 1 control register 0000h t0ic b ff9ch ceh capcom timer 0 interrupt control register - - 00h t0rel fe54h 2ah capcom timer 0 reload register 0000h table 46. list of special function registers (continued) name physical address 8-bit address description reset value
register set st10f273m 122/186 doc id 13453 rev 4 t1 fe52h 29h capcom timer 1 register 0000h t1ic b ff9eh cfh capcom timer 1 in terrupt control register - - 00h t1rel fe56h 2bh capcom timer 1 reload register 0000h t2 fe40h 20h gpt1 timer 2 register 0000h t2con b ff40h a0h gpt1 timer 2 control register 0000h t2ic b ff60h b0h gpt1 timer 2 interrupt control register - - 00h t3 fe42h 21h gpt1 timer 3 register 0000h t3con b ff42h a1h gpt1 timer 3 control register 0000h t3ic b ff62h b1h gpt1 timer 3 interrupt control register - - 00h t4 fe44h 22h gpt1 timer 4 register 0000h t4con b ff44h a2h gpt1 timer 4 control register 0000h t4ic b ff64h b2h gpt1 timer 4 interrupt control register - - 00h t5 fe46h 23h gpt2 timer 5 register 0000h t5con b ff46h a3h gpt2 timer 5 control register 0000h t5ic b ff66h b3h gpt2 timer 5 interrupt control register - - 00h t6 fe48h 24h gpt2 timer 6 register 0000h t6con b ff48h a4h gpt2 timer 6 control register 0000h t6ic b ff68h b4h gpt2 timer 6 interrupt control register - - 00h t7 f050h e 28h capcom timer 7 register 0000h t78con b ff20h 90h capcom timer 7 and 8 control register 0000h t7ic b f17ah e bdh capcom timer 7 interrupt control register - - 00h t7rel f054h e 2ah capcom timer 7 reload register 0000h t8 f052h e 29h capcom timer 8 register 0000h t8ic b f17ch e beh capcom timer 8 interrupt control register - - 00h t8rel f056h e 2bh capcom timer 8 reload register 0000h tfr b ffach d6h trap flag register 0000h wdt feaeh 57h watchdog timer register (read only) 0000h wdtcon b ffaeh d7h watchdog timer control register 00xxh (2) xadrs3 f01ch e 0eh xper address select register 3 800bh xp0ic b f186h e c3h see section 9.1 - - 00h (3) xp1ic b f18eh e c7h see section 9.1 - - 00h (3) xp2ic b f196h e cbh see section 9.1 - - 00h (3) xp3ic b f19eh e cfh see section 9.1 - - 00h (3) table 46. list of special function registers (continued) name physical address 8-bit address description reset value
st10f273m register set doc id 13453 rev 4 123/186 23.2 x-registers the following table lists in order of their name s all x-bus registers wh ich are implemented in the st10f273m. even though they are also physically mapped on xbus memory space, the flash control registers are listed in a separate section. note: the x-registers are not bit-addressable. xpercon b f024h e 12h xper configuration register - - 05h zeros b ff1ch 8eh constant value 0?s register (read only) 0000h 1. the system configuration is selected during reset. syscon reset value is 0000 0xx0 x000 0000b. 2. reset value depends on diffe rent triggered reset event. 3. the xpnic interrupt control registers control interrupt requests from integrated x-bu s peripherals. some software controlled interrupt requests may be generat ed by setting the xpnir bits (of xpnic register) of the unused x-peripheral nodes. table 46. list of special function registers (continued) name physical address 8-bit address description reset value table 47. list of xbus registers name physical address description reset value can1brper ef0ch can1: brp extension register 0000h can1btr ef06h can1: bit timing register 2301h can1cr ef00h can1: can control register 0001h can1ec ef04h can1: error counter 0000h can1if1a1 ef18h can1: if1 arbitration 1 0000h can1if1a2 ef1ah can1: if1 arbitration 2 0000h can1if1cm ef12h can1: if1 command mask 0000h can1if1cr ef10h can1: if1 command request 0001h can1if1da1 ef1eh can1: if1 data a 1 0000h can1if1da2 ef20h can1: if1 data a 2 0000h can1if1db1 ef22h can1: if1 data b 1 0000h can1if1db2 ef24h can1: if1 data b 2 0000h can1if1m1 ef14h can1: if1 mask 1 ffffh can1if1m2 ef16h can1: if1 mask 2 ffffh can1if1mc ef1ch can1: if1 message control 0000h can1if2a1 ef48h can1: if2 arbitration 1 0000h can1if2a2 ef4ah can1: if2 arbitration 2 0000h can1if2cm ef42h can1: if2 command mask 0000h can1if2cr ef40h can1: if2 command request 0001h can1if2da1 ef4eh can1: if2 data a 1 0000h
register set st10f273m 124/186 doc id 13453 rev 4 can1if2da2 ef50h can1: if2 data a 2 0000h can1if2db1 ef52h can1: if2 data b 1 0000h can1if2db2 ef54h can1: if2 data b 2 0000h can1if2m1 ef44h can1: if2 mask 1 ffffh can1if2m2 ef46h can1: if2 mask 2 ffffh can1if2mc ef4ch can1: if2 message control 0000h can1ip1 efa0h can1: interrupt pending 1 0000h can1ip2 efa2h can1: interrupt pending 2 0000h can1ir ef08h can1: interrupt register 0000h can1mv1 efb0h can1: message valid 1 0000h can1mv2 efb2h can1: message valid 2 0000h can1nd1 ef90h can1: new data 1 0000h can1nd2 ef92h can1: new data 2 0000h can1sr ef02h can1: status register 0000h can1tr ef0ah can1: test register 00x0h can1tr1 ef80h can1: transmission request 1 0000h can1tr2 ef82h can1: transmission request 2 0000h can2brper ee0ch can2: brp extension register 0000h can2btr ee06h can2: bit timing register 2301h can2cr ee00h can2: can control register 0001h can2ec ee04h can2: error counter 0000h can2if1a1 ee18h can2: if1 arbitration 1 0000h can2if1a2 ee1ah can2: if1 arbitration 2 0000h can2if1cm ee12h can2: if1 command mask 0000h can2if1cr ee10h can2: if1 command request 0001h can2if1da1 ee1eh can2: if1 data a 1 0000h can2if1da2 ee20h can2: if1 data a 2 0000h can2if1db1 ee22h can2: if1 data b 1 0000h can2if1db2 ee24h can2: if1 data b 2 0000h can2if1m1 ee14h can2: if1 mask 1 ffffh can2if1m2 ee16h can2: if1 mask 2 ffffh can2if1mc ee1ch can2: if1 message control 0000h can2if2a1 ee48h can2: if2 arbitration 1 0000h can2if2a2 ee4ah can2: if2 arbitration 2 0000h table 47. list of xbus registers (continued) name physical address description reset value
st10f273m register set doc id 13453 rev 4 125/186 can2if2cm ee42h can2: if2 command mask 0000h can2if2cr ee40h can2: if2 command request 0001h can2if2da1 ee4eh can2: if2 data a 1 0000h can2if2da2 ee50h can2: if2 data a 2 0000h can2if2db1 ee52h can2: if2 data b 1 0000h can2if2db2 ee54h can2: if2 data b 2 0000h can2if2m1 ee44h can2: if2 mask 1 ffffh can2if2m2 ee46h can2: if2 mask 2 ffffh can2if2mc ee4ch can2: if2 message control 0000h can2ip1 eea0h can2: interrupt pending 1 0000h can2ip2 eea2h can2: interrupt pending 2 0000h can2ir ee08h can2: interrupt register 0000h can2mv1 eeb0h can2: message valid 1 0000h can2mv2 eeb2h can2: message valid 2 0000h can2nd1 ee90h can2: new data 1 0000h can2nd2 ee92h can2: new data 2 0000h can2sr ee02h can2: status register 0000h can2tr ee0ah can2: test register 00x0h can2tr1 ee80h can2: transmission request 1 0000h can2tr2 ee82h can2: transmission request 2 0000h i2cccr1 ea06h i2c clock control register 1 0000h i2cccr2 ea0eh i2c clock control register 2 0000h i2ccr ea00h i2c control register 0000h i2cdr ea0ch i2c data register 0000h i2coar1 ea08h i2c own address register 1 0000h i2coar2 ea0ah i2c own address register 2 0000h i2csr1 ea02h i2c status register 1 0000h i2csr2 ea04h i2c status register 2 0000h rtcah ed14h rtc alarm register high byte xxxxh rtcal ed12h rtc alarm register low byte xxxxh rtccon ed00h rtc control register 000xh rtcdh ed0ch rtc divider counter high byte xxxxh rtcdl ed0ah rtc divider counter low byte xxxxh rtch ed10h rtc programmable counter high byte xxxxh table 47. list of xbus registers (continued) name physical address description reset value
register set st10f273m 126/186 doc id 13453 rev 4 rtcl ed0eh rtc programmable counter low byte xxxxh rtcph ed08h rtc prescaler register high byte xxxxh rtcpl ed06h rtc prescaler register low byte xxxxh xclkoutdiv eb02h clkout divider control register - - 00h xemu0 eb76h xbus emulation regi ster 0 (write only) xxxxh xemu1 eb78h xbus emulation regi ster 1 (write only) xxxxh xemu2 eb7ah xbus emulation regi ster 2 (write only) xxxxh xemu3 eb7ch xbus emulation regi ster 3 (write only) xxxxh xir0clr eb14h x-interrupt 0 clear register (write only) 0000h xir0sel eb10h x-interrupt 0 selection register 0000h xir0set eb12h x-interrupt 0 set register (write only) 0000h xir1clr eb24h x-interrupt 1 clear register (write only) 0000h xir1sel eb20h x-interrupt 1 selection register 0000h xir1set eb22h x-interrupt 1 set register (write only) 0000h xir2clr eb34h x-interrupt 2 clear register (write only) 0000h xir2sel eb30h x-interrupt 2 selection register 0000h xir2set eb32h x-interrupt 2 set register (write only) 0000h xir3clr eb44h x-interrupt 3 clear selection register (write only) 0000h xir3sel eb40h x-interrupt 3 selection register 0000h xir3set eb42h x-interrupt 3 set selection register (write only) 0000h xmisc eb46h xbus miscellaneous features register 0000h xp1didis eb36h port 1 digital disable register 0000h xperemu eb7eh xpercon copy for emulation (write only) xxxxh xpicon eb26h extended port input threshold control register - - 00h xpolar ec04h xpwm module channel polarity register 0000h xpp0 ec20h xpwm module period register 0 0000h xpp1 ec22h xpwm module period register 1 0000h xpp2 ec24h xpwm module period register 2 0000h xpp3 ec26h xpwm module period register 3 0000h xpt0 ec10h xpwm module up/down counter 0 0000h xpt1 ec12h xpwm module up/down counter 1 0000h xpt2 ec14h xpwm module up/down counter 2 0000h xpt3 ec16h xpwm module up/down counter 3 0000h xpw0 ec30h xpwm module pulse width register 0 0000h table 47. list of xbus registers (continued) name physical address description reset value
st10f273m register set doc id 13453 rev 4 127/186 xpw1 ec32h xpwm module pulse width register 1 0000h xpw2 ec34h xpwm module pulse width register 2 0000h xpw3 ec36h xpwm module pulse width register 3 0000h xpwmcon0 ec00h xpwm module control register 0 0000h xpwmcon0clr ec08h xpwm module clear control reg. 0 (write only) 0000h xpwmcon0set ec06h xpwm module set control register 0 (write only) 0000h xpwmcon1 ec02h xpwm module control register 1 0000h xpwmcon1clr ec0ch xpwm module clear control reg. 0 (write only) 0000h xpwmcon1set ec0ah xpwm module set control register 0 (write only) 0000h xpwmport ec80h xpwm module port control register 0000h xs1bg e906h xasc baudrate generator reload register 0000h xs1con e900h xasc control register 0000h xs1conclr e904h xasc clear control register (write only) 0000h xs1conset e902h xasc set contro l register (write only) 0000h xs1port e980h xasc port control register 0000h xs1rbuf e90ah xasc receive buffer register 0000h xs1tbuf e908h xasc transmit buffer register 0000h xsscbr e80ah xssc baudr ate register 0000h xssccon e800h xssc control register 0000h xsscconclr e804h xssc clear contro l register (write only) 0000h xsscconset e802h xssc set control register (write only) 0000h xsscport e880h xssc port control register 0000h xsscrb e808h xssc receive buffer xxxxh xssctb e806h xssc transmit buffer 0000h table 47. list of xbus registers (continued) name physical address description reset value
register set st10f273m 128/186 doc id 13453 rev 4 23.3 flash registers ordered by name the following table lists in the order of their names all flash control registers which are implemented in the st10f273m. these registers are physically mapped on the xbus. note: these registers are not bit-addressable. 23.4 identification registers the st10f273m has four identification registers, mapped in esfr space. these registers contain: a manufacturer identifier a chip identifier with its revision an internal flash and size identifier programming voltage description table 48. list of flash control registers name physical address description reset value farh 0x000e 0012 flash address register - high 0000h farl 0x000e 0010 flash address register - low 0000h fcr0h 0x000e 0002 flash control register 0 - high 0000h fcr0l 0x000e 0000 flash control register 0 - low 0000h fcr1h 0x000e 0006 flash control register 1 - high 0000h fcr1l 0x000e 0004 flash control register 1 - low 0000h fdr0h 0x000e 000a flash data register 0 - high ffffh fdr0l 0x000e 0008 flash data register 0 - low ffffh fdr1h 0x000e 000e flash data register 1 - high ffffh fdr1l 0x000e 000c flash data register 1 - low ffffh fer 0x000e 0014 flash error register 0000h fnvapr0 0x000e dfb8 flash non-volatile access protection reg.0 acffh fnvapr1h 0x000e dfbe flash non-volatile access protection reg.1 - high ffffh fnvapr1l 0x000e dfbc flash non-volatile access protection reg.1 - low ffffh fnvwpirh 0x000e dfb6 flash non-volatile protection i register high ffffh fnvwpirl 0x000e dfb4 flash non-volatile protection i register low ffffh
st10f273m register set doc id 13453 rev 4 129/186 idmanuf (f07eh / 3fh) esfr reset value: 0403h 1514131211109876543210 manuf 00011 ro ro ro ro ro ro table 49. idmanuf register description bit name function 15:5 manuf manufacturer identifier 020h: stmicroelectronics manufacturer (jtag worldwide normalization) idchip (f07ch / 3eh) esfr reset value: 111xh 1514131211109876543210 idchip revid ro ro table 50. idchip register description bit name function 15:4 idchip device identifier 111h: st10f273m id entifier (273) 3:0 revid device revision identifier xh: according to revision number idmem (f07ah / 3dh) esfr reset value: 2080h 1514131211109876543210 memtyp memsize ro ro table 51. idmem register description bit name function 15:12 memsize internal memory size internal memory size is 4 x (memsize) (in kbyte) 080h for 512 kbytes (st10f273m) 11:0 memtyp internal memory type 0h: rom-less 1h: (m) rom memory 2h: (s) standard flash memory (st10f273m) 3h: (h) high performance flash memory 4h...fh: reserved
register set st10f273m 130/186 doc id 13453 rev 4 note: all identification words are read-only registers. idprog (f078h / 3ch) esfr reset value: 0040h 1514131211109876543210 progvpp progvdd ro ro table 52. idprog register description bit name function 15:8 progvpp programming v pp voltage (no need of external v pp ) - 00h 7:0 progvdd programming v dd voltage v dd voltage when programming eprom or flash devices is calculated using the following formula: v dd = 20 x [progvdd] / 256 (volts) - 40h for st10f273m (5v).
st10f273m electrical characteristics doc id 13453 rev 4 131/186 24 electrical characteristics 24.1 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. during overload conditions (v in > v dd or v in < v ss ) the voltage on pins with respect to ground (v ss ) must not exceed the values defined by the absolute maximum ratings. during power-on and power-off transients (including standby entering/exiting phases), the relationships between voltages applied to the device and the main v dd shall be always respected. in particular power-on and power-off of v aref shall be coherent with v dd transient, in order to avoid undesired current injection through the on-chip protection diodes. table 53. absolute maximum ratings symbol parameter values unit v dd voltage on v dd pins with respect to ground (v ss ) -0.5 to +6.5 v v stby voltage on v stby pin with respect to ground (v ss ) -0.5 to +6.5 v aref voltage on v aref pins with respect to ground (v ss ) -0.5 to v dd +0.5 v agnd voltage on v agnd pins with respect to ground (v ss )v ss v io voltage on any pin with respect to ground (v ss ) -0.5 to v dd + 0.5 i ov input current on any pin during overload condition 10 ma i tov absolute sum of all input currents during overload condition | 75 | t st storage temperature -65 to +150 c esd esd susceptibility (human body model) 2000 v
electrical characteristics st10f273m 132/186 doc id 13453 rev 4 24.2 recommended operating conditions 24.3 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: equation 1: t j = t a + (p d x ja ) where: t a is the ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d is the sum of p int and p i/o (p d = p int + p i/o ), p int is the product of i dd and v dd , expressed in watt. this is the chip internal power, p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications p i/o < p int and may be neglected. on the other hand, p i/o may be significant if the device is config ured to drive continuously external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: equation 2: p d = k / (t j + 273c) therefore (solving equations 1 and 2): equation 3: k = p d x (t a + 273c) + ja x p d 2 table 54. recommended operating conditions symbol parameter value unit min max v dd operating supply voltage 4.5 5.5 v v stby operating standby supply voltage (1) 1. the value of the v stby voltage is specified in the range of 4.5 to 5.5 volt. nevertheless, it is acceptable to exceed the upper limit (up to 6.0 volt) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device (about 30 years) . on the other hand, it is possible to exceed the lower limit (down to 4.0 volt) whenever rtc and 32 kh z on-chip oscillator amplifier are turned off (only standby ram powered through vstby pin in standby mode). when v stby voltage is lower than main v dd , the input section of v stby /ea pin can generate a spuri ous static consumption on v dd power supply (in the range of tenth of a). v aref operating analog reference voltage (2) 2. for details on operating c onditions concerning the usage of a/d converter refer to section 24.7 . 0v dd + 0.1 t a ambient temperature under bias -40 +125 c t j junction temperature under bias +150
st10f273m electrical characteristics doc id 13453 rev 4 133/186 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equation 1 and equation 2 iteratively for any value of t a . based on thermal characteristics of the package and with reference to the power consumption figures provided in the next tables and diagrams, the following product classification can be proposed. anyhow, the exact power consumption of the device inside the application must be computed according to different working conditions, thermal profiles, real thermal resistance of the system (including printed circuit board or other substrata), i/o activity, and so on. 24.4 parameter interpretation the parameters listed in the following tabl es represent the characteristics of the st10f273m and its demands on the system. where the st10f273m logic provides signals wit h their respective timing characteristics, the symbol ? cc ? for controller characteristics, is included in the ?symbol? column. where the external system must provide signals with their respective timing characteristics to the st10f273m, the symbol ? sr ? for system requirement, is included in the ?symbol? column. table 55. thermal characteristics symbol description value (typical) unit ja thermal resistance junction-ambient pqfp 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch lqfp 144 - 20 x 20 mm / 0.5 mm pitch lqfp 144 - 20 x 20 mm / 0.5 mm pitch on four-layer fr4 board (2 layers signals / 2 layers power) 30 40 35 c/w table 56. package characteristics package ambient temperature range cpu frequency range pqfp 144 -40 to +125c 1 to 40 mhz lqfp 144
electrical characteristics st10f273m 134/186 doc id 13453 rev 4 24.5 dc characteristics v dd = 5 v 10%, v ss = 0 v, t a = -40 to +125c table 57. dc characteristics symbol parameter test condition limit values unit min max v il sr input low voltage (ttl mode) (except rstin , ea , nmi , rpd, xtal1, ready ) ?-0.30.8v v ils sr input low voltage (cmos mode) (except rstin , ea , nmi , rpd, xtal1, ready ) ?-0.30.3 v dd v v il1 sr input low voltage rstin , ea , nmi , rpd ? -0.3 0.3 v dd v v il2 sr input low voltage xtal1 (cmos only) direct drive mode -0.3 0.3 v dd v v il3 sr input low voltage ready (ttl only) ? -0.3 0.8 v v ih sr input high voltage (ttl mode) (except rstin , ea , nmi , rpd, xtal1) ?2.0v dd + 0.3 v v ihs sr input high voltage (cmos mode) (except rstin , ea , nmi , rpd, xtal1) ? 0.7 v dd v dd + 0.3 v v ih1 sr input high voltage rstin , ea , nmi , rpd ? 0.7 v dd v dd + 0.3 v v ih2 sr input high voltage xtal1 (cmos only) direct drive mode 0.7 v dd v dd + 0.3 v v ih3 sr input high voltage ready (ttl only) ?2.0v dd + 0.3 v v hys cc input hysteresis (ttl mode) (except rstin , ea , nmi , xtal1, rpd) (3) 400 700 mv v hyss cc input hysteresis (cmos mode) (except rstin , ea , nmi , xtal1, rpd) (3) 750 1400 mv v hys1 cc input hysteresis rstin , ea , nmi (3) 750 1400 mv v hys2 cc input hysteresis xtal1 (3) 050mv v hys3 cc input hysteresis ready (ttl only) (3) 400 700 mv v hys4 cc input hysteresis rpd (3) 500 1500 mv v ol cc output low voltage (p6[7:0], ale, rd , wr /wrl , bhe /wrh , clkout, rstin , rstout ) i ol = 8ma i ol = 1ma ? 0.4 0.05 v v ol1 cc output low voltage (p0[15:0], p1[15:0], p2 [15:0], p3[15,13:0], p4[7:0], p7[7 :0], p8[7:0]) i ol1 = 4ma i ol1 = 0.5ma ? 0.4 0.05 v v ol2 cc output low voltage rpd i ol2 = 85a i ol2 = 80a i ol2 = 60a ? v dd 0.5 v dd 0.3 v dd v v oh cc output high voltage (p6[7:0], ale, rd , wr /wrl , bhe /wrh , clkout, rstout ) i oh = -8ma i oh = -1ma v dd -0.8 v dd - 0.08 ?v
st10f273m electrical characteristics doc id 13453 rev 4 135/186 v oh1 cc output high voltage (1) (p0[15:0], p1[15:0], p2 [15:0], p3[15,13:0], p4[7:0], p7[7 :0], p8[7:0]) i oh1 = -4ma i oh1 = -0.5ma v dd -0.8 v dd - 0.08 ?v v oh2 cc output high voltage rpd i oh2 = -2ma i oh2 = -750a i oh2 = -150a 0 0.3 v dd 0.5 v dd ?v | i oz1 | cc input leakage current (p5[15:0]) (2) ??0.2a | i oz2 | cc input leakage current (all except p5[15:0], p2[0], rpd, p3[12], p3[15]) ??0.5a | i oz3 | cc input leakage current (p2[0]) (3) ?? +1.0 -0.5 a | i oz4 | cc input leakage current (rpd) ? ? 3.0 a | i oz5 | cc input leakage current (p3[12], p3[15]) ? ? 1.0 a | i ov1 | sr overload current (all except p2[0]) (3)(4) ?5ma | i ov2 | sr overload current (p2[0]) (3) (3)(4) ? +5 -1 ma r rst cc rstin pull-up resistor 100 k nominal 50 250 k i rwh read/write inactive current (4)(5) v out = 2.4v ? -40 a i rwl read/write active current (4)(7) v out = 0.4v -500 ? a i alel ale inactive current (4)(5) v out = 0.4v 20 ? a i aleh ale active current (4)(7) v out = 2.4v ? 300 a i p6h port 6 inactive current (p6[4:0]) (4)(5) v out = 2.4v ? -40 a i p6l port 6 active current (p6[4:0]) (4)(6) v out = 0.4v -500 ? a i p0h (5) port0 configuration current (4) v in = 2.0v ? -10 a i p0l (6) v in = 0.8v -100 ? a c io cc pin capacitance (digital inputs / outputs) (3)(5) ?10pf i cc1 run mode power supply current (7) (execution from internal ram) ??20+2f cpu ma i cc2 run mode power supply current (8)(9) (execution from internal flash) ? ? 20 + 1.8 f cpu ma i id idle mode supply current (10) ?? 20 + 0.6 f cp u ma i pd1 power down supply current (11) (rtc off, oscillators off, main voltage regulator off) t a = 25c ? 150 a i pd2 power down supply current (11)(12) (rtc on, main oscillator on, main voltage regulator off) t a = 25c ? 8 ma table 57. dc characteristics (continued) symbol parameter test condition limit values unit min max
electrical characteristics st10f273m 136/186 doc id 13453 rev 4 i pd3 power down supply current (11) (rtc on, 32 khz oscillator on, main voltage regulator off) t a = 25c ? 200 a i sb1 standby supply current (13) (rtc off, oscillators off, v dd off, v stby on) v stby = 5.5 v t a = t j = 25c ? 250 a v stby = 5.5 v t a = t j = 125c ? 500 a i sb2 standby supply current (13) (rtc on, 32 khz oscillator on, main v dd off, v stby on) v stby = 5.5 v t a = t j = 25c ? 250 a v stby = 5.5 v t a = t j = 125c ? 500 a i sb3 standby supply current (8)(13) (v dd transient condition) ??2.5ma 1. this specification is not valid for output s which are switched to open drain mode. in this case the respective output will fl oat and the voltage is imposed by the external circuitry. 2. port 5 leakage values are granted for not selected a/d c onverter channel. one channels is always selected (by default, after reset, p5.0 is selected). for the selected channel the leakage value is similar to that of other port pins. 3. consult your vendor to know which vers ion of the on-chip oscillator amplifie r is enabled (low-power or wide-swing). the leakage of p2.0 is higher than other pins due to the additio nal logic (pass gates active only in s pecific test modes) implemented on input path. pay attention to not stress p2.0 input pin with negative over load beyond the specified limits: failures in flash reading may occur (sen se amplifier perturbation). refer to next figure 38 for a scheme of the input circuitry. 4. this specification is only va lid during reset, or during hold- or adapt-mode. po rt 6 pins are only affe cted, if they are used for cs output and the open drain function is not enabled. 5. the maximum current may be drawn while the respective signal li ne remains inactive. 6. the minimum current must be drawn in order to drive the respecti ve signal line active. 7. the power supply current is a function of the operating frequency (f cpu is expressed in mh z). this dependency is illustrated in the figure figure 39 below. this parameter is tested at v ddmax and at maximum cpu clock frequency with all outputs disconnected and all inputs at v il or v ih , rstin pin at v ih1min : this implies that i/o current is not considered . the device is doing the following: fetching code from iram and xram1, accessi ng in read and write to both xram modules watchdog timer is enabled and regularly serviced rtc is running with main oscillat or clock as reference, generating a tick interrupts ever y 192 clock cycles four channels of xpwm are running (waves period: 2, 2.5, 3 and 4 cpu clock cy cles): no output toggling five general purpose timers are running in timer mo de with prescaler equal to 8 (t2, t3, t4, t5, t6) adc is in auto scan continuous conversion mode on all 16 channels of port5 all interrupts generated by xpwm, rtc, timers and adc are not serviced 8. not 100% tested, guaranteed by design characterization. 9. the power supply current is a function of the operating frequency (f cpu is expressed in mh z). this dependency is illustrated in the figure 39 below. this parameter is tested at v ddmax and at maximum cpu clock frequency with all outputs disconnected and all inputs at v il or v ih , rstin pin at v ih1min : this implies that i/o current is not considered . the device is doing the following: fetching code from all sectors of iflash, acce ssing in read (few fetches) and write to xram watchdog timer is enabled and regularly serviced rtc is running with main oscillat or clock as reference, generating a tick interrupts ever y 192 clock cycles four channels of xpwm are running (waves period: 2, 2.5, 3 and 4 cpu clock cy cles): no output toggling five general purpose timers are running in timer mo de with prescaler equal to 8 (t2, t3, t4, t5, t6) adc is in auto scan continuous conversion mode on all 16 channels of port5 all interrupts generated by xpwm, rtc, timers and adc are not serviced 10. the idle mode supply current is a function of the operating frequency (f cpu is expressed in mhz). this dependency is illustrated in the figure 38 below. these parameters are tested and at maximum cpu clock with all outputs disconnected and all inputs at v il or v ih , rstin pin at v ih1min. table 57. dc characteristics (continued) symbol parameter test condition limit values unit min max
st10f273m electrical characteristics doc id 13453 rev 4 137/186 figure 38. port2 test mode structure figure 39. supply current versus the operating frequency (run and idle modes) 11. this parameter is tested including leakage cu rrents. all inputs (including pins configured as inputs ) at 0 v to 0.1 v or at v dd ? 0.1 v to v dd , v aref = 0 v, all outputs (including pins configured as outputs) disconnected. besides, the main voltage regulator is assumed off: in case it is not, additional 1m a shall be assumed. the value for this parameter shall be considered as ?target value? to be c onfirmed by silicon characterization. 12. overload conditions occur if the stan dard operating conditions are exceeded, that is, the voltage on any pin exceeds the specified range (that is, v ov > v dd + 0.3 v or v ov < ?0.3 v). the absolute sum of input overload currents on all port pins may not exceed 50ma. the supply voltage mu st remain within the specified limits. 13. this parameter is tested including leakage cu rrents. all inputs (including pins configured as inputs ) at 0 v to 0.1 v or at v dd ? 0.1 v to v dd , v aref = 0 v, all outputs (including pins configured as outputs) disconnected. besides, the main voltage regulator is assumed off: in case it is not, additional 1m a shall be assumed. the value for this parameter shall be considered as ?target value? to be c onfirmed by silicon characterization. ,qsxw odwfk &orfn 3 &&,2 2xwsxw exiihu 7hvwprgh $owhuqdwhgdwdlqsxw )dvwh[whuqdolqwhuuxswlqsxw )odvk vhqvhdpsolilhu dqgfroxpqghfrghu ("1($'5 i &38 >0+]@ , && , && , ,' ("1($'5
electrical characteristics st10f273m 138/186 doc id 13453 rev 4 24.6 flash characteristics v dd = 5v 10%, v ss = 0v table 58. flash characteristics parameter typical maximum unit notes t a = 25c t a = 125c 0 cycles (1) 1. the figures are given after about 100 cycles due to te sting routines (0 cycles at the final customer). 0 cycles (1) 100k cycles word program (32-bit) (2) 2. word and double word programming times are provi ded as average values deriv ed from a full sector programming time: the absolute value of a word or double word programming time could be longer than the average value. 35 80 290 s ? double word program (64-bit) (2) 60 150 570 s ? bank 0 program (512k) (double word program) 3.9 9.9 37.3 s ? sector erase (8k) 0.6 0.5 0.9 0.8 1.0 0.9 s not preprogrammed preprogrammed sector erase (32k) 1.1 0.8 2.0 1.8 2.7 2.5 s not preprogrammed preprogrammed sector erase (64k) 1.7 1.3 3.7 3.3 5.1 4.7 s not preprogrammed preprogrammed bank 0 erase (512k) (3) 3. bank erase is obtained through a multip le sector erase operation (setting bi ts related to all sectors of the bank). as st10f273m implements only one bank, the bank erase operation is equivalent to module and chip erase operations. 11.2 8.0 27.2 23.9 38.4 35.1 s not preprogrammed preprogrammed recovery from power-down (t pd ) -4040s (4) 4. not 100% tested, guaranteed by design characterization program suspend latency (4) -1010s erase suspend latency (4) -3030s erase suspend request rate (4) 20 20 20 ms minimum delay between 2 requests set protection (4) 40 170 170 s
st10f273m electrical characteristics doc id 13453 rev 4 139/186 24.7 a/d converter characteristics v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, 4.5v v aref v dd , v ss v agnd v ss + 0.2v table 59. flash data retention characteristics number of program / erase cycles (-40c < t a < 125c) data retention time (average ambient temperature 60c) 256 kbyte (code store) 64 kbyte (eeprom emulation) (1) 1. two 64 kbyte flash sectors may be typically used to emulate up to 4, 8 or 16 kbytes of eeprom. therefore, in case of an emulation of a 16 kbyt e eeprom, 100,000 flash progr am / erase cycles are equivalent to 800,000 eeprom program/erase cycles. for an efficient use of the read while write feature and/or eeprom emulation, please refer to the dedicated application note eeprom emulation with st10f2xx (an2061). contact your local field service, local sales person or stmicroelectr onics representative to obtain a co py of such a guideline document. 0 - 100 > 20 years > 20 years 1000 - > 20 years 10000 - 10 years 100000 - 1 year table 60. a/d converter characteristics symbol parameter test condition limit values unit min max v aref sr analog reference voltage (1) 4.5 v dd v v agnd sr analog ground voltage v ss v ss + 0.2 v v ain sr analog input voltage (2) v agnd v aref v i aref cc reference supply current running mode (3) ?5ma power down mode ? 1 a t s cc sample time (4) 1?s t c cc conversion time (5) 3?s dnl cc differential non linearity (6) no overload ?1 +1 lsb inl cc integral non linearity (6) no overload ?1.5 +1.5 lsb ofs cc offset error (6) no overload ?1.5 +1.5 lsb tue cc total unadjusted error (6) port5 port1 - no overload (3) port1 - overload (3) ?2.0 ?5.0 ?7.0 +2.0 +5.0 +7.0 lsb k cc coupling factor between inputs (3)(7) on both port5 and port1 ?10 ?6 ? c p1 cc input pin capacitance (3)(8) ?3pf c p2 cc port5 port1 ? 4 6 pf
electrical characteristics st10f273m 140/186 doc id 13453 rev 4 24.7.1 conversion timing control when a conversion is started, first the capa citances of the converter are loaded via the respective analog input pin to the current analog input voltage. the time to load the capacitances is referred to as sample time. next the sampled voltage is converted to a digital value several successive steps, which correspond to the 10-bit resolution of the adc. during these steps the internal capacitances are repeatedly charged and discharged via the v aref pin. the current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective st ep takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. the maximum current, however, that a source can deliver, depends on its internal resistance. the time that the two different actions (sampling, and converting) take during conversion can be programmed within a certain range in the st10f273m relative to the cpu clock. the absolute time that is consumed by the different conversion steps therefore is independent c s cc sampling capacitance (3)(8) ?3.5pf r sw cc analog switch resistance (3)(8) port5 port1 ? ? 600 1600 r ad cc ? 1300 1. v aref can be tied to ground when a/d converter is not in use: an extra consumption (around 200a) on main v dd is added due to internal analog circuitry not comple tely turned off. therefore, it is suggested to maintain the v aref at v dd level even when not in use, and eventually switch off the a/d converter circuitry by setting bit adoff in adcon register. 2. v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be 0x000 h or 0x3ff h , respectively. 3. not 100% tested, guaranteed by design characterization. 4. during the sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow t he capacitance to reach its final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depends on programming and can be taken from table 61: a/d converter programming . 5. this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result. values for t he conversion clock t cc depend on programming and can be taken from next table 61 . 6. dnl, inl, ofs and tue are tested at v aref = 5.0 v, v agnd = 0v, v dd = 5.0 v. it is guaranteed by design characterization for all other volt ages within the defined voltage range. ?lsb? has a value of v aref /1024. for port5 channels, the specified tue ( 2lsb) is guaranteed also with an overload condition (see i ov specification) occurring on maximum 2 not selected anal og input pins of port5 and if the absolute sum of input overload currents on all port5 anal og input pins does not exceed 10 ma. for port1 channels, the specifi ed tue is guaranteed when no overload c ondition is applied to port1 pins: when an overload condition oc curs on maximum 2 not selected analog input pins of port1 and the input positive overload current on all ana log input pins does not exceed 10 ma (either dynamic or static injection), the specified tue is degraded ( 7lsb). to acheive the sa me accuracy, the negative injection current on port1 pins must not exceed -1ma in case of both dynamic and static injection. 7. the coupling factor is measured on a channel whil e an overload condition occurs on the adjacent not selected channels with the overload cu rrent within the different spec ified ranges (for both positive and negative injection current). 8. refer to scheme in figure 41 . table 60. a/d converter characteristics (continued) symbol parameter test condition limit values unit min max
st10f273m electrical characteristics doc id 13453 rev 4 141/186 from the general speed of the controller. this allows adjusting the a/d converter of the st10f273m to the properties of the system: fast conversion can be achieved by programming the respective times to their absolute possible minimum. this is preferable for scanning high frequency signals. the internal resistance of analog source and analog supply must be sufficiently low, however. high internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum. this is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. the conversion rate in this case may be considerably lower, however. the conversion times are programmed via the upper four bits of register adcon. bit fields adctc and adstc are used to define the basic conversion time and in particular the partition between sample phase and comparison phases. the table below lists the possible combinations. the timings refer to the unit tcl, where f cpu = 1/2tcl. a complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. note: the total conversion time is compatible with the formula valid for st10f269, while the meaning of the bit fields adctc and adstc is no longer compatible: the minimum conversion time is 388 tcl, which at 40 mh z cpu frequency corresponds to 4.85s (see st10f269). 24.7.2 a/d conversion accuracy the a/d converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (v aref ) and converts it into 10-bit digital data. the table 61. a/d converter programming adctc adstc sample comparison extra total conversion 00 00 tcl * 120 tcl * 240 tcl * 28 tcl * 388 00 01 tcl * 140 tcl * 280 tcl * 16 tcl * 436 00 10 tcl * 200 tcl * 280 tcl * 52 tcl * 532 00 11 tcl * 400 tcl * 280 tcl * 44 tcl * 724 11 00 tcl * 240 tcl * 480 tcl * 52 tcl * 772 11 01 tcl * 280 tcl * 560 tcl * 28 tcl * 868 11 10 tcl * 400 tcl * 560 tcl * 100 tcl * 1060 11 11 tcl * 800 tcl * 560 tcl * 52 tcl * 1444 10 00 tcl * 480 tcl * 960 tcl * 100 tcl * 1540 10 01 tcl * 560 tcl * 1120 tcl * 52 tcl * 1732 10 10 tcl * 800 tcl * 1120 tcl * 196 tcl * 2116 10 11 tcl * 1600 tcl * 1120 tcl * 164 tcl * 2884
electrical characteristics st10f273m 142/186 doc id 13453 rev 4 absolute accuracy of the a/d conversion is the deviation between the input analog value and the output digital value. it includes the following errors: offset error (ofs) gain error (ge) quantization error non-linearity error (dif ferential and integral) these four error quantities are explained below using figure 40 . offset error offset error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the minimum (zero voltage) 00 to 01 ( figure 40 , see ofs). gain error gain error is the deviation between the actual and ideal a/d conversion characteristics when the digital output value changes from the 3feh to the maximum 3ffh once offset error is subtracted. gain error combined with offset error represents the so-called full-scale error ( figure 40 , ofs + ge). quantization error quantization error is the intrinsic error of the a/d converter and is expressed as 1/2 lsb. non-linearity error non-linearity error is the deviation between actual and the best-fitting a/d conversion characteristics (see figure 40 ): differential non-linearity error is the actual step dimension versus the ideal one (1 lsb ideal ). integral non-linearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. note that for integral non- linearity error, the effect of offset, gain and quantization errors is not included. note: bisector characteristic is obtained drawing a line from 1/2 lsb before the first step of the real characteristic, and 1/2 lsb after the last step again of the real characteristic. 24.7.3 total unadjusted error the total unadjusted error specifies the maximum deviation from the ideal characteristic: the number provided in the datasheet represents the maximum error with respect to the entire characteristic. it is a combination of the offset, gain and integral linearity errors. the different errors may compensate each other depending on the relative sign of the offset and gain errors. refer to figure 40 , see tue.
st10f273m electrical characteristics doc id 13453 rev 4 143/186 figure 40. a/d conversion characteristics 24.7.4 analog reference pins the accuracy of the a/d converter depends on the accuracy of its analog reference: a noise in the reference results in at least that much error in a conversion. a low pass filter on the a/d converter reference source (supplied through pins v aref and v agnd ) is recommended in order to clean the signal, minimizing the noise. a simple capacitive bypass may be sufficient in most cases; in presence of high rf noise energy, inductors or ferrite beads may be necessary. in this architecture, v aref and v agnd pins also represent the power supply of the analog circuitry of the a/d converter: there is an effective dc current requirement from the reference voltage by the internal resistor string in the r-c dac array and by the rest of the analog circuitry. an external resistance on v aref could introduce error under certain conditions: for this reason, series resistance is not advisable, and more in general any series devices in the filter network should be designed to minimize the dc resistance. analog input pins to improve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; moreover, it sources charge during the sampling phase, when the analog signal source is a high- impedance source. 2iivhw(uuru2)6 2iivhw(uuru2)6 *dlq(uuru*( /6%lghdo 9 $,1 /6% ,'($/ >/6% ,'($/ 9 $5() @ 'ljlwdo 2xw + (; ) ) ) ( ) ' ) & ) % ) $ ([dpsohridqdfwxdowudqvihufxuyh 7khlghdowudqvihufxuyh 'liihuhqwldoqrqolqhdulw\huuru'1/ ,qwhjudoqrqolqhdulw\huuru,1/ &hqwhuridvwhsriwkhdfwxdowudqvihufxuyh 4xdqwl]dwlrqhuuru/6% 7rwdoxqdgmxvwhghuuru78( %lvhfwru&kdudfwhulvwlf ,ghdo&kdudfwhulvwlf ("1($'5
electrical characteristics st10f273m 144/186 doc id 13453 rev 4 a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). th e rc filtering may be limited acco rding to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth). figure 41. a/d converter input pins scheme input leakage and external circuit the series resistor utilized to limit the current to a pin (see r l in figure 41 ), in combination with a large source impedance, can lead to a degradation of a/d converter accuracy when input leakage is present. data about maximum input leakage current at each pin is provided in the datasheet ( electrical characteristics section). input leakage is greatest at high operating temperatures and in general decreases by one half for each 10 c decrease in temperature. considering that, for a 10-bit a/d converter one count is about 5mv (assuming v aref = 5v), an input leakage of 100na acting though an r l = 50k of external resistance leads to an error of exactly one count (5mv); if the resistance were 100k , the error would become two counts. eventual additional leakage due to external clamping diodes must also be taken into account in computing the total leakage affecting the a/d converter measurements. another contribution to the total leakage is represented by the charge-sharing effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of a single channel (maximum when fixed channel continuous conversion mode is selected), it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 250 khz, with c s equal to 4pf, a resistance of 1m is obtained (r eq = 1 / f c c s , where f c represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance 5 ) & ) 5 6 5 / 5 6: & 3 & 6 9 '' 6dpsolqj 6rxufh )lowhu &xuuhqwolplwhu (;7(51$/&,5&8,7 , 17(51$/&,5&8,76&+(0( 5 6 6rxufhlpshgdqfh 5 ) )lowhuuhvlvwdqfh & ) )lowhufdsdflwdqfh 5 / &xuuhqwolplwhuuhvlvwdqfh 5 6: &kdqqhovhohfwlrqvzlwfklpshgdqfh 5 $' 6dpsolqjvzlwfklpshgdqfh & 3 3lqfdsdflwdqfhwzrfrqwulexwlrqv& 3 dqg& 3 & 6 6dpsolqjfdsdflwdqfh & 3 5 $' &kdqqho vhohfwlr q 9 $ ("1($'5
st10f273m electrical characteristics doc id 13453 rev 4 145/186 (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the following relation: the formula above provides constraints for external network design, in particular on a resistive path. a second aspect involving the capacitance network must be considered. assuming the three capacitances c f , c p1 and c p2 initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 41 ), when the sampling phase is started (a/d switch close), a charge-sharing phenomena is installed. figure 42. charge-sharing timing diagram during sampling phase in particular two different transient periods can be distinguished (see figure 42 ): a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time cons tant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is: this relation can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to the following equation: v a r s r f r l r sw r ad +++ + r eq ------------------------------------------------------------------------------ ? 1 2 -- - lsb < 9 $ 9 $ 9 $ w 7 6 9 &6 9rowdjh7udqvlhqwrq& 6 ' 9 /6% w 5 6: 5 $' & 6 7 6 w 5 / & 6 & 3 & 3 ("1($'5 1 r sw r ad + () c p c s ? c p c s + --------------------- - ? = 1 r sw r ad + () c s t s ? ? < v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? =
electrical characteristics st10f273m 146/186 doc id 13453 rev 4 a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraint on r l sizing is obtained: of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). c f being definitively bigger than c p1 , c p2 and c s , the final voltage v a2 (at the end of the charge transfer transient) will then be much higher than v a1 . the following equation must be respected (charge balance assuming now c s already charged at v a1 ): the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing (see figure 43 ). calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. 2 r l < c s c p1 c p2 ++ () ? 10 2 ? 10 r ? l = c s c p1 c p2 ++ () t s ? v a 2 c s c p1 c p2 c f +++ () ? v a c f ? v a 1 + c p1 c p2 +c s + () ? =
st10f273m electrical characteristics doc id 13453 rev 4 147/186 figure 43. anti-aliasing filter and conversion rate the considerations above lead to impose new c onstraints to the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive the following relation between the ideal and real sampled voltage on c s : from this formula, in the worst case (when v a is maximum, that is, for instance 5v), assuming to accept a maximum error of half a count (~2.44mv), a constraint is immediately obvious on c f value: in the next section an example of how to desig n the external network is provided, assuming some reasonable values for the internal parameters and making a hypothesis on the characteristics of the analog signal to be sampled. i i $qdorjvrxufhedqgzlgwk9$ i i 6dpsohgvljqdovshfwuxpi & frqyhuvlrqudwh i & i i ) i d i&1\txlvw i) i$qwldoldvlqjilowhulqjfrqglwlrq 7& d 5)&)&rqyhuvlrqudwhyvilowhusroh 1rlvh ("1($'5 v a v a2 ----------- c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------------ = c f 2048 c s ? >
electrical characteristics st10f273m 148/186 doc id 13453 rev 4 example of external network sizing the following hypotheses are formulated in order to proceed in designing the external network on a/d converter input pins: analog signal source bandwidth (f 0 ): 10 khz conversion rate (f c ): 25 khz sampling time (t s ): 1s pin input capacitance (c p1 ): 5pf pin input routing capacitance (c p2 ): 1pf sampling capacitance (c s ): 4pf maximum input current injection (i inj ): 3ma maximum analog source voltage (v am) :12v analog source impedance (r s ): 100 channel switch resistance (r sw ): 500 sampling switch resistance (r ad ): 200 1. supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 2. using the relation between c f and c s and taking some margin (4000 instead of 2048), it is possible to define c f : 3. as a consequence of step 1 and 2, rc can be chosen: 4. considering the current injection limitation and supposing that the source can go up to 12v, the total series resistance can be defined as: from which is now simple to define the value of r l : 5. now the three elements of the external circuit r f , c f and r l are defined. some conditions discussed in the previous paragraphs have been used to size the component, the other must now be verified. the relation which allows minimization of r c c f 1 2 f 0 ------------ 15.9 s = = c f 4000 c s ? 16nf = = r f 1 2 f 0 c f -------------------- - 995 1k ? = = r s r f r l v am i inj ------------- 4 k = = ++ r l v am i inj ------------- r f r s 2.9k = ? ? =
st10f273m electrical characteristics doc id 13453 rev 4 149/186 the accuracy error introduced by the switched capacitance equivalent resistance is in this case: so the error due to the voltage partitioning between the real resistive path and c s is less then half a count (considering the worst case when v a = 5v): the other condition to be verified is if the time constants of the transients are really and significantly shorter than the sampling period duration t s : for the complete set of parameters characterizing the st10f273m a/d converter equivalent circuit, refer to section 24.7: a/d converter characteristics on page 139 . 24.8 ac characteristics 24.8.1 test waveforms figure 44. input/output waveforms r eq 1 f c c s -------------- -10m = = v a r s r f r l r sw r ad +++ + r eq -------------------------------------------------------------------------- - 2.35mv = ? 1 2 -- - lsb < 1 r sw r ad + () = c s 2.8ns = ? t s = 1 s 10 2 ? 10 r ? l = c s c p1 c p2 ++ () 290ns = ? t s = 1 s 9 9 7hvw3rlqwv 99 9 9 $&lqsxwvgxulqjwhvwlqjduhgul yhqdw9irudorjlf?dqg 9irudorjlf? 7lplqjphdvxuhphqwvduhpdghdw9 ,+ 0lqirudorjlf?dqg9 ,/ pd[irudorjlf? ("1($'5
electrical characteristics st10f273m 150/186 doc id 13453 rev 4 figure 45. float waveform 24.8.2 definition of internal timing the internal operation of the st10f273m is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. the specification of the external timing (ac ch aracteristics) therefore depends on the time between two consecutive edges of the cpu clock, called ?tcl?. the cpu clock signal can be generated by different mechanisms. the duration of tcl and its variation (and also the derived external timing) depends on the mechanism used to generate f cpu . this influence must be regarded when calculating the timings for the st10f273m. the example for pll operation shown in figure 46 refers to a pll factor of 4. the mechanism used to generate the cpu clock is selected during reset by the logic levels on pins p0.15-13 (p0h.7-5). figure 46. generation mechanisms for the cpu clock 7lplqj 5hihuhqfh 3rlqwv 9 /2$' 9 9 /2$' 9 9 2+ 9 9 2/ 9 9 /2$' 9 2/ 9 2+ )ruwlplqjsxusrvhvdsruwslq lvqrorqjhuiordwlqjzkhq9 /2$' fkdqjhvri?p9 ,wehjlqvwriordwzkhqdp9fkdqjhiurpwkhordghg9 2+ 9 2/ ohyhorffxuv, 2+ , 2/ p$ ("1($'5 7&/7&/ 7&/7&/ i &38 i ;7$/ i &38 i ;7$/ 3kdvhorfnhgorrsrshudwlrq 'luhfw forfngulyh 7&/ 7&/ i &38 i ;7$/ 3uhvfdohurshudwlrq ("1($'5
st10f273m electrical characteristics doc id 13453 rev 4 151/186 24.8.3 clock generation modes the next ta bl e 6 2 associates the combinations of thes e three bits with the respective clock generation mode. 24.8.4 prescaler operation when pins p0.15-13 (p0h.7-5) equal ?001? during reset, the cpu clock is derived from the internal oscillator (input cloc k signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f xtal and the high and low time of f cpu (that is, the duration of an individual tcl) is defined by the period of the input clock f xtal . the timings listed in the ac characteristics that refer to tcl therefore can be calculated using the period of f xtal for any tcl. note that if the bit owddis in syscon register is cleared, th e pll runs on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. 24.8.5 direct drive when pins p0.15-13 (p0h.7-5) equal ?011? during reset the on-chip phase locked loop is disabled, the on-chip oscillator am plifier is bypassed and the cpu clock is directly driven by the input clock signal on xtal1 pin. table 62. on-chip clock generator selections p0.15-13 (p0h.7-5) cpu frequency f cpu = f xtal x f external clock input range (1)(2) 1. the external clock input range re fers to a cpu clock range of 1...4 0 mhz. moreover, the pll usage is limited to 4 to 12 mhz input frequency range. all conf igurations need a crystal (or ceramic resonator) to generate the cpu clock through th e internal oscillator amplifier (apart from direct drive): vice versa, the clock can be forced through an external clock source only in direct drive mode (on- chip oscillator amplifier disabled, so no crystal or resonator can be used). 2. the limits on input frequency are 4 to 12 mhz since the us age of the internal oscillat or amplifier is required. also when the pll is not used and the cpu clock corresponds to f xtal /2, an external crystal or resonator shall be used: it is not possible to forc e any clock though an external clock source. notes main osc (mhz) 111 f xtal x 4 4 to 8 default configuration 110 f xtal x 3 5.3 to 10.6 101 f xtal x 8 4 to 5 100 f xtal x 5 6.4 to 8 011 f xtal x 1 1 to 40 direct drive (oscillator bypassed) (3) 3. the maximum depends on the duty cycle of the exte rnal clock signal: when 40 mhz is used, 50% duty cycle shall be granted (low phase = high phase = 12.5ns ); when 20 mhz is select ed, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 12.5ns). 010 f xtal x 10 4 001 f xtal / 2 4 to 12 cpu clock via prescaler (2) 000 - - reserved
electrical characteristics st10f273m 152/186 doc id 13453 rev 4 the frequency of cpu clock (f cpu ) directly follows the frequency of f xtal so the high and low time of f cpu (that is, the duration of an individual tcl) is defined by the duty cycle of the input clock f xtal . therefore, the timings given in this chapter refer to the minimum tcl. this minimum value can be calculated by the following formula: for two consecutive tcls, the deviation caused by the duty cycle of f xtal is compensated, so the duration of 2tcl is always 1/f xtal . the minimum value tcl min has to be used only once for timings that require an odd number of tcls (1,3,...). timings that require an even number of tcls (2,4,...) may use the formula: the address float timings in multiplexed bus mode (t 11 and t 45 ) use the maximum duration of tcl (tcl max = 1/f xtal x dc max ) instead of tcl min . similarly to what happen for pr escaler operation, if the bit owddis in syscon register is cleared, the pll runs on its free-running frequency and delivers the clock signal for the oscillator watchdog. if bit owddis is set, then the pll is switched off. 24.8.6 oscillator watchdog (owd) an on-chip watchdog oscillator is implemented in the st10f2 73m. this feature is used for safety operation with external crystal oscillato r (available only when using direct drive mode with or without prescaler, so the pll is not used to generate the cpu clock multiplying the frequency of the external crys tal oscillator). this watchdog o scillator operates as following. the reset default configuration enables the watchdog oscillator. it can be disabled by setting the owddis (bit 4) of syscon register. when the owd is enabled, the pll runs at its free-running frequency, and it increments the watchdog counter. on each transition of external clock, the watchdog counter is cleared. if an external clock failure occurs, then the watchdog counter overflows (after 16 pll clock cycles). the cpu clock signal will be switched to the pll free-running clock signal, and the oscillator watchdog interrupt request is flagged. the cpu clock will not sw itch back to the external clock even if a valid external clock exits on xtal1 pin. only a hardware reset (or bidirectional software / watchdog reset) can switch the cpu clock source back to direct clock input. when the owd is disabled, the cpu clock is always the external oscillator clock (in direct drive or prescaler operation) and the pll is switched off to decrease consumption supply current. 24.8.7 phase locked loop (pll) for all other combinations of pins p0.15-13 (p0h.7-5) during reset the on-chip phase locked loop is enabled and it provides the cpu clock (see ta b l e 6 2 ). the pll multiplies the input frequency by the factor f which is selected via the combination of pins p0.15-13 (f cpu = tcl min 1f ? xtal l x l dc min = dc duty cycle = 2tcl 1 f xtal ? =
st10f273m electrical characteristics doc id 13453 rev 4 153/186 f xtal x f). with every f?th transition of f xtal the pll circuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, so the cpu clock frequency does not change abruptly. due to this adaptation to the input clock the frequency of f cpu is constantly ad justed so it is locked to f xtal . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. the timings listed in the ac characteristics that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. the real minimum value for tcl depends on the jitter of the pll. the pll tunes f cpu to keep it locked on f xtal . the relative deviation of tcl is the maximum when it is referred to one tcl period. this is especially important for bus cycles usin g wait states and for example, such as for the operation of timers or serial interfaces. for all slower operations and longer periods (for example, such as pulse train generation or measurement, or lower baudrates) the deviation caused by the pll jitter is ne gligible. refer to the next section 24.8.9: pll jitter for more details. 24.8.8 voltage controlled oscillator the st10f273m implements a pll which combines different levels of frequency dividers with a voltage controlled oscillator (vco ) working as freq uency multiplier. table 63 on page 153 gives a detailed summary of the internal settings and vco frequency. note: the pll input frequency ran ge is limited to 1 to 3.5 mhz, wh ile the vco oscillation range is 64 to 128 mhz. the cpu clock frequency range when pll is used is 16 to 40 mhz. table 63. internal pll divider mechanism p0.15-13 (p0h.7-5) xtal frequency input prescaler pll output prescaler cpu frequency f cpu = f xtal x f multiply by divide by 1 1 1 4 to 8 mhz f xtal / 4 64 4 ? f xtal x 4 1 1 0 5.3 to 10.6 mhz 48 f xtal x 3 1 0 1 4 to 5 mhz 64 2 f xtal x 8 1 0 0 6.4 to 8 mhz 40 f xtal x 5 0 1 1 1 to 40 mhz ? pll bypassed f xtal x 1 010 4mhz f xtal / 2 40 2 ? f xtal x 10 0 0 1 4 to 12 mhz ? pll bypassed f pll / 2 f xtal / 2 000 reserved
electrical characteristics st10f273m 154/186 doc id 13453 rev 4 example 1 f xtal = 4 mhz p0(15:13) = ?110? (multiplication by 3) pll input frequency = 1 mhz vco frequency = 48 mhz: not valid , must be 64 to 128 mhz f cpu = not valid example 2 f xtal = 8 mhz p0(15:13) = ?100? (multiplication by 5) pll input frequency = 2 mhz vco frequency = 80 mhz pll output frequency = 40 mhz (vco frequency divided by 2) f cpu = 40 mhz (no effect of output prescaler) 24.8.9 pll jitter the following terminology is hereafter defined: self referred sing le period jitter also called ?period jitter?, it can be defined as the difference of the t max and t min , where t max is maximum time period of the pll output clock and t min is the minimum time period of the pll output clock. self referred long term jitter also called ?n period jitter?, it can be defined as the difference of t max and t min , where t max is the maximum time difference between n + 1 clock rising edges and t min is the minimum time difference between n + 1 clock rising edges. here n should be kept sufficiently large to have the long term jitter. for n = 1, this becomes the single period jitter. jitter at the pll output can be due to the following reasons: jitter in the input clock noise in the pll loop jitter in the input clock pll acts like a low pass filter for any jitter in the input clock. input clock jitter with the frequencies within the pll loop bandwidth is passed to the pll output and higher frequency jitter (frequency > pll bandwidth) is attenuated @20db/decade. noise in the pll loop this contribution again can be caused by the following sources: device noise of the circuit in the pll noise in supply and substrate. device noise of the circuit in the pll the long term jitter is inversely proportional to the bandwidth of the pll: the wider is the loop bandwidth, the lower is the jitter due to noise in the loop. besides, the long term jitter is practically independent on the multiplication factor.
st10f273m electrical characteristics doc id 13453 rev 4 155/186 the most noise sensitive circuit in the pll circ uit is definitively the vco (voltage controlled oscillator). there are two ma in sources of noise : thermal (random noise, frequency independent so practically white noise) and flicker (low frequency noise, 1/f). for the frequency characteristics of the vco circuitry, the effect of the thermal noise results in a 1/f 2 region in the output noise spectrum, while the flicker noise in a 1/f 3 . assuming a noiseless pll input and supposing that the vco is dominated by its 1/f 2 noise, the r.m.s. value of the accumulated jitter is proportional to the square root of n , where n is the number of clock periods within the considered time interval. on the contrary, assuming again a noisele ss pll input and supposing that the vco is dominated by its 1/f 3 noise, the r.m.s. value of the accumulated jitter is proportional to n , where n is the number of clock periods within the considered time interval. the jitter in the pll loop can be modelized as dominated by the i1/f 2 noise for n smaller than a certain value depending on the pll output frequency and on the bandwidth characteristics of loop. above this first value, the jitter becomes dominated by the i1/f 3 noise component. lastly, for n greater than a second value of n, a saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods n). the pll loop acts as a high pass filter for any noise in the loop, with cutoff frequency equal to the bandwidth of the pll. the saturation value corresponds to what has been called self referred long term jitter of the pll. in figure 47 the maximum jitter trend versus the number of clock periods n (for some typical cpu frequencies) is reported: the curves represent the very worst case, computed taking into account all corners of temperature, power supply and process variations: the real jitter is always measured well below the given worst case values. noise in supply and substrate digital supply noise adds deterministic components to the pll output jitter, independent on multiplication factor. its effects is strongly reduced thanks to particular care used in the physical implementation and integration of the pll module inside the device. anyhow, the contribution of the digital noise to the global jitter is widely taken into account in the curves provided in figure 47 .
electrical characteristics st10f273m 156/186 doc id 13453 rev 4 figure 47. st10f273m pll jitter 24.8.10 pll lock / unlock during normal operation, if the pll gets unlocked for any reason, an interrupt request to the cpu is generated, and the reference clock (osc illator) is automatica lly disconnected from the pll input: in this way, the pll goes into free-running mode, providing the system with a backup clock signal (free running frequency f free ). this feature allows to recover from a crystal failure occurrence without risking to go into an undefined configuration: the system is provided with a clock allowing the execution of the pll unlock interrupt routine in a safe mode. the path between reference clock and pll input can be restored only by a hardware reset, or by a bidirectional software or watchdog reset event that forces the rstin pin low. note: the external rc circuit on rstin pin shall be properly sized in order to extend the duration of the low pulse to grant the pll gets locked before the level at rstin pin is recognized high: bidirectional reset internally drives rstin pin low for just 1024 tcl (definitively not sufficient to get the pll locked starting from free-running mode). -lwwhu>qv@ 1&38forfnshulrgv r r 0+] r r r 0+] 0+] 0+] 0+] 7 -,7 ("1($'5
st10f273m electrical characteristics doc id 13453 rev 4 157/186 24.8.11 main oscillator specifications dd = 5v 10%, v ss = 0v, t a = -40 to +125c figure 48. crystal oscillator and resonator connection diagram table 64. pll characteristics (v dd = 5v 10%, v ss =0v, t a = -40c to +125c) symbol parameter conditions value unit min max t psup pll start-up time (1) 1. not 100% tested, guaranteed by design characterization. stable v dd and reference clock ? 300 s t lock pll lock-in time stable v dd and reference clock, starting from free-running mode ? 250 t jit single period jitter (1) (cycle to cycle = 2 tcl) 6 sigma time period variation (peak to peak) -500 +500 ps f free pll free running frequency multiplication factors: 3, 4 250 2000 khz multiplication factors: 5, 8, 10 500 4000 table 65. main oscillator characteristics symbol parameter conditions value unit min typ max g m oscillator transconductance ?81735ma/v v osc oscillation amplitude (1) 1. not 100% tested, guaranteed by design characterization. peak to peak ? v dd ? 0.4 ? v v av oscillation voltage level (1) sine wave middle v dd / 2 ? 0.25 ? t stup oscillator start-up time (1) stable v dd - crystal 3 4 ms stable v dd - resonator 2 3 & $ & $ &u\vwdo ;7$/ ;7$/ 5hvrqdwru ;7$/ ;7$/ 67)0 67)0 ("1($'5
electrical characteristics st10f273m 158/186 doc id 13453 rev 4 the given values of c a do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pf to the values in the table. the crystal shunt capacitance (c 0 ), the package and the stray capacitance between xtal1 and xtal2 pins is globally assumed equal to 4pf. the external resistance between xtal1 and xtal2 is not necessary, since already present on the silicon. 24.8.12 32 khz oscillator specifications v dd = 5v 10%, v ss = 0v, t a = -40 to +125c figure 49. 32 khz crystal oscillator connection diagram table 66. main oscillator negative resistance (module) c a = 12pf 15pf 18pf 22pf 27pf 33pf 39pf 47pf 4 mhz 460 550 675 800 840 1000 1180 1200 8 mhz 380 460 540 640 580 --- 12 mhz 370 420 360 ----- table 67. 32 khz oscillator characteristics symbol parameter conditions value unit min typ max g m32 oscillator transconductance (1) 1. at power-on a high current biasing is applied for faster oscillation start-up. once the oscillation is started, the current biasing is reduced to lower the power consumption of the system. start-up 20 31 50 a/v normal run 8 17 30 v osc32 oscillation amplitude (2) 2. not 100% tested, guaranteed by design characterization. peak to peak 0.5 1.0 2.4 v v av32 oscillation voltage level (2) sine wave middle 0.7 0.9 1.2 t stup32 oscillator start-up time (2) stable v dd ?15s & $ & $ &u\vwdo ;7$/ ;7$/ 67)0 ("1($'5
st10f273m electrical characteristics doc id 13453 rev 4 159/186 the given values of c a do not include the stray capacitance of the package and of the printed circuit board: the negative resistance va lues are calculated assuming additional 5pf to the values in the table. the crystal shunt capacitance (c 0 ) and the package capacitance between xtal3 and xtal4 pins is globally assumed equal to 4pf. the external resistance between xtal3 and xtal4 is not necessar y, since already present on the silicon. warning: direct driving on xtal3 pin is not supported. always use a 32 khz crystal oscillator. 24.8.13 external clock drive xtal1 when direct drive configuration is selected during reset, it is possible to drive the cpu clock directly from the xtal1 pin, without particular restrictions on the maximum frequency, since the on-chip oscillator amp lifier is bypassed. the speed limit is imposed by internal logic that targets a maximum cpu frequency of 40 mhz. in all other clock configurations (direct drive with prescaler or pll usage) the on-chip oscillator amplifier is not bypass ed, so it determines the input clock speed limit. then, when the on-chip oscillator is enabled it is forbidden to use any external clock source different from crystal or ceramic resonator. table 68. minimum values of negative resistance (module) for 32 khz oscillator frequency c a = 6pf c a = 12pf c a = 15pf c a = 18pf c a = 22pf c a = 27pf c a = 33pf 32 khz - - - - 150 k 120 k 90 k table 69. external clock drive xtal1 timing parameter symbol direct drive f cpu = f xtal direct drive with prescaler f cpu = f xtal / 2 pll usage f cpu = f xtal x f unit min max min max min max xtal1 period (1)(2) 1. the minimum value for the xtal1 si gnal period shall be considered as th e theoretical minimum. the real minimum value depends on the duty cycle of the input clock signal. 2. 4 to 12 mhz is the input frequency range when using an external clock source. 40 mhz can be applied with an external clock source only when dire ct drive mode is selected: in this case, the oscillator amplifier is bypassed so it does not limit the input frequency. t osc sr 25 ? 10 250 100 250 ns high time (3) 3. the input clock signal must reach the defined levels v il2 and v ih2 . t 1 sr6 ?3?6? low time (3) t 2 sr6?3?6? rise time (3) t 3 sr?2?2?2 fall time (3) t 4 sr?2?2?2
electrical characteristics st10f273m 160/186 doc id 13453 rev 4 figure 50. external clock drive xtal1 note: when direct drive is selected, an external clock source can be used to drive xtal1. the maximum frequency of the external clock source depends on the duty cycle: when 40 mhz is used, 50% duty cycle shall be granted (low phase = high phase = 12.5ns); when for instance 20 mhz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 12.5ns). 24.8.14 memory cycle variables the tables below use three variables which are derived from the busconx registers and represent the special characteristics of the programmed memory cycle. the following table describes how these variables are to be computed. 24.8.15 external memory bus timing the following sections present the external memory bus timings. the given values are computed for a maximum cpu clock of 40 mhz. note: all external memory bus timings and ssc timings reported in the following tables are based on design characterization and not fully tested in production. 24.8.16 multiplexed bus v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, cl = 50pf, ale cycle time = 6 tcl + 2t a + t c + t f (75ns at 40 mhz cpu clock without wait states) w w w 9 ,/ w w 26& 9 ,+ ("1($'5 table 70. memory cycle variables description symbol values ale extension t a tcl x [alectl] memory cycle time wait states t c 2tcl x (15 - [mctc]) memory tri-statetime t f 2tcl x (1 - [mttc]) table 71. multiplexed bus timings symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max t 5 cc ale high time 4 + t a ? tcl - 8.5 + t a ?ns t 6 cc address setup to ale 1.5 + t a ? tcl - 11 + t a ?ns
st10f273m electrical characteristics doc id 13453 rev 4 161/186 t 7 cc address hold after ale 4 + t a ? tcl - 8.5 + t a ?ns t 8 cc ale falling edge to rd , wr (with rw-delay) 4 + t a ? tcl - 8.5 + t a ?ns t 9 cc ale falling edge to rd , wr (no rw-delay) -8.5 + t a ? -8.5 + t a ?ns t 10 cc address float after rd , wr (with rw-delay) ?6 ? 6ns t 11 cc address float after rd , wr (no rw-delay) 1 ?18.5 ? tcl + 6ns t 12 cc rd , wr low time (with rw-delay) 15.5 + t c ? 2tcl - 9.5 + t c ?ns t 13 cc rd , wr low time (no rw-delay) 28 + t c ? 3tcl - 9.5 + t c ?ns t 14 sr rd to valid data in (with rw-delay) ?6 + t c ? 2tcl - 19 + t c ns t 15 sr rd to valid data in (no rw-delay) ? 18.5 + t c ? 3tcl - 19 + t c ns t 16 sr ale low to valid data in ? 17.5 + t a + t c ? 3tcl - 20 + t a + t c ns t 17 sr address/unlatched cs to valid data in ? 20 + 2t a + t c ?4tcl-30+2t a +t c ns t 18 sr data hold after rd rising edge 0? 0 ?ns t 19 sr data float after rd 1 ? 16.5 + t f ? 2tcl - 8.5 + t f ns t 22 cc data valid to wr 10 + t c ? 2tcl - 15 + t c ?ns t 23 cc data hold after wr 4 + t f ? 2tcl - 8.5 + t f ?ns t 25 cc ale rising edge after rd , wr 15 + t f ? 2tcl - 10 + t f ?ns t 27 cc address/unlatched cs hold after rd , wr 10 + t f ? 2tcl - 15 + t f ?ns t 38 cc ale falling edge to latched cs -4 - t a 10 - t a -4 - t a 10 - t a ns t 39 sr latched cs low to valid data in ? 16.5 + t c + 2t a ?3tcl-21+t c +2t a ns t 40 cc latched cs hold after rd , wr 27 + t f ? 3tcl - 10.5 + t f ?ns t 42 cc ale fall. edge to rdcs , wrcs (with rw delay) 7 + t a ? tcl - 5.5 + t a ?ns t 43 cc ale fall. edge to rdcs , wrcs (no rw delay) -5.5 + t a ? -5.5 + t a ?ns t 44 cc address float after rdcs , wrcs (with rw delay) ? 1.5 ? 1.5 ns table 71. multiplexed bus timings (continued) symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max
electrical characteristics st10f273m 162/186 doc id 13453 rev 4 t 45 cc address float after rdcs , wrcs (no rw delay) ? 14 ? tcl + 1.5 ns t 46 sr rdcs to valid data in (with rw delay) ?4 + t c ? 2tcl - 21 + t c ns t 47 sr rdcs to valid data in (no rw delay) ? 16.5 + t c ? 3tcl - 21 + t c ns t 48 cc rdcs , wrcs low time (with rw delay) 15.5 + t c ? 2tcl - 9.5 + t c ?ns t 49 cc rdcs , wrcs low time (no rw delay) 28 + t c ? 3tcl - 9.5 + t c ?ns t 50 cc data valid to wrcs 10 + t c ? 2tcl - 15 + t c ?ns t 51 sr data hold after rdcs 0? 0 ?ns t 52 sr data float after rdcs 1 ? 16.5 + t f ? 2tcl - 8.5 + t f ns t 54 cc address hold after rdcs , wrcs 6 + t f ? 2tcl - 19 + t f ?ns t 56 cc data hold after wrcs 6 + t f ? 2tcl - 19 + t f ?ns table 71. multiplexed bus timings (continued) symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max
st10f273m electrical characteristics doc id 13453 rev 4 163/186 figure 51. external memory cycle: multiplexed bus, with/ without read/ write delay, normal ale 'dwd,q 'dwd2xw $gguhvv $gguhvv w w 5hdg&\foh :ulwh&\foh w w w w w w w w w w w w w w p w $gguhvv w w w w w w w w w w $gguhvv w w w w &/.287 $/( &6[ $$ $$ $gguhvv'dwd 5' :5 :5/ %+( :5+ %xv3 $gguhvv'dwd %x v3 ("1($'5
electrical characteristics st10f273m 164/186 doc id 13453 rev 4 figure 52. external memory cycle: multiplexed bus, with/ without read/ write delay, extended ale data out address data in address address t 5 t 16 t 6 t 7 t 39 t 40 t 14 t 8 t 18 t 23 t 6 t 27 t 38 t 10 t 19 t 25 t 17 t 9 t 11 t 15 t 12 t 13 t 8 t 10 t 9 t 11 t 12 t 13 t 22 t 27 t 17 t 6 read cycle write cycle clkout ale csx a23-a16 (a15-a8) rd wr wrl bhe wrh address/data bus (p0) address/data bus (p0) gapgcft00935
st10f273m electrical characteristics doc id 13453 rev 4 165/186 figure 53. external memory cycle: multiplexed bus, with/ without read/ write delay, normal ale, read/ write chip select read cycle write cycle clkout ale a23-a16 (a15-a8) bhe data in data out address address t 44 t 5 t 16 t 25 t 27 t 51 t 46 t 50 t 56 t 48 t 42 t 42 t 6 t 52 address t 17 t 6 t 7 t 43 t 45 t 49 t 47 t 16 t 48 t 49 address t 43 rdcsx wrcsx address/data bus (p0) address/data bus (p0) gapgcft00936
electrical characteristics st10f273m 166/186 doc id 13453 rev 4 figure 54. external memory cycle: multiplexed bus, with/ without read/ write delay, extended ale, read/ write chip select data out address data in address address t 5 t 16 t 6 t 7 t 46 t 42 t 42 t 50 t 18 t 56 t 6 t 54 t 44 t 19 t 25 t 17 t 43 t 45 t 47 t 48 t 49 t 49 t 43 t 48 t 44 t 45 read cycle write cycle clkout ale a23-a16 (a15-a8) bhe rdcsx wrcsx address/data bus (p0) address/data bus (p0) gapgcft00937
st10f273m electrical characteristics doc id 13453 rev 4 167/186 24.8.17 demultiplexed bus v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, cl = 50pf, ale cycle time = 4 tcl + 2t a + t c + t f (50ns at 40 mhz cpu clock without wait states). table 72. demultiplexed bus timings symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max t 5 cc ale high time 4 + t a ?tcl - 8.5 + t a ?ns t 6 cc address setup to ale 1.5 + t a ?tcl - 11 + t a ?ns t 80 cc address/unlatched cs setup to rd , wr (with rw-delay) 12.5 + 2t a ? 2tcl - 12.5 + 2t a ?ns t 81 cc address/unlatched cs setup to rd , wr (no rw-delay) 0.5 + 2t a ?tcl - 12 + 2t a ?ns t 12 cc rd , wr low time (with rw-delay) 15.5 + t c ? 2tcl - 9.5 + t c ?ns t 13 cc rd , wr low time (no rw-delay) 28 + t c ? 3tcl - 9.5 + t c ?ns t 14 sr rd to valid data in (with rw-delay) ?6 + t c ?2tcl - 19 + t c ns t 15 sr rd to valid data in (no rw-delay) ? 18.5 + t c ?3tcl - 19 + t c ns t 16 sr ale low to valid data in ? 17.5 + t a + t c ? 3tcl - 20 + t a + t c ns t 17 sr address/unlatched cs to valid data in ? 20 + 2t a + t c ? 4tcl - 30 + 2t a + t c ns t 18 sr data hold after rd rising edge 0? 0 ?ns t 20 sr data float after rd rising edge (with rw-delay) (1) ? 16.5 + t f ? 2tcl - 8.5 + t f + 2t a ns t 21 sr data float after rd rising edge (no rw-delay) (1) ?4 + t f ? tcl - 8.5 + t f + 2t a ns t 22 cc data valid to wr 10 + t c ? 2tcl - 15 + t c ?ns t 24 cc data hold after wr 4 + t f ?tcl - 8.5 + t f ?ns t 26 cc ale rising edge after rd , wr -10 + t f ?-10 + t f ?ns t 28 cc address/unlatched cs hold after rd , wr (2) 0 + t f ?0 + t f ?ns t 28h cc address/unlatched cs hold after wrh -5 + t f ?-5 + t f ?ns t 38 cc ale falling edge to latched cs -4 - t a 6 - t a -4 - t a 6 - t a ns
electrical characteristics st10f273m 168/186 doc id 13453 rev 4 t 39 sr latched cs low to valid data in ? 16.5 + t c + 2t a ? 3tcl - 21 + t c + 2t a ns t 41 cc latched cs hold after rd , wr 2 + t f ? tcl - 10.5 + t f ?ns t 82 cc address setup to rdcs , wrcs (with rw-delay) 14 + 2t a ? 2tcl - 11 + 2t a ?ns t 83 cc address setup to rdcs , wrcs (no rw-delay) 2 + 2t a ? tcl - 10.5 + 2t a ?ns t 46 sr rdcs to valid data in (with rw-delay) ?4 + t c ?2tcl - 21 + t c ns t 47 sr rdcs to valid data in (no rw-delay) ? 16.5 + t c ?3tcl - 21 + t c ns t 48 cc rdcs , wrcs low time (with rw-delay) 15.5 + t c ? 2tcl - 9.5 + t c ?ns t 49 cc rdcs , wrcs low time (no rw-delay) 28 + t c ? 3tcl - 9.5 + t c ?ns t 50 cc data valid to wrcs 10 + t c ? 2tcl - 15 + t c ?ns t 51 sr data hold after rdcs 0? 0 ?ns t 53 sr data float after rdcs (with rw-delay) 3 ? 16.5 + t f ? 2tcl - 8.5 + t f ns t 68 sr data float after rdcs (no rw-delay) 3 ?4 + t f ? tcl - 8.5 + t f ns t 55 cc address hold after rdcs , wrcs -8.5 + t f ? -8.5 + t f ?ns t 57 cc data hold after wrcs 2 + t f ? tcl - 10.5 + t f ?ns 1. rw-delay and t a refer to the next following bus cycle 2. read data are latched with the same clock edge that triggers the address change and the rising rd edge. therefore address changes before the end of rd have no impact on read cycles. table 72. demultiplexed bus timings (continued) symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max
st10f273m electrical characteristics doc id 13453 rev 4 169/186 figure 55. external memory cycle: demultiplexed bus, with/ without read/ write delay, normal ale :ul w hf\fo h &/.287 $/( $ $ $ $3 %+( :5 :5/ :5+ 'dwdlq 'dwd rxw w w w w w w w w w $gguhvv w w w w w w w w w w w w w w x w w w w ruw k &6[ 5h d g f \ f o h 'dwdexv3 5' '''' 'dwdexv3 '''' ("1($'5
electrical characteristics st10f273m 170/186 doc id 13453 rev 4 figure 56. external memory cycle: demultiplexed bus, with/ without read/ write delay, extended ale address t 5 t 16 t 39 t 41 t 14 t 24 t 6 t 38 t 20 t 26 t 17 t 15 t 12 t 13 t 12 t 13 t 22 data in t 18 t 21 t 6 t 17 t 28 t 28 data out t 80 t 81 t 80 t 81 read cycle write cycle clkout ale csx rd wr wrl wrh data bus (p0) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 a23-a16 a15-a0 (p1) bhe gapgcft00939
st10f273m electrical characteristics doc id 13453 rev 4 171/186 figure 57. external memory cycle: demultiplexed bus, with/ without read/ write delay, normal ale, read/ write chip select read cycle write cycle clkout ale data in data out t 5 t 16 t 51 t 46 t 50 t 48 address t 17 t 49 t 47 t 48 t 49 t 68 t 53 t 83 t 82 t 26 t 57 t 55 t 6 t 82 t 83 rdcsx wrcsx data bus (p0) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 a23-a16 a15-a0 (p1) bhe gapgcft00940
electrical characteristics st10f273m 172/186 doc id 13453 rev 4 figure 58. external memory cycle: demultiplexed bus, without read/ write delay, extended ale, read/ write chip select address t 5 t 16 t 46 t 57 t 6 t 53 t 26 t 17 t 47 t 48 t 49 t 48 t 49 t 50 data in t 51 t 68 t 55 data out t 82 t 83 t 82 t 83 read cycle write cycle clkout ale rdcsx wrcsx data bus (p0) (d15-d8) d7-d0 data bus (p0) (d15-d8) d7-d0 a23-a16 a15-a0 (p1) bhe gapgcft00941
st10f273m electrical characteristics doc id 13453 rev 4 173/186 24.8.18 clkout and ready v dd = 5v 10%, v ss = 0v, t a = -40 to + 125c, cl = 50pf table 73. clkout and ready timings symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max t 29 cc clkout cycle time 25 25 2tcl 2tcl ns t 30 cc clkout high time 9 ? tcl ? 3.5 ? t 31 cc clkout low time 10 ? tcl ? 2.5 ? t 32 cc clkout rise time ? 4 ? 4 t 33 cc clkout fall time ? 4 ? 4 t 34 cc clkout rising edge to ale falling edge ? 2 + t a 8 + t a ? 2 + t a 8 + t a t 35 sr synchronous ready setup time to clkout 17 ? 17 ? t 36 sr synchronous ready hold time after clkout 2? 2 ? t 37 sr asynchronous ready low time 35 ? 2tcl + 10 ? t 58 sr asynchronous ready setup time (1) 1. these timings are given for characterization purposes only, in order to assure recognition at a specific clock edge. 17 ? 17 ? t 59 sr asynchronous ready hold time (1) 2? 2 ? t 60 sr async. ready hold time after rd , wr high (demultiplexed bus) (2) 2. demultiplexed bus is the worst case. for multiple xed bus 2tcl are to be added to the maximum values. this adds even more time for deactivating ready. 2t a and t c refer to the next following bus cycle, t f refers to the current bus cycle. 02t a + t c + t f 02t a + t c + t f
electrical characteristics st10f273m 174/186 doc id 13453 rev 4 figure 59. clkout and ready 1. cycle as programmed, including mctc wait states (example shows 0 mctc ws). 2. the leading edge of the respective command depends on rw-delay. 3. ready sampled high at this sampling point generates a ready controlled wait state, ready sampled low at this sampling point terminat es the currently running bus cycle. 4. ready may be deactivated in response to the traili ng (rising) edge of the corresponding command (rd or wr ). 5. if the asynchronous ready signal does not fulfill the indicated setup and hold times with respect to clkout (for example, because clkout is not enabled), it must fulfill t 37 in order to be safely synchronized. this is guaranteed, if ready is re moved in response to the command (see note 4). 6. multiplexed bus modes have a mux wait state added a fter a bus cycle, and an additional mttc wait state may be inserted here. for a multiplexed bus with mttc wait state this delay is two clkout cycles, for a demultiplexed bus without mttc wait state this delay is zero. 7. the next external bus cycle may start here. 24.8.19 external bus arbitration v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, c l = 50pf t 30 t 34 t 35 t 36 t 35 t 36 t 58 t 59 t 58 t 59 wait state ready mux / tri-state 6) t 32 t 33 t 29 running cycle 1) t 31 t 37 3) 3) 5) t 60 4) 6) 2) 7) 3) 3) clkout a le rd , wr synchronous asynchronous ready ready gapgcft00942 table 74. external bus arbitration timings symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max t 61 sr hold input setup time to clkout 18.5 ? 18.5 ? ns t 62 cc clkout to hlda high or breq low delay ? 12.5 ? 12.5 ns
st10f273m electrical characteristics doc id 13453 rev 4 175/186 figure 60. external bus arbitration (releasing the bus) 1. the st10f273m will complete the currently running bus cycle before granting bus access. 2. this is the first possibility for breq to become active. 3. the cs outputs will be resistive high (pull-up) after t 64 . t 63 cc clkout to hlda low or breq high delay ? 12.5 ? 12.5 ns t 64 cc csx release (1) ?20?20ns t 65 cc csx drive -415-415ns t 66 cc other signals release (1) ?20?20ns t 67 cc other signals drive -4 15 -4 15 ns 1. partially tested, guaranteed by design characterization table 74. external bus arbitration timings (continued) symbol parameter f cpu = 40 mhz tcl = 12.5ns variable cpu clock 1/2 tcl = 1 to 40 mhz unit min max min max t 61 t 63 t 66 1) t 64 1) 2) t 62 3) clkout hold hlda breq others csx (p6.x) gapgcft00943
electrical characteristics st10f273m 176/186 doc id 13453 rev 4 figure 61. external bus arbitration (regaining the bus) 1. this is the last chance for breq to trigger the indicated regain-sequence. even if breq is activated earlier, the regain-sequence is initiated by hold going high. please note that hold may also be deactivated without the st10f273m requesting the bus. 2. the next st10f273m driven bus cycle may start here. clkout hold hlda other signals t 62 csx (on p6.x) t 67 t 62 1) 2) t 65 t 61 breq t 63 t 62 gapgcft00944
st10f273m electrical characteristics doc id 13453 rev 4 177/186 24.8.20 high-speed synchronous serial interface (ssc) timing master mode v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, c l = 50pf table 75. ssc master mode timings symbol parameter max. baudrate 6.6mbaud (1) @f cpu = 40 mhz ( = 0002h) variable baudrate ( = 0001h - ffffh) unit min max min max t 300 cc ssc clock cycle time (2) 150 150 8tcl 262144 tcl ns t 301 cc ssc clock high time 63 ? t 300 / 2 - 12 ? t 302 cc ssc clock low time 63 ? t 300 / 2 - 12 ? t 303 cc ssc clock rise time ? 10 ? 10 t 304 cc ssc clock fall time ? 10 ? 10 t 305 cc write data valid after shift edge ? 15 ? 15 t 306 cc write data hold after shift edge (3) -2?-2? t 307p sr read data setup time before latch edge, phase error detection on (sscpen = 1) 37.5 ? 2tcl + 12.5 ? t 308p sr read data hold time after latch edge, phase error detection on (sscpen = 1) 50 ? 4tcl ? t 307 sr read data setup time before latch edge, phase error detection off (sscpen = 0) 25 ? 2tcl ? t 308 sr read data hold time after latch edge, phase error detection off (sscpen = 0) 0?0? 1. when 40 mhz cpu clock is used the maximum baudrate cannot be higher than 6.6mbaud ( = ?2h?) due to the limited granularity of . value ?1h? for can be used only with cpu clock equal to (or lower than) 32 mhz. 2. formula for ssc clock cycle time: t 300 = 4 tcl x ( + 1) where represents the content of the ssc baudrate register, taken as unsigned 16-bit integer. mini mum limit allowed for t 300 is 125ns (corresponding to 6.6mbaud) 3. partially tested, guaranteed by design characterization
electrical characteristics st10f273m 178/186 doc id 13453 rev 4 figure 62. ssc master timing 1. the phase and polarity of shift and latch edge of sclk is programmable. this fi gure uses the leading clock edge as shift edge (drawn in bold), with latch on traili ng edge (sscph = 0b), idle clock line is low, leading clock edge is low-to-high tr ansition (sscpo = 0b). 2. the bit timing is repeated for all bi ts to be transmitted or received. slave mode v dd = 5v 10%, v ss = 0v, t a = -40 to +125c, c l = 50pf t 303 t 304 t 305 t 305 t 305 t 306 t i b t u o t s a l t i b t u o t s 1 2nd out bit t 300 t 302 t 301 1) 2) t 307 2nd.in bit 1st.in bit t 308 t 307 last.in bit t 308 sclk mtsr mrst gapgcft00946 table 76. ssc slave mode timings symbol parameter max. baudrate 6.6 mbaud (1) @f cpu = 40 mhz ( = 0002h) variable baudrate ( = 0001h - ffffh) unit min max min max t 310 sr ssc clock cycle time (2) 150 150 8tcl 262144 tcl ns t 311 sr ssc clock high time 63 ? t 310 / 2 ? 12 ? ns t 312 sr ssc clock low time 63 ? t 310 / 2 ? 12 ? ns t 313 sr ssc clock rise time ? 10 ? 10 ns t 314 sr ssc clock fall time ? 10 ? 10 ns t 315 cc write data valid after shift edge ? 55 ? 2tcl + 30 ns t 316 cc write data hold after shift edge 0 ? 0 ? ns t 317p sr read data setup time before latch edge, phase error detection on (sscpen = 1) 62 ? 4tcl + 12 ? ns t 318p sr read data hold time after latch edge, phase error detection on (sscpen = 1) 87 ? 6tcl + 12 ? ns
st10f273m electrical characteristics doc id 13453 rev 4 179/186 figure 63. ssc slave timing 1. the phase and polarity of shift and latch edge of sclk is programmable. this fi gure uses the leading clock edge as shift edge (drawn in bold), with latch on traili ng edge (sscph = 0b), idle clock line is low, leading clock edge is low-to-high tr ansition (sscpo = 0b). 2. the bit timing is repeated for all bi ts to be transmitted or received. t 317 sr read data setup time before latch edge, phase error detection off (sscpen = 0) 6? 6 ?ns t 318 sr read data hold time after latch edge, phase error detection off (sscpen = 0) 31 ? 2tcl + 6 ? ns 1. when 40 mhz cpu clock is used the maximum baudrate cannot be higher than 6.6mbaud ( = ?2h?) due to the limited granularity of . value ?1h? for may be used only with cpu clock lower than 32 mhz (after checking that resulting timings are suitable for the master). 2. formula for ssc clock cycle time: t 310 = 4 tcl * ( + 1) where represents the content of the ssc b audrate register, taken as unsigned 16-bit integer. minimum limit allowed for t 310 is 150ns (corresponding to 6.6mbaud). table 76. ssc slave mode timings (continued) symbol parameter max. baudrate 6.6 mbaud (1) @f cpu = 40 mhz ( = 0002h) variable baudrate ( = 0001h - ffffh) unit min max min max t 313 t 314 t 315 t 315 t 315 t 316 t i b t u o t s a l t i b t u o t s 12nd out bit t 310 t 312 t 311 1) 2) t 317 2nd.in bit 1st.in bit t 318 t 317 last.in bit t 318 sclk mrst mtsr gapgcft00947
package information st10f273m 180/186 doc id 13453 rev 4 25 package information 25.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 25.2 pqfp144 mechanical data table 77. pqfp144 mechanical data dim mm min. typ. max. a 4.10 a1 0.25 0.50 a2 3.20 3.40 3.60 b 0.29 0.45 c 0.11 0.23 d 30.95 31.20 31.45 d1 27.80 28.00 28.20 d3 22.75 e 30.95 31.20 31.45 e1 27.80 28.00 28.20 e3 22.75 e0.65 l 0.73 0.88 1.03 l1 0.25 l2 1.60 k0 7 ddd 0.10
st10f273m package information doc id 13453 rev 4 181/186 figure 64. pqfp144 package dimensions ("1($'5
package information st10f273m 182/186 doc id 13453 rev 4 25.3 lqfp144 mechanical data table 78. lqfp144 mechanical data dim mm min. typ. max. a 1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 0.20 d 21.80 22.00 22.20 d1 19.80 20.00 20.20 d3 17.50 e 21.80 22.00 22.20 e1 19.80 20.00 20.20 e3 17.50 e0.50 l 0.45 0.60 0.75 l1 1.00 k03.57 ccc 0.8
st10f273m package information doc id 13453 rev 4 183/186 figure 65. lqfp144 package dimensions ("1($'5
ordering information st10f273m 184/186 doc id 13453 rev 4 26 ordering information table 79. order codes order code package packing temperature range cpu frequency range st10f273mr-4q3 pqfp144 tr ay -40 to +125c 1 to 40 mhz st10f273mr-4qr3 tape and reel st10f273mr-4t3 lqfp144 tr ay st10f273mr-4tx3 tape and reel
st10f273m revision history doc id 13453 rev 4 185/186 27 revision history table 80. document revision history date revision changes 03-may-2007 1 initial release 02-jul-2007 2 changed document status from preliminary data to datasheet section 4: memory organization on page 21 : - changed size of b0tf from 8 to 4kbytes - removed ?flash temporary unprotection? from x-miscellaneous features table 2: summary of iflash address range on page 21 : changed size of b0tf from 8 to 4kbytes figure 6: flash structure on page 27 : changed test-flash size from 8 to 4kbytes table 5: flash module sectorization (write operations, or roms1 = ?1?) on page 29 : changed b0tf address and size (8 to 4kbytes) section 14: a/d converter on page 72 : replaced ?40.630 cpu clock cycles? with ?40630 cpu clock cycles? in end of section section 21.1: idle mode on page 109 : made minor text changes section 21.2: power-down mode on page 109 : made minor text changes table 57: dc characteristics on page 134 : - changed max value and unit for i pd1 from 1ma to 150a - changed max value and unit for i pd3 from 1.1ma to 200a - changed test conditions and max values for i sb2 - changed footnote link for symbol i p0h - changed footnote link for symbol i p0l table 58: flash characteristics on page 138 : - modified bank 0 program parameter and values - removed bank 1 program parameter and values - modified bank 0 erase parameter and values - removed bank 1 erase parameter and values section 24.7.4: analog reference pins on page 143 : minor text editing changes table 62: on-chip clock generator selections on page 151 : - changed external clock input range for f xtal x 5 - changed external clock input range for f xtal x 1 - replaced ?cpu clock range of 1. ..60 mhz? with ?cpu clock range of 1...40 mhz? in footnote 1 added section 25.1: ecopack? on page 180 and updated content added section 26.2: mechanical data and package dimensions on page 174 20-aug-2012 3 updated table 17: farh register description updated chapter 25: package information updated table 79: order codes 17-sep-2013 4 updated disclaimer
st10f273m 186/186 doc id 13453 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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