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cy2545, cy2547 quad pll programmable spread spectrum clock generator with serial i 2 c interface cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-13196 rev. *c revised july 5, 2011 features four fully integrated phase locked loops (plls) input frequency range ? external crystal: 8 to 48 mhz ? external reference: 8 to 166 mhz clock wide operating out put frequency range ? 3 to 166 mhz serial programmable over 2-wire i 2 c interface programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles v dd supply voltage options: ? 2.5 v, 3.0 v, and 3.3 v for cy2545 ? 1.8 v for cy2547 selectable output clock voltages independent of v dd supply: ? 2.5 v, 3.0 v, and 3.3 v for cy2545 ? 1.8 v for cy2547 power-down, output enable, or frequency select features low jitter, high accuracy outputs ability to synthesize nonstandard frequencies with fractional-n capability up to eight clock outputs with programmable drive strength glitch-free outputs while frequency switching 24-pin qfn package commercial and industrial temperature ranges benefits multiple high performance plls allow synthesis of unrelated frequencies nonvolatile programming for personalization of pll frequencies, spread spectrum char acteristics, drive strength, crystal load capacitance, and output frequencies application specific programmable emi reduction using spread spectrum for clocks programmable plls for system frequency margin tests meets critical timing requirem ents in complex system designs suitability for pc, consumer, portable, and networking applica- tions capable of zero ppm frequency synthesis error uninterrupted system operation during clock frequency switch application compatibility in standard and lo w power systems logic block diagram osc mux and control logic i2c pll1 pll2 pll3 (ss) pll4 (ss) output dividers and drive strength control clk1 clk 8 clk 7 clk 6 clk 5 clk 4 clk3 clk 2 crossbar switch clkin/rst fs sson xout xin/ exclkin pd#/oe scl sda bank 1 bank 2 bank 3 [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 2 of 17 contents pinouts .............................................................................. 3 general description ......................................................... 5 four configurable plls .............................................. 5 i2c programming ........................................................ 5 input reference clocks .......... .............. .............. ......... 5 multiple power supplies ...... ........................................ 5 output bank settings .................................................. 5 output source selection ............................................. 5 spread spectrum control ............................................ 5 frequency select ........................................................ 5 glitch-free frequency switch ..................................... 5 device reset function ................................................ 5 pd#/oe mode ............................................................. 6 keep alive mode ......................................................... 6 output drive strength .................................................. 6 generic configuration and custom frequency ........... 6 serial i2c programming interface protocol and timing ......................................................... 6 device address ........................................................... 6 data valid .................................................................... 6 data frame ................................................................. 6 acknowledge pulse ..................................................... 6 write operations ............................................................... 7 writing individual bytes ....... .............. .............. ............ 7 writing multiple bytes .................................................. 7 read operations ............................................................... 7 current address read ................................................. 7 random read .............. .............. .............. ............ ....... 7 sequential read .......................................................... 7 serial i2c programming interface timing ...................... 9 serial i2c progra mming interface timing specifications ...................................................... 9 absolute maximum conditions ..................................... 10 recommended operating conditions .......................... 10 dc electrical specifications .......................................... 11 recommended crystal specification for smd package ............................................................ 12 test and measurement setup ........................................ 13 voltage and timing definitions ..................................... 13 ordering information ...................................................... 14 package drawing and dimensions ............................... 15 reference information ................................................... 16 acronyms ................................................................. 16 document conventions ......... .................................... 16 document history page ................................................. 17 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 3 of 17 pinouts figure 1. pin diagram ? cy2545 24-pin qfn 2 3 c l k i n / r s t clk1 pd#oe cy2545 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 dnu clk2 s d a s c l c l k 3 / f s c l k 4 g n d clk5 vdd_clk_b clk6/sson vdd_clk_b clk7 gnd clk8 v d d x o u t x i n / e x c l k i n g n d 24ld qfn table 1. pin definition ? cy2545 24-pin qfn (v dd = 2.5 v, 3.0 v or 3.3 v supply) pin number name i/o description 1 gnd power power supply ground 2 clk1 output programmable clock output. output voltage depends on bank1 voltage 3 vdd_clk_b1 power power supply for bank1 (clk1, clk2) output: 2.5 v/3.0 v/3.3 v 4 pd#/oe input multifunction programmable pin: output enable or power-down mode 5 dnu dnu do not use this pin 6 clk2 output programmable clock output. output voltage depends on bank1 voltage 7 gnd power power supply ground 8 scl input serial data clock 9 sda input/output serial data input/output 10 clk3/fs output/input multifunction programmabl e pin: programmable clock output or frequency select input pin. output voltage of clk3 depends on bank2 voltage 11 clk4 output programmable clock output. ou tput voltage depends on bank2 voltage 12 gnd power power supply ground 13 clk5 output programmable clock output. output voltage depends on bank2 voltage 14 vdd_clk_b2 power power supply for bank2 (c lk3, clk4, clk5) output: 2.5 v/3.0 v/3.3 v 15 clk6/sson output/input multifunction programm able pin: programmable clock output or spread spectrum on/off control input pin. output voltage of clk6 depends on bank3 voltage 16 vdd_clk_b3 power power supply for bank3 (c lk6, clk7, clk8) output: 2.5 v/3.0 v/3.3 v 17 clk7 output programmable clock output. output voltage depends on bank3 voltage 18 gnd power power supply ground 19 gnd power power supply ground 20 clk8 output programmable clock output. output voltage depends on bank3 voltage 21 clkin/rst input/input multifunction programmable pin. high true reset input or 2.5 v/3.0 v/3.3 v external reference clock input. the signal level of clkin input must track v dd power supply on pin 22. 22 v dd power power supply for core and inputs: 2.5 v/3.0 v/3.3 v [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 4 of 17 figure 2. pin diagram ? cy2547 24-pin qfn 23 xout output crystal output 24 xin/exclkin input crystal input or 1.8 v external clock input table 1. pin definition ? cy2545 24-pin qfn (v dd = 2.5 v, 3.0 v or 3.3 v supply) (continued) pin number name i/o description 2 3 c l k i n / r s t clk1 pd#oe cy2547 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 vdd clk2 s d a s c l c l k 4 g n d clk5 vdd_clk_b clk6/sson vdd_clk_b clk7 gnd clk8 v d d x o u t x i n / e x c l k i n g n d 24ld qfn c l k 3 / f s table 2. pin definition ? cy2547 24-pin qfn (v dd = 1.8 v supply) pin number name i/o description 1 gnd power power supply ground 2 clk1 output programmable clock output. output voltage depends on bank1 voltage 3 vdd_clk_b1 power power supply for bank1 (clk1, clk2) output: 1.8 v 4 pd#/oe input multifunction programmable pi n: output enable or power-down mode 5v dd power power supply for core and inputs: 1.8 v 6 clk2 output programmable output clock. output voltage depends on bank1 voltage 7 gnd power power supply ground 8 scl input serial data clock 9 sda input/output serial data input 10 clk3/fs output/input multifunction programmable pin: programmable clock output or frequency select input pin. output voltage of clk3 depends on vdd_clk_b2 voltage 11 clk4 output programmable output clock. output voltage depends on bank2 voltage 12 gnd power power supply ground 13 clk5 output programmable clock output. output voltage depends on bank2 voltage 14 vdd_clk_b2 power power supply for bank2 (clk3, clk4, clk5) output: 1.8 v 15 clk6/sson output/input multifunction programmabl e pin: programmable clock output or spread spectrum on/off control input pin. output voltage of clk6 depends on vdd_clk_b3 voltage 16 vdd_clk_b3 power power supply for bank3 (clk6, clk7, clk8) output: 1.8 v 17 clk7 output programmable clock output. output voltage depends on bank3 voltage 18 gnd power power supply ground 19 gnd power power supply ground 20 clk8 output programmable clock output. output voltage depends on bank3 voltage [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 5 of 17 general description four configurable plls the cy2545 and cy2547 have four i 2 c programmable plls available to generate output frequencies ranging from 3 to 166 mhz. the advantage of having four plls is that a single device generates up to four independent frequencies from a single crystal. two sets of frequencies for each pll can be programmed. this enables in sy stem frequency switching using multifunction frequency select pin, fs. i 2 c programming the cy2545 and cy2547 have a serial i 2 c interface that programs the configuration memory array to synthesize output frequencies by programmable output divider, spread character- istics, drive strength, and crystal load capacitance. i 2 c can also be used for in system control of these programmable features. input reference clocks the input to the cy2545 and cy2547 is either a crystal or a clock signal. the input frequency range for crystals is 8 mhz to 48 mhz. there is provision for two reference clock inputs, clkin and exclkin with frequency range of 8 mhz to 166 mhz. for both devices, when clkin signal at pin 21 is used as a reference input, a valid signal at exclkin (as specified in the ac and dc electrical specification table), mu st be present for the devices to operate properly. multiple power supplies the cy2545 and cy2547 are designed to operate at internal core supply voltage of 1.8 v. in the case of the high voltage part (cy2545), an internal regulator is used to generate 1.8 v from the 2.5 v/3.0 v/3.3 v v dd supply voltage at pin 22. for the low voltage part (cy2547), this internal regulator is bypassed and 1.8 v at v dd pin 22 is directly used. output bank settings these devices have eight clock outputs grouped in three output driver banks. the bank 1, bank 2, and bank 3 correspond to (clk1, clk2), (clk3, clk4, clk5), and (clk6, clk7, clk8), respectively. separate power supplies are used for each of these banks and they can be any of 2.5 v, 3.0 v, or 3.3 v for cy2545 and 1.8 v for cy2547 giving user multiple choice of output clock voltage levels. output source selection these devices have eight clock outputs (clk1 - 8). there are six available clock sources for these outputs. these clock sources are: xin/exclkin, clkin, pll1, pll2, pll3, or pll4. output clock source selection is done us ing four out of six crossbar switch. thus, any one of these six available clock sources can be arbitrarily selected for the clock outputs. this gives user a flexibility to have up to four independent clock outputs. spread spectrum control two of the four plls (pll3 a nd pll4) have spread spectrum capability for emi reduction in the system. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the pll. the spread spectrum feature can be turned on or off using a multifunction control pin (clk7/ sson). it can be programmed to either center spread range from 0.125% to 2.50% or down spread range from ?0.25% to ?5.0% with lexmark or linear profile. frequency select the device can store two different pll frequency configurations, output source selection and outp ut divider values for all eight outputs in its nonvolatile memory location. there is a multi- function programmable pin, clk3/fs which, if programmed as frequency select input, can be used to select between these two arbitrarily programmed settings. glitch-free frequency switch when the frequency select pin (fs) is used to switch frequency, the outputs are glitch-free prov ided frequency is switched using output dividers. this featur e enables uninterrupted system operation while clock frequency is switched. device reset function there is a multifunction clki n/rst (pin 21) that can be programmed to use for the device reset function. there are two different programmable modes of operation for this device reset function. first one (called por like reset), when used brings the device in the default register se ttings loosing all configuration changes made through the i 2 c interface. the second (called clean start), keeps the i 2 c programmed values while giving all outputs a simultaneous clean start from its low pull-down state. 21 clkin/rst input/input multifunction programmable pin : high true reset input or 1.8 v external low voltage reference clock input 22 v dd power power supply for core and inputs: 1.8 v 23 xout output crystal output 24 xin/exclkin input crystal input or 1.8 v external clock input table 2. pin definition ? cy2547 24-pin qfn (v dd = 1.8 v supply) (continued) pin number name i/o description [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 6 of 17 pd#/oe mode pd#/oe (pin 4) is programmable to operate as either power-down (pd#) or output enable (oe) mode. pd# is a low true input. if activated it shuts off the entire chip, resulting in minimum device power consumption. setting this signal high brings the device into operational mode with default register settings. when this pin is programmed as output enable (oe), clock outputs are enabled or disabled using oe pin. individual clock outputs can be programmed to be sensitive to this oe pin. keep alive mode by activating the device in the keep alive mode, power-down mode is changed to power saving mode. this disables all plls and outputs, but preserves the conten ts of the volatile registers. thus, any configuration changes made through the i 2 c interface are preserved. by deactivating the keep alive mode, i 2 c memory is not preserved during power-dow n, but power consumption is reduced relative to the keep alive mode. output drive strength the dc drive strength of the individual clock output can be programmed for different values. table 4 shows the typical rise and fall times for different drive strength settings. generic configuration and custom frequency there is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. the device, cy2545/cy2547 can be custom programmed to any desired frequencies and listed feat ures. for customer specific programming and i 2 c programmable memory bitmap definitions, please contact your local cypress field application engineer (fae) or sales representative. serial i 2 c programming interface protocol and timing to enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, are individually enabled or disabled. the registers associated with the serial data inte rface initialize to their default setting upon power-up and therefor e, use of this interface is optional. clock device register changes are normally made at system initialization, if any are required. the cy2545 and cy2547 use a 2-wire serial interface sda and scl that operates up to 400 kbits/s in read or write mode. the sda and scl timing and data transfer sequence is shown in figure 3 . the basic write serial format is: start bit; 7-bit device address (da); r/w bit; slave clock acknowledge (ack); 8-bit memory address (ma); ack; 8-bit data; ack; 8-bit data in ma+1 if desired; ack; 8-bit data in ma+2; ack; etc. until stop bit. the basic serial format is illus- trated in figure 4 . device address the device serial interface address is 69h. the device address is combined with a read/write bit as the lsb and is sent after each start bit. data valid data is valid when the clock is high, and is only transitioned when the clock is low, as illustrated in figure 5 . data frame a start and stop sequence indicates every new data frame, as illustrated in figure 6 . start sequence - the start frame is indicated by sda going low when scl is high. every time a start signal is supplied, the next 8-bit data must be the device address (seven bits) and a r/w bit, followed by register address (eight bits) and register data (eight bits). stop sequence - the stop frame is indicated by sda going high when scl is high. a stop frame frees the bus to go to another part on the same bus or to another random register address. acknowledge pulse during write mode the cy2545/cy2547 responds with an acknowledge pulse after every eight bits. do this by pulling the sda line low during the n 9 th clock cycle as illustrated in figure 7 (n = the number of bytes transmitted). during read mode, the master generates the acknowledge pulse after reading the data packet. table 3. output drive strength output drive strength rise/fall time (ns) (typical value) low 6.8 mid low 3.4 mid high 2.0 high 1.0 [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 7 of 17 write operations writing individual bytes a valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (ack = 0/low). the next eight bits must contain the data word intended for storage. after the data word is received, th e slave responds with another acknowledge bit (ack = 0/low), and the master must end the write sequence with a stop condition. writing multiple bytes to write multiple bytes at a ti me, the master does not end the write sequence with a stop co ndition; instead, the master sends multiple contiguous bytes of data to be stored. after each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accepts data until the stop condition responds to the acknowledge bit. when receiving multiple bytes, the cy2545 and cy2547 internal ly increment the register address. read operations read operations are initiated the same way as write operations except that the r/w bi t of the slave address is set to ?1? (high). there are three basic read oper ations: current address read, random read, and sequential read. current address read the cy2545 and cy2547 have an onboard address counter that retains 1 more than the address of the last word access. if the last word written or read was word ?n?, then a current address read operation returns the value stored in location ?n+1?. when the cy2545/cy2547 receive the sl ave address with the r/w bit set to a ?1?, the cy2545/cy2547 issue an acknowledge and transmit the 8-bit word. the master device does not acknowledge the transfer, but generates a stop condition, which causes the cy2545/cy 2547 to stop transmission. random read through random read operations, the master may access any memory location. to perform this type of read operation, first the word address must be set. this is done by sending the address to the cy2545/cy2547 as part of a write operation. after sending the word address, the master generates a start condition following the acknowledge. this terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. next, the master reissues the control byte with the r/w byte set to ?1?. the cy2545/cy2547 then issue an acknowledge and transmit the 8-bit word. the master device does not acknowledge the transfer, but generates a stop condition, which causes the cy2545/cy2547 to stop transmission. sequential read sequential read operations follow the same process as random reads except that the master i ssues an acknowledge instead of a stop condition after transmitting the first 8-bit data word. this action increments the internal address pointer, and subsequently output of the next 8-bit data word. by continuing to issue acknowledges instead of stop conditions, the master serially reads the entire contents of t he slave device memory. when the internal address pointer points to the ffh register, after the next increment, the pointer points to the 00h register. [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 8 of 17 figure 3. data transfer sequence on the serial bus figure 4. data frame architecture figure 5. data valid and data transition periods scl start condition sda stop data may address or acknowledge valid be changed condition sda write start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 8-bit register data stop signal multiple contiguous registers slave 1 bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1 bit ack 8-bit register data (xxh+2) slave 1 bit ack 8-bit register data (ffh) slave 1 bit ack 8-bit register data (00h) slave 1 bit ack slave 1 bit ack sda read start signal device address 7-bit r/w = 1 1 bit 8-bit register data slave 1 bit ack slave 1 bit ack stop signal sda read start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 7-bit device stop signal multiple contiguous registers master 1 bit ack 8-bit register data master 1 bit ack (xxh) (xxh) master 1 bit ack 8-bit register data (xxh+1) master 1 bit ack 8-bit register data (ffh) master 1 bit ack 8-bit register data (00h) master 1 bit ack master 1 bit ack current address read address +r/w=1 repeated start bit sda scl data valid transition to next bit clk low clk high vih vil t su t dh [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 9 of 17 serial i 2 c programming interface timing figure 6. .start and stop frame figure 7. frame format (device address, r/w , register address, register data) sda scl start transition to next bit stop sda scl da6 da5 da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + + serial i 2 c programming interface timing specifications parameter description min max unit f scl frequency of scl ? 400 khz start mode time from sda low to scl low 0.6 ? s clk low scl low period 1.3 ? s clk high scl high period 0.6 ? s t su data transition to scl high 250 ? ns t dh data hold (scl low to data transition) 0 ? ns rise time of scl and sda ? 300 ns fall time of scl and sda ? 300 ns stop mode time from scl high to sda high 0.6 ? s stop mode to start mode 1.3 ? s [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 10 of 17 absolute maximum conditions parameter description condition min max unit v dd supply voltage for cy2545 ?0.5 4.5 v v dd supply voltage for cy2547 ?0.5 2.6 v v dd_clk_bx output bank supply voltage ?0.5 4.5 v v in input voltage for cy2545 relative to v ss ?0.5 v dd + 0.5 v v in input voltage for cy2547 relative to v ss ?0.5 2.2 v t s temperature and storag e nonfunctional ?65 +150 c esd hbm esd protection (human body model ) jedec eia/jesd22-a114-e 2000 v ul-94 flammability rating v-0 at1/8 in. 10 ppm msl moisture sensitivity level 3 recommended oper ating conditions parameter description min typ max unit v dd v dd operating voltage for cy2545 2.25 ? 3.60 v v dd v dd operating voltage for cy2547 1.65 1.8 1.95 v v dd_clk_bx output driver voltage for bank 1, 2 and 3 1.43 ? 3.60 v t ac commercial ambient temperature 0 ? +70 c t ai industrial ambient temperature ?40 ? +85 c c load maximum load capacitance ? ? 15 pf t pu power-up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 11 of 17 dc electrical specifications parameter description conditions min typ max unit v ol output low voltage i ol = 2 ma, drive strength = [00] ? ? 0.4 v i ol = 3 ma, drive strength = [01] i ol = 7 ma, drive strength = [10] i ol = 12 ma, drive strength = [11] v oh output high voltage i oh = ?2 ma, drive strength = [00] v dd_clk_bx ? 0.4 ??v i oh = ?3 ma, drive strength = [01] i oh = ?7 ma, drive strength = [10] i oh = ?12 ma, drive strength = [11] v olsd output low voltage, sda i ol = 4 ma ? ? 0.4 v v il1 input low voltage of pd#/oe, rst, fs, and sson ? ? 0.2 v dd v v il2 input low voltage of clkin for cy2545 ? ? 0.1 v dd v v il3 input low voltage of exclkin for cy2545 ? ? 0.18 v v il4 input low voltage of clkin, exclkin for cy2547 ? ? 0.1 v dd v v ih1 input high voltage of pd#/oe, rst, fs, and sson 0.8 v dd ??v v ih2 input high voltage of clkin for cy2545 0.9 v dd ??v v ih3 input high voltage of exclkin for cy2545 1.62 ? 2.2 v v ih4 input high voltage of clkin, exclkin for cy2547 0.9 v dd ??v i ilpd input low current of rst and pd#/oe v il = 0 v ? ? 10 a i ihpd input high current of rst and pd#/oe v ih = v dd ??10a i ilsr input low current of sson and fs v il = 0 v (internal pull-down = 160 k typ) ? ? 10 a i ihsr input high current of sson and fs v ih = v dd (internal pull-down = 160 k typ) 14 ? 36 a r dn pull-down resistor of (clk1-clk8) when off, clk6/sson and clk3/fs 100 160 250 k i dd [1, 2] supply current for cy2547 pd# = high, no load ? 20 ? ma supply current for cy2545 pd# = high, no load ? 22 ? ma i dds [1] standby current pd# = low, no load, with i 2 c circuit not in keep alive mode ?3?a i pd [1] power-down current pd# = low, no load, with i 2 c circuit in keep alive mode ??1ma c in [1] input capacitance sson, rst, pd#/oe or fs inputs ? 7 pf notes 1. guaranteed by design but not 100% tested. 2. configuration dependent. [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 12 of 17 notes 3. guaranteed by design but not 100% tested. 4. configuration dependent. ac electrical specifications parameter description conditions min typ max unit f in (crystal) crystal frequency, xin 8 ? 48 mhz f in (clock) input clock frequency clock inputs clkin or exclkin 8 ? 166 mhz f clk output clock frequency 3 ? 166 mhz dc1 output duty cycle, all clocks except ref out duty cycle is defined in figure 9 ; t 1 /t 2 , measured 50% of v dd 45 50 55 % dc2 ref out clock duty cycle r ef in min 45%, max 55% 40 ? 60 % t rf1 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 10 , c load = 15 pf, drive strength [00] ?6.8? ns t rf2 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 10 , c load = 15 pf, drive strength [01] ?3.4? ns t rf3 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 10 , c load = 15 pf, drive strength [10] ?2.0? ns t rf4 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 10 , c load = 15 pf, drive strength [11] ?1.0? ns t ccj [3, 4] cycle-to-cycle jitter max (pk-pk) configuration dependent. see ta b l e 4 ? 150 ? ps t lock [3] pll lock time measured from 90% of the applied power supply level ? 1 3 ms table 4. configuration example for c-c jitter ref. freq. (mhz) clk1 output clk2 output clk3 output clk4 output clk5 output freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) 14.3181 8.0 134 166 103 48 92 74.25 81 not used 19.2 74.25 99 166 94 8 91 27 110 48 75 27 48 67 27 109 166 103 74.25 97 not used 48 48 93 27 123 166 137 166 138 8 103 recommended crystal spec ification for smd package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 28 mhz fmax maximum frequency 14 28 48 mhz r1 motional resistance (esr) 135 50 30 c0 shunt capacitance 4 4 2 pf cl parallel load capacitance 18 14 12 pf dl(max) maximum crystal drive level 300 300 300 w recommended crystal specific ation for thru-hole package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 24 mhz fmax maximum frequency 14 24 32 mhz r1 motional resistance (esr) 90 50 30 c0 shunt capacitance 7 7 7 pf cl parallel load capacitance 18 12 12 pf dl(max) maximum crystal drive level 1000 1000 1000 w [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 13 of 17 test and measurement setup figure 8. test and measurement setup voltage and timing definitions figure 9. duty cycle definition figure 10. rise time = t rf , fall time = t rf 0.1 f v dd outputs c load gnd dut clock output v dd_clk_b x 50% of v dd_clk_b x 0v t 1 t 2 clock output t rf t rf v dd_clk_bx 80% of v dd_clk_bx 20% of v dd_clk_bx 0v [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 14 of 17 ordering code definitions ordering information all product offerings are factory programmed customer specific devices with customized part num bers. the possible configuration s table shows the available device types, but not complete part nu mbers. contact your local cypress fae of sales representative f or more information. possible configurations part number [5] type v dd (v) production flow pb-free cy2545cxxx 24-pin qfn supply voltage: 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2545cxxxt 24-pin qfn tape and reel supply voltage: 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2547cxxx 24-pin qfn supply voltage: 1.8 v commercial, 0 c to 70 c cy2547cxxxt 24-pin qfn tape and reel supply voltage: 1.8 v commercial, 0 c to 70 c cy2545ixxx 24-pin qfn supply voltage: 2.5 v, 3.0 v or 3.3 v industrial, ?40 c to 85 c cy2545ixxxt 24-pin qfn tape and reel supply voltage: 2.5 v, 3.0 v or 3.3 v industrial, ?40 c to 85 c cy2547ixxx 24-pin qfn supply voltage: 1.8 v industrial, ?40 c to 85 c cy2547ixxxt 24-pin qfn tape and reel supply voltage: 1.8 v industrial, ?40 c to 85 c cy 2545/7 c xxx t tape and reel three digit numeric custom configuration code temperature range: c = commercial, i = industrial base part number company code: cy = cypress note 5. xxx indicates factory programmable and are factory programmed c onfigurations. for more details, contact your local cypress fa e or cypress sales representative. [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 15 of 17 package drawing and dimensions figure 11. 24-pin qfn 4 4 mm (subcon punch ty pe package with 2.49 2.49 epad) lf24a/ly24a 51-85203 *b [+] feedback
cy2545, cy2547 document #: 001-13196 rev. *c page 16 of 17 reference information acronyms document conventions units of measure table 5. acronyms used in this document acronym description pll phase-locked loop i 2 c inter integrated circuit qfn quad flat no leads jedec eia joint electron device engineering council electronic industries alliance esd electrostatic discharge esr equivalent series resistance table 6. units of measure symbol unit of measure c degree celsius khz kilohertz mhz megahertz a microampere s microsecond w microwatt ma milliampere ms millisecond ns nanosecond wohm ppm parts per million % percent pf picofarad ps picosecond vvolt wwatt [+] feedback
document #: 001-13196 rev. *c revised july 5, 2011 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2545, cy2547 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy2545 cy2547 quad pll programmable spread spectrum clock generator with serial i 2 c interface document number: 001-13196 revision ecn orig. of change submission date description of change ** 870780 rgl/aesa see ecn new datasheet *a 1504843 rgl/aesa see ecn changed i2c tsu specification from 100 ns to 250 ns changed esd spec from mil-std to jedec combined v dd operating condition spec for cy2545 to a single v dd spec changed name from vdd_core to v dd *b 2899681 cxq 03/26/2010 updated ordering information updated package diagram *c 3302754 cxq 07/05/2011 updated template and st yle to meet current cypress standards. included table of contents. added ordering code definitions, acronyms and units of measure. [+] feedback

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