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rev. 1.0 2/14 copyright ? 2014 by silicon laboratories c8051f85x/86x c8051f85x/86x low-cost 8-bit mcu family with up to 8 kb of flash memory - up to 8 kb flash - flash is in-system programmable in 512-byte sectors - up to 512 bytes ram (256 + 256) on-chip debug - on-chip debug circuitry facilitate s full speed, non-intrusive in- system debug (no emulator required) - provides breakpoints, single st epping, inspect/modify memory and registers 12-bit analog-to-digital converter - up to 16 input channels - up to 200 ksps 12-bit mode or 800 ksps 10-bit mode - internal vref or external vref supported internal low-power oscillator - calibrated to 24.5 mhz - low supply current - 2% accuracy over supply and temperature internal low-frequency oscillator - 80 khz nominal operation - low supply current - independent clock source for watchdog timer 2 analog comparators - programmable hysteresis and response time - configurable as interrupt or reset source - low current general-purpose i/o - up to 18 pins - 5 v-tolerant - crossbar-enabled high-speed cip-51 c core - efficient, pipelined instruction architecture - up to 25 mips throughput with 25 mhz clock - uses standard 8051 instruction set - expanded interrupt handler communication peripherals - uart - i 2 c / smbus? - spi? timer/counters and pwm - 4 general-purpose 16-bit timer/counters - 16-bit programmable counter array (pca) with three channels of pwm, capture/compare, or frequency output capability, and hardware kill/safe state capability additional support peripherals - independent watchdog timer clocked from lfo - 16-bit crc engine unique identifier - 32-bit unique key for each device supply voltage - 2.2 to 3.6 v package options - 16-pin soic - 20-pin qfn, 3 x 3 mm - 24-pin qsop - available in die form - qualified to aec-q100 standards temperature ranges: - ?40 to +125 c (-ix) and ?40 to +85 c (-gx) cip-51 (25 mhz) 2-8 kb flash 256-512 b ram watchdog supply monitor core / memory / support c2 serial debug / programming core ldo clocking / oscillators 80 khz low frequency oscillator 24.5 mhz low power oscillator external clock (cmos input) clock selection analog peripherals sar adc (12-bit 200 ksps,10-bit 800 ksps) 2 x low current comparators digital peripherals uart 4 x 16-bit timers 3-channel pca voltage reference flexible pin muxing priority crossbar encoder 18 multi-function 5v-tolerant i/o pins i2c / smbus spi 16-bit crc
2 rev. 1.0
rev. 1.0 2 table of contents 1. electrical sp ecifications8 1.1. electrical characteristics8 1.2. typical performance curves19 1.2.1. operating supply current19 1.2.2. adc s upply current20 1.2.3. port i/o output drive21 1.3. thermal conditions21 1.4. absolute maximum ratings22 2. system overview23 2.1. power25 2.1.1. ldo 25 2.1.2. voltage supply monitor (vmon0)25 2.1.3. device power modes25 2.2. i/o26 2.2.1. general features26 2.2.2. crossbar26 2.3. clocking27 2.4. counters/timers and pwm27 2.4.1. programmable co unter array (pca0)27 2.4.2. timers (timer 0, ti mer 1, timer 2 and timer 3)27 2.4.3. watchdog timer (wdt0)27 2.5. communications and other digital peripherals28 2.5.1. universal asynchronous re ceiver/transmitter (uart0)28 2.5.2. serial peripheral interface (spi0)28 2.5.3. system management bus / i2c (smbus0)28 2.5.4. 16/32-bit crc (crc0)28 2.6. analog peripherals29 2.6.1. 12-bit analog-to-dig ital converter (adc0)29 2.6.2. low current compar ators (cmp0, cmp1)29 2.7. reset sources30 2.8. on-chip debugging30 3. pin definitions31 3.1. c8051f850/1/2/3/4/5 qs op24 pin definitions31 3.2. c8051f850/1/2/3/4/5 qfn20 pin definitions34 3.3. c8051f860/1/2/3/4/5 so ic16 pin definitions37 4. ordering information40 5. qsop-24 package specifications42 6. qfn-20 package specifications44 7. soic-16 package specifications47 8. memory organization49 8.1. program memory50 8.1.1. movx instructi on and program memory50
3 rev. 1.0 8.2. data memory50 8.2.1. internal ram50 8.2.2. external ram51 8.2.3. special function registers51 9. special function register memory map52 10. flash memory57 10.1.security options57 10.2.programming the flash memory59 10.2.1.flash lock and key functions59 10.2.2.flash erase procedure59 10.2.3.flash write procedure59 10.3.non-volatile data storage60 10.4.flash write and erase guidelines60 10.4.1.voltage supply maintenance and t he supply monitor60 10.4.2.pswe maintenance60 10.4.3.system clock61 10.5.flash contro l registers62 11. device identification a nd unique identifier64 11.1.device identification registers65 12. interrupts68 12.1.mcu interrupt so urces and vectors68 12.1.1.interrupt priorities68 12.1.2.interrupt latency68 12.2.interrupt cont rol registers70 13. power management and internal regulator76 13.1.power modes76 13.1.1.idle mode76 13.1.2.stop mode77 13.2.ldo regulator77 13.3.power control registers77 13.4.ldo control registers78 14. analog-to-digital converter (adc0)79 14.1.adc0 analog multiplexer80 14.2.adc operation81 14.2.1.starting a conversion81 14.2.2.tracking modes81 14.2.3.burst mode82 14.2.4.settling time requirements83 14.2.5.gain setting84 14.3.8-bit mode84 14.4.12-bit mode84 14.5.power considerations85 14.6.output code formatting87 14.7.programmable window detector88 14.7.1.window detector in single-ended mode88
rev. 1.0 4 14.8.voltage and ground reference options90 14.8.1.external voltage reference90 14.8.2.internal voltage reference90 14.8.3.analog ground reference90 14.9.temperature sensor91 14.9.1.calibration91 14.10.adc control registers92 15. cip-51 microcontroller core106 15.1.performance106 15.2.programming and debugging support107 15.3.instruction set107 15.3.1.instruction and cpu timing107 15.4.cpu core registers112 16. clock sources and se lection (hfosc0, lfosc0, and extclk)118 16.1.programmable high- frequency oscillator118 16.2.programmable low-frequency oscillator118 16.2.1.calibrating the inte rnal l-f oscillator118 16.3.external clock118 16.4.clock selection119 16.5.high frequency oscillato r control registers120 16.6.low frequency oscillat or control registers121 16.7.clock selection control registers122 17. comparators (cmp0 and cmp1)123 17.1.system connectivity123 17.2.functional description126 17.3.comparator c ontrol registers127 18. cyclic redundancy check unit (crc0)133 18.1.crc algorithm133 18.2.preparing for a crc calculation135 18.3.performing a c rc calculation135 18.4.accessing the crc0 result135 18.5.crc0 bit re verse feature135 18.6.crc control registers136 19. external interrupt s (int0 and int1)142 19.1.external interrupt control registers143 20. programmable counter array (pca0)145 20.1.pca counter/timer146 20.2.pca0 interrupt sources146 20.3.capture/co mpare modules147 20.3.1.output polarity147 20.3.2.edge-trigger ed capture mode148 20.3.3.software time r (compare) mode149 20.3.4.high-speed output mode150 20.3.5.frequency output mode151 20.4.pwm waveform generation152
5 rev. 1.0 20.4.1.edge aligned pwm152 20.4.2.center aligned pwm154 20.4.3. 8 to11-bit pulse width modulator modes156 20.4.4. 16-bit pulse wi dth modulator mode157 20.5.comparator clear function158 20.6.pca control registers159 21. port i/o (port 0, port 1, port 2, crossbar, and port match)176 21.1.general port i/o initialization177 21.2.assigning port i/o pins to analog and digi tal functions178 21.2.1.assigning port i/o pins to analog functions178 21.2.2.assigning port i/o pi ns to digital functions178 21.2.3.assigning port i/o pins to fixed digital functions179 21.3.priority crossbar decoder180 21.4.port i/o mode s of operation182 21.4.1.configuring port pins for a nalog modes182 21.4.2.configuring port pi ns for digit al modes182 21.4.3.port drive strength182 21.5.port match183 21.6.direct read/write a ccess to port i/o pins183 21.7.port i/o and pi n configuration c ontrol registers184 22. reset sources and supply monitor202 22.1.power-on reset203 22.2.power-fail reset / supply monitor204 22.3.enabling the vdd monitor204 22.4.external reset205 22.5.missing clock detector reset205 22.6.comparator0 reset205 22.7.watchdog timer reset205 22.8.flash error reset205 22.9.software reset205 22.10.reset sources co ntrol registers206 22.11.supply monitor c ontrol registers207 23. serial peripheral interface (spi0)208 23.1.signal descriptions209 23.1.1.master out, slave in (mosi)209 23.1.2.master in, slave out (miso)209 23.1.3.serial clock (sck)209 23.1.4.slave select (nss)209 23.2.spi0 master mode operation210 23.3.spi0 slave mode operation212 23.4.spi0 interrupt sources212 23.5.serial clock phase and polarity212 23.6.spi special function registers214 23.7.spi control registers218 24. system management bus / i2c (smbus0)222
rev. 1.0 6 24.1.supporting documents223 24.2.smbus configuration223 24.3.smbus operation223 24.3.1.transmitter vs. receiver224 24.3.2.arbitration224 24.3.3.clock low extension224 24.3.4.scl low timeout224 24.3.5.scl high (smb us free) timeout225 24.4.using the smbus225 24.4.1.smbus configuration register225 24.4.2.smbus pin swap227 24.4.3.smbus timing control227 24.4.4.smb0cn control register227 24.4.5.hardware slave address recognition229 24.4.6.data register229 24.5.smbus transfer modes230 24.5.1.write sequence (master)230 24.5.2.read sequence (master)231 24.5.3.write sequence (slave)232 24.5.4.read sequence (slave)233 24.6.smbus status decoding233 24.7.i2c / smbus control registers238 25. timers (timer0, timer1, timer2 and timer3)245 25.1.timer 0 and timer 1246 25.1.1.mode 0: 13-bit counter/timer247 25.1.2.mode 1: 16-bit counter/timer247 25.1.3.mode 2: 8-bit counter /timer with auto-reload248 25.1.4.mode 3: two 8-bit count er/timers (timer 0 only)249 25.2.timer 2 and timer 3250 25.2.1.16-bit timer with auto-reload250 25.2.2.8-bit timers with auto-reload251 25.2.3.capture mode252 25.3.timer contro l registers253 26. universal asynchronous r eceiver/transmitter (uart0)271 26.1.enhanced baud rate generation271 26.2.operational modes273 26.2.1.8-bit uart273 26.2.2.9-bit uart274 26.3.multiprocessor communications275 26.4.uart control registers277 27. watchdog timer (wdt0)280 27.1.enabling / re setting the wdt281 27.2.disabling the wdt281 27.3.disabling the wdt lockout281 27.4.setting the wdt interval281
7 rev. 1.0 27.5.watchdog timer control registers282 28. revision-specific behavior284 28.1.revision identification284 28.2.temperature sensor offset and slope286 28.3.flash endurance286 28.4.latch-up performance286 28.5.unique identifier286 29. c2 interface287 29.1.c2 pin sharing287 29.2.c2 interface registers288 document change list293 contact information294
rev. 1.0 8 1. electrical specifications 1.1. electrical characteristics all electrical parameters in all tabl es are specified under the conditions listed in table 1.1, unless stated otherwise. table 1.1. recommended operating conditions parameter symbol test condition min typ max unit operating supply voltage on vdd v dd 2.2 ? 3.6 v system clock frequency f sysclk 0 ? 25 mhz operating ambient temperature t a commercial grade devices (-gm, -gs, -gu) ?40 ? 85 c industrial grade devices (-im, -is, -iu) ?40 ? 125 c note: all voltages with respect to gnd table 1.2. power consumption parameter symbol test condition min typ max unit digital core supply current (?gx devices, -40c to +85c) normal mode?full speed with code executing from flash i dd f sysclk = 24.5 mhz 2 ? 4.45 4.85 ma f sysclk = 1.53 mhz 2 ? 915 1150 a f sysclk = 80 khz 3 , t a = 25 c ? 250 290 a f sysclk = 80 khz 3 ? 250 380 a idle mode?core halted with peripherals running i dd f sysclk = 24.5 mhz 2 ? 2.05 2.3 ma f sysclk = 1.53 mhz 2 ? 550 700 a f sysclk = 80 khz 3 , t a = 25 c ? 125 130 a f sysclk = 80 khz 3 ? 125 200 a stop mode?core halted and all clo cks stopped, supply monitor off. i dd internal ldo on, t a = 25 c ? 105 120 a internal ldo on ? 105 170 a internal ldo off ? 0.2 ? a notes: 1. c urrents are additive. for example, where i dd is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. incl udes supply current from internal regulator, supply monitor, and high frequency oscillator. 3. incl udes supply current from internal regulator, supply monitor, and low frequency oscillator. 4. ad c0 always-on power excludes internal reference supply current. 5. t he internal reference is enabled as-needed when operating the adc in burst mode to save power.
9 rev. 1.0 digital core supply current (?ix devices, -40c to +125c) normal mode?full speed with code executing from flash i dd f sysclk = 24.5 mhz 2 ? 4.45 5.25 ma f sysclk = 1.53 mhz 2 ? 915 1600 a f sysclk = 80 khz 3 , t a = 25 c ? 250 290 a f sysclk = 80 khz 3 ? 250 725 a idle mode?core halted with peripherals running i dd f sysclk = 24.5 mhz 2 ? 2.05 2.6 ma f sysclk = 1.53 mhz 2 ? 550 1000 a f sysclk = 80 khz 3 , t a = 25 c ? 125 130 a f sysclk = 80 khz 3 ? 125 550 a stop mode?core halted and all clo cks stopped, supply monitor off. i dd internal ldo on, t a = 25 c ? 105 120 a internal ldo on ? 105 270 a internal ldo off ? 0.2 ? a analog peripheral supply current s ( both ?gx and ?ix devices) high-frequency oscillator i hfosc operating at 24.5 mhz, t a = 25 c ? 155 ? a low-frequency oscillator i lfosc operating at 80 khz, t a = 25 c ? 3.5 ? a adc0 always-on 4 i adc 800 ksps, 10-bit conversions or 200 ksps, 12-bit conversions normal bias settings v dd = 3.0 v ? 845 1200 a 250 ksps, 10-bit conversions or 62.5 ksps 12-bit conversions low power bias settings v dd = 3.0 v ? 425 580 a adc0 burst mode, 10-bit sin - gle conversions, external ref - erence i adc 200 ksps, v dd = 3.0 v ? 370 ? a 100 ksps, v dd = 3.0 v ? 185 ? a 10 ksps, v dd = 3.0 v ? 19 ? a table 1.2. power consumption (continued) parameter symbol test condition min typ max unit notes: 1. currents are additive. for example, where i dd is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. includes supply current from internal regulator, supply monitor, and high frequency oscillator. 3. includes supply current from internal regulator, supply monitor, and low frequency oscillator. 4. adc0 always-on power excludes internal reference supply current. 5. the internal reference is enabled as-needed when operating the adc in burst mode to save power.
rev. 1.0 10 adc0 burst mode, 10-bit sin - gle conversions, internal ref - erence, low power bias se ttings i adc 200 ksps, v dd = 3.0 v ? 490 ? a 100 ksps, v dd = 3.0 v ? 245 ? a 10 ksps, v dd = 3.0 v ? 23 ? a adc0 burst mode, 12-bit sin - gle conversions, external ref - erence i adc 100 ksps, v dd = 3.0 v ? 530 ? a 50 ksps, v dd = 3.0 v ? 265 ? a 10 ksps, v dd = 3.0 v ? 53 ? a adc0 burst mode, 12-bit sin - gle conversions, internal ref - erence i adc 100 ksps, v dd = 3.0 v, normal bias ? 950 ? a 50 ksps, v dd = 3.0 v, low power bias ? 420 ? a 10 ksps, v dd = 3.0 v, low power bias ? 85 ? a internal adc0 reference, a lways-on 5 i iref normal power mode ? 680 790 a low power mode ? 160 210 a temperature sensor i tsense ? 75 120 a comparator 0 (cmp0), comparator 1 (cmp1) i cmp cpnmd = 11 ? 0.5 ? a cpnmd = 10 ? 3 ? a cpnmd = 01 ? 10 ? a cpnmd = 00 ? 25 ? a voltage supply monitor (vmon0 ) i vmon ? 15 20 a table 1.2. power consumption (continued) parameter symbol test condition min typ max unit notes: 1. currents are additive. for example, where i dd is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount. 2. includes supply current from internal regulator, supply monitor, and high frequency oscillator. 3. includes supply current from internal regulator, supply monitor, and low frequency oscillator. 4. adc0 always-on power excludes internal reference supply current. 5. the internal reference is enabled as-needed when operating the adc in burst mode to save power.
11 rev. 1.0 table 1.3. reset and supply monitor parameter symbol test condition min typ max unit v dd supply monitor threshold v vddm 1.85 1.95 2.1 v power-on reset (por) threshold v por rising voltage on v dd ? 1.4 ? v falling voltage on v dd 0.75 ? 1.36 v v dd ramp time t rmp time to v dd > 2.2 v 10 ? ? s reset delay from por t por relative to v dd > v por 3 10 31 ms reset delay from non-por source t rst time between release of reset source and code execution ? 39 ? s rst low time to generate reset t rstl 15 ? ? s missing clock detector response t ime (final rising edge to reset) t mcd f sysclk > 1 mhz ? 0.625 1.2 ms missing clock detector trigger frequency f mcd ? 7.5 13.5 khz v dd supply monitor turn-on time t mon ? 2 ? s table 1.4. flash memory parameter symbol test condition min typ max units write time 1 , 2 t write one byte, f sysclk = 24.5 mhz 19 20 21 s erase time 1 , 2 t erase one page, f sysclk = 24.5 mhz 5.2 5.35 5.5 ms v dd voltage during programming 3 v prog 2.2 ? 3.6 v endurance (write/erase cycles) n we 20k 100k ? cycles notes: 1. do es not include sequencing time before and after the writ e/erase operation, which may be multiple sysclk cycles. 2. t he internal high-frequency oscillator has a programmabl e output frequency using the oscicl register, which is factory programmed to 24.5 mhz. if user firmware adjusts the oscilla to r speed, it must be between 22 and 25 mhz du ring any flash write or erase operation. it is recommended to write the oscicl register back to its reset value when writing or erasing flash. 3. f lash can be safely programmed at any voltage above the supply monitor threshold ( v vddm ). 4. da ta retention information is published in the quarterly quality and reliability report.
rev. 1.0 12 table 1.5. internal oscillators parameter symbol test condition min typ max unit high frequency oscillator (24.5 mhz) oscillator frequency f hfosc full temperature and supply range 24 24.5 25 mhz power supply sensitivity pss hfosc t a = 25 c ? 0.5 ? %/v temperature sensitivity ts hfosc v dd = 3.0 v ? 40 ? ppm/c low frequency oscillator (80 khz) oscillator frequency f lfosc full temperature and supply range 75 80 85 khz power supply sensitivity pss lfosc t a = 25 c ? 0.05 ? %/v temperature sensitivity ts lfosc v dd = 3.0 v ? 65 ? ppm/c table 1.6. external clock input parameter symbol test condition min typ max unit external input cmos clock frequency (at extclk pin) f cmos 0 ? 25 mhz external input cmos clock high time t cmosh 18 ? ? ns external input cmos clock low time t cmosl 18 ? ? ns
13 rev. 1.0 table 1.7. adc parameter symbol test condition min typ max unit resolution n bits 12 bit mode 12 bits 10 bit mode 10 bits throughput rate (high speed mode) f s 12 bit mode ? ? 200 ksps 10 bit mode ? ? 800 ksps throughput rate (low power mode) f s 12 bit mode ? ? 62.5 ksps 10 bit mode ? ? 250 ksps tracking time t trk high speed mode 230 ? ? ns low power mode 450 ? ? ns power-on time t pwr 1.2 ? ? s sar clock frequency f sar high speed mode, reference is 2.4 v internal ? ? 6.25 mhz high speed mode, reference is not 2.4 v internal ? ? 12.5 mhz low power mode ? ? 4 mhz conversion time t cnv 10-bit conversion, sar clock = 12.25 mhz, system clock = 24.5 mhz. 1.1 s sample/hold capacitor c sar gain = 1 ? 5 ? pf gain = 0.5 ? 2.5 ? pf input pin capacitance c in ? 20 ? pf input mux impedance r mux ? 550 ? voltage reference range v ref 1 ? v dd v input voltage range* v in gain = 1 0 ? v ref v gain = 0.5 0 ? 2xv ref v power supply rejection ratio psrr adc ? 70 ? db dc performance integral nonlinearity inl 12 bit mode ? 1 2.3 lsb 10 bit mode ? 0.2 0.6 lsb differential nonlinearity (guaranteed monotonic) dnl 12 bit mode ?1 0.7 1.9 lsb 10 bit mode ? 0.2 0.6 lsb *note: absolute input pin voltage is limited by the v dd supply.
rev. 1.0 14 offset error e off 12 bit mode, vref = 1.65 v ?3 0 3 lsb 10 bit mode, vref = 1.65 v ?2 0 2 lsb offset temperature coeffi - cient tc off ? 0.004 ? lsb/c slope error e m 12 bit mode ? 0.02 0.1 % 10 bit mode ? 0.06 0.24 % dynamic performance 10 khz sine wave input 1db below full s cale, max throughput, using agnd pin signal-to-noise snr 12 bit mode 61 66 ? db 10 bit mode 53 60 ? db signal-to-noise plus distor - tion sndr 12 bit mode 61 66 ? db 10 bit mode 53 60 ? db total harmonic distortion (up to 5th har monic) thd 12 bit mode ? 71 ? db 10 bit mode ? 70 ? db spurious-free dynamic rang e sfdr 12 bit mode ? ?79 ? db 10 bit mode ? ?74 ? db table 1.7. adc (continued) parameter symbol test condition min typ max unit *note: absolute input pin voltage is limited by the v dd supply.
15 rev. 1.0 table 1.8. voltage reference parameter symbol test condition min typ max unit internal fast settling reference output voltage (full temperature and supply ra nge) v reffs 1.65 v setting 1.62 1.65 1.68 v 2.4 v setting, v dd > 2.6 v 2.35 2.4 2.45 v temperature coefficient tc reffs ? 50 ? ppm/c turn-on time t reffs ? ? 1.5 s power supply rejection psrr reffs ? 400 ? ppm/v external reference input current i extref sample rate = 800 ksps; vref = 3.0 v ? 5 ? a table 1.9. temperature sensor parameter symbol test condition min typ max unit offset v off t a = 0 c ? 757 ? mv offset error* e off t a = 0 c ? 17 ? mv slope m ? 2.85 ? mv/c slope error* e m ? 70 ? v/c linearity ? 0.5 ? c turn-on time ? 1.8 ? s *note: represents one standard deviation from the mean.
rev. 1.0 16 table 1.10. comparators parameter symbol test condition min typ max unit response time, cpnmd = 00 (highest speed) t resp0 +100 mv differential ? 100 ? ns ?100 mv differential ? 150 ? ns response time, cpnmd = 11 (lowest power) t resp3 +100 mv differential ? 1.5 ? s ?100 mv differential ? 3.5 ? s positive hysterisis mode 0 (cpnmd = 00) hys cp+ cpnhyp = 00 ? 0.4 ? mv cpnhyp = 01 ? 8 ? mv cpnhyp = 10 ? 16 ? mv cpnhyp = 11 ? 32 ? mv negative hysterisis mode 0 (cpnmd = 00) hys cp- cpnhyn = 00 ? -0.4 ? mv cpnhyn = 01 ? ?8 ? mv cpnhyn = 10 ? ?16 ? mv cpnhyn = 11 ? ?32 ? mv positive hysterisis mode 1 (cpnmd = 01) hys cp+ cpnhyp = 00 ? 0.5 ? mv cpnhyp = 01 ? 6 ? mv cpnhyp = 10 ? 12 ? mv cpnhyp = 11 ? 24 ? mv negative hysterisis mode 1 (cpnmd = 01) hys cp- cpnhyn = 00 ? -0.5 ? mv cpnhyn = 01 ? ?6 ? mv cpnhyn = 10 ? ?12 ? mv cpnhyn = 11 ? ?24 ? mv positive hysterisis mode 2 (cpnmd = 10) hys cp+ cpnhyp = 00 ? 0.7 ? mv cpnhyp = 01 ? 4.5 ? mv cpnhyp = 10 ? 9 ? mv cpnhyp = 11 ? 18 ? mv negative hysterisis mode 2 (cpnmd = 10) hys cp- cpnhyn = 00 ? -0.6 ? mv cpnhyn = 01 ? ?4.5 ? mv cpnhyn = 10 ? ?9 ? mv cpnhyn = 11 ? ?18 ? mv
17 rev. 1.0 positive hysteresis mode 3 (cpnmd = 11) hys cp+ cpnhyp = 00 ? 1.5 ? mv cpnhyp = 01 ? 4 ? mv cpnhyp = 10 ? 8 ? mv cpnhyp = 11 ? 16 ? mv negative hysteresis mode 3 (cpnmd = 11) hys cp- cpnhyn = 00 ? -1.5 ? mv cpnhyn = 01 ? ?4 ? mv cpnhyn = 10 ? ?8 ? mv cpnhyn = 11 ? ?16 ? mv input range (cp+ or cp?) v in -0.25 ? v dd +0.25 v input pin capacitance c cp ? 7.5 ? pf common-mode rejection ratio cmrr cp ? 70 ? db power supply rejection ratio psrr cp ? 72 ? db input offset voltage v off t a = 25 c -10 0 10 mv input offset tempco tc off ? 3.5 ? v/c table 1.10. comparators parameter symbol test condition min typ max unit
rev. 1.0 18 table 1.11. port i/o parameter symbol test condition min typ max unit output high voltage (high drive) v oh i oh = ?3 ma v dd ? 0.7 ? ? v output low voltage (high drive) v ol i ol = 8.5 ma ? ? 0.6 v output high voltage (low drive) v oh i oh = ?1 ma v dd ? 0.7 ? ? v output low voltage (low drive) v ol i ol = 1.4 ma ? ? 0.6 v input high voltage v ih v dd ? 0.6 ? ? v input low voltage v il ? ? 0.6 v pin capacitance c io ? 7 ? pf weak pull-up current (v in = 0 v) i pu v dd = 3.6 ?30 ?20 ?10 a input leakage (pullups off or analog) i lk gnd < v in < v dd ?1.1 ? 1.1 a input leakage current with v in above v dd i lk v dd < v in < v dd +2.0 v 0 5 150 a
19 rev. 1.0 1.2. typical performance curves 1.2.1. operating supply current figure 1.1. typical operating current running from 24.5 mhz internal oscillator figure 1.2. typical operating current running from 80 khz internal oscillator 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 supply current (ma) operating frequency (mhz) normal mode idle mode 100 120 140 160 180 200 220 240 260 10 20 30 40 50 60 70 80 supply current ( a) operating frequency (khz) normal mode idle mode
rev. 1.0 20 1.2.2. adc supply current figure 1.3. typical adc and internal reference power consumption in burst mode figure 1.4. typical adc power consumption in normal (always-on) mode 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 20 40 60 80 100 120 supply current ( a) sample rate (ksps) 12rbit burst mode, single conversions internal reference, normal bias internal reference, lp bias other reference 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 50 100 150 200 250 300 supply current ( a) sample rate (ksps) 10r bit burst mode, single conversions internal reference, normal bias internal reference, lp bias other reference 650 700 750 800 850 900 950 100 200 300 400 500 600 700 800 supply current ( a) sample rate (ksps) 10rbit conversions, normal bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v 350 360 370 380 390 400 410 420 430 440 450 50 150 250 supply current ( a) sample rate (ksps) 10rbit conversions, low power bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v 650 700 750 800 850 900 950 25 50 75 100 125 150 175 200 supply current ( a) sample rate (ksps) 12rbit conversions, normal bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v 350 360 370 380 390 400 410 420 430 440 450 10 20 30 40 50 60 supply current ( a) sample rate (ksps) 12rbit conversions, low power bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v
21 rev. 1.0 1.2.3. port i/o output drive figure 1.5. typical v oh vs. source current figure 1.6. typical v ol vs. sink current 1.3. thermal conditions table 1.12. thermal conditions parameter symbol test condition min typ max unit thermal resistance* ja soic-16 packages ? 70 ? c/w qfn-20 packages ? 60 ? c/w qsop-24 packages ? 65 ? c/w *note: thermal resistance assumes a multi-layer pcb with any exposed pad soldered to a pcb pad. 0 0.5 1 1.5 2 2.5 3 3.5 4 0 5 10 15 20 25 v o v orce current (ma) typical v oh vs. source current in high drive mode vdd = 3.6 v vdd = 3.3 v vdd = 2.7 v vdd = 2.2 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0 2 4 6 8 10 12 14 16 18 v o v orce current (ma) typical v oh vs. source current in low drive mode vdd = 3.6 v vdd = 3.3 v vdd = 2.7 v vdd = 2.2 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0 5 10 15 20 25 30 35 40 45 v ol v in current (ma) typical v ol vs. sink current in high drive mode vdd = 3.6 v vdd = 3.3 v vdd = 2.7 v vdd = 2.2 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0 5 10 15 20 25 v ol v in current (ma) typical v ol vs. sink current in low drive mode vdd = 3.6 v vdd = 3.3 v vdd = 2.7 v vdd = 2.2 v
rev. 1.0 22 1.4. absolute maximum ratings stresses above those listed under ta ble 1.13 may cause permanent damage to the device. this is a stress rating only and functional operati on of the devices at those or any ot her conditions above those indicated in the operation listings of this sp ecification is not implie d. exposure to maximum rating conditions for extended periods may af fect device reliability. for more information on t he available quality and re liability data, see the qua lity and reliability monitor report at http://www.silabs.com/support/ quality/pages/default.aspx . table 1.13. absolute maximum ratings parameter symbol test condition min max unit ambient temperature under bias t bias ?55 125 c storage temperature t stg ?65 150 c voltage on v dd v dd gnd?0.3 4.2 v voltage on i/o pins or rst v in v dd > 3.3 v gnd?0.3 5.8 v v dd < 3.3 v gnd?0.3 v dd +2.5 v total current su n k into supply pin i vdd ? 400 ma total current sourced out of gr ound pin i gnd 400 ? ma current sourced or sunk by any i/ o pin or rst i pio -100 100 ma operating junction temperature t j commercial grade devices (-gm, -gs, -gu) ?40 105 c industrial grade devices (-im, -is, -iu) ?40 125 c note: exposure to maximum rating conditions for extended periods may affect device reliability.
23 rev. 1.0
rev. 1.0 23 2. system overview the c8051f85x/86x device family ar e fully integrated, mixed-signal sy stem-on-a-chip mc us. highlighted features are listed below. refer to table 4.1 for specific product feature selection and part ordering numbers. ?? core: ?? pipelined cip-51 core ?? fully compatible with standard 8051 instruction set ?? 70% of instructions execute in 1-2 clock cycles ?? 25 mhz maximum operating frequency ?? memory: ?? 2-8 kb flash; in-system progra mmable in 512-byte sectors ?? 512 bytes ram (including 256 bytes standard 8051 ram and 256 bytes on-chip xram) ?? power: ?? internal low drop-out (ldo) regulator for cpu core voltage ?? power-on reset circuit and brownout detectors ?? i/o: up to 18 total multifunction i/o pins: ?? all pins 5 v tolerant under bias ?? flexible peripheral crossbar for peripheral routing ?? 5 ma source, 12.5 ma sink allows direct drive of leds ?? clock sources: ?? low-power internal oscillator: 24.5 mhz 2% ?? low-frequency internal oscillator: 80 khz ?? external cmos clock option ?? timers/counters and pwm: ?? 3-channel programmable counter a rray (pca) supporting pwm, captur e/compare and frequency output modes ?? 4x 16-bit general-purpose timers ?? independent watchdog timer, clocked from low frequency oscillator ?? communications and other digital peripherals: ?? uart ?? spi ? ?? i 2 c / smbus ? ?? 16-bit crc unit, supporting automatic crc of flash at 256-byte boundaries ?? analog: ?? 12-bit analog-to-digital converter (adc) ?? 2 x low-current comparators ?? on-chip debugging with on-chip power-on reset, volta ge supply monitor, watchdog timer, and clock oscillator, the c8051f85x/ 86x devices are truly standalone system-on-a-chip solutions. the flash memory is reprogrammable in- circuit, providing non-volatile data storage and allowing field upgrades of the firmware. the on-chip debugging interface (c2) allows non-intru sive (uses no on-chip re sources), full speed, in- circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging. each device is specified for 2.2 to 3.6 v operation, a nd are available in 20-pin qfn, 16-pin soic or 24-pin qsop packages. all package options are lead-free an d rohs compliant. the device is available in two temperature grades: -40 to +85 c or ?40 to +125 c. see table 4.1 for ordering information. a block diagram is included in figure 2.1.
24 rev. 1.0 figure 2.1. c8051f85x/86x family block diagram (qsop-24 shown) port 0 drivers digital peripherals priority crossbar decoder p0.0/vref p0.1/agnd p0.2 p0.3/extclk p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 8k byte isp flash program memory 256 byte sram sfr bus 256 byte xram port 2 driver p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 crc analog peripherals 2 comparators power net vdd gnd sysclk system clock configuration cmos oscillator input 24.5 mhz 2% oscillator debug / programming hardware power on reset reset c2d c2ck/rst 12/10 bit adc a m u x temp sensor vref vdd vdd extclk low-freq. oscillator independent watchdog timer internal reference + - + - port 1 drivers p2.0/c2d p1.6 p1.7 p2.1 uart timers 0, 1, 2, 3 3-ch pca i2c / smbus spi
rev. 1.0 25 2.1. power 2.1.1. ldo the c8051f85x/86x devices include an in ternal regulator to regulate the supply voltage down the core operating voltage of 1.8 v. this ldo consumes little power, but can be shut down in the power-saving stop mode. 2.1.2. voltage supply monitor (vmon0) the c8051f85x/86x devices include a voltage supply mo nitor which allows devices to function in known, safe operating condition without the need for external hardware. the supply monitor module includes the following features: ?? holds the device in reset if the main v dd supply drops below the vdd reset threshold. 2.1.3. device power modes the c8051f85x/86x devices feature three low power modes in addition to normal operating mode, allo wing the designer to save power when the core is not in use. all power modes are detailed in table 2.1. in addition, the user may choose to lower the clock speed in normal and idle modes to save power when the cpu requirement s allow for lower speed. table 2.1. c8051f85x/86x power modes mode description mode entrance mode exit normal cor e and peripherals operating at full speed idle ?? core halted ?? peripherals operate at full speed set idle bit in pcon an y enabled interrupt or reset source stop ?? all clocks stopped ?? core ldo and (optionally) comparators still running ?? pins retain state clear stopcf in reg0md an d set stop bit in pcon device reset shutdown ?? all clocks stopped ?? core ldo and all analog circuits shut down ?? pins retain state set stopcf in reg0md an d set stop bit in pcon device reset
26 rev. 1.0 2.1.3.1. normal mode normal mode encompasses the typical full-speed operat ion. the power consumption of the device in this mode will vary depending on the system clock speed and any an alog peripherals th at are enabled. 2.1.3.2. idle mode setting the idle bit in pcon causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit complete s execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle bit to be cleared and the cpu to resume operation. the pending interrupt will be serviced and the next instruction to be executed after th e return from in terrupt (reti) will be the instruction immediately following the one that set th e idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. 2.1.3.3. stop mode (regulator on) setting the stop bit in pcon when stopcf in reg0cn is clear causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. in stop mode the internal oscillator, cpu, and all digital peripherals are stopped. each analog peripheral may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. 2.1.3.4. shutdown mode (regulator off) shutdown mode is an extension of the normal stop m ode operation. setting the stop bit in pcon when stopcf in reg0cn is also set c auses the controller core to enter shutdown mode as soon as the instruction that sets the bit completes execution, and then the internal regulator is powered down. in shutdown mode, all core functions, memories and peri pherals are powered off. an external pin reset or power-on reset is required to exit shutdown mode. 2.2. i/o 2.2.1. general features the c8051f85x/86x ports have the following features: ?? push-pull or open-drain output modes and analog or digital modes. ?? port match allows the device to recognize a change on a port pin value and wake from idle mode or generate an interrupt. ?? internal pull-up resistors can be globally enabled or disabled. ?? two external interrupts provide unique interrup t vectors for monitoring time-critical events. ?? above-rail tolerance allows 5 v interface when device is powered. 2.2.2. crossbar the c8051f85x/86x devices have a digital peri p heral crossbar with the following features: ?? flexible peripheral assignment to port pins. ?? pins can be individually skipped to move peripherals as needed for design or layout considerations. the crossbar has a fixed priority for each i/o function a nd assigns these functions to the port pins. when a digital resource is selected, the least-significant unassi gned port pin is assigned to that resource. if a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. this provides some flexibility when designing a system: pins involved with sensitive analog measur ements can be moved away from digital i/o and peripherals can be moved around the chip as needed to ease layout constraints.
rev. 1.0 27 2.3. clocking the c8051f85x/86x devices have two in ternal oscillators and the option to use an external cmos input at a pin as the system clock. a programmable divider allows the user to internally run the system clock at a slower rate than the sele cted oscillator if desired. 2.4. counters/timers and pwm 2.4.1. programmable counter array (pca0) the c8051f85x/86x devices include a three-channel, 16-bit programmable counter array with the follo wing features: ?? 16-bit time base. ?? programmable clock divisor and clock source selection. ?? three independently-configurable channels. ?? 8, 9, 10, 11 and 16-bit pwm modes (center or edge-aligned operation). ?? output polarity control. ?? frequency output mode. ?? capture on rising, falling or any edge. ?? compare function for arbitrary waveform generation. ?? software timer (internal compare) mode. ?? can accept hardware ?kill? signal from comparator 0. 2.4.2. timers (timer 0, ti mer 1, t imer 2 and timer 3) timers include the following features: ?? timer 0 and timer 1 are standard 8051 timers, supp orting backwards-compa tibility with firmware and hardware. ?? timer 2 and timer 3 can each operate as 16-bit auto-reload or two independent 8-bit auto-reload timers, and include pin or lf o clock capture capabilities. 2.4.3. watchdog timer (wdt0) the watchdog timer includes a 16-bit timer with a programmable reset period. the registers are protected fr om inadvertent access by an independent lock and key interface. the watchdog timer has the following features: ?? programmable timeout interval. ?? runs from the low frequency oscillator. ?? lock-out feature to prevent any modification until a system reset.
28 rev. 1.0 2.5. communications and other digital peripherals 2.5.1. universal asynchronous receiver/transmitter (uart0) the uart uses two signals (tx and rx) and a predet er mined fixed baud rate to provide asynchronous communications with other devices. the uart module provides the following features: ?? asynchronous transmissions and receptions. ?? baud rates up to sysclk / 2 (tra nsmit) or sysclk / 8 (receive). ?? 8- or 9-bit data. ?? automatic start and stop generation. 2.5.2. serial peripheral interface (spi0) spi is a 3- or 4-wire communication interface that in clu des a clock, input data, output data, and an optional select signal. the spi module includes the following features: ?? supports 3- or 4-wire master or slave modes. ?? supports external clock frequencies up to sysclk / 2 in mast er mode and sysclk / 10 in slave mode. ?? support for all clock phase and polarity modes. ?? 8-bit programmable clock rate. ?? support for multiple masters on the same data lines. 2.5.3. system management bus / i2c (smbus0) the smbus interface is a two-wire, bi-directional serial bu s compatible with both i2c and smbus protocols. the two clock and data signals operate in open-drain mode with external pull-ups to support automatic bus arbitration. reads and writes to the in terface are byte -oriented with the sm bus interface autonomously co ntrolling the serial transfer of the data. data can be transferred at up to 1/8th of the system clock as a master or slave, which can be faster than allowed by the smbus / i2c specification, depending on the clock source used. a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple masters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and generation. the smbus module includes the following features: ?? standard (up to 100 kbps) and fast (400 kbps) transfer speeds. ?? support for master, slave, and multi-master modes. ?? hardware synchronization and arbitration for multi-master mode. ?? clock low extending (clock stretching) to interface with faster masters. ?? hardware support for 7-bit slave and general call address recognition. ?? firmware support for 10-bit slave address decoding. ?? ability to inhibit all slave states. ?? programmable data setup/hold times. 2.5.4. 16/32-bit crc (crc0) the crc module is designed to provide hardware ca lculations for flash memory verification and communications protocols. the crc module supports the standard ccitt-16 16-bit polynomial (0x1021), and includes the following features: ?? support for four ccitt-16 polynomial.
rev. 1.0 29 ?? byte-level bit reversal. ?? automatic crc of flash contents on one or more 256-byte blocks. ?? initial seed selection of 0x0000 or 0xffff.
30 rev. 1.0 2.6. analog peripherals 2.6.1. 12-bit analog-to-digital converter (adc0) the adc0 module on c8051f85x/86x devices is a su cce ssive approximation register (sar) analog to digital converter (adc). the key features of the adc module are: ?? single-ended 12-bit and 10-bit modes. ?? supports an output update rate of 200 ksps samples per second in 12 -bit mode or 800 ksps sam ples per second in 10-bit mode. ?? operation in low power modes at lower conversion speeds. ?? selectable asynchronous hardware conversion trigger. ?? output data window comparator allows automatic range checking. ?? support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. ?? conversion complete and window compare interrupts supported. ?? flexible output data formatting. ?? includes an internal fast-settling reference with two levels (1.65 v and 2.4 v) and support for ex ternal reference and signal ground. 2.6.2. low current comparators (cmp0, cmp1) the comparators take two analog input voltages and ou tpu t the relationship between these voltages (less than or greater than) as a digital signal. the low power comparator module includes the following features: ?? multiple sources for the positive and negativ e poles, including vdd, vref, and i/o pins. ?? two outputs are available: a digital synchronous latched output and a digital asynchronous raw output. ?? programmable hysteresis and response time. ?? falling or rising edge interrupt opt ions on the co mparator output. ?? provide ?kill? signal to pca module. ?? comparator 0 can be used to reset the device.
rev. 1.0 31 2.7. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ?? the core halts program execution. ?? module registers are initialized to their defined re set values unless the bits reset only with a power- on reset. ?? external port pins are forced to a known state. ?? interrupts and timers are disabled. all registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. the contents of ram are unaffected during a reset; any previously stored data is preserved as long as power is not lost. the port i/o latches are reset to 1 in open-drain mode. weak pullups are enabled during and after the reset. for vdd supply monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the internal low-power oscillator. the watchdog timer is enabled with the low frequency oscillator (lfo0) as its clock source. program execution begins at location 0x0000. 2.8. on-chip debugging the c8051f85x/86x devices include an on-chip silicon labs 2-wire (c2) debug interface to allow flash programming and in-system debugging with the producti on part installed in the end application. the c2 interface uses a clock sig nal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a hos t system. see the c2 interface specificat ion for details on the c2 protocol.
32 rev. 1.0
rev. 1.0 31 3. pin definitions 3.1. c8051f850/1/2/3/4/ 5 qsop24 pin definitions figure 3.1. c8051f850/1/2/3/4/5-gu and c8051f850/1/2/3/4/5-iu pinout table 3.1. pin definitions for c8051f850/1/2/3/4/5-gu and c8051f850/1/2/3/4/5-iu pin name type pin numbers crossbar capability additional digital functions analog functions gnd ground 5 vdd power 6 rst / c2ck active-low reset / c2 debug clock 7 n/c p0.2 p0.1 / agnd p0.0 / vref gnd vdd rst / c2ck c2d / p2.0 p1.7 p1.6 p1.5 p2.1 n/c p0.3 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 n/c 2 1 4 3 5 6 7 24 pin qsop (top view) 8 9 10 11 12 23 24 21 22 20 19 18 17 16 15 14 13
32 rev. 1.0 p0.0 standard i/o 4 yes p0mat.0 int0.0 int1.0 adc0.0 cp0p.0 cp0n.0 vref p0.1 standard i/o 3 yes p0mat.1 int0.1 int1.1 adc0.1 cp0p.1 cp0n.1 agnd p0.2 standard i/o 2 yes p0mat.2 int0.2 int1.2 adc0.2 cp0p.2 cp0n.2 p0.3 / extclk standard i/o / external cmos clock input 23 yes p0mat.3 extclk int0.3 int1.3 adc0.3 cp0p.3 cp0n.3 p0.4 standard i/o 22 yes p0mat.4 int0.4 int1.4 adc0.4 cp0p.4 cp0n.4 p0.5 standard i/o 21 yes p0mat.5 int0.5 int1.5 adc0.5 cp0p.5 cp0n.5 p0.6 standard i/o 20 yes p0mat.6 cnvstr int0.6 int1.6 adc0.6 cp0p.6 cp0n.6 p0.7 standard i/o 19 yes p0mat.7 int0.7 int1.7 adc0.7 cp0p.7 cp0n.7 table 3.1. pin definitions for c8051f850/1/2/3/4/5-gu and c8051f850/1/2/3/4/5-iu pin name type pin numbers crossbar capability additional digital functions analog functions
rev. 1.0 33 p1.0 standard i/o 18 yes p1mat.0 adc0.8 cp1p.0 cp1n.0 p1.1 standard i/o 17 yes p1mat.1 adc0.9 cp1p.1 cp1n.1 p1.2 standard i/o 16 yes p1mat.2 adc0.10 cp1p.2 cp1n.2 p1.3 standard i/o 15 yes p1mat.3 adc0.11 cp1p.3 cp1n.3 p1.4 standard i/o 14 yes p1mat.4 adc0.12 cp1p.4 cp1n.4 p1.5 standard i/o 11 yes p1mat.5 adc0.13 cp1p.5 cp1n.5 p1.6 standard i/o 10 yes p1mat.6 adc0.14 cp1p.6 cp1n.6 p1.7 standard i/o 9 yes p1mat.7 adc0.15 cp1p.7 cp1n.7 p2.0 / c2d standard i/o / c2 debug data 8 p2.1 standard i/o 12 table 3.1. pin definitions for c8051f850/1/2/3/4/5-gu and c8051f850/1/2/3/4/5-iu pin name type pin numbers crossbar capability additional digital functions analog functions
34 rev. 1.0 n/c no connection 1 13 24 table 3.1. pin definitions for c8051f850/1/2/3/4/5-gu and c8051f850/1/2/3/4/5-iu pin name type pin numbers crossbar capability additional digital functions analog functions
rev. 1.0 35 3.2. c8051f850/1/2/3/4/ 5 qfn20 pin definitions figure 3.2. c8051f850/1/2/3/4/5-gm and c8051f850/1/2/3/4/5-im pinout table 3.2. pin definitions for c8051f850/1/2/3/4/5-gm and c8051f850/1/2/3/4/5-im pin name type pin numbers crossbar capability additional digital functions analog functions gnd ground center 3 12 vdd power 4 rst / c2ck active-low reset / c2 debug clock 5 20 19 18 17 2 3 4 5 7 8 9 10 15 14 13 12 20 pin qfn (top view) p0.1 / agnd p0.0 / vref gnd vdd rst / c2ck c2d / p2.0 p1.6 p1.5 p1.4 p1.3 p0.6 p0.7 p1.0 p1.1 gnd p1.2 p0.2 p0.3 p0.4 p0.5 gnd 1 6 11 16
36 rev. 1.0 p0.0 standard i/o 2 yes p0mat.0 int0.0 int1.0 adc0.0 cp0p.0 cp0n.0 vref p0.1 standard i/o 1 yes p0mat.1 int0.1 int1.1 adc0.1 cp0p.1 cp0n.1 agnd p0.2 standard i/o 20 yes p0mat.2 int0.2 int1.2 adc0.2 cp0p.2 cp0n.2 p0.3 standard i/o 19 yes p0mat.3 extclk int0.3 int1.3 adc0.3 cp0p.3 cp0n.3 p0.4 standard i/o 18 yes p0mat.4 int0.4 int1.4 adc0.4 cp0p.4 cp0n.4 p0.5 standard i/o 17 yes p0mat.5 int0.5 int1.5 adc0.5 cp0p.5 cp0n.5 p0.6 standard i/o 16 yes p0mat.6 cnvstr int0.6 int1.6 adc0.6 cp0p.6 cp0n.6 p0.7 standard i/o 15 yes p0mat.7 int0.7 int1.7 adc0.7 cp0p.7 cp0n.7 table 3.2. pin definitions for c8051f850/1/2/3/4/5-gm and c8051f850/1/2/3/4/5-im pin name type pin numbers crossbar capability additional digital functions analog functions
rev. 1.0 37 p1.0 standard i/o 14 yes p1mat.0 adc0.8 cp1p.0 cp1n.0 p1.1 standard i/o 13 yes p1mat.1 adc0.9 cp1p.1 cp1n.1 p1.2 standard i/o 11 yes p1mat.2 adc0.10 cp1p.2 cp1n.2 p1.3 standard i/o 10 yes p1mat.3 adc0.11 cp1p.3 cp1n.3 p1.4 standard i/o 9 yes p1mat.4 adc0.12 cp1p.4 cp1n.4 p1.5 standard i/o 8 yes p1mat.5 adc0.13 cp1p.5 cp1n.5 p1.6 standard i/o 7 yes p1mat.6 adc0.14 cp1p.6 cp1n.6 p2.0 / c2d standard i/o / c2 debug data 6 table 3.2. pin definitions for c8051f850/1/2/3/4/5-gm and c8051f850/1/2/3/4/5-im pin name type pin numbers crossbar capability additional digital functions analog functions
38 rev. 1.0 3.3. c8051f860/1/2/3/4/ 5 soic16 pin definitions figure 3.3. c8051f860/1/2/3/4/5-gs and c8051f860/1/2/3/4/5-is pinout table 3.3. pin definitions for c8051f860/1/2/3/4/5-gs and c8051f860/1/2/3/4/5-is pin name type pin numbers crossbar capability additional digital functions analog functions gnd ground 4 vdd power 5 rst / c2ck active-low reset / c2 debug clock 6 p0.0 standard i/o 3 yes p0mat.0 int0.0 int1.0 adc0.0 cp0p.0 cp0n.0 p0.2 p0.1 / agnd p0.0 / vref gnd vdd rst / c2ck c2d / p2.0 p1.3 p0.3 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 2 1 4 3 5 6 7 15 16 13 14 12 11 10 16 pin soic (top view) 8 9
rev. 1.0 39 p0.1 standard i/o 2 yes p0mat.1 int0.1 int1.1 adc0.1 cp0p.1 cp0n.1 p0.2 standard i/o 1 yes p0mat.2 int0.2 int1.2 adc0.2 cp0p.2 cp0n.2 p0.3 / extclk standard i/o / external cmos clock input 16 yes p0mat.3 extclk int0.3 int1.3 adc0.3 cp0p.3 cp0n.3 p0.4 standard i/o 15 yes p0mat.4 int0.4 int1.4 adc0.4 cp0p.4 cp0n.4 p0.5 standard i/o 14 yes p0mat.5 int0.5 int1.5 adc0.5 cp0p.5 cp0n.5 p0.6 standard i/o 13 yes p0mat.6 cnvstr int0.6 int1.6 adc0.6 cp1p.0 cp1n.0 p0.7 standard i/o 12 yes p0mat.7 int0.7 int1.7 adc0.7 cp1p.1 cp1n.1 p1.0 standard i/o 11 yes p1mat.0 adc0.8 cp1p.2 cp1n.2 table 3.3. pin definitions for c8051f860/1/2/3/4/5-gs and c8051f860/1/2/3/4/5-is pin name type pin numbers crossbar capability additional digital functions analog functions
40 rev. 1.0 p1.1 standard i/o 10 yes p1mat.1 adc0.9 cp1p.3 cp1n.3 p1.2 standard i/o 9 yes p1mat.2 adc0.10 cp1p.4 cp1n.4 p1.3 standard i/o 8 yes p1mat.3 adc0.11 cp1p.5 cp1n.5 p2.0 / c2d standard i/o / c2 debug data 7 table 3.3. pin definitions for c8051f860/1/2/3/4/5-gs and c8051f860/1/2/3/4/5-is pin name type pin numbers crossbar capability additional digital functions analog functions
rev. 1.0 40 4. ordering information figure 4.1. c8051f85x/86x part numbering all c8051f85x/86x family member s have the following features: ?? cip-51 core running up to 25 mhz ?? two internal oscillators (24.5 mhz and 80 khz) ?? i2c/smbus ?? spi ?? uart ?? 3-channel programmable counter array (pwm, clock generation, capture/compare) ?? 4 16-bit timers ?? 2 analog comparators ?? 16-bit crc unit in addition to these features, each part number in the c 805 1f85x/86x family has a se t of features that vary across the product line. the product selection guide in table 4.1 shows the features available on each family member. all devices in table 4.1 are also available in an industrial version. for the industr ial version, the -g in the ordering part number is replaced with -i. for example, the industrial version of the c8051f850-c-gm is the c8051f850-c-im. c8051 f 850 ? c ? silicon labs 8051 family memory type ? f (flash) family and features ? 85x and 86x revision temperature grade g (-40 to +85), i (-40 to +125) g m package type m (qfn), u (qsop), s (ssop)
41 rev. 1.0 table 4.1. product selection guide ordering part number flash memory (kb) ram (bytes) digital port i/os (total) number of adc0 channels i/o with comparator 0/1 inputs pb-free (rohs compliant) aec-q100 qualified temperature range package c8051f850-c-gm 8 512 16 15 15 ? ? -40 to 85 c qfn-20 c8051f850-c-gu 8 512 18 16 16 ? ? -40 to 85 c qsop-24 c8051f851-c-gm 4 512 16 15 15 ? ? -40 to 85 c qfn-20 c8051f851-c-gu 4 512 18 16 16 ? ? -40 to 85 c qsop-24 c8051f852-c-gm 2 256 16 15 15 ? ? -40 to 85 c qfn-20 C8051F852-C-GU 2 256 18 16 16 ? ? -40 to 85 c qsop-24 c8051f853-c-gm 8 512 16 ? 15 ? ? -40 to 85 c qfn-20 c8051f853-c-gu 8 512 18 ? 16 ? ? -40 to 85 c qsop-24 c8051f854-c-gm 4 512 16 ? 15 ? ? -40 to 85 c qfn-20 c8051f854-c-gu 4 512 18 ? 16 ? ? -40 to 85 c qsop-24 c8051f855-c-gm 2 256 16 ? 15 ? ? -40 to 85 c qfn-20 c8051f855-c-gu 2 256 18 ? 16 ? ? -40 to 85 c qsop-24 c8051f860-c-gs 8 512 13 12 12 ? ? -40 to 85 c soic-16 c8051f861-c-gs 4 512 13 12 12 ? ? -40 to 85 c soic-16 c8051f862-c-gs 2 256 13 12 12 ? ? -40 to 85 c soic-16 c8051f863-c-gs 8 512 13 ? 12 ? ? -40 to 85 c soic-16 c8051f864-c-gs 4 512 13 ? 12 ? ? -40 to 85 c soic-16 c8051f865-c-gs 2 256 13 ? 12 ? ? -40 to 85 c soic-16
rev. 1.0 42 -im, -iu and -is extended temperature range devices (-40 to 125 c) ar e also available. table 4.1. product selection guide ordering part number flash memory (kb) ram (bytes) digital port i/os (total) number of adc0 channels i/o with comparator 0/1 inputs pb-free (rohs compliant) aec-q100 qualified temperature range package
43 rev. 1.0
c8051f85x/86x rev. 1.0 42 5. qsop-24 package specifications figure 5.1. qsop-24 package drawing table 5.1. qsop-24 package dimensions dimension min nom max dimension min nom max a ? ? 1.75 e 0.635 bsc a1 0.10 ? 0.25 l 0.40 ? 1.27 b 0.20 ? 0.30 0o ? 8o c 0.10 ? 0.25 aaa 0.20 d 8.65 bsc bbb 0.18 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.10 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. di mensioning and tolerancing per ansi y14.5m-1994. 3. t his drawing conforms to je dec outline mo-137, variation ae. 4. re commended card reflow profile is per the je dec/ipc j-std-020 specification for small body components.
c8051f85x/86x 43 rev. 1.0 figure 5.2. qsop-24 pcb land pattern table 5.2. qsop-24 pcb land pattern dimensions dimension min max c 5.20 5.30 e 0.635 bsc x 0.30 0.40 y 1.50 1.60 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder ma sk defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a st ainless steel, laser-cut and electro-po lished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly 7. a no-cle an, type-3 solder paste is recommended. 8. t he recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f85x/86x rev. 1.0 44 6. qfn-20 package specifications figure 6.1. qfn-20 package drawing table 6.1. qfn-20 package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.70 0.75 0.80 f 2.53 bsc a1 0.00 0.02 0.05 l 0.3 0.40 0.5 b 0.20 0.25 0.30 l1 0.00 ? 0.10 c 0.25 0.30 0.35 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.6 1.70 1.8 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.6 1.70 1.8 notes: 1. all dime nsions are shown in millimeters unless otherwise noted. 2. dimen sioning and tolerancing per ansi y14.5m-1994.
c8051f85x/86x 45 rev. 1.0 figure 6.2. qfn-20 landing diagram
c8051f85x/86x rev. 1.0 46 table 6.2. qfn-20 landing diagram dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimen sions shown are in millimeters (mm) unless otherwise noted. 2. dimensi oning and tolerancing is per the ansi y14.5m- 1994 specification. 3. thi s land pattern design is based on ipc-sm-782 guidelines. 4. all dimen sions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes: solder mask design 1. all met al pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a st ainless steel, laser-cut and electro-po lished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides app roximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. notes: card assembly 1. a no -clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is pe r the jedec/ipc j-std-020 specification for small body components.
c8051f85x/86x 47 rev. 1.0
c8051f85x/86x rev. 1.0 47 7. soic-16 package specifications figure 7.1. soic-16 package drawing table 7.1. soic-16 package dimensions dimension min nom max dimension min nom max a ? 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 ? h 0.25 0.50 b 0.31 0.51 0o 8o c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. di mensioning and tolerancing per ansi y14.5m-1994. 3. t his drawing conforms to the jedec so lid state outline ms-012, variation ac. 4. re commended card reflow profile is per the je dec/ipc j-std-020 specification for small body components.
c8051f85x/86x 48 rev. 1.0 figure 7.2. soic-16 pcb land pattern table 7.2. soic-16 pcb land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. t his land pattern design is based on ipc-7 351 pattern soic127p600x165-16n for density level b (median land protrusion). 3. all feature sizes shown are at maximum materi al condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
rev. 1.0 49 8. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f85x/86x device family is shown in figure 8.1. figure 8.1. c8051f85x/86x memory map (8 kb flash version shown) program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function registers (direct addressing only) data memory (ram) 32 general purpose registers 0x1f 0x20 0x2f 32 bit-addressable bytes lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 256 bytes (accessable using movx instruction) 0x0000 0x00ff same 256 bytes as 0x0000 to 0x00ff, wrapped on 256-byte boundaries 0x0100 0xffff 8 kb flash (in-system programmable in 512 byte sectors) 0x0000 0x1fff
50 rev. 1.0 8.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f85x/86x family implements 8 kb, 4 kb or 2 kb of this program memory space as in-system, re-programmable flash memory. the last address in the flash block (0x1fff on 8 kb devices, 0x0fff on 4 kb devices and 0x07ff on 2 kb devices) serves as a security lock byte for the device, and provides read, write and erase protec tion. addresses above the lock byte within the 64 kb address space are reserved. figure 8.2. flash program memory map 8.1.1. movx instruction and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f85x/86x devices, the movx instruction is norma lly used to read and write on-chip xram, but can be re-configured to write and eras e on-chip flash memory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase a nd write flash. this flash access feature provides a mechanism for the c8051f85x/86x to update program code and use the program memory space for non-volatile data storage. refer to section ?10. flash memory? on page 57 for further details. 8.2. data memory the c8051f85x/86x device family includes up to 51 2 bytes of ram data memory. 256 bytes of this memory is mapped into the internal ram space of th e 8051. on devices with 512 bytes total ram, 256 additional bytes of memory are ava ilable as on-chip ?external? memory. the data memory map is shown in figure 8.1 for reference. 8.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the low er 128 bytes of data memory are used for genera l purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 byte s, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. lock byte 0x0000 0x07ff 0x07fe flash memory organized in 512-byte pages 0x0600 flash memory space lock byte 0x0000 0x0fff 0x0ffe 0x0e00 flash memory space lock byte 0x0000 0x1fff 0x1ffe 0x1e00 flash memory space c8051f850/3 c8051f860/3 c8051f851/4 c8051f861/4 c8051f852/5 c8051f862/5 lock byte page lock byte page lock byte page
rev. 1.0 51 the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 8.1 illustra tes the data memory organization of the c8051f85x/ 86x. revision c c8051f852/5 and c8051f862/5 devices implement the upper four bytes of internal ram as a 32-bit unique identifier. more information can be found in ?device identification and unique identifier? on page 64. 8.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of general-purpose registers. each bank consists of eight byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bits in the program status word (psw) register, rs0 and rs1, select the active regi ster bank. this allows fast contex t switching when entering subroutines and interrupt service routines. indirect addressing modes use registers r0 an d r1 as index registers. 8.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destin ation operands as opposed to a byte source or destination). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 8.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is designated using the stack po inter (sp) sfr. the sp will point to th e last location us ed. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 8.2.2. external ram on devices with 512 bytes total ram, there are 256 bytes of on-chip ram mapped into the external data me mory space. all of these address locations ma y be accessed using the exte rnal move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. note: the 16-bit movx instruction is also used for writes to the flash memo ry. see section ?10. flash memory? on page 57 for details. the movx instruction accesses xram by default. for a 16-bit movx operation (@dptr), the upper 8 bits of the 16-bit external data memory address word are "don't cares". as a result, addresses 0x0000 through 0x00ff are mapped modulo style over the entire 64 k external data memory address range. for exam ple, the xram byte at address 0x0000 is shadowed at addresses 0x0100, 0x0200, 0x0300, 0x0400, etc. revision c c8051f850/1/3/4 and c8051f860/1/3/4 devi ces implement the upper f our bytes of external ram as a 32-bit unique identifier. more information can be found in ?device identification and unique identifier? on page 64.
52 rev. 1.0 8.2.3. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruction set. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x 0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided.
rev. 1.0 52 9. special function register memory map this section details the special function regi ster memory map for the c8051f85x/86x devices. table 9.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 p0mat p0mask vdm0cn f0 b p0mdin p1mdin eip1 - - prtdrv pca0pwm e8 adc0cn0 pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 p1mat p1mask rstsrc e0 acc xbr0 xbr1 xbr2 it01cf - eie1 - d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 crc0in crc0dat adc0pwr d0 psw ref0cn crc0auto crc0cnt p0skip p1skip smb0adm smb0adr c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h crc0cn crc0flip c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth oscicl b8 ip adc0tk - adc0mx adc0cf adc0l adc0h cpt1cn b0 - osclcn adc0cn1 adc0ac - deviceid revid flkey a8 ie clksel cpt1mx cpt1md smb0tc derivid - - a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout - 98 scon0 sbuf0 - cpt0cn pca0clr cpt0md pca0cent cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h pca0pol wdtcn 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph - - - pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable) table 9.2. special function registers register address register description page acc 0xe0 accumulator 115 adc0ac 0xb3 adc0 accumulator configuration 97 adc0cf 0xbc adc0 configuration 96 adc0cn0 0xe8 adc0 control 0 94 adc0cn1 0xb2 adc0 control 1 95 adc0gth 0xc4 adc0 greater-than high byte 102 adc0gtl 0xc3 adc0 greater-than low byte 103 adc0h 0xbe adc0 data word high byte 100
53 rev. 1.0 adc0l 0xbd adc0 data word low byte 101 adc0lth 0xc6 adc0 less-than high byte 104 adc0ltl 0xc5 adc0 less-than low byte 105 adc0mx 0xbb adc0 multiplexer selection 106 adc0pwr 0xdf adc0 power control 98 adc0tk 0xb9 adc0 burst mode track time 99 b 0xf0 b register 116 ckcon 0x8e clock control 255 clksel 0xa9 clock selection 122 cpt0cn 0x9b comparator 0 control 127 cpt0md 0x9d comparator 0 mode 128 cpt0mx 0x9f comparator 0 multiplexer selection 129 cpt1cn 0xbf comparator 1 control 130 cpt1md 0xab comparator 1 mode 131 cpt1mx 0xaa comparator 1 multiplexer selection 132 crc0auto 0xd2 crc0 automatic control 139 crc0cn 0xce crc0 control 136 crc0cnt 0xd3 crc0 automatic flash sector count 140 crc0dat 0xde crc0 data output 138 crc0flip 0xcf crc0 bit flip 141 crc0in 0xdd crc0 data input 137 derivid 0xad derivative identification 66 deviceid 0xb5 device identification 65 dph 0x83 data pointer low 113 dpl 0x82 data pointer high 112 eie1 0xe6 extended interrupt enable 1 74 eip1 0xf3 extended interrupt priority 1 76 flkey 0xb7 flash lock and key 63 table 9.2. special function registers (continued) register address register description page
rev. 1.0 54 ie 0xa8 interrupt enable 71 ip 0xb8 interrupt priority 73 it01cf 0xe4 int0 / int1 configuration 143 oscicl 0xc7 high frequency oscillator calibration 120 osclcn 0xb1 low frequency oscillator control 121 p0 0x80 port 0 pin latch 191 p0mask 0xfe port 0 mask 189 p0mat 0xfd port 0 match 190 p0mdin 0xf1 port 0 input mode 192 p0mdout 0xa4 port 0 output mode 193 p0skip 0xd4 port 0 skip 194 p1 0x90 port 1 pin latch 197 p1mask 0xee port 1 mask 195 p1mat 0xed port 1 match 196 p1mdin 0xf2 port 1 input mode 198 p1mdout 0xa5 port 1 output mode 199 p1skip 0xd5 port 1 skip 200 p2 0xa0 port 2 pin latch 201 p2mdout 0xa6 port 2 output mode 202 pca0cent 0x9e pca center alignment enable 170 pca0clr 0x9c pca comparator clear control 163 pca0cn 0xd8 pca control 160 pca0cph0 0xfc pca capture module high byte 0 168 pca0cph1 0xea pca capture module high byte 1 174 pca0cph2 0xec pca capture module high byte 2 176 pca0cpl0 0xfb pca capture module low byte 0 167 pca0cpl1 0xe9 pca capture module low byte 1 173 pca0cpl2 0xeb pca capture module low byte 2 175 table 9.2. special function registers (continued) register address register description page
55 rev. 1.0 pca0cpm0 0xda pca capture/compare mode 0 164 pca0cpm1 0xdb pca capture/compare mode 1 171 pca0cpm2 0xdc pca capture/compare mode 1 172 pca0h 0xfa pca counter/timer low byte 166 pca0l 0xf9 pca counter/timer high byte 165 pca0md 0xd9 pca mode 161 pca0pol 0x96 pca output polarity 169 pca0pwm 0xf7 pca pwm configuration 162 pcon 0x87 power control 77 prtdrv 0xf6 port drive strength 188 psctl 0x8f program store control 62 psw 0xd0 program status word 117 ref0cn 0xd1 voltage reference control 107 reg0cn 0xc9 voltage regulator control 78 revid 0xb6 revision identification 67 rstsrc 0xef reset source 206 sbuf0 0x99 uart0 serial port data buffer 279 scon0 0x98 uart0 serial port control 277 smb0adm 0xd6 smbus0 slave address mask 246 smb0adr 0xd7 smbus0 slave address 245 smb0cf 0xc1 smbus0 configuration 240 smb0cn 0xc0 smbus0 control 243 smb0dat 0xc2 smbus0 data 247 smb0tc 0xac smbus0 timing and pin control 242 sp 0x81 stack pointer 114 spi0cfg 0xa1 spi0 configuration 218 spi0ckr 0xa2 spi0 clock control 222 spi0cn 0xf8 spi0 control 220 table 9.2. special function registers (continued) register address register description page
rev. 1.0 56 spi0dat 0xa3 spi0 data 223 tcon 0x88 timer 0/1 control 257 th0 0x8c timer 0 high byte 261 th1 0x8d timer 1 high byte 262 tl0 0x8a timer 0 low byte 259 tl1 0x8b timer 1 low byte 260 tmod 0x89 timer 0/1 mode 258 tmr2cn 0xc8 timer 2 control 263 tmr2h 0xcd timer 2 high byte 268 tmr2l 0xcc timer 2 low byte 267 tmr2rlh 0xcb timer 2 reload high byte 266 tmr2rll 0xca timer 2 reload low byte 265 tmr3cn 0x91 timer 3 control 269 tmr3h 0x95 timer 3 high byte 274 tmr3l 0x94 timer 3 low byte 273 tmr3rlh 0x93 timer 3 reload high byte 272 tmr3rll 0x92 timer 3 reload low byte 271 vdm0cn 0xff supply monitor control 207 wdtcn 0x97 watchdog timer control 282 xbr0 0xe1 port i/o crossbar 0 185 xbr1 0xe2 port i/o crossbar 1 186 xbr2 0xe3 port i/o crossbar 2 187 table 9.2. special function registers (continued) register address register description page
57 rev. 1.0
rev. 1.0 57 10. flash memory on-chip, re-programmable flash memory is included for program code and non-volatile data storage. the flash memory is organized in 512-byte pages. it can be erased and written through the c2 interface or from firmware by overloading the movx inst ruction. any individual byte in flash memory must only be written once between page erase operations. 10.1. security options the cip-51 provides security options to protect th e flash memory from inadv ertent modification by software as well as to prevent the viewing of prop rietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash memory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located in flash user space offers protection of the fl ash program memory from access (reads, writes, or erases) by unprotected c ode or the c2 interface. see section ?8. memory organization? on page 49 for the location of the secu rity byte. the flash securi ty mechanism allows the user to lock n 512-byte flash pages, starting at pa ge 0 (addresses 0x0000 to 0x01ff), where n is the 1?s complement number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are ?1?) and locked when any other flash pages are locked (any bit of the lock byte is ?0?). an example is shown in figure 10.1. figure 10.1. security byte decoding the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, and erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on lock ed pages. table 10.1 summarizes the flash security features of the c8051f85x/86x devices. table 10.1. flash security summary action c2 debug in terface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages ( except page with lock byte) permitted permitted permitted read, write or erase locked pages ( except page with lock byte) not permitted flash error reset permitted read or write page containing lock byte ( if no pages are locked) permitted permitted n/a read or write page containing lock byte (if an y page is locked) not permitted flash error reset permitted security lock byte: 11111101b 1s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page)
58 rev. 1.0 read contents of lock byte (if no pages are locked) permitted permitted n/a read contents of lock byte (if an y page is locked) not permitted flash error reset permitted erase page containing lock byte ( if no pages are locked) permitted permitted n/a erase page containing lock byte?unlock all p ages (if any page is locked) c2 device erase on ly flash error reset flash error reset lock additional pages (cha nge 1s to 0s in the lock byte) not permitted flash error reset flash error reset unlock individual pages (cha nge 0s to 1s in the lock byte) not permitted flash error reset flash error reset read, write or erase reserved area not permitted flash error reset flash error reset c2 device erase?erases all flash pages in clu ding the page containing the lock byte. flash error reset ?not permitted; causes flash error de vice reset (ferror bit in rs tsrc is '1' after reset). - all prohibited operations that are per formed via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks the page containing the lock byte. - once written to, the lock byte cannot be modifi e d except by performing a c2 device erase. - if user code writes to the lock byte, the lock do es not take effect until the next device reset. table 10.1. flash security summary (continued)
rev. 1.0 59 10.2. programming the flash memory writes to flash memory clear bits from logic 1 to lo gic 0, and can be performed on single byte locations. flash erasures set bits back to logic 1, and occur on ly on full pages. the write and erase operations are automatically timed by hard ware for proper execution; data polling to determine the end of th e write/erase operation is not required. code execution is stalled during a flash write/erase operation. the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non- initialized device. to ensure the integrity of flash contents, it is st rongly recommended that the on-chip supply monitor be enabled in any system that includes code that writ es and/or erases flash memory from software. 10.2.1. flash lock and key functions flash writes and erases by user so f tware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in seque nce, before fl ash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes hav e been written properly. the flash lock resets after each write or erase; the key codes must be wri tten again before a following flash operation can be performed. 10.2.2. flash erase procedure the flash memory can be programmed by software us ing the movx write instruction with the address and data byte to be programmed provided as normal op erands. before writing to flash memory using movx, flash write operations must be enabled by: (1) setti ng the pswe program store write enable bit in the psctl register to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire page, perform the following steps: 1. disable interrupts (recommended). 2. set the psee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. 6. using the movx instru ction, write a data byte to any location within the page to be erased. 7. clear the pswe and psee bits. 10.2.3. flash write procedure flash bytes are programmed by software with the following sequence: 1 . disable interrupts (recommended). 2. erase the flash page containing the tar get location, as descri bed in section 10.2.2. 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instru ction, write a single data byte to the desired location within the desired
60 rev. 1.0 page. 8. clear the pswe bit. steps 5?7 must be repeated for each byte to be writte n. after flash writes are complete, pswe should be cleared so that movx instructions do not target program memory. 10.3. non-volatile data storage the flash memory can be used for non-volatile data storage as well as progra m code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. 10.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from soft ware involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of supply voltage, system clock frequency or temper ature. this accidental execution of flash modifying code can result in al teration of flash memory contents causing a system failure that is only recoverable by re-flashing the code in the device. to help prevent the accidental modi fication of flash by firmware, ha rdware restricts flash writes and erasures when the supply monitor is not active and se lected as a reset source. as the monitor is enabled and selected as a reset source by default, it is re commended that systems writing or erasing flash simply maintain the default state. the following guidelines are recommended for any syst em which contains routin es which write or erase flash from code. 10.4.1. voltage supply maintenance and the supply monitor 1. if the system power supply is subject to vo ltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum supply rise time specification is met. if the system cannot meet this rise time specification, then add an exte rnal supply brownout circuit to the rst pin of the device that holds the device in reset un til the voltage supply reaches t he lower limit, and re-asserts rst if the supply drops below the low supply limit. 3. do not disable the supply monitor. if the supp ly monitor must be disabled in the system, firmware should be added to the startup routine to enable the on-chip supply monitor and enable the supply monitor as a reset source as early in code as possi ble. this should be the first set of instructions executed after the reset vector. for c-based systems, this may involve modifying the startup code added by the c compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the supply monitor and enabling the supply monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware", available from the silicon laboratories web site. note that the supply monitor must be enabled and enabled as a reset source when writing or erasing flash memory. a flash error reset will occur if either condition is not met. 4. as an added precaution if the supply monitor is ever disabled, explicitly enable the supply monitor and enable the supply monitor as a reset source inside the functions that write and erase flash memory. the supply monitor enable instructions shoul d be placed just after the instruction to set pswe to a 1, but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sour ces) register use direct assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example, "rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regist er explicitly set the pors f bit to a '1'. areas to check are initialization code which enables othe r reset sources, such as the missing clock
rev. 1.0 61 detector or comparator, for example, and instru ctions which force a software reset. a global search on "rstsrc" can quickly verify this. 10.4.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (in register psctl) is set to a 1. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one routine in code that sets pswe and psee both to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop variable maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in ?an201: writing to flash from firmware", available from the silicon laboratories web site. 9. disable interrupts prior to setting pswe to a '1' and leave them disabled until after pswe has been reset to 0. any interrupts posted during the flash write or er ase operation will be serviced in priority order after the flash operation has been completed and interrupts have been re-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas. 11. add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal ad dress does not resu lt in modification of the flash. 10.4.3. system clock 12. if operating from an external crystal-bas ed sour ce, be advised that crystal performance is susceptible to electrical interferen ce and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the intern al oscillator or use an external cmos clock. 13. if operating from the external oscillator, switch to the internal oscillator du ring flash write or erase operations. the external oscillato r can continue to run, and th e cpu can switch back to the external oscillator after the flash operation has completed. additional flash recommendations and example code can be found in ?an201: writing to flash from firmware", available from th e silicon laboratories website.
62 rev. 1.0 10.5. flash control registers register 10.1. psctl: program store control bit 7 6 5 4 3 2 1 0 name reserved psee pswe ty pe r rw rw r e s e t00000000 sfr address: 0x8f table 10.2. psctl register bit descriptions bit name function 7:2 reserved must write reset value. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program mem - ory to be erased. if this bit is logic 1 and f lash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruct ion will erase the entire page that contains the location addressed by the movx instructio n. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of dat a to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash me mory.
rev. 1.0 63 register 10.2. flkey: flash lock and key bit 7 6 5 4 3 2 1 0 name flkey ty pe rw r e s e t00000000 sfr address: 0xb7 table 10.3. flkey register bit descriptions bit name function 7:0 flkey flash lock and key register. write: this register provides a lock and key function for flash er asures and writes. flash writes and erases are enabled by writing 0xa5 followed by 0x f1 to the flkey register. flash writes and erases are automatically disabled af ter the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disabled, the flash will be permanently locked from writes or erasures until the next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases are disabled until the next reset.
64 rev. 1.0
rev. 1.0 64 11. device identification and unique identifier the c8051f85x/86x has sfrs that identify the device family, derivative, and revision. these sfrs can be read by firmware at runtime to determine the capabilities of the mcu that is execut ing code. this allows the same firmware image to run on mcus with different memory sizes and peripherals, and dynamically change functionality to suit the capabilities of that mcu. in addition to the device identification registers, a 32-bit unique identifier (uid) is pre-programmed into all revision c and later devices. the uid resides in t he last four bytes of xram (c8051f850/1/3/4 and c8051f860/1/3/4) or ram (c8051f852/5 and c8051f8 62/5). for devices with th e uid in ram, the uid can be read by firmware using indirect data access es. for devices with the uid in xram, the uid can be read by firmware using movx instru ctions. the uid can also be read through the debug port for all devices. firmware can overwrite th e uid during normal operat ion, and the bytes in me mory will be automatically reinitialized with the uid value after any device reset. firmwa re using this area of memory should always initialize the memory to a known valu e, as any previous data stored at these locations will be overwritten and not retained through a reset. table 11.1. uid implementation information device memory segment addresses c8051f850 c8 051f851 c8051f853 c8051f854 c8051f860 c8051f861 c8051f863 c8051f864 xram (msb) 0x00ff, 0x00fe, 0x00fd, 0x00fc (lsb) c8051f852 c8051f855 c8051f862 c8051f865 ram (indirect) (msb) 0xff, 0xfe, 0xfd, 0xfc (lsb)
65 rev. 1.0 11.1. device identi fication registers register 11.1. deviceid: device identification bit 7 6 5 4 3 2 1 0 name deviceid ty pe r r e s e t00110000 sfr address: 0xb5 table 11.2. deviceid register bit descriptions bit name function 7:0 deviceid device id. this read-only register returns the 8 -bit device id: 0x30 (c8051f85x/86x).
rev. 1.0 66 register 11.2. derivid: derivative identification bit 7 6 5 4 3 2 1 0 name derivid ty pe r r e s e txxxxxxxx sfr address: 0xad table 11.3. derivid register bit descriptions bit name function 7:0 derivid derivative id. this read-only register returns the 8-bit derivative id, which can be used by firmware to identify which device in the product family th e code is executing on. the ?{r}? tag in the part numbers below indicates the device revision letter in the ordering code. 0xd0: c8051f850-{r}-gu 0xd1: c8051f851-{r}-gu 0xd2: c8051f852-{r}-gu 0xd3: c8051f853-{r}-gu 0xd4: c8051f854-{r}-gu 0xd5: c8051f855-{r}-gu 0xe0: c8051f860-{r}-gs 0xe1: c8051f861-{r}-gs 0xe2: c8051f862-{r}-gs 0xe3: c8051f863-{r}-gs 0xe4: c8051f864-{r}-gs 0xe5: c8051f865-{r}-gs 0xf0: c8051f850-{r}-gm 0xf1: c8051f851-{r}-gm 0xf2: c8051f852-{r}-gm 0xf3: c8051f853-{r}-gm 0xf4: c8051f854-{r}-gm 0xf5: c8051f855-{r}-gm
67 rev. 1.0 register 11.3. revid: revision identifcation bit 7 6 5 4 3 2 1 0 name revid ty pe r r e s e txxxxxxxx sfr address: 0xb6 table 11.4. revid register bit descriptions bit name function 7:0 revid revision id. this read-only register returns the 8-bit revision id. 00000000: revision a 00000001: revision b 00000010: revision c 00000011-11111111: reserved.
rev. 1.0 68 12. interrupts the c8051f85x/86x includes an extended interrupt system supporting multiple interrupt sources with two priority levels. the allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device . each interrupt source ha s one or more associated interrupt-pending flag(s) located in an sfr. when a pe ripheral or external source meets a valid interrupt condition, the associated interrup t-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instruct ion is complete, the cpu generates an lcall to a predetermined address to begin execution of an interrup t service routine (isr). each isr must end with an reti instruction, which re turns program execution to the next instru ction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as nor mal. the interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state. each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie and eie1). however, interrupts must first be globally enabled by setting the ea bit in the ie register to logic 1 before the individual interrupt enables are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction. 12.1. mcu interrupt sources and vectors the c8051f85x/86x mcus support interrupt sources for each peripheral on the device. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be ge nerated and the cpu will vector to the isr address associated with the interrupt-pending flag. mcu interrupt sources, associated vector addresses , priority order and control bits are summarized in table 12.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 12.1.1. interr upt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low p riority interrupt service routine can be preempted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 12.1. 12.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sam pled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interr upt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock
69 rev. 1.0 cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr comple tes, including the reti and following instruction. if more than one interrupt is pending when the cpu exits an isr, the cpu will service the next highest priority inte rrupt that is pending.
rev. 1.0 70 table 12.1. interrupt summary interrupt source interrupt vector priority order pending flags bit addressable? cleared by hw? enable flag reset 0x0000 to p none n/a n/a always enabled external interrupt 0 ( int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) external interrupt 1 ( int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) uart0 0x0023 4 ri (scon0.0) ti (scon0.1) y n es0 (ie.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) port match 0x0043 8 none n/a n/a emat (eie1.1) adc0 window compare 0x004b 9 adwint (adc0cn.3) y n ewadc0 (eie1.2) adc0 conversion complete 0x0053 10 adint (adc0cn.5) y n eadc0 (eie1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) covf (pca0pwm.6) y n epca0 (eie1.4) comparator0 0x0063 12 cpfif (cpt0cn.4) c prif (cpt0cn.5) n n ecp0 (eie1.5) comparator1 0x006b 13 cpfif (cpt1cn.4) c prif (cpt1cn.5) n n ecp1 (eie1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7)
71 rev. 1.0 12.2. interrupt control registers register 12.1. ie: interrupt enable bit 7 6 5 4 3 2 1 0 name ea espi0 et2 es0 et1 ex1 et0 ex0 t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xa8 (bit-addressable) table 12.2. ie register bit descriptions bit name function 7 ea enable all interrupts. globally enables/disables all interrupts and overrides individual interrupt mask settings. 0: disable all in te rrupt sources. 1: enable each interr up t according to its individual mask setting. 6 espi0 enable spi0 interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5 et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua r t0 interrupt. 3 et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti m er 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1 et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti m er 0 interrupt. 1: enable interrupt requests generated by the tf0 flag.
rev. 1.0 72 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. table 12.2. ie register bit descriptions bit name function
73 rev. 1.0 register 12.2. ip: interrupt priority bit 7 6 5 4 3 2 1 0 name reserved pspi0 pt2 ps0 pt1 px1 pt0 px0 t yper rwrwrwrwrwrwrw r e s e t10000000 sfr address: 0xb8 (bit-addressable) table 12.3. ip register bit descriptions bit name function 7 reserved must write reset value. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority lev el. 1: uart0 interrupt set to high priority lev el. 3 pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of th e external interr upt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. 1 pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of th e external interr upt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level.
rev. 1.0 74 register 12.3. eie1: extended interrupt enable 1 bit 7 6 5 4 3 2 1 0 name et3 ecp1 ecp0 epca0 eadc0 ewadc0 emat esmb0 t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xe6 table 12.4. eie1 register bit descriptions bit name function 7 et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the comparator 1 cprif or cpfif flags. 5 ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the comparator 0 cprif or cpfif flags. 4 epca0 enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupt s. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversi on complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the adint flag. 2 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (adwint). 1 emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port matc h interrupts. 1: enable interrupt requests generated by a port match.
75 rev. 1.0 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all sm b0 interrupts. 1: enable interrupt requests generated by smb0. table 12.4. eie1 register bit descriptions bit name function
rev. 1.0 76 register 12.4. eip1: extended interrupt priority 1 bit 7 6 5 4 3 2 1 0 name pt3 pcp1 pcp0 ppca0 padc0 pwadc0 pmat psmb0 t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xf3 table 12.5. eip1 register bit descriptions bit name function 7 pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. 6 pcp1 comparator1 (cp1) interrupt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 5 pcp0 comparator0 (cp0) interrupt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) in terrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete inte rr upt set to high priority level. 2 pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt se t to high priority level. 1 pmat port match interrupt priority control. this bit sets the priority of the port match event interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level.
77 rev. 1.0 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. table 12.5. eip1 register bit descriptions bit name function
rev. 1.0 76 13. power management and internal regulator all internal circuitry on the c8051f85x/86x devices draws power from the vdd supply pin. circuits with external connections (i/o pins, analog muxes) are powered directly from the vdd supply voltage, while most of the internal circuitry is supplied by an on-chip ldo regulator. the regulator output is fully internal to the device, and is available also as an adc inpu t or reference source for the comparators and adc. the devices support the standard 8051 power modes: idle and stop. for further power savings in stop mode, the internal ldo regulator may be disabled, shutting down the majority of the power nets on the device. although the c8051f85x/86x has idle and stop modes available, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers and serial buses, have their cl ocks gated off and draw little pow er when they are not in use. 13.1. power modes idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers are inacti ve, and the internal oscillator is st opped (analog periph erals remain in their selected states; the external oscillator is not affected). sinc e clocks are running in idle mode, power consumption is dependent upon the system clock frequen cy and the number of peripherals left in active mode before entering idle. stop mode consumes the l east power because the majori ty of the device is shut down with no clocks active. the powe r control register (pcon) is us ed to control the c8051f85x/86x's stop and idle power management modes. 13.1.1. idle mode setting the idle mode select bit (pcon.0) causes the ha rdware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is termin ated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instruction following the write of the idle bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruct ion that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructio ns that set the idle bit should be fo llowed by an instruction that has two or more opcode bytes, for example: // in ?c?: pco n |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal wa tchdog reset and thereby terminate the idle mode. this feat ure protects the system from an uni ntended permanent s hutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. this provides the opportunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an ex ternal stimulus to wake up the system.
77 rev. 1.0 13.1.2. stop mode setting the stop mode select bit (pcon.1) causes th e controller core to enter stop mode as soon as the instruction that sets the bit completes execution. before entering stop mode, the system clock must be sourced by the internal high-frequency oscillator. in st op mode the internal oscilla tor, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circ uit) may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an inte rnal reset and thereby te rminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. 13.2. ldo regulator c8051f85x/86x devices include an internal regulator that regulates the internal core and logic supply. under default conditio ns, the internal regulator will remain on wh en the device enters stop mode. this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the internal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin and a full power cycle of the device are the only methods of generating a reset. 13.3. power control registers register 13.1. pcon: power control bit 7 6 5 4 3 2 1 0 name gf stop idle t ype rw rw rw r e s e t00000000 sfr address: 0x87 table 13.1. pcon register bit descriptions bit name function 7:2 gf general purpose flags 5-0. these are general purpose flags for use under software control. 1 stop stop mode select. setting this bit will place the cip-51 in stop mode. this bit w ill always be read as 0. 0 idle idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0.
rev. 1.0 78 13.4. ldo cont rol registers register 13.2. reg0cn: voltage regulator control bit 7 6 5 4 3 2 1 0 name reserved stopcf reserved ty pe r rw r r e s e t00000000 sfr address: 0xc9 table 13.2. reg0cn register bit descriptions bit name function 7:4 reserved must write reset value. 3 stopcf stop mode configuration. this bit configures the regulator's behavior when the device enters stop mode. 0: regulator is still active in s top mode. any enabled rese t source will reset the device. 1: regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 2:0 reserved must write reset value.
79 rev. 1.0
rev. 1.0 79 14. analog-to-digital converter (adc0) the adc is a successive-approximation-register (sar ) adc with 12-, 10-, and 8-bit modes, integrated track-and-hold and a programmable window detector. these different modes allow the user to trade off speed for resolution. adc0 also has an autonomous low-power burst mode which can automatically enable adc0, capture and accumulate samples, then place adc0 in a low power shutdown mode without cpu intervention. it also has a 16-bit accumulator that can automatically oversample and average the adc results. the adc is fully configurab le under software control via several r egisters. the adc0 operates in single- ended mode and may be configured to measure different signals using the analog multiplexer. the voltage reference for the adc is selectable between internal and external reference sources. figure 14.1. adc0 functional block diagram adc0 p0 pins (8) p1 pins (8) sar analog to digital converter accumulator window compare sysclk clock divider less than greater than device ground agnd 0.5x ? 1x gain control / configuration adc0 vdd vref internal ldo 1.65 v / 2.4 v reference trigger selection adwint (window interrupt) sar clock temp sensor vdd gnd internal ldo input selection adbusy (on demand) timer 0 overflow timer 2 overflow timer 3 overflow cnvstr (external pin) adint (interrupt flag) reference selection
80 rev. 1.0 14.1. adc0 analog multiplexer adc0 on c8051f85x/86x has an analog multiplexer capable of selecting any pin on ports p0 and p1 (up to 16 total), the on-chip temperature sensor, the internal regulated supply, the vdd supply, or gnd. adc0 input channels are selected using the adc0mx register. table 14.1. adc0 input multiplexer channels adc0mx setting signal name qsop24 pin name qfn20 pin name soic16 pin name 00000 adc0.0 p0.0 p0.0 p0.0 00001 adc0.1 p0.1 p0.1 p0.1 00010 adc0.2 p0.2 p0.2 p0.2 00011 adc0.3 p0.3 p0.3 p0.3 00100 adc0.4 p0.4 p0.4 p0.4 00101 adc0.5 p0.5 p0.5 p0.5 00110 adc0.6 p0.6 p0.6 p0.6 00111 adc0.7 p0.7 p0.7 p0.7 01000 adc0.8 p1.0 p1.0 p1.0 01001 adc0.9 p1.1 p1.1 p1.1 01010 adc0.10 p1.2 p1.2 p1.2 01011 adc0.11 p1.3 p1.3 p1.3 01100 adc0.12 p1.4 p1.4 reserved 01101 adc0.13 p1.5 p1.5 reserved 01110 adc0.14 p1.6 p1.6 reserved 01111 adc0.15 p1.7 reserved reserved 10000 temp sensor internal temperature sensor 10001 ldo internal 1.8 v ldo output 10010 vdd vdd supply pin 10011 gnd gnd supply pin 10100-11111 none no connection
rev. 1.0 81 important note about adc0 input configuration: port pi ns selected as adc0 inpu ts should be configured as analog inputs, and should be skipped by the crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmdin and disable the digital driver (pnmdout = 0 and port latch = 1). to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip.
82 rev. 1.0 14.2. adc operation the adc is clocked by an adjustable conversion clock (sarclk). sarclk is a divided version of the selected system clock when burst mode is disabled (adbmen = 0), or a divided version of the high- frequency oscillator when burst mode is enabled (adbmen = 1). the clock divide value is determined by the adsc bits in the adc0cf register. in most ap plications, sarclk should be adjusted to operate as fast as possible, without exceeding the maximum electr ical specifications. the sarclk does not directly determine sampling times or sampling rates. 14.2.1. starting a conversion a conversion can be initiated in many ways, depending on the programmed states of the adc0 start of co nversion mode field (adcm) in register adc0cn0. conversions may be initiated by one of the following: 1. writing a 1 to the adbusy bit of register adc0cn0 (software-triggered) 2. a timer overflow (see the adc0cn0 regist er and the timer section for timer options) 3. a rising edge on the cnvstr input signal (external pin-triggered) writing a 1 to adbusy provides software contro l of adc0 whereby conversions are performed "on- demand". all other trigger sources occur autonomous to code execution. when the conversion is complete, the adc posts the result to its output register and sets the adc interrupt flag (adint). adint may be used to trigger a system interrupts, if enabled, or polled by firmware. during conversion, the adbusy bit is set to logic 1 an d reset to logic 0 when the conversion is complete. however, when polling for adc conversion completions, the adc0 interrupt flag (a dint) should be used instead of the adbusy bit. convert ed data is available in the adc0 dat a registers, adc0h:adc0l, when the conversion is complete. important note about using cnvstr: when the cnvstr input is used as the adc0 conversion source, the associated port pin should be skipped in the crossbar settings. 14.2.2. tracking modes each adc0 conversion must be preceded by a minimum tr acking time in order for the converted result to be accurate. the minimum tracking time is given in th e electrical specifications tables. the adtm bit in register adc0cn0 controls the adc0 track-and-hold mode. in its default state when burst mode is disabled, the adc0 input is continuously tracked, exc ept when a conversion is in progress. a conversion will begin immediately when the star t-of-conversion trigger occurs. when the adtm bit is logic 1, each conversion is preceded by a tracking period of 4 sar clocks (after the start-of-conversion signal) for any internal (non-cnvstr) conversion trigger source. when the cnvstr signal is used to initiate conversions with adtm se t to 1, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 14.2). setting adtm to 1 is primarily useful when amux settings are frequently changed and conversions are started using the adbusy bit.
rev. 1.0 83 figure 14.2. 10-bit adc track and conversi on example t iming (adbmen = 0) 14.2.3. burst mode burst mode is a power saving feature that allows a dc0 to remain in a low power state between conversions. when burst mode is enabled, adc0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or 64 samples using the internal low-power high-frequency osc illator, then re-enters a low power state. since the burst mode clock is independent of the sys tem clock, adc0 can perfo rm multiple conversions then enter a low power state within a single system cl ock cycle, even if the system clock is slow (e.g. 80 khz). burst mode is enabled by setting adbmen to logic 1. when in burst mode, aden controls the adc0 idle power state (i.e. the state adc0 enters when not tracki ng or performing conversion s). if aden is set to logic 0, adc0 is powered down after each burst. if aden is set to logic 1, adc0 remains enabled after each burst. on each convert start signal, adc0 is awak ened from its idle power state. if adc0 is powered down, it will automatically power up and wait the programmable power- up time controlled by the adpwr bits. otherwise, adc0 will start tracking and conver ting immediately. figure 14.3 shows an example of burst mode operation with a slow syst em clock and a repeat count of 4. when burst mode is enabled, a single convert start will initiate a numb er of conversions e qual to th e repeat count. when burst mode is disabled, a convert start is required to initiate each conversion. in both modes, the adc0 end of conversion interr upt flag (adint) will be set after ?r epeat count? conversions have been accumulated. similarly, the window comparator will not compare the resu lt to the greate r-than and less- than registers until ?repeat count? conversions have been accumulated. write '1' to adbusy, timer overflow adtm=1 track convert low power mode adtm=0 track or convert convert track low power or convert sar clocks sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr adtm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track adtm=0 track convert low power mode low power or convert 10 11 12 13 14 123456789 10 11 12 13 14 123456789 10 11 12 13 14 15 16 17 18
84 rev. 1.0 in burst mode, tracking is determined by the sett ings in adpwr and adtk. se ttling time requirements may need adjustment in some applications. refer to ?14.2.4. settling time requirements? on page 84 for more details. notes: ?? setting adtm to 1 will insert an additional 4 sar clocks of tracking before each conversion, regardless of the settings of adpwr and adtk. ?? when using burst mode, care must be taken to issue a convert start signal no faster than once every four sysclk periods. this includes external convert start signals. the adc will ignore convert start signals which arrive before a burst is finished. figure 14.3. burst mode tracking example with repeat count set to 4 14.2.4. settling time requirements a minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. this tracking time is determined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that when adtm is set to 1, four sar clocks are us ed for tracking at the start of every conversion. large external source impedance will increase the required tracking time. figure 14.4 shows the equivalent adc0 input circui t. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 14.1. when measuring any internal source, r total reduces to r mux . see the electrical specification tables fo r adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 14.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. convert start adtm = 1 aden = 0 powered down powered down system clock t 4 c power-up and track t c t c t c power-up and track t c.. adtm = 0 aden = 0 powered down powered down c power-up and track t c t c t c power-up and track t c.. adpwr t = tracking set by adtk t4 = tracking set by adtm (4 sar clocks) c = converting adtk t 4 t 4 t 4 t 2 n sa ------ - ?? ?? r total c sample
rev. 1.0 85 n is the adc resolution in bits (8/10/12). figure 14.4. adc0 equivalent input circuits 14.2.5. gain setting the adc has gain settings of 1x and 0.5x. in 1x mo de, the full scale reading of the adc is determined directly by vref. in 0.5x mode, the full-scale read ing of the adc occurs when the input voltage is vref x 2. the 0.5x gain setting ca n be useful to obtain a higher input voltage range when using a small vref voltage, or to measure input voltages that ar e between vref and vdd. gain settings for the adc are controlled by the adgn bit in register adc0cf. no te that even with a gain setting of 0.5, voltages above the supply rail cannot be measured directly by the adc. 14.3. 8-bit mode setting the adc08be bit in register adc0cf to 1 will put the adc in 8- bit mode. in 8-bit mode, only the 8 msbs of data are converted, allowing the conversion to be completed in fewer sar clock cycles than a 10-bit conversion. t he two lsbs of a conversion are always 00 in this mode , and the adc0l register will always read back 0x00. 14.4. 12-bit mode when configured for 12-bit conversi ons, the adc performs four 10-bit conversions using four different reference voltages and combines the results into a single 12-bit value. unlike simple averaging techniques, this method provides true 12-bit resoluti on of ac or dc input signals without depending on noise to provide dithering. the converter also empl oys a hardware dynamic element matching algorithm that reconfigures the largest elements of the internal dac for each of the four 10-bit conversions. this reconfiguration cancels any matching errors and ena bles the converter to achieve 12-bit linearity performance to go along with its 12-bit resolution. the 12-bit mode is enabled by setting the ad12be bit in register adc0ac to logic 1 and configuring the adc in burst mode (adbmen = 1) for four or more conversions. the conversion can be initiated using any of the conversion start sources, and the 12-bit result will appear in the adc0h and adc0l registers. since the 12-bit result is formed from a combination of four 10-bit results, the maximum output value is 4 x (1023) = 4092, rather than the max value of (2^12 ? 1) = 4095 that is produced by a traditional 12-bit converter. to further increase resolution, the burst mode repeat va lue may be configured to any multiple of four conversions. for example, if a re peat value of 16 is selected, th e adc0 output will be a 14-bit number (sum of four 12-bit numbers) with 13 effective bits of resolution. the ad12sm bit in register adc0tk controls when the ad c will track and sample th e input signal. when ad12sm is set to 1, the selected input signal will be tracked before the fi rst conversion of a set and held internally during all four conversions. when ad12sm is cleared to 0, the a dc will track and sample the selected input before each of the four conversions in a set. when maximum throughput (180-200 ksps) is r mux c sample rc input = r mux * c sample mux select p0.x note: the value of csample depends on the pga gain. see electrical specifications for details.
86 rev. 1.0 needed, it is recommended that ad12sm be set to 1 and adtk to 0x3f, and that the adc be placed in always-on mode (aden = 1). for sample rates under 180 ksps, or when accumula ting multiple samples, ad12sm should normally be cleared to 0, and ad tk should be configured to provide the appropriate settling time for the subsequent conversions. 14.5. power considerations the adc has several power-saving features whic h can help the user optimize power consumption according to the needs of the applicat ion. the most efficient way to use the adc for slower sample rates is by using burst mode. burst mode dynamically controls power to the adc and (if used) the internal voltage reference. by completely powering off these circuits when the adc is not tracking or converting, the average supply current required for lowe r sampling rates is re duced significantly. the adc also provides low power optio ns that allow reduction in operating current when operating at low sar clock frequencies or with longer tracking times. the internal common-mode buffer can be configured for low power mode by se tting the adlpm bit in adc0pwr to 1. two other fields in the adc0pwr register (adbias and admxlp) may be used together to adjust the power consumed by the adc and its multiplexer and reference buffers, respectively. in general, these options are used together, when operating with a sar conversion clock frequency of 4 mhz. table 14.2. adc0 optimal power configuration (8- and 10-bit mode) required throughput reference source mode configuration sar clock speed other register field settings 325-800 ksps any always-on (a den = 1 adbmen = 0) 12.25 mhz (adsc = 1) adc0pwr = 0x40 adc0tk = n/a adrpt = 0 0-325 ksps external burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 0 250-325 ksps internal burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 0 200-250 ksps internal always-on (aden = 1 adbmen = 0) 4.08 mhz (adsc = 5) adc0pwr = 0xf0 adc0tk = n/a adrpt = 0 0-200 ksps internal burst mode (aden = 0 adbmen = 1) 4.08 mhz (adsc = 5) adc0pwr = 0xf4 adc0tk = 0x34 adrpt = 0 notes: 1. for always-on configuration, adsc setti ngs assume sysclk is the internal 24.5 mhz high-frequency oscillator. adj ust adsc as needed if using a different source for sysclk. 2. adrpt reflects the minimum setting for this bit field. when using the adc in burst mode, up to 64 samples may be auto-accumulated per conversion start by adjusting adrpt.
rev. 1.0 87 for applications where burst mode is used to automati cally accumulate multiple results, additional supply current savings can be realized. the length of time t he adc is active during each burst contains power-up time at the beginning of the burst as well as the conv ersion time required for each conversion in the burst. the power-on time is only required at the beginning of each burst. when compared with single-sample bursts to collect the same number of conversions, mult i-sample bursts will consume significantly less power. for example, performing an eight-cycle burst of 10-bt conversions consumes about 61% of the power required to per form those same eight samples in single- cycle bursts. for 12-bit conversions, an eight-cycle burst results in about 85% of the equiva lent single-cycle bursts. figure 14.5 shows this relationship for the diff erent burst cycle lengths. see the electrical characteristics chapter for details on power consumption and the maximum clock frequencies allowed in each mode. table 14.3. adc0 optimal power configuration (12-bit mode) required throughput reference source mode configuration sar clock speed other register field settings 180-200 ksps any always -on + burst mode (aden = 1 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x40 adc0tk = 0xbf adrpt = 1 125-180 ksps any always-on + burst mode (aden = 1 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x40 adc0tk = 0x3a adrpt = 1 0-125 ksps external burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 1 50-125 ksps internal burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 1 0-50 ksps internal burst mode (aden = 0 adbmen = 1) 4.08 mhz (adsc = 5) adc0pwr = 0xf4 adc0tk = 0x34 adrpt = 1 note: adrpt reflects the minimum setting for this bit field. when using the adc in burst mode, up to 64 samples may be auto-accumulated per conversion trigger by adjusting adrpt.
88 rev. 1.0 figure 14.5. burst mode accumulation power savings 14.6. output code formatting the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the adsjst field. when the repeat count is set to 1 in 10-bit mode, conversion codes are represented as 10-bit unsigned integers. inputs ar e measured from 0 to vref x 1023/1024. example codes are shown below for both right-justified and left -justified data. unused bits in the adc0h and adc0l registers are set to 0. when the repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions performed and is updated after the last co nversion in the series is finished. sets of 4, 8, 16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. the repeat count can be selected using the adrpt bits in the adc0ac register. when a repeat count is higher than 1, the adc output must be right-justified (adsjst = 0xx); unused bits in the adc0h and adc0l registers are set to 0. the example below shows the ri ght-justified result for various input voltages and repeat counts. notice that accumulating 2 n samples is equivalent to left-shifting by n bit positions when all samples returned from the adc have the same value. input voltage right-justified adc0h:adc0l (adsjst = 000) left-justified adc0h:adc0l (adsjst = 100) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage repeat count = 4 repeat count = 16 repeat count = 64 v ref x 1023/1024 0x0ffc 0x3ff0 0xffc0 v ref x 512/1024 0x0800 0x2000 0x8000 v ref x 511/1024 0x07fc 0x1ff0 0x7fc0 0 0x0000 0x0000 0x0000 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 1 2 4 8 16 32 64 average current compared to single r cycle number of cycles accumulated in burst 10r bit burst mode power 80% 82% 84% 86% 88% 90% 92% 94% 96% 98% 100% 124816 average current compared to singler cycle number of cycles accumulated in burst 12rbit burst mode power
rev. 1.0 89 the adsjst bits can be used to format the contents of the 16-bit accumulator. the accumulated result can be shifted right by 1, 2, or 3 bit positions. base d on the principles of oversampling and averaging, the effective adc resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4. the example below shows how to increase the effective adc resolution by 1, 2, and 3 bits to obtain an effective adc resolution of 11-bit, 12-bit, or 13-bit respectively wi thout cpu intervention. 14.7. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user- programmed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving c ode space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (adwint in register adc0cn0) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison values. the window detector flag can be programmed to indicate when measured data is inside or outside of the user-p rogrammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. 14.7.1. window detector in single-ended mode figure 14.6 shows two example window comparisons for right-justified data, with adc0l th:adc0ltl = 0x0080 (128d) and adc0gth: adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left exam ple, an adwint interrupt will be gene rated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080 ). in the right example, and ad wint interrupt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 14.7 shows an example using left- justified data with the sa me comparison values. input voltage repeat count = 4 shift right = 1 11-bit result repeat count = 16 shift right = 2 12-bit result repeat count = 64 shift right = 3 13-bit result v ref x 1023/1024 0x07f7 0x0ffc 0x1ff8 v ref x 512/1024 0x0400 0x0800 0x1000 v ref x 511/1024 0x03fe 0x04fc 0x0ff8 0 0x0000 0x0000 0x0000
90 rev. 1.0 figure 14.6. adc window compare example: right-justified single-ended data figure 14.7. adc window compare example: lef t-justified single-ended data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint=1 adwint not affected adwint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint not affected adwint=1 adwint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint=1 adwint not affected adwint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint not affected adwint=1 adwint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
rev. 1.0 91 14.8. voltage and gr ound reference options the voltage reference multiplexer is configurable to use an externally connected voltage reference, the internal voltage reference, or one of two power su pply voltages. the ground reference mux allows the ground reference for adc0 to be selected between the ground pin (gnd) or a port pin dedicated to analog ground (agnd). the voltage and ground reference options ar e configured using the ref0cn register. important note about the vref and agnd inputs: port pins are used as the external vref and agnd inputs. when using an external voltage reference, vref should be configured as an analog input and skipped by the digital crossbar. when using agnd as the ground reference to adc0, agnd should be configured as an analog input and skipped by the digital crossbar. 14.8.1. external vo ltage reference to use an external voltage reference, refsl should be se t to 00. bypass capacitors should be added as recommended by the manufacturer of the external volt age reference. if the manufacturer does not provide recommendations, a 4.7uf in parallel with a 0.1uf capacitor is recommended. 14.8.2. internal vo ltage reference for applications requiring the maximum number of port i/ o pins, or very short vref turn-on time, the high- speed reference will be the best internal reference optio n to choose. the internal reference is selected by setting refsl to 11. when selected, the internal refe rence will be automatically enabled/disabled on an as-needed basis by the adc. the reference can be se t to one of two voltage values: 1.65 v or 2.4 v, depending on the value of the ireflvl bit. for applications with a non-varying power supply voltag e, using the power supply as the voltage reference can provide the adc with added dynamic range at the co st of reduced power supply noise rejection. to use the external supply pin (vdd) or the 1.8 v regulated digital supply voltage as the reference source, refsl should be set to 01 or 10, respectively. internal reference sources are not routed to the vref pin, and do not require external capacitors. the electrical specifications tables detail sar clock an d throughput limitations for each reference source. 14.8.3. analog ground reference to prevent ground noise generated by switching dig ital logic from affecting sensitive analog measurements, a separate analog ground reference op tion is available. when enabled, the ground reference for the adc during both the tracking/sam pling and the conversion periods is taken from the agnd pin. any external sensors sampled by the a dc should be referenced to the agnd pin. if an external voltage reference is used, the agnd pin sh ould be connected to the ground of the external reference and its associated decoupling capacitor. the separate analog ground reference option is enabled by setting gndsl to 1. note that when samplin g the internal temperature sensor, the internal chip ground is always used for the sampling operation, rega rdless of the setting of the gndsl bit. similarly, whenever the internal 1.65 v high-s peed reference is selected, the intern al chip ground is always used during the conversion period, regardless of the setting of the gndsl bit.
92 rev. 1.0 14.9. temperature sensor an on-chip temperature sensor is included, which c an be directly accessed via the adc multiplexer in single-ended configuration. to use the adc to me asure the temperature sensor, the adc mux channel should select the temperature sensor. the temperature sensor transfer function is shown in figure 14.8. the output voltage (v temp ) is the positive adc input when the adc multiplexer is set correctly. the tempe bit in register ref0cn enables/disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance state and any adc measurements performed on the sensor will result in meaningless data. refer to the electrical specificat ion tables for the slope and offset parameters of the temperature sensor. figure 14.8. temperature sensor transfer function 14.9.1. calibration the uncalibrated temperature sensor output is extr eme ly linear and suitable for relative temperature measurements. for absolute temperature measurements , offset and/or gain calibration is recommended. typically a 1-point (offset) calibra tion includes the following steps: 1. control/measure the ambient temperat ure (this temperature must be known). 2. power the device, and delay for a few seconds to allow for self-heating. 3. perform an adc conversion with the te mperature sensor selected as the adc input. 4. calculate the offset characteristics, and st ore this value in non-vol atile memory for use with subsequent temperature sensor measurements. temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope
rev. 1.0 93 14.10. adc control registers register 14.1. adc0cn0: adc0 control 0 bit 7 6 5 4 3 2 1 0 name aden adbmen adint adbusy adwint adcm t ype rw rw rw rw rw rw r e s e t00000000 sfr address: 0xe8 (bit-addressable) table 14.4. adc0cn0 register bit descriptions bit name function 7 aden enable. 0: adc0 disabled (low-power shutdown). 1: adc0 enabled (active and re ady for data conversions). 6 adbmen burst mode enable. 0: adc0 burst mode disabled. 1: adc0 burst mo de enabled. 5 adint conversion complete interrupt flag. set by hardware upon completion of a data conversion (adbmen=0), or a burst of con - versions (adbmen=1). can trigger an interrupt. must be cleared by software. 4 adbusy adc busy. writing 1 to this bit initiates an adc conv er sion when adc0cm = 000. this bit should not be polled to indicate when a conversion is complete. instead, the adint bit should be used when polling for conversion completion. 3 adwint window compare interrupt flag. set by hardware when the contents of adc0 h:adc0l fall within the window s pecified by adc0gth:adc0gtl and adc0lth:adc0ltl. can trigger an in terrupt. must be cleared by software. 2:0 adcm start of conversion mode select. specifies the adc0 start of conversion so ur ce. all remaining bit combinations are reserved. 000: adc0 conversion initiat e d on write of 1 to adbusy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 3. 100: adc0 conversion initiated on rising edge of cnvstr. 101-111: reserved.
94 rev. 1.0 register 14.2. adc0cn1: adc0 control 1 bit 7 6 5 4 3 2 1 0 name reserved adcmbe ty pe r rw r e s e t00000000 sfr address: 0xb2 table 14.5. adc0cn1 register bit descriptions bit name function 7:1 reserved must write reset value. 0 adcmbe common mode buffer enable. 0: disable the common mode buffer. this setting should be used only if the tracking time o f the signal is greater than 1.5 us. 1: enable the common mode buff er . this setting should be us ed in most cases, and will give the best dynamic adc performance. the common mode buffer must be enabled if signal tracking time is less than or equal to 1.5 us.
rev. 1.0 95 register 14.3. adc0cf: adc0 configuration bit 7 6 5 4 3 2 1 0 name adsc ad8be adtm adgn t ype rw rw rw rw r e s e t11111000 sfr address: 0xbc table 14.6. adc0cf register bit descriptions bit name function 7:3 adsc sar clock divider. this field sets the adc clock divider value. it sh ould be configured to be as close to the maximum sar clock speed as the datasheet will allow. the sar clock frequency is given by the following equation: f adcclk is equal to the selected sysclk when adbmen is 0 and the high-frequency oscillator when adbmen is 1. 2 ad8be 8-bit mode enable. 0: adc0 operates in 10-bit or 12-bit mode (normal operation). 1: adc0 operates in 8-bit mode. 1 adtm track mode. selects between normal or delayed tracking modes. 0: normal track mode. when adc0 is enabled, conversion begins immediately following the start-of-conversion signal. 1: delayed track mode. when adc0 is enab led, conversion begins 4 sar clock cycles following the start-of-conversion signal. the adc is allowed to track during this time. 0 adgn gain control. 0: the on-chip pga gain is 0.5. 1: the on-chip pga gain is 1. f clksar f adcclk adsc 1 + ------------------------ - =
96 rev. 1.0 register 14.4. adc0ac: adc0 accumulator configuration bit 7 6 5 4 3 2 1 0 name ad12be adae adsjst adrpt t ype rw rw rw rw r e s e t00000000 sfr address: 0xb3 table 14.7. adc0ac register bit descriptions bit name function 7 ad12be 12-bit mode enable. enables 12-bit mode. in 12-bit mode, the adc throughput is reduced by a factor of 4. 0: 12-bit mode disabled. 1: 12-bit mode enabled. 6 adae accumulate enable. enables multiple conversions to be accumulated when burst mode is disabled. 0: adc0h:adc0l contain the result of the la test conversion when burst mode is dis - abled. 1: adc0h:adc0l contain the accumulated conv e rsion results when burst mode is dis - abled. software must write 0x0000 to adc0h:adc0l to clear the accumulated result. 5:3 adsjst accumulator shift and justify. specifies the format of data read from a dc0h:adc0l. all remain ing bit combinations are reserved. 000: right justified. no shif ting applied. 001: right justified. shifted right by 1 bit. 010: right justified. shifted right by 2 bits. 011: right justified. shifted right by 3 bits. 100: left justified. no shifting applied. 101-111: reserved. 2:0 adrpt repeat count. selects the number of conversions to perform and accumulate in burst mode. this bit field must be set to 000 if burst mode is disabled. 000: perform and accumulate 1 conversion (not used in 12-bit mode). 001: perform and accumulate 4 conversions (1 conversion in 12-bit mode). 010: perform and accumulate 8 conversions (2 conversions in 12-bit mode). 011: perform and accumulate 16 conversions (4 conversions in 12-bit mode). 100: perform and accumulate 32 conver sions (8 conversions in 12-bit mode). 101: perform and accumulate 64 conver sions (1 6 conversions in 12-bit mode). 110-111: reserved.
rev. 1.0 97 register 14.5. adc0pwr: adc0 power control bit 7 6 5 4 3 2 1 0 name adbias admxlp adlpm adpwr t ype rw rw rw rw r e s e t00001111 sfr address: 0xdf table 14.8. adc0pwr register bit descriptions bit name function 7:6 adbias bias power select. this field can be used to adjust the adc' s power consumption based on the conversion speed. higher bias currents allow for faster conversion times. 00: select bias current mode 0. recommended to use modes 1, 2, or 3. 01: select bias current mode 1 (sarclk <= 16 mhz). 10: select bias current mode 2. 11: select bias current mode 3 (sarclk <= 4 mhz). 5 admxlp mux and reference low power mode enable. enables low power mode operation for the multiplexer and voltage reference buffers. 0: low power mode disabled. 1: low power mode enabled (sar clock < 4 mhz). 4 adlpm low power mode enable. this bit can be used to reduce power to the adc's internal common mode buffer. it can b e set to 1 to reduce power when tracking times in the application are longer (slower sample rates). 0: disable low power mode. 1: enable low power mode (requires extended tracking time). 3:0 adpwr burst mode power up time. this field sets the time delay allowed for t he adc to po wer up from a low power state. when adtm is set, an additional 4 sarclks are added to this time. t pwrtime 8adpwr f hfosc ------------------------------ =
98 rev. 1.0 register 14.6. adc0tk: adc0 burst mode track time bit 7 6 5 4 3 2 1 0 name ad12sm reserved adtk t ype rw rw rw r e s e t00011110 sfr address: 0xb9 table 14.9. adc0tk register bit descriptions bit name function 7 ad12sm 12-bit sampling mode. this bit controls the way that the adc sample s the in put when in 12-bit mode. when the adc is configured for multiple 12-bit conversions in burst mode, the ad12sm bit should be cleared to 0. 0: the adc will re-track and sa mple the input four times during a 12-bit conversion. 1: the adc will sample the input once at the beginning of each 12-bit conversion. the adtk field can be set to 63 to maximize throughput. 6 reserved must write reset value. 5:0 adtk burst mode tracking time. this field sets the time delay between co nsecutive co nversions performed in burst mode. when adtm is set, an additio nal 4 sarclks are added to this time. the burst mode track delay is not inserted prior to the first conversion. the required trac king time for the first conversion should be defined with the adpwr field. t bmtk 64 adtk ? f hfosc ---------------------------- =
rev. 1.0 99 register 14.7. adc0h: adc0 data word high byte bit 7 6 5 4 3 2 1 0 name adc0h ty pe rw r e s e t00000000 sfr address: 0xbe table 14.10. adc0h register bit descriptions bit name function 7:0 adc0h data word high byte. when read, this register returns the most significant byte of the 16-bit adc0 accumulator for matted according to the settings in adsjst . the register may also be written to set the upper byte of the 16-bit adc0 accumulator. note: if accumulator shifting is enabled, the most significant bits of the value read will be zeros. this register should not be written when the sync bit is set to 1.
100 rev. 1.0 register 14.8. adc0l: adc0 data word low byte bit 7 6 5 4 3 2 1 0 name adc0l ty pe rw r e s e t00000000 sfr address: 0xbd table 14.11. adc0l register bit descriptions bit name function 7:0 adc0l data word low byte. when read, this register returns the least significan t byte of the 16-bit adc0 accumula - tor, formatted acco rding to t he settings in adsjst. the register may also be written, to set the lower byte of the 16-bit adc0 accumulator. note: if accumulator shifting is enabled, the most significant bits of the value read will be zeros. this register should not be written when the sync bit is set to 1.
rev. 1.0 101 register 14.9. adc0gth: adc0 greater-than high byte bit 7 6 5 4 3 2 1 0 name adc0gth ty pe rw r e s e t11111111 sfr address: 0xc4 table 14.12. adc0gth register bit descriptions bit name function 7:0 adc0gth greater-than high byte. most significant byte of the 16-bit greater-than window compare register.
102 rev. 1.0 register 14.10. adc0gtl: adc0 greater-than low byte bit 7 6 5 4 3 2 1 0 name adc0gtl ty pe rw r e s e t11111111 sfr address: 0xc3 table 14.13. adc0gtl register bit descriptions bit name function 7:0 adc0gtl greater-than low byte. least significant byte of the 16-bit gr eater-than window compare register. note: in 8-bit mode, this register should be set to 0x00.
rev. 1.0 103 register 14.11. adc0lth: adc0 less-than high byte bit 7 6 5 4 3 2 1 0 name adc0lth ty pe rw r e s e t00000000 sfr address: 0xc6 table 14.14. adc0lth register bit descriptions bit name function 7:0 adc0lth less-than high byte. most significant byte of the 16-bit less-than window compare register.
104 rev. 1.0 register 14.12. adc0ltl: adc0 less-than low byte bit 7 6 5 4 3 2 1 0 name adc0ltl ty pe rw r e s e t00000000 sfr address: 0xc5 table 14.15. adc0ltl register bit descriptions bit name function 7:0 adc0ltl less-than low byte. least significant byte of the 16-bit le ss-than window compare register. note: in 8-bit mode, this register should be set to 0x00.
rev. 1.0 105 register 14.13. adc0mx: adc0 multiplexer selection bit 7 6 5 4 3 2 1 0 name reserved adc0mx ty pe r rw r e s e t00011111 sfr address: 0xbb table 14.16. adc0mx register bit descriptions bit name function 7:5 reserved must write reset value. 4:0 adc0mx amux0 positive input selection. selects the positive input channel for adc0. fo r reserved bit comb inations, no input is selected. 00000: adc0.0 00001: adc0.1 00010: adc0.2 00011: adc0.3 00100: adc0.4 00101: adc0.5 00110: adc0.6 00111: adc0.7 01000: adc0.8 01001: adc0.9 01010: adc0.10 01011: adc0.11 01100: adc0.12 01101: adc0.13 01110: adc0.14 01111: adc0.15 10000: temperature sensor. 10001: internal ldo regulator output. 10010: vdd 10011: gnd 10100-11111: reserved.
106 rev. 1.0 register 14.14. ref0cn: voltage reference control bit 7 6 5 4 3 2 1 0 name ireflvl reserved gnds l refsl tempe reserved t y p er wrr wr wr w r r e s e t00011000 sfr address: 0xd1 table 14.17. ref0cn register bit descriptions bit name function 7 ireflvl internal voltage reference level. sets the voltage level for the internal reference source. 0: the internal reference operates at 1.65 v nominal. 1: the internal reference operates at 2.4 v nominal. 6 reserved must write reset value. 5 gndsl analog ground reference. selects the adc0 ground reference. 0: the adc0 ground reference is the gnd pin. 1: the adc0 ground reference is the agnd pin. 4:3 refsl voltage reference select. selects the adc0 voltage reference. 00: the adc0 voltage reference is the vref pin. 01: the adc0 voltage reference is the vdd pin. 10: the adc0 voltage reference is the internal 1.8 v digital supply voltage. 11: the adc0 voltage reference is the internal voltage reference. 2 tempe temperature sensor enable. enables/disables the internal temperature sensor. 0: temperature sensor disabled. 1: temperature sensor enabled. 1:0 reserved must write reset value.
rev. 1.0 107
108 rev. 1.0
rev. 1.0 106 15. cip-51 microcontroller core the c8051f85x/86x uses the cip-51 microcontroller. the cip-51 is fully comp atible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the mcu family has a superset of all the peripherals includ ed with a standard 8051. the cip-51 also includes on- chip debug hardware and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system so lution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 15.1 for a block diagram). the cip-51 includes the following features: 15.1. performance the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. the cip-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. figure 15.1. cip-51 block diagram with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 ?? fully compatible with mc s-51 instruction set ?? 25 mips peak throughput with 25 mhz clock ?? 0 to 25 mhz clock frequency ?? extended interrupt handler ?? reset input ?? power management modes ?? on-chip debug logic ?? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
107 rev. 1.0 15.2. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon labs 2-wire deve lopment interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. this method of on-chip debugging is complete ly non-intrusive, requiri ng no ram, stack, timers, or other on-chip resources. the cip-51 is supported by development tools from silicon labs and third part y vendors. silicon labs provides an integrated development environment (ide ) including editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-system device programming and debugging. third party macro assemblers and c compilers are also available. 15.3. instruction set the instruction set of the cip-51 system controlle r is fully compatible wit h the standard mcs-51? instruction set. standard 8051 development tools can be used to develop software for the cip-51. all cip- 51 instructions are the binary and functional equiva lent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, instruction timing is di fferent than that of the standard 8051. 15.3.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as oppo sed to when the branch is taken. table 15.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. number of instructions 26 50 5 14 7 3 1 2 1
rev. 1.0 108 table 15.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3
109 rev. 1.0 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 table 15.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
rev. 1.0 110 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 table 15.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
111 rev. 1.0 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 15.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (twos complement) offset relative to the first byte of the following in struction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00?0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall and ajmp . the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall and lj mp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 1.0 112 15.4. cpu core registers register 15.1. dpl: data pointer low bit 7 6 5 4 3 2 1 0 name dpl ty pe rw r e s e t00000000 sfr address: 0x82 table 15.2. dpl register bit descriptions bit name function 7:0 dpl data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed flash memory or xram.
113 rev. 1.0 register 15.2. dph: data pointer high bit 7 6 5 4 3 2 1 0 name dph ty pe rw r e s e t00000000 sfr address: 0x83 table 15.3. dph register bit descriptions bit name function 7:0 dph data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed flash memory or xram.
rev. 1.0 114 register 15.3. sp: stack pointer bit 7 6 5 4 3 2 1 0 name sp ty pe rw r e s e t00000111 sfr address: 0x81 table 15.4. sp register bit descriptions bit name function 7:0 sp stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre - mented before every push operation. the sp r egister defaults to 0x07 after reset.
115 rev. 1.0 register 15.4. acc: accumulator bit 7 6 5 4 3 2 1 0 name acc ty pe rw r e s e t00000000 sfr address: 0xe0 (bit-addressable) table 15.5. acc register bit descriptions bit name function 7:0 acc accumulator. this register is the accumulator for arithmetic operations.
rev. 1.0 116 register 15.5. b: b register bit 7 6 5 4 3 2 1 0 name b ty pe rw r e s e t00000000 sfr address: 0xf0 (bit-addressable) table 15.6. b register bit descriptions bit name function 7:0 b b register. this register serves as a second accumu lator for certain arithmetic operations.
117 rev. 1.0 register 15.6. psw: program status word bit 7 6 5 4 3 2 1 0 name cy ac f0 rs ov f1 parity t ype rw rw rw rw rw rw r r e s e t00000000 sfr address: 0xd0 (bit-addressable) table 15.7. psw register bit descriptions bit name function 7 cy carry flag. this bit is set when the last arithmetic operatio n r esulted in a carry (addition) or a borrow (subtraction). it is cleared to logic 0 by all other arithmetic operations. 6 ac auxiliary carry flag. this bit is set when the last ar ithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith - metic operations. 5 f0 user flag 0. this is a bit-addressable, general purpose flag for use under software control. 4:3 rs register bank select. these bits select which register ba nk is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2 ov overflow flag. this bit is set to 1 under the following circumstances: 1. an add, addc, or subb instruct ion caus es a sign-change overflow. 2. a mul instruction results in an overflow (result is greater than 255). 3. a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, ad dc, subb, mul, and div instructions in all other cases. 1 f1 user flag 1. this is a bit-addressable, general purpose flag for use under software control. 0 parity parity flag. this bit is set to logic 1 if the sum of the ei ght bit s in the accumulator is odd and cleared if the sum is even.
rev. 1.0 118 16. clock sources and selection (hfosc0, lfosc0, and extclk) the c8051f85x/86x devices can be cl ocked from the internal low power 24.5 mhz oscillator, the internal low-frequency 80 khz oscillator, or an external cmos clock signal at the extclk pin. an adjustable clock divider allows the selected clock source to be post-scaled by powers of 2, up to a factor of 128. by default, the system clock comes up as the 24.5 mhz oscillator divided by 8. figure 16.1. clocking options 16.1. programmable high-frequency oscillator all c8051f85x/86x devices include a programmable internal hi gh-frequency oscillator that defaults as the system clock after a system reset. the oscillator is automat ically enabled when it is requested. the internal oscillator period can be adjusted via the oscicl register. on c8051f85x/86x devices, oscicl is factory calibrated to obtain a 24.5 mhz base frequency. 16.2. programmable low-frequency oscillator a programmable low-fr equency internal os cillator is also included. t he low-frequency oscillator is calibrated to a nominal frequency of 80 khz. a divider at the oscillator output is capable of dividing the output clock of the module by 1, 2, 4, or 8, using the oscld bits in th e osclcn register. additionally, the osclf bits can be used to coarsely ad just the oscillator?s output frequency. 16.2.1. calibrating the internal l-f oscillator timer 3 includes a capture f unction that can be used to capture the oscillator frequency, when running from a known time base. when timer 3 is configured for l-f oscillator capture mode, a rising edge of the low- frequency oscillator?s output will caus e a capture event on the corresp onding timer. as a capture event occurs, the current timer value (tmr3h:tmr3l) is copied into the timer reload registers (tmr3rlh:tmr3rll). by recording the difference be tween two successive time r capture values, the low- frequency oscillator?s period can be calculated. the osclf bits can then be adjusted to produce the desired oscillator frequency. clock control programmable divider: 1, 2, 4...128 sysclk low frequency 80 khz oscillator high frequency 24.5 mhz oscillator external clock input (extclk) to core and peripherals
119 rev. 1.0 16.3. external clock an external cmos clock source is also supported by the c8051f85x/86x family. the extclk pin on the device serves as the external clock input when runn ing in this mode. the extcl k input may also be used to clock some of the digital peri pherals (e.g., timers, pca, etc.) while sysclk runs from one of the internal oscillator sources. when not selected as the sysclk source , the extclk input is always re- synchronized to sysclk. 16.4. clock selection the clksel register is used to select the clock s ource for the syst em. the clksl field selects which oscillator source is used as the system clock, wh ile clkdiv contro ls the programmable divider. clksl must be set to 01b for the system cl ock to run from the external oscilla tor; however the external oscillator may still clock certain peripherals (timers, pca) when the internal oscillator is selected as the system clock. in these cases, th e external oscillator source is synchr onized to the sysclk source. the system clock may be switched on-the-fly between any of the oscillator sources so long as the selected clock source is enabled and has settled, and clkdiv may be changed at any time. the internal high-frequency and low-frequency oscillators require little start-up ti me and may be selected as the system clock immediately following the register write which enables the os cillator. when selecting the extclk pin as a clock input source, the pin should be skipped in the crossbar and configured as a digital input. firmware should ensure that the extern al clock source is present or enable the missing clock detector before switching the clksl field.
rev. 1.0 120 16.5. high frequency osci llator control registers register 16.1. oscicl: high frequency oscillator calibration bit 7 6 5 4 3 2 1 0 name oscicl ty pe rw r e s e txxxxxxxx sfr address: 0xc7 table 16.1. oscicl register bit descriptions bit name function 7:0 oscicl oscillator calibration bits. these bits determine the intern al oscillator period. w hen se t to 00000000b, the oscillator operates at its fastest settin g. when set to 11111111b, the os cillator operates at its slow - est setting. the reset value is factory calib rated to genera te an internal oscillator fre - quency of 24.5 mhz.
121 rev. 1.0 16.6. low frequency osci llator control registers register 16.2. osclcn: low frequency oscillator control bit 7 6 5 4 3 2 1 0 name osclen osclrdy osclf oscld ty pe rw r rw rw r e s e t0 0xxxx0 0 sfr address: 0xb1 table 16.2. osclcn register bit descriptions bit name function 7 osclen internal l-f oscillator enable. this bit enables the internal low-frequency os cillato r. note that the low-frequency oscilla - tor is automatically enabled when the watchdog timer is active. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. 6 osclrdy internal l-f oscillator ready. 0: internal l-f oscillato r frequency not stabilized. 1: internal l-f oscilla tor frequenc y stabilized. 5:2 osclf internal l-f oscillator frequency control bits. fine-tune control bits for the internal l-f o scillator frequency . when set to 0000b, the l-f oscillator operates at its fastes t setting. when set to 1111b, the l-f oscillator operates at its slowest setting. the osclf bits should only be changed by firmware when the l-f oscillator is disabled (osclen = 0). 1:0 oscld internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected. note: osclrdy is only set back to 0 in the event of a device reset or a change to the oscld bits.
rev. 1.0 122 16.7. clock selecti on control registers register 16.3. clksel: clock select bit 7 6 5 4 3 2 1 0 name reserved clkdiv reserved clksl ty pe r rw r rw r e s e t00110000 sfr address: 0xa9 table 16.3. clksel register bit descriptions bit name function 7 reserved must write reset value. 6:4 clkdiv clock source divider. this field controls the divider applied to th e clock source selected by clksl. the output of this divider is the system clock (sysclk). 000: sysclk is equal to selected clock source divided by 1. 001: sysclk is equal to selected clock source divided by 2. 010: sysclk is equal to selected clock source divided by 4. 011: sysclk is equal to select ed clock source divided by 8. 100: sysclk is equal to selected clock source divided by 16. 101: sysclk is equal to selected clock source divided by 32. 110: sysclk is equal to select ed clock source divided by 64. 111: sysclk is equal to selected clock source divided by 128. 3:2 reserved must write reset value. 1:0 clksl clock source select. selects the system clock source. 00: clock derived from the inte rnal high-frequency osc illator. 01: clock derived from the external oscillator circuit. 10: clock derived from the inte rnal low -frequ ency oscillator. 11: reserved.
123 rev. 1.0
rev. 1.0 123 17. comparators (cmp0 and cmp1) c8051f85x/86x devices include two on-chip progra mmable voltage comparators, cmp0 and cmp1. the two comparators are functionally identical, but have different connectivity within the device. a functional block diagram is shown in figure 17.1. figure 17.1. comparator functional block diagram 17.1. system connectivity comparator inputs are routed to port i/o pins or internal signals using the comparator mux registers. the comparator?s synchronous and asynchronous outputs can optionally be routed to port i/o pins through the port i/o crossbar. the output of either comparator may also be configured to generate a system interrupt. cmp0 may also be used as a reset source, or as a trigger to k ill a pca output channel. the cmp0 inputs are selected in the cpt0mx regi ster, while cpt1mx selects the cmp1 inputs. the cmxp field selects the comparator?s positive input (cpn p.x); the cmxn field selects the comparator?s neg- ative input (cpnn.x). table 17.1 through table 17.4 de tail the comparator input multiplexer options on the c8051f85x/86x family. see the port i/o crossbar sections for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. important note about comparator inputs: the port pins selected as comparator inputs should be con- figured as analog inputs in their associated port conf iguration register, and configured to be skipped by the crossbar. cmpn cpn+ cpn- programmable hysteresis programmable response time d q q cpn (synchronous) cpna (asynchronous) sysclk gnd port pins (8) negative input selection port pins (8) positive input selection internal ldo
124 rev. 1.0 table 17.1. cmp0 positive input multiplexer channels cmxp setting in register cpt0mx signal name qsop24 pin name qfn20 pin name soic16 pin name 0000 cp0p.0 p0.0 p0.0 p0.0 0001 cp0p.1 p0.1 p0.1 p0.1 0010 cp0p.2 p0.2 p0.2 p0.2 0011 cp0p.3 p0.3 p0.3 p0.3 0100 cp0p.4 p0.4 p0.4 p0.4 0101 cp0p.5 p0.5 p0.5 p0.5 0110 cp0p.6 p0.6 p0.6 reserved 0111 cp0p.7 p0.7 p0.7 reserved 1000 ldo internal 1.8 v ldo output 1001-1111 none no connection table 17.2. cmp0 negative input multiplexer channels cmxn setting in register cpt0mx signal name qsop24 pin name qfn20 pin name soic16 pin name 0000 cp0n.0 p0.0 p0.0 p0.0 0001 cp0n.1 p0.1 p0.1 p0.1 0010 cp0n.2 p0.2 p0.2 p0.2 0011 cp0n.3 p0.3 p0.3 p0.3 0100 cp0n.4 p0.4 p0.4 p0.4 0101 cp0n.5 p0.5 p0.5 p0.5 0110 cp0n.6 p0.6 p0.6 reserved 0111 cp0n.7 p0.7 p0.7 reserved 1000 gnd gnd 1001-1111 none no connection
rev. 1.0 125 table 17.3. cmp1 positive input multiplexer channels cmxp setting in register cpt1mx signal name qsop24 pin name qfn20 pin name soic16 pin name 0000 cp1p.0 p1.0 p1.0 p0.6 0001 cp1p.1 p1.1 p1.1 p0.7 0010 cp1p.2 p1.2 p1.2 p1.0 0011 cp1p.3 p1.3 p1.3 p1.1 0100 cp1p.4 p1.4 p1.4 p1.2 0101 cp1p.5 p1.5 p1.5 p1.3 0110 cp1p.6 p1.6 p1.6 reserved 0111 cp1p.7 p1.7 reserved reserved 1000 ldo internal 1.8 v ldo output 1001-1111 none no connection table 17.4. cmp1 negative input multiplexer channels cmxn setting in register cpt1mx signal name qsop24 pin name qf n20 pin name so ic16 pin name 0000 cp1n.0 p1.0 p1.0 p0.6 0001 cp1n.1 p1.1 p1.1 p0.7 0010 cp1n.2 p1.2 p1.2 p1.0 0011 cp1n.3 p1.3 p1.3 p1.1 0100 cp1n.4 p1.4 p1.4 p1.2 0101 cp1n.5 p1.5 p1.5 p1.3 0110 cp1n.6 p1.6 p1.6 reserved 0111 cp1n.7 p1.7 reserved reserved 1000 gnd gnd 1001-1111 none no connection
126 rev. 1.0 17.2. functional description the comparator offers programmable response time a nd hysteresis, an analog input multiplexer, and two outputs that are optionally available at the port pi ns: a synchronous ?latched? output (cpn), or an asynchronous ?raw? output (cpna) . the asynchronous cpna signal is available even when the system clock is not active. this allows the comparator to ope rate and generate an output with the device in stop mode. when disabled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the comparator is turned off. the comparator response time may be configured in software via the cptnmd re gister. selecting a longer response time reduces the comparator supply current. figure 17.2. comparator hysteresis plot the comparator hysteresis is software-programmable via its comparator control register cptncn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hyst eresis around the threshold voltage. the comparator hysteresis is programmable using the cphyn and cphyp fields in the comparator control register cptncn. the amount of negative hyster esis voltage is determined by the settings of the cphyn bits. as shown in figure 17.2, settings of 20, 10, or 5 mv (nominal) of negative hysteresis can be programmed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cphyp bits. comparator interrupts can be generated on both rising-edge and falling-edge output transitions. the cpfif flag is set to logic 1 upon a comparator falling-ed ge occurrence, and the cpri f flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by software. the comparator rising-edge interrupt mask is enable d by setting cprie to a logic 1. the comparator falling-edge interrupt mask is enabled by setting cpfie to a logic 1. the output state of the comparator can be obtained at any time by reading the cpout bit. the comparator is enabled by setting the cpen bit to logic 1, an d is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is fi rst powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a sh ort time after the comparator is enabled or its mode bits have been changed, before enabling comparator interrupts. cpn- positive programmable hysteresis (cphyp) cpn+ negative programmable hysteresis (cphyn) cp0 (out)
rev. 1.0 127 17.3. comparator control registers register 17.1. cpt0cn: comparator 0 control bit 7 6 5 4 3 2 1 0 name cpen cpout cprif c pfif cphyp cphyn type rw r rw rw rw rw r e s e t00000000 sfr address: 0x9b table 17.5. cpt0cn register bit descriptions bit name function 7 cpen comparator 0 enable bit. 0: comparator disabled. 1: comparator enabled. 6 cpout comparator 0 output state flag. 0: voltage on cp0p < cp0n. 1: voltage on cp0p > cp0n. 5 cprif comparator 0 rising-edge flag. must be cleared by software. 0: no comparator rising edge has occurr e d since this flag was last cleared. 1: comparator rising edge has occurred. 4 cpfif comparator 0 falling-edge flag. must be cleared by software. 0: no comparator falling-edge has occurr ed since this flag was last cleared. 1: comparator fallin g-edge has occurred. 3:2 cphyp comparator 0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cphyn comparator 0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
128 rev. 1.0 register 17.2. cpt0md: comparator 0 mode bit 7 6 5 4 3 2 1 0 name cplout reserved cprie cpfie reserved cpmd ty pe rw r rw rw r rw r e s e t00000010 sfr address: 0x9d table 17.6. cpt0md register bit descriptions bit name function 7 cplout comparator 0 latched output flag. this bit represents the comparator output valu e a t the most recent pca counter overflow. 0: comparator output was logic low at last pca overflow. 1: comparator output was logic high at last pca overflow. 6 reserved must write reset value. 5 cprie comparator 0 rising-edge interrupt enable. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. 4 cpfie comparator 0 falling-edge interrupt enable. 0: comparator falling-ed ge interrupt disabled. 1: comparator falling- edge interrupt enabled. 3:2 reserved must write reset value. 1:0 cpmd comparator 0 mode select. these bits affect the response time and power consumption of the comparator. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
rev. 1.0 129 register 17.3. cpt0mx: comparator 0 multiplexer selection bit 7 6 5 4 3 2 1 0 name cmxn cmxp t ype rw rw r e s e t11111111 sfr address: 0x9f table 17.7. cpt0mx register bit descriptions bit name function 7:4 cmxn comparator 0 negative input mux selection. 0000: external pin cp0n.0 0001: external pin cp0n.1 0010: external pin cp0n.2 0011: external pin cp0n.3 0100: external pin cp0n.4 0101: external pin cp0n.5 0110: external pin cp0n.6 0111: external pin cp0n.7 1000: gnd 1001-1111: reserved. 3:0 cmxp comparator 0 positive input mux selection. 0000: external pin cp0p.0 0001: external pin cp0p.1 0010: external pin cp0p.2 0011: external pin cp0p.3 0100: external pin cp0p.4 0101: external pin cp0p.5 0110: external pin cp0p.6 0111: external pin cp0p.7 1000: internal ldo output 1001-1111: reserved.
130 rev. 1.0 register 17.4. cpt1cn: comparator 1 control bit 7 6 5 4 3 2 1 0 name cpen cpout cprif c pfif cphyp cphyn type rw r rw rw rw rw r e s e t00000000 sfr address: 0xbf table 17.8. cpt1cn register bit descriptions bit name function 7 cpen comparator 1 enable bit. 0: comparator disabled. 1: comparator enabled. 6 cpout comparator 1 output state flag. 0: voltage on cp1p < cp1n. 1: voltage on cp1p > cp1n. 5 cprif comparator 1 rising-edge flag. must be cleared by software. 0: no comparator rising edge has occurr e d since this flag was last cleared. 1: comparator rising edge has occurred. 4 cpfif comparator 1 falling-edge flag. must be cleared by software. 0: no comparator falling edge has occurr ed since this flag was last cleared. 1: comparator falling edge has occurred. 3:2 cphyp comparator 1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cphyn comparator 1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
rev. 1.0 131 register 17.5. cpt1md: comparator 1 mode bit 7 6 5 4 3 2 1 0 name cplout reserved cprie cpfie reserved cpmd ty pe rw r rw rw r rw r e s e t00000010 sfr address: 0xab table 17.9. cpt1md register bit descriptions bit name function 7 cplout comparator 1 latched output flag. this bit represents the comparator output valu e a t the most recent pca counter overflow. 0: comparator output was logic low at last pca overflow. 1: comparator output was logic high at last pca overflow. 6 reserved must write reset value. 5 cprie comparator 1 rising-edge interrupt enable. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. 4 cpfie comparator 1 falling-edge interrupt enable. 0: comparator falling-ed ge interrupt disabled. 1: comparator falling- edge interrupt enabled. 3:2 reserved must write reset value. 1:0 cpmd comparator 1 mode select. these bits affect the response time and power consumption of the comparator. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
132 rev. 1.0 register 17.6. cpt1mx: comparator 1 multiplexer selection bit 7 6 5 4 3 2 1 0 name cmxn cmxp t ype rw rw r e s e t11111111 sfr address: 0xaa table 17.10. cpt1mx register bit descriptions bit name function 7:4 cmxn comparator 1 negative input mux selection. 0000: external pin cp1n.0 0001: external pin cp1n.1 0010: external pin cp1n.2 0011: external pin cp1n.3 0100: external pin cp1n.4 0101: external pin cp1n.5 0110: external pin cp1n.6 0111: external pin cp1n.7 1000: gnd 1001-1111: reserved. 3:0 cmxp comparator 1 positive input mux selection. 0000: external pin cp1p.0 0001: external pin cp1p.1 0010: external pin cp1p.2 0011: external pin cp1p.3 0100: external pin cp1p.4 0101: external pin cp1p.5 0110: external pin cp1p.6 0111: external pin cp1p.7 1000: internal ldo output 1001-1111: reserved.
rev. 1.0 133 18. cyclic redundancy check unit (crc0) c8051f85x/86x devices include a cyclic redundancy check unit (crc0) that can perform a crc using a 16-bit polynomial. crc0 accepts a stream of 8-bit dat a written to the crc0in register. crc0 posts the 16- bit result to an internal register. the internal result register may be accessed indirectly using the crcpnt bits and crc0dat register, as shown in figure 18.1. crc0 also has a bit reverse register for quick data manipulation. figure 18.1. crc0 block diagram 18.1. crc algorithm the crc unit generates a crc result equivalent to the following algorithm: 1. xor the input with the most-significant bits of t he current crc result. if this is the first iteration of the crc unit, the current crc re sult will be the set init ial value (0x 0000 or 0xffff). 2a. if the msb of the crc result is set, shift the crc result an d xor the result with the selected polynomial. 2b. if the msb of the crc result is not set, shift the crc result. repeat steps 2a/2b for the number of input bits (8). the algorithm is also described in the following example. crc0 crc0dat crc0in byte-level bit reversal hardware crc calculation unit seed (0x0000 or 0xffff) automatic flash read control 8 8 8 8 8 flash memory crc0flip 8
134 rev. 1.0 the 16-bit crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } // return the final remainder (crc value) return crc_acc; } table 18.1 lists several input values and the a ssociated outputs using the 16-bit crc algorithm: table 18.1. example 16-bit crc outputs input output 0x63 0xbd35 0x8c 0xb1f4 0x7d 0x4eca 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166
rev. 1.0 135 18.2. preparing fo r a crc calculation to prepare crc0 for a crc calculation, software should set the initial value of the result. the polynomial used for the crc computation is 0x1021. the crc0 result may be initialized to one of two values: 0x0000 or 0xffff. the following steps can be used to initialize crc0. 1. select the initial result value (set crcval to 0 for 0x0000 or 1 for 0xffff). 2. set the result to its initial value (write 1 to crcinit). 18.3. performing a crc calculation once crc0 is initialized, the input data stream is sequenti ally written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. the crc engine may also be configured to automatically perform a crc on one or more 256 byte blocks read from flash. the following steps can be used to automatically perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. write the index of the starting page to crc0auto. 3. set the autoen bit to 1 in crc0auto. 4. write the number of 256 byte blocks to perform in the crc calculation to crccnt. 5. write any value to crc0cn (or or its contents with 0x00) to initiate the crc calculation. the cpu will not execute code any additional code unt il the crc operation completes. see the note in the crc0cn register definition fo r more information on how to prop erly initiate a crc calculation. 6. clear the autoen bit in crc0auto. 7. read the crc result. 18.4. accessing th e crc0 result the internal crc0 result is 16 bits. the crcpnt bits select the byte that is targeted by read and write operations on crc0dat and increment after each read or write. the ca lculation result will remain in the internal cr0 result register until it is set, overwritten, or addi tional data is written to crc0in. 18.5. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of each bit in a byte as shown in figure 18.2. each byte of data written to crc0flip is read back bit reversed. for example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathem atical function used in algorithms such as the fft. figure 18.2. bit reversal crc0flip (write) crc0flip (read)
136 rev. 1.0 18.6. crc control registers register 18.1. crc0cn: crc0 control bit 7 6 5 4 3 2 1 0 name reserved crcinit crcval reserved crcpnt ty pe r rw rw r rw r e s e t00010000 sfr address: 0xce table 18.2. crc0cn register bit descriptions bit name function 7:4 reserved must write reset value. 3 crcinit crc result initialization bit. writing a 1 to this bit initializes the entire cr c result based on crcval. 2 crcval crc set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x0000 on write of 1 to crcinit. 1: crc result is set to 0xffff on write of 1 to crcinit. 1 reserved must write reset value. 0 crcpnt crc result pointer. specifies the byte of the crc result to be read/w ritten on the ne xt access to crc0dat. this bit will automatically togg le upon each read or write. 0: crc0dat accesses bits 7- 0 of the 16-bit crc result. 1: crc0dat accesses bits 15-8 of the 16-bit crc result. note: upon initiation of an automatic crc calculation, the three cycl es following a write to crc0cn that initiate a crc operation must only contain inst ructions which execute in t he same number of cycles as the number of bytes in the instruction. an example of such an in struction is a 3-byte mov that targets the crc0flip register. when programming in c, the dummy value written to crc0flip should be a non -zero value to prevent the co mpiler from generating a 2- byte mov instruction.
rev. 1.0 137 register 18.2. crc0in: crc0 data input bit 7 6 5 4 3 2 1 0 name crc0in ty pe rw r e s e t00000000 sfr address: 0xdd table 18.3. crc0in register bit descriptions bit name function 7:0 crc0in crc data input. each write to crcin results in th e written data being computed into the existing crc result according to the crc algorithm.
138 rev. 1.0 register 18.3. crc0dat: crc0 data output bit 7 6 5 4 3 2 1 0 name crc0dat ty pe rw r e s e t00000000 sfr address: 0xde table 18.4. crc0dat register bit descriptions bit name function 7:0 crc0dat crc data output. each read or write performed on crc0dat targ et s the crc result bits pointed to by the crc0 result pointer (crc0pnt bits in crc0cn). note: crc0dat may not be valid for one cycle after setting the crc0init bit in the crc0cn register to 1. any time crc0init is written to 1 by firmware, at least one instruction should be performed before reading crc0dat.
rev. 1.0 139 register 18.4. crc0auto: crc0 automatic control bit 7 6 5 4 3 2 1 0 name autoen reserved crcst ty pe rw r rw r e s e t00000000 sfr address: 0xd2 table 18.5. crc0auto register bit descriptions bit name function 7 autoen automatic crc calc ulation enable. when autoen is set to 1, any write to c rc0cn will initiate an automatic crc starting at flash sector crcst and continuing for crccnt sectors. 6 reserved must write reset value. 5:0 crcst automatic crc ca lculation s tarting block. these bits specify the flash block to start the automatic crc calculation. the starting address of the first flash block included in the automatic crc calculation is crcst x block_size, where block_size is 256 bytes.
140 rev. 1.0 register 18.5. crc0cnt: crc0 automatic flash sector count bit 7 6 5 4 3 2 1 0 name crcdn reserved crccnt ty pe r r rw r e s e t10000000 sfr address: 0xd3 table 18.6. crc0cnt register bit descriptions bit name function 7 crcdn automatic crc calcul ation complete. set to 0 when a crc calculation is in progre ss. co de execution is stopped during a crc calculation; therefore, reads fr om firmware will always return 1. 6:5 reserved must write reset value. 4:0 crccnt automatic crc calcul ation block count. these bits specify the number of fla sh blocks to include in an automatic crc calculation. the last address of the last flash block in cluded in the automatic crc calculation is (crcst+crccnt) x block size - 1. the block size is 256 bytes.
rev. 1.0 141 register 18.6. crc0flip: crc0 bit flip bit 7 6 5 4 3 2 1 0 name crc0flip ty pe rw r e s e t00000000 sfr address: 0xcf table 18.7. crc0flip register bit descriptions bit name function 7:0 crc0flip crc0 bit flip. any byte written to crc0flip is read back in a bit-r eversed order, i.e., the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the dat a read back will be 0x03. if 0x05 is written to crc0flip, the dat a read back will be 0xa0.
142 rev. 1.0
rev. 1.0 142 19. external interrupts ( int0 and int1) the c8051f85x/86x device family includes tw o external digital interrupt sources (int0 and int1 ), with dedicated interrupt sources (up to 16 additional i/o interrupts are available through the port match function). as is the case on a standard 8051 archit ecture, certain controls for these two interrupt sources are available in the timer0/1 registers. extensions to these controls which provid e additional functionality on c8051f85x/86x devices are availa ble in the it01cf register. int0 and int1 are configurable as active high or low, edge- or level-sensitive. the in0pl and in1p l bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon select level- or edge-sensitive. the table below lists the possible configurations. int0 and int1 are assigned to port pins as define d in the it01cf register. note that int0 and int1 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins without disturbing the peripheral that was as signed the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). ie0 and ie1 in the tcon register serve as the interrupt-pending flags for the int0 and int1 external interrupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitiv e, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding pola rity bit (in0pl or in1pl); the flag remains logic 0 while the input is inactive. the external interrupt source must hold the i nput active until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge-sensitive 1 0 active low, edge-sensitive 1 1 active high, edge-sensitive 1 1 active high, edge-sensitive 0 0 active low, level-sensitive 0 0 active low, level-sensitive 0 1 active high, level-sensitive 0 1 active high, level-sensitive
143 rev. 1.0 19.1. external interrupt control registers register 19.1. it01cf: int0/int1 configuration bit 7 6 5 4 3 2 1 0 name in1pl in1sl in0pl in0sl t ype rw rw rw rw r e s e t00000001 sfr address: 0xe4 table 19.1. it01cf register bit descriptions bit name function 7 in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl int1 port pin selection bits. these bits select which port pin is assigned to int1. this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin without dist urbing the peripheral that has been assigned the port pin via t he crossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3 in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high.
rev. 1.0 144 2:0 in0sl int0 port pin selection bits. these bits select which port pin is assigned to int0. this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via t he crossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 table 19.1. it01cf register bit descriptions bit name function
145 rev. 1.0
rev. 1.0 145 20. programmable counter array (pca0) the programmable counter array (pca0) provides three channels of enhanced timer and pwm functionality while requiring less cpu intervention than standard counte r/timers. the pca consists of a dedicated 16-bit counter/timer and three 16-bit captur e/compare modules. the counter/timer is driven by a programmable timebase that can select between seve n sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source di vided by 8, low frequency oscillator divided by 8, timer 0 overfl ows, or an external clock signal on the eci input pin. each capture/ compare module may be configured to operate i ndependently in one of six modes: edge-triggered capture, software timer, high-speed output, frequen cy output, 8 to 11-bit pwm, or 16-bit pwm. additionally, all pwm modes support both center and edge-aligned operation. the ex ternal oscillator and lfo oscillator clock options allow the pca to be clocked by an external oscilla tor or the lfo while the internal oscillator drives the system clock. each c apture/compare module has it s own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the i/o signals have programmable polarity and comparator 0 can optionally be used to perf orm a cycle-by-cycle kill operation on the pca outputs. a pca block diagram is shown in figure 20.1 figure 20.1. pca0 block diagram channel 2 mode control capture / compare channel 1 mode control capture / compare pca0 eci cex0 extclk / 8 l-f oscillator / 8 timer 0 overflow sysclk sysclk / 4 sysclk / 12 polarity select control / configuration comparator clear enable output drive logic pca counter channel 0 mode control capture / compare cex1 cex2 comparator 0 output interrupt logic sync sync sync sysclk
146 rev. 1.0 20.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bit sfrs: pca0l and pca0h. pca0h is the high byte of the 16-bit counter/timer and pca0l is the low byte. reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accurate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 20.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by software. clearing the cidl bit in the pca0md register allows the pca to continue normal operation while the cpu is in idle mode. 20.2. pca0 interrupt sources the pca0 module shares one interrupt vector among all of its modules. there are are several event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an intermediate overflow flag (covf), which can be set on an overflow from the 8th - 11th bit of the pca0 counter, and the individual flags for each pca channel (ccfn), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flag s can be individually selected to generate a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pca0 interrupts must be globally enabled be fore any individual interrupt sources are recognized by the processor. pca0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. table 20.1. pca timebase input options cps2 cps1 cps0 timebase 000 system clock divided by 12 001 system clock divided by 4 010 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) * 100 system clock 101 external oscillator s ource divided by 8 * 110 low frequency oscillator divided by 8 * 111 reserved *note: synchronized with the system clock.
rev. 1.0 147 20.3. capture/compare modules each module can be configured to operate independent ly in one of six operation modes: edge-triggered capture, software timer, high-speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit pulse width modulator. table 20.2 summarizes the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare module?s operating mode. note that all modules set to use 8-, 9-, 10-, or 11-bit pwm mode must use the same cycle length (8?11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. 20.3.1. output polarity the output polarity of each pca channel is individual l y selectable using the pca0 pol register. by default, all output channels are configured to drive the pca out put signals (cexn) with their internal polarity. when the cexnpol bit for a specific channel is set to 1, that cha nnel?s output signal will be inverted at the pin. all other properties of the channel are unaffected, an d the inversion does not apply to pca input signals. note that changes in the pca0pol register take effect immediately at the associated output pin. table 20.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number 7 6 5 4 3 2 1 0 7 6 5 4?3 2?0 capture triggered by positive edge on cexn x x 1 0 0 0 0 a 0 x b xx xxx capture triggered by negative edge on cexn x x 0 1 0 0 0 a 0 x b xx xxx capture triggered by any transition on cexn x x 1 1 0 0 0 a 0 x b xx xxx software timer x c 0 0 1 0 0 a 0 x b xx xxx high speed output x c 0 0 1 1 0 a 0 x b xx xxx frequency output x c 0 0 0 1 1 a 0 x b xx xxx 8-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a 0 x b xx 000 9-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xx 001 10-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xx 010 11-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xx 011 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xx xxx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th - 11th bit overflow interr upt (depends on setting of clsel). 4. c = when set to 0, the digital comparator is off. for high sp eed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, th is generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pc a0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pwm mode use the same cycle length setting.
148 rev. 1.0 20.3.2. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture th e value of the pca counter/ timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cp mn register are used to select the type of transition that triggers the capture: low-to-high transi tion (positive edge), high -to-low transition (negative edge), or either transition (positive or negative ed ge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by soft ware. if both cappn and capnn bi ts are set to logic 1, then the state of the port pin associated with cexn can be read directly to determi ne whether a rising-edge or falling-edge caused the capture. figure 20.2. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hard ware. cexn pca0l pca0cpln pca0h pca0cphn cappn capnn ccfn (interrupt flag) pca clock capture
rev. 1.0 149 20.3.3. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 20.3. pca software timer mode diagram pca0l pca0cpln pca0h pca0cphn ecomn (compare enable) pca clock 16-bit comparator match ccfn (interrupt flag) matn (match enable)
150 rev. 1.0 20.3.4. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vect ors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high-speed output mode. if ecomn is cleared, the associated pin will retain its state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 20.4. pca high-speed output mode diagram pca0l pca0cpln pca0h pca0cphn ecomn (compare enable) pca clock 16-bit comparator match ccfn (interrupt flag) matn (match enable) toggle togn (toggle enable) cexn
rev. 1.0 151 20.3.5. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte hol ds the number of pca clocks to count before the output is toggled. the frequency of the s quare wave is then defined by equation 20.1. equation 20.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, n is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn register. note that the matn bit should normally be set to 0 in this mode. if the ma tn bit is set to 1, the ccfn flag for the channel will be set when the 16-bit pca0 counter and the 16-bit capture/compare register for the channel are equal. figure 20.5. pca frequency output mode f cexn f pca 2 pca0 cphn note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. pca0l ecomn (compare enable) pca clock 8-bit comparator match toggle togn (toggle enable) cexn 8-bit adder adder enable pca0cpln pca0cphn
152 rev. 1.0 20.4. pwm waveform generation the pca can generate edge- or center-aligned pwm wavefo rms with resolutions of 8, 9, 10, 11 or 16 bits. pwm resolution depends on the module setup, as specified within the individual module pca0cpmn registers as well as the pca0pwm register. modules can be configured for 8-11 bit mode, or for 16-bit mode individually using the pca0cpmn registers. all modules configur ed for 8-11 bit mode will have the same resolution, specified by the pca0pwm register . when operating in one of the pwm modes, each module may be individually configured for center or edge-aligned pwm waveforms. each channel has a single bit in the pca0cent register to select between the two options. 20.4.1. edge aligned pwm when configured for e dge-aligned mode , a module will generate an edge transi tion at two points for every 2 n pca clock cycles, where n is the selected pwm reso lution in bits. in edge-aligned mode, these two edges are referred to as the ?match? and ?overflow? edges. the polarity at the output pin is selectable, and can be inverted by setting the appropriate channel bit to ?1? in the pca0pol regist er. prior to inversion, a match edge sets the channel to logic high, and an overflow edge clears the channel to logic low. the match edge occurs when the the lowest n bits of the module?s pca0cpn register match the corresponding bits of the main pca0 counter register. for example, with 10-bit pwm, the match edge will occur any time bits 9-0 of the pca0cpn regist er match bits 9-0 of the pca0 counter value. the overflow edge occurs when an overflow of the pc a0 counter happens at the desired resolution. for example, with 10-bit pwm, the overflow edge will occur wh en bits 0-9 of the pca0 counter transition from all 1?s to all 0?s. all modules co nfigured for edge-aligne d mode at the same re solution will align on the overflow edge of the waveforms. an example of the pwm timing in edge-aligned mode for two channels is shown in figure 20.6. in this example, the cex0pol and cex1pol bits are cleared to 0. figure 20.6. edge-aligned pwm timing for a given pca resolution, the unused high bits in the pca0 counter and the pca0cpn compare registers are ignored, and only the used bits of the pca0cpn register determine the duty cycle. equation 20.2 describes the duty cycle when cexn pol in the pca0pol regsiter is cleared to 0. equation 20.3 describes the duty cycle when cexnpo l in the pca0pol regsiter is set to 1. a 0% duty cycle for the channel (with cexnpol = 0) is achieved by clearing the module?s ecom bit to 0. this will 0xffff 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 counter (pca0) 0x0001 capture / compare (pca0cp0) output (cex0) pca clock match edge overflow edge 0x0005 capture / compare (pca0cp1) output (cex1) match edge
rev. 1.0 153 disable the comparison, and prevent the match edge from occuring. note that although the pca0cpn compare register determines the duty cycle, it is not always appropriate for firmware to update this register directly. see the sections on 8 to 11-bit and 16-bit pw m mode for additional details on adjusting duty cycle in the various modes. equation 20.2. n-bit edge-aligned pwm duty cycle with cexnpol = 0 (n = pwm resolution) equation 20.3. n-bit edge-aligned pwm duty cycle with cexnpol = 0 (n = pwm resolution) duty cycle 2 n pca0cpn ? () 2 n ----------------------------------------- - = duty cycle pca0cpn 2 n ------------------------ - =
154 rev. 1.0 20.4.2. center aligned pwm when configured for center -aligned mode, a module will generate an edge transition at two points for every 2 (n+1) pca clock cycles, where n is the selected pwm re solution in bits. in ce nter-aligned mode, these two edges are referred to as the ?up? and ?down? edges . the polarity at the output pin is selectable, and can be inverted by setting the appropriate channel bit to ?1? in the pca0pol register. the generated waveforms are centered about the points where the lower n bits of the pca0 counter are zero. the (n+1) th bit in the pca0 counter acts as a selection between up and down edges. in 16-bit mode, a special 17th bit is implemented inte rnally for this purpose. at the center point, the (non-inverted) channel output will be low when the (n+1) th bit is ?0? and high when the (n+1) th bit is ?1?, except for cases of 0% and 100% duty cycle. prior to inversion, an up edge sets the channel to logic high, and a down edge clears the channel to logic low. down edges occur when the (n+1) th bit in the pca0 counter is one, and a logical inversion of the value in the module?s pca0cpn register matches the main pc a0 counter register for the lowest n bits. for example, with 10-bit pwm, the down edge will occu r when the one?s complement of bits 9-0 of the pca0cpn register match bits 9-0 of the pca0 co unter, and bit 10 of the pca0 counter is ?1?. up edges occur when the (n+1) th bit in the pca0 counter is zero, and the lowest n bits of the module?s pca0cpn register match the value of (pca0 - 1). for example, with 10-bit pwm, the up edge will occur when bits 9-0 of the pca0cpn register are one less th an bits 9-0 of the pca0 counter, and bit 10 of the pca0 counter is ?0?. an example of the pwm timing in center-aligned mode for two channels is shown in figure 20.7. in this example, the cex0pol and cex1pol bits are cleared to 0. figure 20.7. center-aligned pwm timing 0xfb 0xfc 0xfd 0xfe 0xff 0x00 0x01 0x02 0x03 0x04 counter (pca0l) 0x01 capture / compare (pca0cpl0) output (cex0) pca clock down edge 0x04 capture / compare (pca0cpl1) output (cex1) up edge down edge up edge center center center
rev. 1.0 155 equation 20.4 describes the duty cycle when cexn pol in the pca0pol regsiter is cleared to 0. equation 20.5 describes the duty cycle when cexnpol in the pc a0pol regsiter is set to 1. the equations are true only when the lowest n bits of the pca0cpn register are not all 0?s or all 1?s. with cexnpol equal to zero, 100% duty cycle is produced when the lowest n bits of pca0cpn are all 0, and 0% duty cycle is produced when the lowest n bits of pca0cpn are all 1. for a given pca resolution, the unused high bits in the pca0 counter and the pca0cp n compare registers are ignored, and only the used bits of the pca0cpn register determine the duty cycle. note that although the pca0cpn compare register determ ines the duty cycle, it is not always appropriate for firmware to update this register directly. see t he sections on 8 to 11-bit and 16-bit pwm mode for additional details on adjusting du ty cycle in the various modes. equation 20.4. n-bit center-aligned pwm duty cycle wi th cexnpol = 0 (n = pwm resolution) equation 20.5. n-bit center-aligned pwm duty cycle wi th cexnpol = 1 (n = pwm resolution) duty cycle 2 n pca0cpn ? () 1 2 -- - ? 2 n -------------------------------------------------- - = duty cycle pca0cpn 1 2 -- - + 2 n ---------------------------------- =
156 rev. 1.0 20.4.3. 8 to11-bit pulse width modulator modes each module can be used independently to gener ate a pulse width modulated (pwm) output on its associated cexn pin. the frequency of the output is dependent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8 throug h 11-bits). for backwards-c ompatibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mo de operates slightly different than 9 through 11- bit pwm modes. it is important to note that all channels configured for 8 to 11-b it pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11-bit mode (for example). however, other pca channels ca n be configured to pin capture, high-speed output, software timer, frequency output, or 16-bit pwm mode independently. each channel configured for a pwm mode can be individually selected to operate in edge-aligned or center-aligned mode. 20.4.3.1. 8-bit pulse width modulator mode in 8-bit pwm mode, the duty cycle is determined by the value of the low byte of the pca0cpn register (pca0cpln). to adjust the duty cycle, pca0cpln shou ld not normally be written directly. instead, it is recommended to adjust the duty cycle using the high by te of the pca0cpn register (register pca0cphn). this allows seamless updating of the pwm waveform, as pca0cpln is reloaded automatically with the value stored in pca0cphn during the overflow edge (in edge-aligned mode) or the up edge (in center- aligned mode). setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode . if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cycles. 20.4.3.2. 9 to 11-bit pulse width modulator mode in 9 to 11-bit pwm mode, the duty cycle is determined by the value of the least significant n bits of the pca0cpn register, where n is the selected pwm resolution. to adjust the duty cycle, pca0cpn should not normally be written directly. inste ad, it is recommended to adjust the duty cycle by writing to an ?auto-reload ? register, which is dual-mapped into the pca0cphn and pca0cpln register locations. the data written to de fine the duty cycle should be right-justified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. this allows seamless updating of the pwm waveform, as the pca0cpn regist er is reloaded automatically with the value stored in the auto-reload registers during the overflow edge (in edge-aligned mode) or the up edge (in center- aligned mode). setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode . if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the covf flag in pca0pwm can be used to detect the overflow or down edge. the 9 to 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the covf flag in pca0pwm can be used to detect the overflow or down edge. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1.
rev. 1.0 157 20.4.4. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm m ode. 16-bit pwm mode is independent of the other (8 through 11-bit) pwm modes. the entire pca0cp regist er is used to determine the duty cycle in 16-bit pwm mode. to output a varying duty cycle, new value writes s hould be synchronized with the pca ccfn match flag to ensure seamless updates. 16-bit pwm mode is enabled by se tting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, the match interrupt flag should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compare regist er writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the cf flag in pca0cn can be used to detect the overflow or down edge. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1.
158 rev. 1.0 20.5. comparator clear function in 8/9/10/11/16-bit pwm modes, the comparator clear function utilizes the comp arator0 output synchronized to the system clock to clear cexn to logic low for the current pwm cycle. this comparator clear function can be enabled for each pwm channel by setting the cpcen bits to 1 in the pca0clr sfr. when the comparator clear function is disabled, cexn is unaffected. the asynchronous comparator 0 output is logic high wh en the voltage of cp0+ is greater than cp0- and logic low when the voltage of cp0+ is less than cp0-. the polarity of the comparator 0 output is used to clear cexn as follows: when cpcpol = 0, cexn is cleared on the falling edge of the comparator0 output (see figure 20.8); when cpcpol = 1, cexn is cleare d on the rising edge of th e comparator0 output (see figure 20.9). figure 20.8. cexn with cpcen = 1, cpcpol = 0 figure 20.9. cexn with cpcen = 1, cpcpol = 1 in the pwm cycle following the current cycle, should the comparator 0 output remain logic low when cpcpol = 0 or logic high when cp cpol = 1, cexn will continue to be cleared. see figure 20.10 and figure 20.11. figure 20.10. cexn with cpcen = 1, cpcpol = 0 cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 0) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 1) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 0)
rev. 1.0 159 figure 20.11. cexn with cpcen = 1, cpcpol = 1 cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 1)
160 rev. 1.0 20.6. pca cont rol registers register 20.1. pca0cn: pca control bit 7 6 5 4 3 2 1 0 name cf cr reserved ccf2 ccf1 ccf0 t yperwrw r rwrwrw r e s e t00000000 sfr address: 0xd8 (bit-addressable) table 20.3. pca0cn register bit descriptions bit name function 7 cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when th e counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hard - ware and must be cleared by software. 6 cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:3 reserved must write reset value. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or cap ture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or cap ture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or cap ture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software.
rev. 1.0 161 register 20.2. pca0md: pca mode bit 7 6 5 4 3 2 1 0 name cidl reserved cps ecf ty pe rw r rw rw r e s e t00000000 sfr address: 0xd9 table 20.4. pca0md register bit descriptions bit name function 7 cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while the system controller is in idle mode. 6:4 reserved must write reset value. 3:1 cps pca counter/time r pu lse select. these bits select the timebase source for the pca counter. 000: system clock divided by 12. 001: system clock divided by 4. 010: timer 0 overflow. 011: high-to-low transitions on eci (max rate = system clock divided by 4). 100: system clock. 101: external clock divided by 8 (s y nchronized with the system clock). 110: low frequency os cillator divided by 8. 111: reserved. 0 ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co un ter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow inte rr upt request when cf (pca0cn.7) is set.
162 rev. 1.0 register 20.3. pca0pwm: pca pwm configuration bit 7 6 5 4 3 2 1 0 name arsel ecov covf reserved clsel t ype rw rw rw r rw r e s e t00000000 sfr address: 0xf7 table 20.5. pca0pwm register bit descriptions bit name function 7 arsel auto-reload register select. this bit selects whether to read and writ e th e normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9 to 11-bit pwm modes. in all other modes, the auto- reload registers have no function. 0: read/write capture/compare regi ster s at pca0cphn and pca0cpln. 1: read/write auto-reload registers at pca0cphn and pca0cpln. 6 ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not genera te pc a interrupts. 1: a pca interrupt will be g enerated when covf is set. 5 covf cycle overflow flag. this bit indicates an overflow of the 8th to 11th bit of the main pca counter (pca0). the sp ecific bit used for this flag depends on t he setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by software. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:3 reserved must write reset value. 2:0 clsel cycle length select. when 16-bit pwm mode is not selected, these bit s select the length of the pwm cycle. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels configured to16-bit pwm mode. 000: 8 bits. 001: 9 bits. 010: 10 bits. 011: 11 bits. 100-111: reserved.
rev. 1.0 163 register 20.4. pca0clr: pca comparator clear control bit 7 6 5 4 3 2 1 0 name cpcpol reserved cpce2 cpce1 cpce0 t yperw r rwrwrw r e s e t00000000 sfr address: 0x9c table 20.6. pca0clr register bit descriptions bit name function 7 cpcpol comparator clear polarity. selects the polarity of the c omparator result that w ill clear the pca channel(s). 0: pca channel(s) will be cleared when comp arator result goes logic low. 1: pca channel(s) will be cleared when comp arator result goes logic high. 6:3 reserved must write reset value. 2 cpce2 comparator clear enable for cex2. enables the comparator clear function on pca channel 2. 1 cpce1 comparator clear enable for cex1. enables the comparator clear function on pca channel 1. 0 cpce0 comparator clear enable for cex0. enables the comparator clear function on pca channel 0.
164 rev. 1.0 register 20.5. pca0cpm0: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16 ecom capp capn mat tog pwm eccf t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xda table 20.7. pca0cpm0 register bit descriptions bit name function 7 pwm16 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecom comparator function enable. this bit enables the comparator function. 5 capp capture positive function enable. this bit enables the positive edge capture capability. 4 capn capture negative function enable. this bit enables the negative edge capture capability. 3 mat match function enable. this bit enables the match function. when en ab led, matches of the pca counter with a module's capture/compare regist er cause the ccf0 bit in the pca0md register to be set to logic 1. 2 tog toggle function enable. this bit enables the toggle function. when ena ble d, matches of the pca counter with the capture/compare register cause the logic leve l on the cex0 pin to toggle. if the pwm bit is also set to logic 1, the module operates in frequency output mode. 1 pwm pulse width modulation mode enable. this bit enables the pwm function. when enabled, a pulse width modulated signal is out - put on the cex0 pin. 8 to 11-bit pwm is used if pwm16 is cleared; 16-bit mode is used if pwm16 is set to logic 1. if the tog bit is also set, the module operates in frequency output mode. 0 eccf capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccf0) interrupt. 0: disable ccf0 interrupts. 1: enable a capture/compare flag interrupt request when ccf0 is set.
rev. 1.0 165 register 20.6. pca0l: pca counter/timer low byte bit 7 6 5 4 3 2 1 0 name pca0l ty pe rw r e s e t00000000 sfr address: 0xf9 table 20.8. pca0l register bit descriptions bit name function 7:0 pca0l pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer.
166 rev. 1.0 register 20.7. pca0h: pca counter/timer high byte bit 7 6 5 4 3 2 1 0 name pca0h ty pe rw r e s e t00000000 sfr address: 0xfa table 20.9. pca0h register bit descriptions bit name function 7:0 pca0h pca counter/timer high byte. the pca0h register holds the high byte (msb ) of the 16-bit pca counter/timer. reads of this register will read the c ontents of a snapshot register , whose contents are updated only when the contents of pca0l are read.
rev. 1.0 167 register 20.8. pca0cpl0: pca capture module low byte bit 7 6 5 4 3 2 1 0 name pca0cpl0 ty pe rw r e s e t00000000 sfr address: 0xfb table 20.10. pca0cpl0 register bit descriptions bit name function 7:0 pca0cpl0 pca capture module low byte. the pca0cpl0 register holds the low byte (lsb) of the 16-bit capture module.this reg - ister address also allows access to the low byte of the corresponding pca channels a uto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will clear the module?s ecom bit to a 0.
168 rev. 1.0 register 20.9. pca0cph0: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cph0 ty pe rw r e s e t00000000 sfr address: 0xfc table 20.11. pca0cph0 register bit descriptions bit name function 7:0 pca0cph0 pca capture module high byte. the pca0cph0 register holds the high byte (m sb) of the 16-bit capture module.this register address also allows access to the high byte of the corresponding pca channels auto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will set the module?s ecom bit to a 1.
rev. 1.0 169 register 20.10. pca0pol: pca output polarity bit 7 6 5 4 3 2 1 0 name reserved cex2pol cex1pol cex0pol t ype r rwrwrw r e s e t00000000 sfr address: 0x96 table 20.12. pca0pol register bit descriptions bit name function 7:3 reserved must write reset value. 2 cex2pol cex2 output polarity. selects the polarity of the cex2 output channe l. when this bit is modified, the change takes effect at the pin immediately. 0: use default polarity. 1: invert polarity. 1 cex1pol cex1 output polarity. selects the polarity of the cex1 output channe l. when this bit is modified, the change takes effect at the pin immediately. 0: use default polarity. 1: invert polarity. 0 cex0pol cex0 output polarity. selects the polarity of the cex0 output channe l. when this bit is modified, the change takes effect at the pin immediately. 0: use default polarity. 1: invert polarity.
170 rev. 1.0 register 20.11. pca0cent: pca center alignment enable bit 7 6 5 4 3 2 1 0 name reserved cex2cen cex1cen cex0cen t ype r rwrwrw r e s e t00000000 sfr address: 0x9e table 20.13. pca0cent register bit descriptions bit name function 7:3 reserved must write reset value. 2 cex2cen cex2 center alignment enable. selects the alignment properties of the cex2 ou tput channel when operated in any of the pwm modes. this bit does not affect the operation of non-pwm modes. 0: edge-aligned. 1: center-aligned. 1 cex1cen cex1 center alignment enable. selects the alignment properties of the cex1 ou tput channel when operated in any of the pwm modes. this bit does not affect the operation of non-pwm modes. 0: edge-aligned. 1: center-aligned. 0 cex0cen cex0 center alignment enable. selects the alignment properties of the cex0 ou tput channel when operated in any of the pwm modes. this bit does not affect the operation of non-pwm modes. 0: edge-aligned. 1: center-aligned.
rev. 1.0 171 register 20.12. pca0cpm1: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16 ecom capp capn mat tog pwm eccf t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xdb table 20.14. pca0cpm1 register bit descriptions bit name function 7 pwm16 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecom comparator function enable. this bit enables the comparator function. 5 capp capture positive function enable. this bit enables the positive edge capture capability. 4 capn capture negative function enable. this bit enables the negative edge capture capability. 3 mat match function enable. this bit enables the match function. when en ab led, matches of the pca counter with a module's capture/compare regist er cause the ccf1 bit in the pca0md register to be set to logic 1. 2 tog toggle function enable. this bit enables the toggle function. when ena ble d, matches of the pca counter with the capture/compare register cause the logic leve l on the cex1 pin to toggle. if the pwm bit is also set to logic 1, the module operates in frequency output mode. 1 pwm pulse width modulation mode enable. this bit enables the pwm function. when enabled, a pulse width modulated signal is out - put on the cex1 pin. 8 to 11-bit pwm is used if pwm16 is cleared; 16-bit mode is used if pwm16 is set to logic 1. if the tog bit is also set, the module operates in frequency output mode. 0 eccf capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccf1) interrupt. 0: disable ccf1 interrupts. 1: enable a capture/compare flag interrupt request when ccf1 is set.
172 rev. 1.0 register 20.13. pca0cpm2: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16 ecom capp capn mat tog pwm eccf t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xdc table 20.15. pca0cpm2 register bit descriptions bit name function 7 pwm16 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecom comparator function enable. this bit enables the comparator function. 5 capp capture positive function enable. this bit enables the positive edge capture capability. 4 capn capture negative function enable. this bit enables the negative edge capture capability. 3 mat match function enable. this bit enables the match function. when en ab led, matches of the pca counter with a module's capture/compare regist er cause the ccf2 bit in the pca0md register to be set to logic 1. 2 tog toggle function enable. this bit enables the toggle function. when ena ble d, matches of the pca counter with the capture/compare register cause the logic leve l on the cex2 pin to toggle. if the pwm bit is also set to logic 1, the module operates in frequency output mode. 1 pwm pulse width modulation mode enable. this bit enables the pwm function. when enabled, a pulse width modulated signal is out - put on the cex2 pin. 8 to 11-bit pwm is used if pwm16 is cleared; 16-bit mode is used if pwm16 is set to logic 1. if the tog bit is also set, the module operates in frequency output mode. 0 eccf capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccf2) interrupt. 0: disable ccf2 interrupts. 1: enable a capture/compare flag interrupt request when ccf2 is set.
rev. 1.0 173 register 20.14. pca0cpl1: pca capture module low byte bit 7 6 5 4 3 2 1 0 name pca0cpl1 ty pe rw r e s e t00000000 sfr address: 0xe9 table 20.16. pca0cpl1 register bit descriptions bit name function 7:0 pca0cpl1 pca capture module low byte. the pca0cpl1 register holds the low byte (lsb) of the 16-bit capture module.this reg - ister address also allows access to the low byte of the corresponding pca channels a uto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will clear the modules ecom bit to a 0.
174 rev. 1.0 register 20.15. pca0cph1: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cph1 ty pe rw r e s e t00000000 sfr address: 0xea table 20.17. pca0cph1 register bit descriptions bit name function 7:0 pca0cph1 pca capture module high byte. the pca0cph1 register holds the high byte (m sb) of the 16-bit capture module.this register address also allows access to the high byte of the corresponding pca channels auto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will set the modules ecom bit to a 1.
rev. 1.0 175 register 20.16. pca0cpl2: pca capture module low byte bit 7 6 5 4 3 2 1 0 name pca0cpl2 ty pe rw r e s e t00000000 sfr address: 0xeb table 20.18. pca0cpl2 register bit descriptions bit name function 7:0 pca0cpl2 pca capture module low byte. the pca0cpl2 register holds the low byte (lsb) of the 16-bit capture module.this reg - ister address also allows access to the low byte of the corresponding pca channels a uto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will clear the modules ecom bit to a 0.
176 rev. 1.0 register 20.17. pca0cph2: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cph2 ty pe rw r e s e t00000000 sfr address: 0xec table 20.19. pca0cph2 register bit descriptions bit name function 7:0 pca0cph2 pca capture module high byte. the pca0cph2 register holds the high byte (m sb) of the 16-bit capture module.this register address also allows access to the high byte of the corresponding pca channels auto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will set the modules ecom bit to a 1.
rev. 1.0 176 21. port i/o (port 0, port 1, port 2, crossbar, and port match) digital and analog resources on the c8051f85x/86x fam ily are externally available on the device?s multi- purpose i/o pins. port pins p0.0-p1.7 can be defined as general-purpose i/o (gpio), assigned to one of the internal digital resources through the crossbar, or assigned to an analog function. port pins p2.0 and p2.1 can be used as gpio. port pin p2.0 is shared with the c2 interface data signal (c2d). the designer has complete control over which functions are assign ed, limited only by the number of physical i/o pins. this resource assignment flexibility is achieved through the use of a prio rity crossbar dec oder. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder (figure 21.2 and figure 21.3). the registers xbr0, xbr1 and xbr2 are used to select internal digital functions. the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1). additionally, each bank of port pins (p0, p1, and p2) has two selectable drive strength settings. figure 21.1. port i/o functional block diagram p2.1 p2.0 / c2d port 2 control & config uart0 spi0 smbus0 cmp0 out sysclk pca (cexn) timer 0 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.7 p1.0 port 1 control & config cmp1 out timer 1 timer 2 2 4 2 2 2 1 3 pca (eci) 1 1 1 1 priority crossbar decoder adc0 in cmp0/1 in int0 / int1 port match p0.0 / vref p0.1 / agnd p0.2 p0.3 / extclk p0.4 p0.6 / cnvstr p0.7 p0.5 port 0 control & config
177 rev. 1.0 21.1. general port i/o initialization port i/o initialization cons ists of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) for all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals. 5. enable the crossbar (xbare = ?1?). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process save s power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. the output driver characteristics of the i/o pins are defined using the port output mode registers (pnmdout). each port output driver can be configured as either open drain or push -pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bit in xbr1 is ?0 ?, a weak pullup is enabled for all port i/o configured as open- drain. weakpud does not affect the push-pull port i/o. furthermo re, the weak pullup is turned off on an output that is driving a ?0? to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp riate values to select the digital i/o functions required by the design. se tting the xbare bit in xbr2 to ?1? enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode table; as an alternative, silicon labs provides configuration utility soft ware to determine the port i/o pin- assignments based on the crossbar register settings. the crossbar must be enabled to use port pins as st andard port i/o in output mode. port output drivers of all crossbar pins are disabled whenever the crossbar is disabled.
rev. 1.0 178 21.2. assigning port i/o pins to analog and digital functions port i/o pins can be assigned to various analog, digita l, and external interrupt functions. the port pins assigned to analog functions should be configured for analog i/o, and port pins assigned to digital or external interrupt functions should be configured for digital i/o. 21.2.1. assigning port i/o pins to analog functions table 21.1 shows all available analog functions that re quire port i/o assignme nts. table 21.1 shows the potential mapping of port i/o to each analog function. 21.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigne d to digital functions or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. table 21.2 shows all digital functions available through the crossbar and the potential mapping of port i/o to each function. table 21.1. port i/o assignment for analog functions analog function potentially assignable port pins sfr(s) used for assignme nt adc input p0.0 - p1.7 adc0mx, pnskip, pnmdin comparator0 input p0.0 - p1.7 cpt0mx, pnskip, pnmdin comparator1 input p0.0 - p1.7 cpt1mx, pnskip, pnmdin voltage reference (vref) p0.0 ref0cn, pnskip, pnmdin reference ground (agnd) p0.1 ref0cn, pnskip, pnmdin table 21.2. port i/o assignment for digital functions digital function potentially assign able por t pins sfr(s) used for as signment uart0, spi0, smbus0, cp0, cp0a, cp1, cp1a, sysclk, pca0 (cex0- 2 an d eci), t0 , t1 or t2. any port pin available for assignment by the cro ssbar. this includes p0.0 - p1.7 pins which have their pnskip bit set to ?0?. note: the cros sbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1, xbr2 any pin used for gpio p0.0 - p2.1 p0skip, p1skip, p2sk ip
179 rev. 1.0 21.2.3. assigning port i/o pins to fixed digital functions fixed digital functions include external clock input as well as external event trigger functions, which can be used to trigger events such as an adc conversion, fire an interrupt or wake th e device from idle mode when a transition occurs on a digital i/o pin. the fixed digital functions do not require dedicated pins and will function on both gpio pins and pi ns in use by the crossbar. fixed digital functions cannot be used on pins configured for analog i/o. table 21.3 shows all available fixed digital functions and the potential mapping of port i/o to each function. table 21.3. port i/o assignment for fixed digital functions function potentially assign able por t pins sfr(s) used for as signment external interrupt 0 p0.0 - p0.7 it01cf external interrupt 1 p0.0 - p0.7 it01cf conversion start (cnvstr) p0.6 adc0cn external clock input (extclk) p0.3 oscxcn port match p0.0 - p1.7 p0mask, p0mat p1mask, p1mat
rev. 1.0 180 21.3. priority crossbar decoder the priority crossbar decoder assigns a priority to eac h i/o function, starting at the top with uart0. when a digital resource is selected, the least-significan t unassigned port pin is assigned to that resource (excluding uart0, which is always at pins p0.4 and p0.5 ). if a port pin is assigned, the crossbar skips that pin when assigning the next sele cted resource. additionally, the cr ossbar will skip port pins whose associated bits in the pnskip registers are set. the pnsk ip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.0 if vr ef is used, p0.1 if agnd is used, p0.3 if the extclk input is enabled, p0.6 if the adc is configured to use the external conversion start signal (cnvstr), and any selected adc or compar ator inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. figure 21.2 shows all of the potential peripheral-to- pin assignments available to the crossbar. note that this does not mean any peripheral can always be assigned to the highlig hted pins. the actual pin assignments are determined by the priority of the enabled peripherals. figure 21.2. crossbar priority decoder - possible pin assignments uart0-tx uart0-rx sysclk pca0-cex0 pca0-cex1 pca0-cex2 pca0-eci timer0-t0 timer1-t1 0 1 2 3 4 5 6 7 p0 port pin number 0 0 0 0 0 0 0 0 p0skip pin skip settings spi0-sck spi0-miso spi0-mosi spi0-nss* 0 1 2 3 4 5 6 7 p1 0 0 0 0 0 0 0 0 p1skip 0 1 p2 the crossbar peripherals are assigned in priority order from top to bottom. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be ?skipped? by setting the corresponding bit in pnskip to 1. * nss is only pinned out when the spi is in 4-wire mode. smb0-sda smb0-scl qsop-24 package vref extclk cnvstr c2d qfn-20 package pins not available on crossbar timer2-t2 cmp0-cp0 cmp0-cp0a cmp1-cp1 cmp1-cp1a n/a soic-16 package n/a n/a n/a n/a
181 rev. 1.0 registers xbr0, xbr1 and xbr2 are used to assign the di gital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assigns both pins associated with the smbus (sda and scl); when uart0 is selected, the crossbar as signs both pins associated with uart0 (tx and rx). uart0 pin assignments are fixed for bootloading pur poses: uart0 tx is always assigned to p0.4; uart0 rx is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. figure 21.3 shows an example of the resulting pin assignments of the device with uart0 and spi0 enabled and the extclk (p0.3) pin skipped (p0skip = 0x08). uart0 is the highest priority and it will be assigned first. the uart0 pins can only appear on p0 .4 and p0.5, so that is where it is assigned. the next-highest enabled peripheral is spi0. p0.0, p0.1 and p0.2 are free, so spi0 takes these three pins. the fourth pin, nss, is routed to p0.6 because p0.3 is skipped and p0.4 and p0.5 are already occupied by the uart. the other pins on the device are available for use as general-purpose digital i/o or analog functions. figure 21.3. crossbar priority decoder example uart0-tx uart0-rx sysclk pca0-cex0 pca0-cex1 pca0-cex2 pca0-eci timer0-t0 timer1-t1 0 1 2 3 4 5 6 7 p0 port pin number 0 0 0 1 0 0 0 0 p0skip pin skip settings spi0-sck spi0-miso spi0-mosi spi0-nss* 0 1 2 3 4 5 6 7 p1 0 0 0 0 0 0 0 0 p1skip 0 1 p2 the crossbar peripherals are assigned in priority order from top to bottom. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be ?skipped? by setting the corresponding bit in pnskip to 1. * nss is only pinned out when the spi is in 4-wire mode. smb0-sda smb0-scl qsop-24 package vref extclk cnvstr c2d qfn-20 package pins not available on crossbar timer2-t2 cmp0-cp0 cmp0-cp0a cmp1-cp1 cmp1-cp1a n/a soic-16 package n/a n/a n/a n/a
rev. 1.0 182 note: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1? nssmd0 bits in register spi0cn. ac cording to the spi mode, the nss signal may or may not be routed to a port pin. the order in which smbus pins are a ssigned is defined by the swap bit in the smb0tc register.
183 rev. 1.0 21.4. port i/o m odes of operation port pins are configured by firmware as digital or anal og i/o using the pnmdin registers. on reset, all port i/o cells default to a high impedance state with weak pu ll-ups enabled. until the crossbar is enabled, both the high and low port i/o drive circuits are explicitly disa bled on all crossbar pins. port pins configured as digital i/o may still be used by anal og peripherals; however, this pr actice is not recommended and may result in measurement errors. 21.4.1. configuring port pins for analog modes any pins to be used for analog functions should be config ured for analog mode. when a pin is configured for analog i/o, its weak pullup, digital driver, and digital receiver are disabled. port pins configured for analog functions will always read ba ck a value of ?0? in the corresponding pn port latch register. to configure a pin as analog, the following steps should be taken: 1. clear the bit associated with the pin in the pnmdin register to ?0?. this selects analog mode for the pin. 2. set the bit associat ed with the pin in the pn register to ?1?. 3. skip the bit associated with the pin in the pnski p register to ensure the crossbar does not attempt to assign a function to the pin. 21.4.2. configurin g port pins for digital modes any pins to be used by digital peripherals or as gpio should be configured as digital i/o (pnmdin.n = ?1?). fo r digital i/o pins, one of two output modes (pus h-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = ?1?) drive the port pad to the supply rails based on the output logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to the low-side rail when the output logic value is ?0? and become high impedance inputs (both high low drivers turned off) when the output logic value is ?1?. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the high-side rail to ensure the digital input is at a de fined logic state. weak pull-ups are disabled when the i/o cell is driven low to minimize power consumptio n, and they may be globally disabled by setting weakpud to ?1?. the user should ensure that digital i/o are alwa ys internally or externally pu lled or driven to a valid logic state to minimize power consumption. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic va lue of the port pin. to configure a pin as digital input: 1. set the bit associated with the pin in the pnmdin register to ?1?. this selects digital mode for the pin. 2. clear the bit associated with the pin in the pn mdout register to ?0?. this configures the pin as open-drain. 3. set the bit associated with the pin in the pn register to ?1?. this tells the output driver to ?drive? logic high. because the pin is configured as open-drain, the high-side driver is not active, and the pin may be used as an input. open-drain outputs are configured exactly as digital inputs. however, the pin may be driven low by an assigned peripheral, or by writing ?0? to the associat ed bit in the pn register if the signal is a gpio. to configure a pin as a digital, push-pull output: 1. set the bit associated with the pin in the pnmdin register to ?1?. this selects digital mode for the pin. 2. set the bit associated with the pin in the pnmdout register to ?1?. this configures the pin as push- pull. if a digital pin is to be used as a general-purpose i/o, or with a digita l function that is not part of the crossbar, the bit associated with the pin in the pnski p register can be set to ?1? to ensure the crossbar does not attempt to assign a function to the pin.
rev. 1.0 184 21.4.3. port drive strength port drive strength can be controlled on a port-by-port basis using the prtdrv register. each port has a bit in prtdrv to select the high or low drive strength setting for all pins on that port. by default, all ports are configured for high drive strength. figure 21.4. port i/o cell block diagram 21.5. port match port match functionality allows system events to be triggered by a logic value change on one or more port i/o pins. a software controlled value stored in the pnmatch registers specifies the expected or normal logic values of the associated port pins (for exam ple, p0match.0 would correspond to p0.0). a port mismatch event occurs if the logic levels of the port ?s input pins no longer match the software controlled value. this allows software to be notified if a certain change or pattern occurs on the input pins regardless of the xbrn settings. the pnmask registers can be used to individually se lect which pins should be compared against the pnmatch registers. a port mi smatch event is generated if (pn & pn mask) does not equal (pnmatch & pnmask) for all ports with a pnmat and pnmask register. a port mismatch event may be used to generate an interrupt or wake the device from idle mode. see the interrupts and power options chapters for more details on interrupt and wake-up sources. 21.6. direct read/write access to port i/o pins all port i/o are accessed through corresponding spec ial function registers (sfrs) that are both byte addressable and bit addressable. when writing to a por t, the value written to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jb c, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indivi dual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. gnd vdd vdd (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable)
185 rev. 1.0 21.7. port i/o and pin configur ation control registers register 21.1. xbr0: port i/o crossbar 0 bit 7 6 5 4 3 2 1 0 name syscke cp1ae cp1e cp0ae cp0e smb0e spi0e urt0e t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xe1 table 21.4. xbr0 register bit descriptions bit name function 7 syscke sysclk output enable. 0: sysclk unavailable at port pin. 1: sysclk output routed to port pin. 6 cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. 5 cp1e comparator1 output enable. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. 4 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 3 cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 2 smb0e smbus0 i/o enable. 0: smbus0 i/o unavailable at port pins. 1: smbus0 i/o routed to port pins. 1 spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. the spi can be assigned either 3 or 4 gpio pins. 0 urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx, rx routed to port pins p0.4 and p0.5.
rev. 1.0 186 register 21.2. xbr1: port i/o crossbar 1 bit 7 6 5 4 3 2 1 0 name reserved t2e t1e t0e ecie pca0me t yper rwrwrwrwrw rw r e s e t00000000 sfr address: 0xe2 table 21.5. xbr1 register bit descriptions bit name function 7:6 reserved must write reset value. 5 t2e t2 enable. 0: t2 unavailable at port pin. 1: t2 routed to port pin. 4 t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 3 t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 2 ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 1:0 pca0me pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins.
187 rev. 1.0 register 21.3. xbr2: port i/o crossbar 2 bit 7 6 5 4 3 2 1 0 name weakpud xbare reserved ty pe rw rw r r e s e t00000000 sfr address: 0xe3 table 21.6. xbr2 register bit descriptions bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5:0 reserved must write reset value.
rev. 1.0 188 register 21.4. prtdrv: port drive strength bit 7 6 5 4 3 2 1 0 name reserved p2drv p1drv p0drv t ype r rwrwrw r e s e t00000111 sfr address: 0xf6 table 21.7. prtdrv register bit descriptions bit name function 7:3 reserved must write reset value. 2 p2drv port 2 drive strength. 0: all pins on p2 use low drive strength. 1: all pins on p2 use high drive strength. 1 p1drv port 1 drive strength. 0: all pins on p1 use low drive strength. 1: all pins on p1 use high drive strength. 0 p0drv port 0 drive strength. 0: all pins on p0 use low drive strength. 1: all pins on p0 use high drive strength.
189 rev. 1.0 register 21.5. p0mask: port 0 mask bit 7 6 5 4 3 2 1 0 name p0mask ty pe rw r e s e t00000000 sfr address: 0xfe table 21.8. p0mask register bit descriptions bit name function 7:0 p0mask port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.x pin logic value is ignored and will cause a port mismatch event. 1: p0.x pin logic value is compared to p0mat.x.
rev. 1.0 190 register 21.6. p0mat: port 0 match bit 7 6 5 4 3 2 1 0 name p0mat ty pe rw r e s e t11111111 sfr address: 0xfd table 21.9. p0mat register bit descriptions bit name function 7:0 p0mat port 0 match value. match comparison value used on p0 pins for bits in p0mask which are set to 1. 0: p0.x pin logic value is compared with logic low. 1: p0.x pin logic value is compared with logic high.
191 rev. 1.0 register 21.7. p0: port 0 pin latch bit 7 6 5 4 3 2 1 0 name p0 ty pe rw r e s e t11111111 sfr address: 0x80 (bit-addressable) table 21.10. p0 register bit descriptions bit name function 7:0 p0 port 0 data. writing this register sets the port latch logi c va lue for the associated i/o pins configured as digital i/o. reading this register returns the logic value at th e pin, regardless if it is configured as output or input.
rev. 1.0 192 register 21.8. p0mdin: port 0 input mode bit 7 6 5 4 3 2 1 0 name p0mdin ty pe rw r e s e t11111111 sfr address: 0xf1 table 21.11. p0mdin register bit descriptions bit name function 7:0 p0mdin port 0 input mode. port pins configured for analog mode have t heir weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.x pin is configured for analog mode. 1: corresponding p0.x pin is configured for digital mode.
193 rev. 1.0 register 21.9. p0mdout: port 0 output mode bit 7 6 5 4 3 2 1 0 name p0mdout ty pe rw r e s e t00000000 sfr address: 0xa4 table 21.12. p0mdout register bit descriptions bit name function 7:0 p0mdout port 0 output mode. these bits are only applicable when the pin is configured for digital mode using the p0 mdin register. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull.
rev. 1.0 194 register 21.10. p0skip: port 0 skip bit 7 6 5 4 3 2 1 0 name p0skip ty pe rw r e s e t00000000 sfr address: 0xd4 table 21.13. p0skip register bit descriptions bit name function 7:0 p0skip port 0 skip. these bits select port pins to be skipped by the crossbar decoder. port pins used for ana - log, special functions or gpio should be skipped. 0: corresponding p0.x pin is not skipped by the crossbar. 1: corresponding p0.x pin is skipped by the crossbar.
195 rev. 1.0 register 21.11. p1mask: port 1 mask bit 7 6 5 4 3 2 1 0 name p1mask ty pe rw r e s e t00000000 sfr address: 0xee table 21.14. p1mask register bit descriptions bit name function 7:0 p1mask port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.x pin logic value is ignored and will cause a port mismatch event. 1: p1.x pin logic value is compared to p1mat.x. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
rev. 1.0 196 register 21.12. p1mat: port 1 match bit 7 6 5 4 3 2 1 0 name p1mat ty pe rw r e s e t11111111 sfr address: 0xed table 21.15. p1mat register bit descriptions bit name function 7:0 p1mat port 1 match value. match comparison value used on p1 pins for bits in p1mask which are set to 1. 0: p1.x pin logic value is compared with logic low. 1: p1.x pin logic value is compared with logic high. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
197 rev. 1.0 register 21.13. p1: port 1 pin latch bit 7 6 5 4 3 2 1 0 name p1 ty pe rw r e s e t11111111 sfr address: 0x90 (bit-addressable) table 21.16. p1 register bit descriptions bit name function 7:0 p1 port 1 data. writing this register sets the port latch logi c va lue for the associated i/o pins configured as digital i/o. reading this register returns the logic value at th e pin, regardless if it is configured as output or input. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
rev. 1.0 198 register 21.14. p1mdin: port 1 input mode bit 7 6 5 4 3 2 1 0 name p1mdin ty pe rw r e s e t11111111 sfr address: 0xf2 table 21.17. p1mdin register bit descriptions bit name function 7:0 p1mdin port 1 input mode. port pins configured for analog mode have t heir weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.x pin is configured for analog mode. 1: corresponding p1.x pin is configured for digital mode. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
199 rev. 1.0 register 21.15. p1mdout: port 1 output mode bit 7 6 5 4 3 2 1 0 name p1mdout ty pe rw r e s e t00000000 sfr address: 0xa5 table 21.18. p1mdout register bit descriptions bit name function 7:0 p1mdout port 1 output mode. these bits are only applicable when the pin is configured for digital mode using the p1 mdin register. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
rev. 1.0 200 register 21.16. p1skip: port 1 skip bit 7 6 5 4 3 2 1 0 name p1skip ty pe rw r e s e t00000000 sfr address: 0xd5 table 21.19. p1skip register bit descriptions bit name function 7:0 p1skip port 1 skip. these bits select port pins to be skipped by the crossbar decoder. port pins used for ana - log, special functions or gpio should be skipped. 0: corresponding p1.x pin is not skipped by the crossbar. 1: corresponding p1.x pin is skipped by the crossbar. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
201 rev. 1.0 register 21.17. p2: port 2 pin latch bit 7 6 5 4 3 2 1 0 name reserved p2 ty pe r rw r e s e t00000011 sfr address: 0xa0 (bit-addressable) table 21.20. p2 register bit descriptions bit name function 7:2 reserved must write reset value. 1:0 p2 port 2 data. writing this register sets the port latch logi c va lue for the associated i/o pins configured as digital i/o. reading this register returns the logic value at th e pin, regardless if it is configured as output or input. note: port 2 consists of 2 bits (p2.0-p2.1) on qsop24 devices and 1 bit (p2.0) on qfn20 and soic16 packages.
rev. 1.0 202 register 21.18. p2mdout: port 2 output mode bit 7 6 5 4 3 2 1 0 name reserved p2mdout ty pe r rw r e s e t00000000 sfr address: 0xa6 table 21.21. p2mdout register bit descriptions bit name function 7:2 reserved must write reset value. 1:0 p2mdout port 2 output mode. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. note: port 2 consists of 2 bits (p2.0-p2.1) on qsop24 devices and 1 bit (p2.0) on qfn20 and soic16 packages.
203 rev. 1.0
rev. 1.0 202 22. reset sources and supply monitor reset circuitry allows the controller to be easily placed in a predefined default condition. upon entering this reset state, the following events occur: ?? cip-51 halts program execution ?? special function registers (sfrs) are in itialized to their defined reset values ?? external port pins are placed in a known state ?? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lost, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain, low-drive mode. weak pullups are enabled during and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. note that during a power-on event, there may be a short delay before the por circuitry fires and the rst pin is driven low. during that time, the rst pin will be weakly pulled to the v dd supply pin. on exit from the reset state, the program counter (pc) is reset, the watchdog timer is enabled and the system clock defaults to the internal oscillator. program execution begin s at location 0x0000. figure 22.1. reset sources reset sources rst supply monitor or power-up missing clock detector watchdog timer software reset comparator 0 system reset flash error
203 rev. 1.0 22.1. power-on reset during power-up, th e por circuit will fire. when por fires, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . two delays are present during the supply ramp time. first, a delay will occur before the por ci rcuitry fires and pulls the rst pin low. a second delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 22.2. plots the power-on reset timing. for ramp times less than 1 ms, the power-on reset time (t por ) is typically less than 0. 3 ms. additionally, the power supply must reach v rst before the por circuit will re lease the device from reset. on exit from a power-on reset, the porsf flag (rstsr c.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was the cause of reset. the content of internal data memory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 22.2. power-on reset timing power-on reset rst t volts logic high logic low t por v d d
rev. 1.0 204 22.2. power-fail reset / supply monitor c8051f85x/86x devices have a supply monitor that is enabled and selected as a reset source after each power-on. the supply monitor senses the voltage on the device vdd supply and can generate a reset if the supply drops below the corresponding threshold. this monito r is enabled and enabled as a reset source after initial power-on to protect the device until vdd is an adequate and stable voltage. when enabled and selected as a reset source, any power down transition or power irregularity that causes vdd to drop below the rese t threshold will drive the rst pin low and hold the core in a reset state. when vdd returns to a level above the rese t threshold, the monitor will release th e core from the reset state. the reset status can then be read using the device reset sources module. after a power-fail reset, the porf flag reads 1 and all of the other reset flags in the rstsrc register are indeterminate. the power-on reset delay (t por ) is not incurred after a supply monitor reset. the contents of ram should be presumed invalid after a vdd monitor reset. the enable state of the vdd supply monitor and its sele ction as a reset source is not altered by device resets. for example, if the vdd supp ly monitor is de-selected as a reset source and disabled by software, and then firmware performs a softwa re reset, the vdd supply monitor will remain disabled and de-selected after the reset. to protect the integrity of flash contents, the vdd supply monitor must be enabled and selected as a reset source if software contains routines that erase or write flash memory. if the vdd supply monitor is not enabled, any erase or write performed on flas h memory will be ignored. figure 22.3. vdd supply monitor threshold 22.3. enabling the vdd monitor the vdd supply monitor is enabled by default. however, in systems which disable the supply monitor, it must be enabled before selecting it as a reset source. selecting the vdd supply monitor as a reset source before it has stabilized may generate a system reset. in systems where th is reset would be undesirable, a delay should be introduced between enabling the vdd supply monitor and selecting it as a reset source. no delay should be introduced in systems where soft ware contains routines th at erase or write flash memory. the procedure for enabling the vdd supply monitor and selecting it as a reset source is: t volts vdd reset threshold (v rst ) vdd monitor reset rst
205 rev. 1.0 1. enable the vdd supply monitor (vmonen = 1). 2. wait for the vdd supply monitor to stabilize (optional). 3. enable the vdd monitor as a reset source in the rstsrc register. 22.4. external reset the external rst pin provides a means for external circuitr y to force the device into a reset state. asserting an active-low signal on the rst pin generates a reset; an exte rnal pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-i nduced resets. the pinrsf flag is set on exit from an external reset. 22.5. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than the mcd time window, the on e-shot will time out and generate a reset. after a mcd reset, the mcdrsf flag will read 1, signifying the m cd as the reset source; otherwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock detector; writing a 0 disables it. the state of the rst pin is unaffected by this reset. 22.6. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag. comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted reset. the comparator0 rese t is active-low: if the non-inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, the c0rsef flag will read 1 signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. 22.7. watchdog timer reset the programmable watchdog timer (wdt) can be used to prevent software from running out of control during a system malfunction. the wdt function can be enabled or disabled by software as described in the watchdog timer section. if a sys tem malfunction prevents user software from updating the wdt, a reset is generated and the wdtrsf bit is set to ?1?. the state of the rst pin is unaffected by this reset. 22.8. flash error reset if a flash read/write/erase or progra m read targets an illegal address, a system reset is generated. this may occur due to any of the following: ?? a flash write or erase is attempted above user code space. ?? a flash read is attempted above user code space. ?? a program read is attempted above user code sp ace (i.e. a branch instruction to the reserved area). ?? a flash read, write or erase attempt is re stricted due to a flash security setting. the ferror bit is set following a flash error reset. the state of the rst pin is unaffected by this reset. 22.9. software reset software may force a reset by writing a 1 to the swrsf bit. the swrsf bit will read 1 following a software forced reset. the state of the rst pin is unaffected by this reset.
rev. 1.0 206 22.10. reset sources control registers register 22.1. rstsrc: reset source bit 7 6 5 4 3 2 1 0 name reserved ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf t ype r r rw rw r rw rw r r e s e t0xxxxxxx sfr address: 0xef table 22.1. rstsrc register bit descriptions bit name function 7 reserved must write reset value. 6 ferror flash error reset flag. this read-only bit is set to 1 if a flash re ad/w rite/erase error c aused the last reset. 5 c0rsef comparator0 reset enable and flag. read: this bit reads 1 if comparator0 caused the last reset. write: writing a 1 to this bit enables co mp arator0 (active-low) as a reset source. 4 swrsf software reset force and flag. read: this bit reads 1 if last reset was caused by a write to swrsf. write: writing a 1 to this bit forces a system reset. 3 wdtrsf watchdog timer reset flag. this read-only bit is set to 1 if a watchd og timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. read: this bit reads 1 if a missing clock detector timeout caused the last reset. write: writing a 1 to this bit enables the mi ssing clock detector. the mcd triggers a reset if a missing clock condition is detected. 1 porsf power-on / supply monitor reset flag, and supply monitor reset enable. read: this bit reads 1 anytime a power-on or supply monitor reset has occurred. write: writing a 1 to this bit enables the supply monitor as a reset source. 0 pinrsf hw pin reset flag. this read-only bit is set to 1 if the rst pin caused the last reset. notes: 1. reads and writes of the rstsrc register access different logic in the device. reading the register always returns status information to indicate the source of the most recent reset. writing to the register activates certain options as reset sources. it is recommended to not use any kind of read-modify-write operation on this register. 2. when the porsf bit reads back 1 all other rstsrc flags are indeterminate. 3. writing 1 to the porsf bit when the supply monitor is not enabled and st abilized may cause a system reset.
207 rev. 1.0 22.11. supply monito r control registers register 22.2. vdm0cn: supply monitor control bit 7 6 5 4 3 2 1 0 name vdmen vddstat reserved ty pe rw r r r e s e txxxxxxxx sfr address: 0xff table 22.2. vdm0cn register bit descriptions bit name function 7 vdmen supply monitor enable. this bit turns the supply monitor circuit on/off. the supply monitor cannot generate sys - tem resets until it is also selected as a rese t source in register rstsrc. selecting the supply monitor as a reset sour ce before it has st abilized may generate a system reset. in systems where this reset would be undesirable, a delay should be introduced between enabling the supply monitor and selecting it as a reset source. 0: supply monitor disabled. 1: supply monitor enabled. 6 vddstat supply status. this bit indicates the current power s upp ly status (supply monitor output). 0: v dd is at or below the supply monitor threshold. 1: v dd is above the supply monitor threshold. 5:0 reserved must write reset value.
rev. 1.0 208 23. serial peripheral interface (spi0) the serial peripheral interface (spi0) provides acce ss to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in bo th 3-wire or 4-wire modes, and supports multiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in mast er mode, or disabled for 3-wire operation. additional general purpose port i/o pins can be used to se lect multiple slave devices in master mode. figure 23.1. spi0 block diagram spi0 shift register miso mosi clock rate generator sysclk bus control master or slave sck polarity sck phase nss control sck nss spi0dat tx buffer rx buffer
209 rev. 1.0 23.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 23.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to the slave. this signal is an output when spi0 is operating as a master and an input w hen spi0 is operating as a slave. da ta is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 23.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave d evice and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operating as a master and an output when spi0 is operating as a slave. data is transferred most- significant bit first. the miso pin is placed in a hi gh-impedance state when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not selected. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 23.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the ma ster and slave on the mosi and miso lines. spi0 generates this signal when operating as a master. t he sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 23.1.4. slave select (nss) the function of the slave-select (nss) signal is d ependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always se lected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disa bles the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 operates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determines wh at logic level the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 23.2, figure 23.3, and figure 23.4 for typi cal connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device.
rev. 1.0 210 23.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, n ss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an interrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi- master mode, slave devices can be addressed indivi dually (if needed) using general-purpose i/o pins. figure 23.2 shows a connection diagram between tw o master devices and a single slave in multiple- master mode. 3-wire single-master mode is active when nssmd1 ( spi0cn.3) = 0 and nssmd0 (s pi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 23.3 shows a connection diagram between a master dev ice in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 23.4 shows a connection diagram for a master device and a slave device in 4-wire mode.
211 rev. 1.0 figure 23.2. multiple-master mode connection diagram figure 23.3. 3-wire single master and 3-wire single slave mode connection diagram figure 23.4. 4-wire single master mode and 4-wire slave mode connection diagram master device 1 miso mosi sck nss slave device miso mosi sck nss master device 2 miso mosi sck nss port pin port pin slave device master device miso mosi sck miso mosi sck slave device master device miso mosi sck miso mosi sck nss nss
rev. 1.0 212 23.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin and out through th e miso pin by a master device controlling the sck signal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift register, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is rese t on a falling edge of nss. note that the nss signal must be driven low at least 2 system clocks be fore the first active edge of sck for each byte transfer. figure 23.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. the 3-wire slave mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 23.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 23.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ?? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ?? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmit buffe r will not be written.this flag can occur in all spi0 modes. ?? the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disabl e spi0 and allow another master device to access the bus. ?? the receive overrun flag rxovrn (spi0cn.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a pr evious transfer. the new byte is not transferred to the receive buff er, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 23.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0
213 rev. 1.0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 23.5. for slave mode, the clock and data relationships are shown in figure 23.6 and figure 23.7. note that ckpha should be set to 0 on both the master and slave spi when communicat ing between two silicon labs c8051 devices. the spi0 clock rate register (spi0ckr) controls the master mode serial cl ock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a slave, the ma ximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master iss ues sck, nss (in 4-wire slave mode), and the serial input data synchronously with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wa nts to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex oper ation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is pr ovided that the master issues sck, nss, and the serial input data synchronously with the slave?s system clock. figure 23.5. master mode data/clock timing sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode)
rev. 1.0 214 figure 23.6. slave mode data/clock timing (ckpha = 0) figure 23.7. slave mode data/clock timing (ckpha = 1) 23.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
215 rev. 1.0 figure 23.8. spi master timing (ckpha = 0) figure 23.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
rev. 1.0 216 figure 23.10. spi slave timing (ckpha = 0) figure 23.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
217 rev. 1.0 table 23.1. spi slave timing parameters parameter description min max units master mode timing (s ee figure 23.8 and figure 23.9 ) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figure 23.10 and figure 23.11 ) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk).
rev. 1.0 218 23.7. spi control registers register 23.1. spi0cfg: spi0 configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt t y p err wr wr wrrrr r e s e t00000111 sfr address: 0xa1 table 23.2. spi0cfg register bit descriptions bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. 1: data centered on second edge of sck period. 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is hi gh (slave not selected). this bit does not indi - cate the instantaneous value at the nss pin, but rather a de-glitched version of the pin in put. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is pr esent on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been transferred in/out of the shif t register, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to prov ide maximum settling time for the slave device.
219 rev. 1.0 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the receive buf fer has been read and contains no new information. if there is new information available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. table 23.2. spi0cfg register bit descriptions bit name function note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to prov ide maximum settling time for the slave device.
rev. 1.0 220 register 23.2. spi0cn: spi0 control bit 7 6 5 4 3 2 1 0 name spif wcol modf rxovrn nssmd txbmt spien t ype rw rw rw rw rw r rw r e s e t00000110 sfr address: 0xf8 (bit-addressable) table 23.3. spi0cn register bit descriptions bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at th e end of a data transfer. if spi interrupts are enabled, an interrupt will be generated. this bit is not automatically cl eared by hardware, and must be cleared by software. 6 wcol write collision flag. this bit is set to logic 1 if a write to spi0d a t is attempted when txbmt is 0. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be written. if spi interrupts are en abled, an interrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware when a mast er mode collision is detected (nss is low, msten = 1, and nssmd = 01). if spi interrupts are enabled , an interrupt will be generated. this bit is not automatically cl eared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware when the receive buffer still ho lds unread data from a previous transfer and the last bit of the curr ent transfer is shifted into the spi0 shift reg - ister. if spi interrupts are enabled, an interrupt will be generated. this bit is not automat - ically cleared by hardware, and must be cleared by software. 3:2 nssmd slave select mode. selects between the following nss operation modes: 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efau lt). nss is an input to the device. 10: 4-wire single-master mode. nss is an output and logic low. 11: 4-wire single-master mode. ns s is an output and logic high. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new data has been written to the transmit buf fer. when data in the transmit buffer is transferred to the spi shift regist er, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
221 rev. 1.0 0 spien spi0 enable. 0: spi disabled. 1: spi enabled. table 23.3. spi0cn register bit descriptions bit name function
rev. 1.0 222 register 23.3. spi0ckr: spi0 clock rate bit 7 6 5 4 3 2 1 0 name spi0ckr ty pe rw r e s e t00000000 sfr address: 0xa2 table 23.4. spi0ckr register bit descriptions bit name function 7:0 spi0ckr spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is config - ured for master mode operation. the sck clock frequency is a divided version of the sys tem clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 f sck sysclk 2 spi0ckr 1 + () ----------------------------------------------- =
223 rev. 1.0 register 23.4. spi0dat: spi0 data bit 7 6 5 4 3 2 1 0 name spi0dat ty pe rw r e s e t00000000 sfr address: 0xa3 table 23.5. spi0dat register bit descriptions bit name function 7:0 spi0dat spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0 - dat places the data into the transmit buffer and initiates a transfer when in master mode. a re ad of spi0dat returns the contents of the receive buffer.
rev. 1.0 222 24. system management bus / i 2 c (smbus0) the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, versi on 1.1, and compatible with the i 2 c serial bus. reads and writes to the smbus by the system contro ller are byte oriented with the smbus interface autonomously controlling the serial tr ansfer of the data. data can be tr ansferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending th e clock-low duration is available to accommodate devices with different speed capabilities on the same bus. the smbus may operate as a master and/or slave, and may function on a bus with multiple masters. the smbus provides control of sda (serial data), scl (ser ial clock) generation and sy nchronization, arbitration logic, and start/stop control and generation. the smbus peripherals can be fully driven by software (i.e., software accepts/rejects slave addresses, and generates acks), or hardware slave address recognition and automatic ack generation can be enabled to minimize software overhead. a block diagram of the smbus0 peripheral is shown in figure 24.1. figure 24.1. smbus0 block diagram smbus0 slave address recognition smb0dat master scl clock generation shift register sda scl state control logic si timers 0, 1 or 2 scl low timer 3 data / address
223 rev. 1.0 24.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including sp ecifications), ph ilips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bu s specification?version 1. 1, sbs implementers forum. 24.2. smbus configuration figure 24.2 shows a typical smbus configuration. th e smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. however, the maximum voltage on any port pin must conform to the electrical characteristic s specifications. the bi- directional scl (serial clock) and sd a (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. every device connected to the bus must have an open- drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limit ed only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 24.2. typical smbus configuration 24.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbi tration. it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 24.3). if the receiving de vice does not ack, the transmitting device will read a nack (not acknowledge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl
rev. 1.0 224 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmits the slave address and direction bit. if the transaction is a write operation from the master to th e slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations, the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop co ndition to terminate the transaction a nd free the bus. figur e 24.3 illustrates a typical smbus transaction. figure 24.3. smbus transaction 24.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or d ata byte to another device on the bus. a device is a ?receiver? when an ad dress or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 24.3.2. arbitration a master may start a transfer only if the bus is free. th e b us is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?24.3.5. scl high (smbus free) timeout? on page 225). in the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master a ttempting the high will detect a lo w sda and lose the arbitration. the winning master continues its transmission without interruption; the losing ma ster becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destructive: one device always wins, and no data is lost. 24.3.3. clock low extension smbus provides a clock synchronizati on mec hanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 24.3.4. scl low timeout if the scl line is held low by a slave device on the bus, n o further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that hav e detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
225 rev. 1.0 for the smbus0 interface, timer 3 is used to implement scl low timeouts. the scl low timeout feature is enabled by setting the smb0toe bit in smb0cf. the associated timer is forced to reload when scl is high, and allowed to count when scl is low. with the associated timer enabled and configured to overflow after 25 ms (and smb0toe set), the timer interrupt se rvice routine can be used to reset (disable and re- enable) the smbus in the event of an scl low timeout. 24.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if th e scl and sda lines remain high for more that 50 s, the bus is designated as free. when the smb0fte bit in smb0 cf is set, the bus will be co nsidered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implementation. 24.4. using the smbus the smbus can operate in both master and slave mo des. the interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. the smbus interface provides the following application-independent features: ?? byte-wise serial data transfers ?? clock signal generation on scl (master mode only) and sda data synchronization ?? timeout/bus error recognition, as defined by the smb0cf configuration register ?? start/stop timing, detection, and generation ?? bus arbitration ?? interrupt generation ?? status information ?? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver. when a transmitter (i.e., sending address/data, receiving an ack), this inte rrupt is generated after the ack cycle so that software may read the received ack value; when receiving data (i.e., receiving addre ss/data, sending an ack), this interrupt is generated before the ack cycle so that software may define the outgoing ack value. if hardware acknowledgement is enabled, these interrupts are always generated after the ack cycle. se e section 24.5 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. table 24.5 provides a quick smb0cn decoding reference. 24.4.1. smbus conf ig uration register the smbus configuration register (s mb0 cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer).
rev. 1.0 226 the smbcs bit field selects the smbus clock source, wh ich is used only when op erating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 24.1.the selected clock source may be shared by other peripherals so long as the timer is left running at all times. equation 24.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equ ation 24.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 24.2. equation 24.2. typical smbus bit rate figure 24.4 shows the typical scl generation de scribed by equation 24.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will neve r exceed the limits defined by equation equation 24.1. figure 24.4. typical smbus scl generation table 24.1. smbus clock source selection smbcs smbus0 clock source 00 timer 0 overflow 01 timer 1 overflow 10 timer 2 high byte overflow 11 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = scl timer source overflows scl high timeout t low t high
227 rev. 1.0 setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requ irements of 250 ns and 300 ns, respectively. table 24.2 shows the minimum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary for smbus comp liance when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?24.3.4. scl low timeout? on page 224). the smbu s interface will force the associated timer to reload while scl is high, and a llow the timer to count when scl is low. the timer interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 24.4). 24.4.2. smbus pin swap the smbus peripheral is assigned to pins using the pr iority crossbar decoder. by default, the smbus signals are assigned to port pins starting with sd a on the lower-numbered pin, and scl on the next available pin. the swap bit in the smbtc register can be set to 1 to reverse the order in which the smbus signals are assigned. 24.4.3. smbus timing control the sdd field in the smbtc register is used to rest rict th e detection of a st art condition under certain circumstances. in some systems where there is si gnificant mismatch between the impedance or the capacitance on the sda and scl lines, it may be possible for scl to fall after sda during an address or data transfer. such an event can cause a false star t detection on the bus. these kind of events are not expected in a standard smbu s or i2c-compliant system. in most systems this pa rameter should not be adjusted, and it is recommended that it be left at its default value. by default, if the scl falling edge is detected afte r the falling edge of sda (i .e. one sysclk cycle or more), the device will detect this as a start cond ition. the sdd field is used to increase the amount of hold time that is require d between sda and scl falling before a start is recogniz ed. an additio nal 2, 4, or 8 sysclks can be added to prev ent false start detection in s ystems where the bus conditions warrant this. table 24.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgment, the s/ w delay occurs between the time smb0dat or ack is written and when si0 is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero.
rev. 1.0 228 24.4.4. smb0cn control register smb0cn is used to control the interface and to provide status information. the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is transmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a master. writing a 1 to sta will caus e the smbus interface to enter ma ster mode and generate a start when the bus becomes free (sta is not cleared by ha rdware after the start is generated). writing a 1 to sto while in master mode will cause the interface to g enerate a stop an d end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condition. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see table 24.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 24.4.4.1. software ack generation when the ehack bit in register smb0adm is clear ed to 0, the firmware on the device must detect incoming slave addresses and ack or nack the slave address and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, so ftware should write the desired outgoing value to the ack bit before clearing si. a na ck will be generated if software do es not write the ack bit before clearing si. sda will reflect the defined ack value im mediately following a write to the ack bit; however scl will remain low until si is cleared. if a receiv ed slave address is not ac knowledged, further slave events will be ignored until th e next start is detected. 24.4.4.2. hardwa re ack generation when the ehack bit in register smb0adm is set to 1, automatic slave address recognition and ack generation is enabled. more detail about automatic slave address recognition can be found in section 24.4.5. as a receiver, the value currently specified by the ack bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a tr ansmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further slave events will be ignored until the next start is detected, and no interrupt will be generated. table 24.3 lists all sources for hardware changes to the smb0cn bits. refer to table 24.5 for smbus status decoding using the smb0cn register. table 24.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by ha rdware when: master ?? a start is generated. ?? a stop is generated. ?? arbitration is lost. txmode ?? start is generated. ?? smb0dat is written before the start of an smbus frame. ?? a start is detected. ?? arbitration is lost. ?? smb0dat is not written before the start of an smbus frame.
229 rev. 1.0 24.4.5. hardware slave address recognition the smbus hardware has the capability to automatically recognize incoming slav e addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a mast er or slave). more detail on automatic hardware ack generation can be found in section 24.4.4.2. the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register and the smbus slave address mask register. a single address or range of addresses (including the general call address 0x00) can be specified using these two register s. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in a bit of the slave address mask slvm enables a comparison between th e received slave address and the hardware?s slave address slv for that bit. a 0 in a bit of the slave address mask means t hat bit will be treated as a ?don?t care? for comparison purposes. in this case, either a 1 or a 0 value are acceptable on the incoming slave address. additionally, if the gc bit in register smb0adr is set to 1, hardware will recognize the general call address (0x00). table 24.4 shows some example parameter sett ings and the slave addresses that will be recognized by hardware under those conditions. sta ?? a start followed by an address byte is received. ?? must be cleared by software. sto ?? a stop is detected while addressed as a slave. ?? arbitration is lost due to a detected stop. ?? a pending stop is generated. ackrq ?? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ?? after each ack cycle. arblost ?? a repeated start is detected as a master when sta is low (unwanted repeated start). ?? scl is sensed low while attempting to generate a stop or repeated start condition. ?? sda is sensed low while transmitting a 1 (excluding ack bits). ?? each time sin is cleared. ack ?? the incoming ack value is low (acknowledge). ?? the incoming ack value is high (not acknowledge). si ?? a start has been generated. ?? lost arbitration. ?? a byte has been transmitted and an ack/ nack received. ?? a byte has been received. ?? a start or repeated start followed by a slave address + r/w has been received. ?? a stop has been received. ?? must be cleared by software. table 24.3. sources for hardware changes to smb0cn (continued) bit set by hardware when: cleared by hardware when:
rev. 1.0 230 24.4.6. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last dat a byte present on the bus. in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. table 24.4. hardware address recognition examples (ehack = 1) hardware slave address slv slave address mask slvm gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c
231 rev. 1.0 24.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. the position of the ack in terrupt when operating as a receiver depends on whether hardware ack generation is enabled. as a receiver, the interrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. as a transmitter, interrupts occur after the ack, regardless of whet her hardware ack generation is enabled or not. 24.5.1. write se que nce (master) during a write sequence, an smbus master w rites data to a slave device. the master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface generates the start condition and transmits the first by te containing the address of the target slave and the data direction bit. in this ca se the data direction bit (r/w) will be logic 0 (write). the master then transmits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is end ed when the sto bit is set and a stop is generated. the interface will switch to master receiver mode if smb0dat is not written follo wing a master transmitter interrupt. figure 24.5 shows a typical master write sequence . two transmit data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of w hether hardware ack generati on is enabled. figure 24.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
rev. 1.0 232 24.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. the smbus interface generates the start condition and transmits the first by te containing the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be lo gic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the interface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 24.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 24.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
233 rev. 1.0 24.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. if ha rdware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, the hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave receiver mode after receiving a stop . the interface will switch to slave transmitter mode if smb0da t is written while an active slave receiv er. figure 24.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 24.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
rev. 1.0 234 24.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiv er mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are transmitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters sl ave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an ac knowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (an error cond ition may be generated if smb0dat is written following a received nack while in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. the inte rface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 24.8 shows a typi cal slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitte d. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 24.8. typical slave read sequence 24.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. table 24.5 descri bes the typical actions when hardware slave address recognition and ack generation is disabled. table 24.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, txmode, sta, and sto. the shown response options are only the typical responses; application-spec ific procedures are allowed as long as they conform to the smbus specification. highlighted responses are allowed by hardware but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
235 rev. 1.0 table 24.5. smbus status decoding: hardware ack disabled (ehack = 0) mode values read current smbus state typical response options values to wr ite next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 1100 000 a ma ster data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 0 1 x ? 001 a ma ster data or address byte was transmitted; ack received. load next data byte into smb0- dat. 0 0 x 1100 end transfer with stop. 0 1 x ? end transfer with stop and start an other transfer. 1 1 x ? send repeated start. 1 0 x 1110 switch to master receiver mode ( clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi ca te last byte, and send stop. 0 1 0 ? send nack to indi ca te last byte, and send stop followed by start. 1 1 0 1110 send ack followed by repeated st art. 1 0 1 1110 send nack to indi ca te last byte, and send repeated start. 1 0 0 1110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
rev. 1.0 236 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave b yte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x a n illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 0 0 x ? slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with d ata byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 11x l ost arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with d ata byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received addres s. 1 0 0 1110 0001 00 x a stop was detected while addressed as a slave transmitter or slave receiver. clear sto. 0 0 x ? 11x lost a rbitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? table 24.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
237 rev. 1.0 bus error condition 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x l ost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmitting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1 0 0 1110 table 24.6. smbus status decoding: hardware ack enabled (ehack = 1) mode values read current smbus state typical response options values to wr ite next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 1100 000 a ma ster data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 0 1 x ? 001 a ma ster data or address byte was transmitted; ack received. load next data byte into smb0- dat. 0 0 x 1100 end transfer with stop. 0 1 x ? end transfer with stop and start an other transfer. 1 1 x ? send repeated start. 1 0 x 1110 switch to master receiver mode ( clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 table 24.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 1.0 238 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data by te as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a ma ster data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 ? read smb0dat; send stop follo wed by start. 1 1 0 1110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave b yte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x a n illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 0 0 x ? table 24.6. smbus status decoding: hardware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
239 rev. 1.0 slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with da ta byte 0 0 x 0100 01x l ost arbitration as master; slave address + r/w rece ived; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with da ta byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00 x a stop was detected while addressed as a slave transmitter or slave receiver. clear sto. 0 0 x ? 01x lost a rbitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 ? 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0da t. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x l ost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while transmitting a data byte as master. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 table 24.6. smbus status decoding: hardware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 1.0 240 24.7. i2c / smbus cont rol registers register 24.1. smb0cf: smbus0 configuration bit 7 6 5 4 3 2 1 0 name ensmb inh busy exthold smbtoe smbfte smbcs t yperwrw r rwrwrw rw r e s e t00000000 sfr address: 0xc1 table 24.7. smb0cf register bit descriptions bit name function 7 ensmb smbus0 enable. this bit enables the smbus0 interface when set to 1. when enabled, the interface con - stantly monitors the sda and scl pins. 6 inh smbus0 slave inhibit. when this bit is set to logic 1, the smbus0 do es not generate an interrupt when slave events occur. this effectively removes the smbus0 slave from the bus. master mode interrupts are not affected. 5 busy smbus0 busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 whe n a stop or free-timeout is sensed. 4 exthold smbus0 setup and hold time extension enable. this bit controls the sda setup and hold times. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3 smbtoe smbus0 scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus0 forces timer 3 to re load while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only th e high byte of the timer is held in reload while scl is high. timer 3 should be programmed to gener ate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus0 communication. 2 smbfte smbus0 free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if sc l and sda remain high for more than 10 smbus clock source periods.
241 rev. 1.0 1:0 smbcs smbus0 clock source selection. these two bits select the smbus0 clock sour ce, which is used to generate the smbus0 bit rate. see the smbus clock timing section for additional details. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow table 24.7. smb0cf register bit descriptions bit name function
rev. 1.0 242 register 24.2. smb0tc: smbus0 timing and pin control bit 7 6 5 4 3 2 1 0 name swap reserved sdd ty pe rw r rw r e s e t00000000 sfr address: 0xac table 24.8. smb0tc register bit descriptions bit name function 7 swap smbus0 swap pins. this bit swaps the order of the smbus0 pins on the crossbar. 0: sda is mapped to the lower-numbered port pin, and scl is mapped to the higher- n umbered port pin. 1: scl is mapped to the lower-numbered port pin, an d sda is mapped to the higher- numbered port pin. 6:2 reserved must write reset value. 1:0 sdd smbus0 start detection window. these bits increase the hold time requirement between sd a falling and scl falling for start detection. 00: no additional hold time window (0-1 sysclk). 01: increase hold time window to 2-3 sysclks. 10: increase hold time window to 4-5 sysclks. 11: increase hold time window to 8-9 sysclks.
243 rev. 1.0 register 24.3. smb0cn: smbus0 control bit 7 6 5 4 3 2 1 0 name master txmode sta sto ackrq arblost ack si t ype r r rw rw r r rw rw r e s e t00000000 sfr address: 0xc0 (bit-addressable) table 24.9. smb0cn register bit descriptions bit name function 7 master smbus0 master/slave indicator. this read-only bit indicates when the smbus0 is operating as a master. 0: smbus0 operating in slave mode. 1: smbus0 operating in master mode. 6 txmode smbus0 transmit mode indicator. this read-only bit indicates when the smbus0 is operating as a transmitter. 0: smbus0 in receiver mode. 1: smbus0 in transmitter mode. 5 sta smbus0 start flag. when reading sta, a 1 indicates that a start or repeated start condition was detected on th e bus. writing a 1 to the sta bit initiates a start or repeated start on the bus. 4 sto smbus0 stop flag. when reading sto, a 1 indicates that a stop condition was detected on the bus (in slave mo de) or is pending (in master mode). when acting as a master, writing a 1 to the sto bit initiates a stop condition on the bus. th is bit is cleared by hardware. 3 ackrq smbus0 acknowledge request. 0: no ack requested. 1: ack requested. 2 arblost smbus0 arbitration lost indicator. 0: no arbitration error. 1: arbitration error occurred. 1 ack smbus0 acknowledge. when read as a master, the ack bit indica tes whethe r an ack (1) or nack (0) is received during the most recent byte transfer. as a slave, this bit should be written to send an ack (1) or nack (0) to a master r equest. note that the logic level of the ack bit on the smbus interface is inverted from the logic of the register ack bit.
rev. 1.0 244 0 si smbus0 interrupt flag. this bit is set by hardware to indicate that the current smbus0 state machine operation (such as writing a data or address byte) is co mplete. while si is se t, scl0 is held low and smbus0 is stalled. si0 must be cleared by software. clearing si0 initiates the next smbus0 state machine operation. table 24.9. smb0cn register bit descriptions bit name function
245 rev. 1.0 register 24.4. smb0adr: smbus0 slave address bit 7 6 5 4 3 2 1 0 name slv gc t ype rw rw r e s e t00000000 sfr address: 0xd7 table 24.10. smb0adr register bit descriptions bit name function 7:1 slv smbus hardware slave address. defines the smbus0 slave address(es) for aut o matic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm are checked against the incoming address. this allows multiple addresses to be recognized. 0 gc general call address enable. when hardware address recogn ition is enabled (ehac k = 1), this bit will determine whether the general call address (0x00) is also recognized by hardware. 0: general call address is ignored. 1: general call address is recognized.
rev. 1.0 246 register 24.5. smb0adm: smbus0 slave address mask bit 7 6 5 4 3 2 1 0 name slvm ehack t ype rw rw r e s e t11111110 sfr address: 0xd6 table 24.11. smb0adm register bit descriptions bit name function 7:1 slvm smbus0 slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, a nd which bits are ignored. any bit set to 1 in slvm enables comparisons with the corre - sponding bit in slv. bits set to 0 are ignored (can be either 0 or 1 in the incoming a ddress). 0 ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled.
247 rev. 1.0 register 24.6. smb0dat: smbus0 data bit 7 6 5 4 3 2 1 0 name smb0dat ty pe rw r e s e t00000000 sfr address: 0xc2 table 24.12. smb0dat register bit descriptions bit name function 7:0 smb0dat smbus0 data. the smb0dat register contains a byte of dat a to be transmitted on the smbus0 serial interface or a byte that has just been receiv ed on the smbus0 serial interface. the cpu can safely read from or write to this register whenever the si serial interrupt flag is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the s ystem may be in the process of shifting data in/out and the cpu should not attempt to access this register.
rev. 1.0 245 25. timers (timer0, timer1, timer2 and timer3) each mcu in the c8051f85x/86x family includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timers for timing peripherals or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requ ests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 and timer 3 are also identical and offer both 16-bit and split 8-bit timer functionality with auto-r eload capabilities. timer 2 and timer 3 both offer a capture function, but are different in their system-level connections. timer 2 is capable of performing a capture function on an external signal input routed through the crossbar, while the timer 3 capture is dedicated to the low- frequency oscillator output. ta ble 25.1 summarizes the mode s available to each timer. timers 0 and 1 may be clocked by one of five sour ces, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked. timer 0/1 may then be configured to use this pre-sc aled clock signal or the system clock. timer 2 and timer 3 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a frequency of up to one-fourth the system clock frequency can be counted. the input signal need not be periodic, but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. all four timers are capable of clocking other peripherals and triggering events in the system. the individual peripherals select which timer to use for their resp ective functions. table 25.2 summarizes the peripheral connections for each timer. note that the timer 2 and timer 3 high overflows apply to the full timer when operating in 16-bit mode or the high-byte timer when operating in 8-bit split mode. table 25.1. timer modes timer 0 and timer 1 modes timer 2 modes timer 3 modes 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer two 8-bit timers with auto-reload two 8-bit timers with auto-reload 8-bit counter/timer wit h auto-reload input pin capture l ow-frequency oscillator capture two 8-bit counter/timers (timer 0 only) table 25.2. timer peripheral clocking / event triggering function t0 ov erflow t1 over flow t2 high over flow t2 low overflow t3 high ove rflow t3 low ov erflow uart0 baud rate x smbus0 clock rate x x x x smbus0 scl low timeout x pca0 clock x
246 rev. 1.0 adc0 conversion start x x* x* x* x* *note: the high-side overflow is used when the timer is in16-bit mode. the low-side overflow is used in 8-bit mode. table 25.2. timer peripheral clocking / event triggering function t0 overflow t1 overflow t2 high overflow t2 low overflow t3 high overflow t3 low overflow
rev. 1.0 247 25.1. timer 0 and timer 1 timer 0 and timer 1 are each implemented as a16-bit re gister accessed as two se parate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the count er/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie register. timer 1 interrupts can be enabled by setting the et1 bit in the ie register. both counter/ timers operate in one of four primary modes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently for the operating modes described below.
248 rev. 1.0 25.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 interrupts are enabled. the ct0 bit in the tmod register selects the counter/t imer's clock source. when ct0 is set to logic 1, high-to-low transitions at the selected timer 0 inpu t pin (t0) increment the timer register. clearing ct selects the clock defined by the t0m bit in register ckcon. when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source se lected by the clock scale bits in ckcon. setting the tr0 bit enables the timer when either gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in 0pl in register it01cf. setting gate0 to 1 allows the timer to be controlled by the external input signal int0 , facilitating pulse width measurements. setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the /int1 polarity is defined by bit in1pl in register it01cf. figure 25.1. t0 mode 0 block diagram tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care tclk tr0 0 1 0 1 sysclk pre-scaled clock gate0 in0pl xor t0m t0 int0 ct0 tl0 (5 bits) th0 (8 bits) tf0 (interrupt flag)
rev. 1.0 249 25.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the counter/timers are enabled and configured in mode 1 in the same manner as for mode 0.
250 rev. 1.0 25.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8- bit counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts ar e enabled, an interr upt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit enables the timer when either gate0 in the tmod register is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it01cf. figure 25.2. t0 mode 2 block diagram reload tl0 (8 bits) th0 (8 bits) tf0 (interrupt flag) tclk tr0 0 1 0 1 sysclk pre-scaled clock gate0 in0pl xor t0m t0 int0 ct0
rev. 1.0 251 25.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8- bit counter/timers held in tl0 and th0. the counter/ timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, ct0, gate0 and tf0. tl0 can use ei ther the system clock or an external input si gnal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 25.3. t0 mode 3 block diagram tclk tr0 0 1 0 1 sysclk pre-scaled clock gate0 in0pl xor t0m t0 int0 ct0 tr1 tl0 (8 bits) tf0 (interrupt flag) th0 (8 bits) tf1 (interrupt flag)
252 rev. 1.0 25.2. timer 2 and timer 3 timer 2 and timer 3 are functionally equivalent, with the only differences being the top-level connections to other parts of the system, as detailed in table 25.1 and table 25.2. the timers are 16 bits wide, formed by two 8-bit sfrs: tmrnl (low byte) and tmrnh (high byte). each timer may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the tnsplit bit in tmrncn defines the timer operation mode. the timers may be clocked by the syst em clock, the system clock divided by 12, or the external oscillator source divided by 8. note that th e external oscillator sour ce divided by 8 is syn chronized with the system clock. 25.2.1. 16-bit time r w ith auto-reload when tnsplit is zero, the timer operates as a 16-bit tim er with auto-reload. in this mode, the timer may be configured to clock from sysclk , sysclk divided by 12, or the external oscillato r clock source divided by 8. as the 16-bit timer register increm ents and overflows from 0xffff to 0x0000, the 16-bit value in the timer reload registers (tmrnrlh and tmrn rll) is loaded into the main timer count register as shown in figure 25.4, and the high byte overflow fl ag (tfnh) is set. if the ti mer interrupts are enabled, an interrupt will be generated on each timer overflow. additionally, if the timer interrupts are enabled and the tfnlen bit is set, an interrup t will be generated each ti me the lower 8 bits (tmrnl) overflow from 0xff to 0x00. figure 25.4. 16-bit mode block diagram tclk / 8 ysclk / 12 sysclk tmrnl tmrnh reload tclk 0 1 trn 0 1 tnxclk inter tfnl overflow tfnh overflow tnml tmrnrll tmrnrlh tfnlen
rev. 1.0 253 25.2.2. 8-bit timers with auto-reload when tnsplit is set, the timer operates as two 8- bit timers (tmrnh and tmrnl). both 8-bit timers operate in auto-reload mode as shown in figure 25.5. tmrnrll holds the reload value for tmrnl; tmrnrlh holds the reload value for tmrnh. the trn bit in tmrncn handles t he run control for tmrnh. tmrnl is always running when configured for 8-bit auto-reload mode. each 8-bit timer may be configured to clock from sysclk, sysclk di vided by 12, or the external oscillator clock source divided by 8. the clock select bits (tnmh and tnml in ckcon) select either sysclk or the clock defined by th e external clock select bit (tnxclk in tmrncn), as follows: the tfnh bit is set when tmrnh overflows from 0xff to 0x00; the tfnl bit is set when tmrnl overflows from 0xff to 0x00. when timer interrupts are enabled, an interrupt is generated each time tmrnh overflows. if timer interrupts are enabled and tfnlen is set, an interrupt is generated each time either tmrnl or tmrnh overflows. when tfnlen is enabled , software must check the tfnh and tfnl flags to determine the source of the timer interrupt. the tfnh and tfnl interrupt flags are not cleared by hardware and must be manually cleared by software. figure 25.5. 8-bit mode block diagram tnmh tnxclk tmrnh clock source tnml tnxclk tmrnl clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk tclk 0 1 trn xternal clock / 8 sysclk / 12 0 1 tnxclk 1 0 tmrnh tmrnrlh reload reload tclk tmrnrll interrupt tfnl overflow tfnlen sysclk tmrnl tfnh overflow tnml tnmh
254 rev. 1.0 25.2.3. capture mode capture mode allows an exte rnal input (timer 2) or the low-frequency osc illator clock (timer 3) to be measured against the system clock or an external oscillator sour ce. the timer can be clocked from the system clock, the system clock divided by 12, or the external oscillator divided by 8, dependi ng on the tnml, and tnxclk settings. setting tfncen to 1 enables capture mode. in this mode, tnsplit should be set to 0, as the full 16-bit timer is used. upon a fallin g edge of the input capture signal, th e contents of the timer register (tmrnh:tmrnl) are loaded into the reload registers (tmrnrlh:tmrnrll) and the tfnh flag is set. by recording the difference between two successive time r capture values, the period of the captured signal can be determined with respect to the selected timer clock. figure 25.6. capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 0 1 tnxclk tmrnl tmrnh tclk trn tmrnrll tmrnrlh capture t2 pin (timer 2) l-f oscillator (timer 3) tfncen tnml tfnh (interrupt)
rev. 1.0 255 25.3. timer control registers register 25.1. ckcon: clock control bit 7 6 5 4 3 2 1 0 name t3mh t3ml t2mh t2ml t1m t0m sca t ype rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0x8e table 25.3. ckcon register bit descriptions bit name function 7 t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6 t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5 t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4 t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3 t1m timer 1 clock select. selects the clock source su pp lied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale field, sca. 1: timer 1 uses the system clock. 2 t0m timer 0 clock select. selects the clock source su pp lied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defined by the prescale field, sca. 1: counter/timer 0 uses the system clock.
256 rev. 1.0 1:0 sca timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (s yn chronized with the system clock) table 25.3. ckcon register bit descriptions bit name function
rev. 1.0 257 register 25.2. tcon: timer 0/1 control bit 7 6 5 4 3 2 1 0 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 t ype rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0x88 (bit-addressable) table 25.4. tcon register bit descriptions bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. th is flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6 tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. th is flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4 tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3 ie1 external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can b e cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2 it1 interrupt 1 type select. this bit selects whether the conf igured in t1 interrup t will be edge or level sensitive. int1 is configured active low or high by the in1pl bit in register it01cf. 0: int1 is level triggered. 1: int1 is edge triggered. 1 ie0 external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can b e cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0 it0 interrupt 0 type select. this bit selects whether the conf igured in t0 interrup t will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf. 0: int0 is level triggered. 1: int0 is edge triggered.
258 rev. 1.0 register 25.3. tmod: timer 0/1 mode bit 7 6 5 4 3 2 1 0 name gate1 ct1 t1m gate0 ct0 t0m t ype rw rw rw rw rw rw r e s e t00000000 sfr address: 0x89 table 25.5. tmod register bit descriptions bit name function 7 gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in reg - ister it01cf. 6 ct1 counter/timer 1 select. 0: timer mode. timer 1 increments on the clock defined by t1m in the ckcon register. 1: counter mode. timer 1 increments on high-t o -low transitions of an external pin (t1). 5:4 t1m timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3 gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in reg - ister it01cf. 2 ct0 counter/timer 0 select. 0: timer mode. timer 0 increments on the clock defined by t0m in the ckcon register. 1: counter mode. timer 0 increments on high-t o -low transitions of an external pin (t0). 1:0 t0m timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers
rev. 1.0 259 register 25.4. tl0: timer 0 low byte bit 7 6 5 4 3 2 1 0 name tl0 ty pe rw r e s e t00000000 sfr address: 0x8a table 25.6. tl0 register bit descriptions bit name function 7:0 tl0 timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0.
260 rev. 1.0 register 25.5. tl1: timer 1 low byte bit 7 6 5 4 3 2 1 0 name tl1 ty pe rw r e s e t00000000 sfr address: 0x8b table 25.7. tl1 register bit descriptions bit name function 7:0 tl1 timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1.
rev. 1.0 261 register 25.6. th0: timer 0 high byte bit 7 6 5 4 3 2 1 0 name th0 ty pe rw r e s e t00000000 sfr address: 0x8c table 25.8. th0 register bit descriptions bit name function 7:0 th0 timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0.
262 rev. 1.0 register 25.7. th1: timer 1 high byte bit 7 6 5 4 3 2 1 0 name th1 ty pe rw r e s e t00000000 sfr address: 0x8d table 25.9. th1 register bit descriptions bit name function 7:0 th1 timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1.
rev. 1.0 263 register 25.8. tmr2cn: timer 2 control bit 7 6 5 4 3 2 1 0 name tf2h tf2l tf2len tf2cen t2split tr2 reserved t2xclk t ype rw rw rw rw rw rw r rw r e s e t00000000 sfr address: 0xc8 (bit-addressable) table 25.10. tmr2cn register bit descriptions bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes th e cpu to vector to the timer 2 interrupt ser - vice routine. this bit is not au toma tically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the t imer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automat - ically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 low by te interrupts. if timer 2 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 2 overflows. 4 tf2cen timer 2 capture enable. when set to 1, this bit enables timer 2 capture mode. if tf2cen is set and timer 2 interrupt s are enabled, an inte rrupt will be generated on a fallin g edge of the selected t2 input pin, and the cu rrent 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2rll. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. 2 tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is always enabled in split mode. 1 reserved must write reset value.
264 rev. 1.0 0 t2xclk timer 2 external clock select. this bit selects the external clock source for t imer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clock divided by 8 (synchronized with sysclk). table 25.10. tmr2cn register bit descriptions bit name function
rev. 1.0 265 register 25.9. tmr2rll: timer 2 reload low byte bit 7 6 5 4 3 2 1 0 name tmr2rll ty pe rw r e s e t00000000 sfr address: 0xca table 25.11. tmr2rll register bit descriptions bit name function 7:0 tmr2rll timer 2 reload low byte. when operating in one of the auto-reload modes, tmr2rll holds the reload value for the low byte of timer 2 (tmr2l). when operating in capture mode, tmr2rll is the cap - tured value of tmr2l.
266 rev. 1.0 register 25.10. tmr2rlh: timer 2 reload high byte bit 7 6 5 4 3 2 1 0 name tmr2rlh ty pe rw r e s e t00000000 sfr address: 0xcb table 25.12. tmr2rlh register bit descriptions bit name function 7:0 tmr2rlh timer 2 reload high byte. when operating in one of the auto-reload modes, tmr2rlh holds the reload value for the high byte of timer 2 (tmr2h). when o eprating in capture mo de, tmr2rlh is the captured value of tmr2h.
rev. 1.0 267 register 25.11. tmr2l: timer 2 low byte bit 7 6 5 4 3 2 1 0 name tmr2l ty pe rw r e s e t00000000 sfr address: 0xcc table 25.13. tmr2l register bit descriptions bit name function 7:0 tmr2l timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit m ode, tmr2l contains the 8-bit low byte timer value.
268 rev. 1.0 register 25.12. tmr2h: timer 2 high byte bit 7 6 5 4 3 2 1 0 name tmr2h ty pe rw r e s e t00000000 sfr address: 0xcd table 25.14. tmr2h register bit descriptions bit name function 7:0 tmr2h timer 2 high byte. in 16-bit mode, the tmr2h register contains t he hig h byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value.
rev. 1.0 269 register 25.13. tmr3cn: timer 3 control bit 7 6 5 4 3 2 1 0 name tf3h tf3l tf3len tf3cen t3split tr3 reserved t3xclk t ype rw rw rw rw rw rw r rw r e s e t00000000 sfr address: 0x91 table 25.15. tmr3cn register bit descriptions bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16-bit mode, this will occur when timer 3 overflows from 0x ffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes th e cpu to vector to the timer 3 interrupt ser - vice routine. this bit is not au toma tically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the t imer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not automat - ically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 low by te interrupts. if timer 3 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 3 overflows. 4 tf3cen timer 3 capture enable. when set to 1, this bit enables timer 3 capture mode. if tf3cen is set and timer 3 interrupt s are enabled, an interrupt will be generated on a falling e dge of the low-fre - quency oscillator output, and the current 16-bit timer valu e in tmr3h:tmr3l will be cop - ied to tmr3rlh:tmr3rll. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. 2 tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabled in split mode. 1 reserved must write reset value.
270 rev. 1.0 0 t3xclk timer 3 external clock select. this bit selects the external clock source for t imer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 clock is the system clock divided by 12. 1: timer 3 clock is the external clock divided by 8 (synchronized with sysclk). table 25.15. tmr3cn register bit descriptions bit name function
rev. 1.0 271 register 25.14. tmr3rll: timer 3 reload low byte bit 7 6 5 4 3 2 1 0 name tmr3rll ty pe rw r e s e t00000000 sfr address: 0x92 table 25.16. tmr3rll register bit descriptions bit name function 7:0 tmr3rll timer 3 reload low byte. when operating in one of the auto-reload modes, tmr3rll holds the reload value for the low byte of timer 3 (tmr3l). when operating in capture mode, tmr3rll is the cap - tured value of tmr3l.
272 rev. 1.0 register 25.15. tmr3rlh: timer 3 reload high byte bit 7 6 5 4 3 2 1 0 name tmr3rlh ty pe rw r e s e t00000000 sfr address: 0x93 table 25.17. tmr3rlh register bit descriptions bit name function 7:0 tmr3rlh timer 3 reload high byte. when operating in one of the auto-reload modes, tmr3rlh holds the reload value for the high byte of timer 3 (tmr3h). when o eprating in capture mo de, tmr3rlh is the captured value of tmr3h.
rev. 1.0 273 register 25.16. tmr3l: timer 3 low byte bit 7 6 5 4 3 2 1 0 name tmr3l ty pe rw r e s e t00000000 sfr address: 0x94 table 25.18. tmr3l register bit descriptions bit name function 7:0 tmr3l timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit m ode, tmr3l contains the 8-bit low byte timer value.
274 rev. 1.0 register 25.17. tmr3h: timer 3 high byte bit 7 6 5 4 3 2 1 0 name tmr3h ty pe rw r e s e t00000000 sfr address: 0x95 table 25.19. tmr3h register bit descriptions bit name function 7:0 tmr3h timer 3 high byte. in 16-bit mode, the tmr3h register contains t he hig h byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value.
rev. 1.0 271 26. universal asynchronous receiver/transmitter (uart0) uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?26.1. enhanced baud rate generation? on page 271). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti is set in scon0), or a data byte has been received (ri is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interrupt serv ice routine. they must be cleared manually by soft- ware, allowing software to determine the cause of th e uart0 interrupt (transmit complete or receive com- plete). figure 26.1. uart0 block diagram 26.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 26.2), which is not user- accessible. both tx and rx timer overflows are divid ed by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. uart0 sbuf (8 lsbs) input shift register rx baud rate generator (timer 1) start detection output shift register tx tb8 (9 th bit) rb8 (9 th bit) control / configuration ti, ri interrupts tx clk rx clk
272 rev. 1.0 figure 26.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload. the timer 1 reload value should be set so that overflows will occur at two times the desired uart baud rate frequency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysclk/12, sysclk/48, the external oscillator clock/8, or an external input t1. for any given timer 1 overflow rate, the uart0 baud rate is determined by equation 26.1. equation 26.1. uart0 baud rate timer 1 overflow rate is selected as described in th e t imer section. a quick reference for typical baud rates and system clock frequencies is given in table 26.1. start detection tx clock 2 rx clock 2 tl1 th1 rx timer baud rate generator (in timer 1) uartbaudrate 1 2 -- - t1_overflow_rate =
rev. 1.0 273 26.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit in register scon. 26.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: on e start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx pin and received at the rx pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb8 in the scon register. data transmission begins when so ftware writes a data byte to the sbuf0 register. the ti transmit interrupt flag is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren receive enable bit is se t to logic 1. after the stop bit is received, the data byte will be loaded into the sbuf0 rece ive register if the follo wing conditions are met: ri must be logic 0, and if mce is logic 1, the stop bit must be logic 1. in the event of a receive data overrun, the first received 8 bits are latched into the sbuf0 receive regist er and the following overrun data bits are lost. if these conditions are met, the eight bits of data is st ored in sbuf0, the stop bit is stored in rb8 and the ri flag is set. if these conditions are not met, sbuf0 and rb8 will not be loaded and the ri flag will not be set. an interrupt will occu r if enabled when either ti or ri is set. figure 26.3. 8-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
274 rev. 1.0 26.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programmable ninth data bit, and a stop bit. the state of the ninth transmit data bit is determined by the value in tb8, which is assigned by user software. it c an be assigned the value of the parity flag (bit p in register psw) for error detection, or used in multipro cessor communications. on receive, the ninth data bit goes into rb8 and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti transmit interrupt flag is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren receive enable bit is set to 1. after the stop bit is received, the data byte will be loaded into the sbuf0 receive register if the follo wing conditions are met: (1) ri must be logic 0, and (2) if mce is logic 1, the 9th bit must be logic 1 (wh en mce is logic 0, the stat e of the ninth data bit is unimportant). if these conditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb8, and the ri flag is set to 1. if the above conditions are not me t, sbuf0 and rb8 will not be loaded and the ri flag will not be set to 1. a uart0 interrupt will occur if ena bled when either ti or ri is set to 1. figure 26.4. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
rev. 1.0 275 26.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce bit of a slave processor configures its uart such that when a stop bit is received, the uart will generate an inte rrupt only if the nint h bit is logic 1 (rb8 = 1) sign ifying an address byte has been received. in the uart interrupt ha ndler, software will compare the rece ived address with the slave's own assigned 8-bit address. if the addresse s match, the slave will clear its mce bit to enable interrupts on the reception of the following data byte(s). slaves that weren't addressed leave their mce bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce bit to ignore all transmissions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 26.5. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
276 rev. 1.0 table 26.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator frequency: 49 mhz target baud rate (b ps) baud rate % error oscillator divide fac tor timer clock source sca1?sca0 (pre-scale se lect) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in timer1 chapter. 2. x = don?t care.
rev. 1.0 277 26.4. uart control registers register 26.1. scon0: uart0 serial port control bit 7 6 5 4 3 2 1 0 name smode reserved mce ren tb8 rb8 ti ri t yperw r rwrwrwrwrwrw r e s e t01000000 sfr address: 0x98 (bit-addressable) table 26.2. scon0 register bit descriptions bit name function 7 smode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate (mode 0). 1: 9-bit uart with variable baud rate (mode 1). 6 reserved must write reset value. 5 mce multiprocessor communication enable. this bit enables checking of the stop bit or th e 9th bit in multi-drop communication buses. the function of this bit is dependent on th e uart0 operation mode selected by the smode bit. in mode 0 (8-bits), the peripheral will check that the stop bit is logic 1. in mode 1 (9-bits) the peripheral will ch eck for a logic 1 on the 9th bit. 0: ignore level of 9th bit / stop bit. 1: ri is set and an interrupt is generated only when the stop bit is logic 1 (mode 0) or when the 9th bit is logic 1 (mode 1). 4 ren receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3 tb8 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bit in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2 rb8 ninth receive bit. rb8 is assigned the value of the stop bit in mod e 0; it is assigned the value of the 9th data bit in mode 1. 1 ti transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8 -bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit ca uses the cpu to vector to the uart0 inter - rupt service routine. this bit must be clea red manually by software.
278 rev. 1.0 0 ri receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop b it sampling time). when the uart0 interrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software. table 26.2. scon0 register bit descriptions bit name function
rev. 1.0 279 register 26.2. sbuf0: uart0 serial port data buffer bit 7 6 5 4 3 2 1 0 name sbuf0 ty pe rw r e s e t00000000 sfr address: 0x99 table 26.3. sbuf0 register bit descriptions bit name function 7:0 sbuf0 serial data buffer bits. this sfr accesses two registers: a transmit sh ift register and a receive latch register. when data is written to sbuf0, it goes to the tr ansmit shift register and is held for serial transmission. writing a byte to sbuf0 in itiates the transmission. a read of sbuf0 returns the contents of the receive latch.
280 rev. 1.0
rev. 1.0 280 27. watchdog timer (wdt0) the c8051f85x/86x family includes a programmable watchdog timer (wdt) running off the low- frequency oscillator. a wdt overflow will force the mcu into the reset state. to prevent the re set, the wdt must be restarted by application software before overflow. if the system experiences a software or hardware malfunction preventing the software from restarting the wdt, the wdt will overflow and cause a reset. following a reset the wdt is automatically enabled and running with the default maximum time interval. if desired the wdt can be disabled by system software or locked on to prevent accidental disabling. once locked, the wdt cannot be disabled until th e next system reset. the state of the rst pin is unaffected by this reset. the wdt consists of an internal ti mer running from the lo w-frequency oscillator. the timer measures the period between specific writes to its control register. if this period exceeds the programmed limit, a wdt reset is generated. the wdt can be enabled and disabled as needed in software, or can be permanently enabled if desired. when the wdt is active, the low-frequency oscillator is forced on. all watchdog features are controlled via the watchdog timer control register (wdtcn). figure 27.1. watchdog timer block diagram watchdog timer lfosc0 watchdog timer lock and key watchdog reset timeout interval
281 rev. 1.0 27.1. enabling / resetting the wdt the watchdog timer is both enabled and reset by writing 0xa5 to the wdtcn register. the user's application software should include periodic writes of 0xa5 to wdtcn as needed to prevent a watchdog timer overflow. the wdt is enabled and re set as a result of any system reset. 27.2. disabling the wdt writing 0xde followed by 0xad to the wdtcn regi ster disables the wdt. the following code segment illustrates disabling the wdt: clr ea ; disable all interrupts mov wdtcn,#0deh ; disable software watchdog timer mov wdtcn,#0adh setb ea ; re-enable interrupts the writes of 0xde and 0xad must occur within 4 clo ck cycles of each other, or the disable operation is ignored. interrupts should be disabled during this procedure to avoid delay between the two writes. 27.3. disabling the wdt lockout writing 0xff to wdtcn locks out the disable feature. once locked out, the disable operation is ignored until the next system reset. writing 0xff does not enabl e or reset the watchdog timer. applications always intending to use the watchdog should writ e 0xff to wdtcn in the initialization code. 27.4. setting the wdt interval wdtcn.[2:0] controls the watchdog ti meout interval. the interval is given by the following equation, where t lfosc is the low-frequency oscillator clock period: this provides a nominal interval range of 0.8 ms to 13 .1 s. wdtcn.7 must be logic 0 when setting this interval. reading wdtcn returns the programmed interv al. wdtcn.[2:0] reads 111b after a system reset. t lfosc 4 wdtcn[2:0] 3 + ()
rev. 1.0 282 27.5. watchdog timer control registers register 27.1. wdtcn: watchdog timer control bit 7 6 5 4 3 2 1 0 name wdtcn ty pe rw r e s e t00010111 sfr address: 0x97 table 27.1. wdtcn register bit descriptions bit name function 7:0 wdtcn wdt control. the wdt control field has different behavior for reads and writes. read: when reading the wdtcn register, the lower three bits (wdtcn[2:0]) indicate the cur - rent timeout interval. bit wdtcn.4 indicates wh ether the wdt is active (logic 1) or inac - tive (logic 0). write: writing the wdtcn register can set the tim eou t interval, enable the wdt, disable the wdt, reset the wdt, or lock the wdt to prevent disabling. writing to wdtcn with the msb (wdtcn.7) clea red to 0 will set the timeout interval to the value in bits wdtcn[2:0]. writing 0xa5 both enables and reloads the wdt. writing 0xde followed within 4 system clo cks by 0xad disables the wdt. writing 0xff locks out the disable feature until the next device reset.
283 rev. 1.0
rev. 1.0 284 28. revision-specific behavior c8051f85x/86x revision b devices have di fferences from revision c devices: ?? temperature sensor offset and slope ?? flash endurance ?? latch-up performance ?? unique identifier 28.1. revision identification the lot id code on the top side of the device package can be used for decoding device revision information. figure 28.1, figure 28.2, and figure 28.3 sh ow how to find the lot id code on the top side of the device package. firmware can distinguish between a revision b and revision c device using the value of the revid register described in ?device identification and unique identifier? on page 64. figure 28.1. qsop-24 package revision marking c8051f850 1342 c 00000 e3 this character identifies the device revision
285 rev. 1.0 figure 28.2. qfn-20 package revision marking figure 28.3. soic-16 package revision marking this first character identifies the device revision f850 c 000 342+ c8051f860 1342c 00000 this character identifies the device revision e3
rev. 1.0 286 28.2. temperature sens or offset and slope the temperature sensor slope and offset characteristi cs of revision b devices are different than the slope and offset characteristics of revi sion c devices. the differences are: firmware that uses the slope and offset of the temperature sensor to calculate the temperature from the se nsor adc reading can detect the revision of the device by reading the revid register and adjust the slope and offset calculations based on the result. a revid value of 0x01 indicates a revision b device, and a revid value of 0x02 indicates a revision c device. 28.3. flash endurance the flash endurance, or number of times the flash may be written and erased, on some revision b devices may be lower than expected. table 1.4 specifies a minimum endurance (write/erase cycles) as 20000, but some revision b de vices may support a minimum of ~5000 cycles. 28.4. latch-up performance pulling the device pins below ground and drawing si gnificant current (~3.5 ma) can cause a power-on reset event with revision b devices. some pins, like p0.0 and p0.1, are more susceptible to this behavior than others. this behavior is outside normal operatin g parameters and would typically be seen during latch-up or esd performance testing. 28.5. unique identifier revision b devices do not implement the unique iden tifier described in ?device identification and unique identifier? on page 64. table 28.1. temperature sensor revision differences parameter symbol test condition min typ max unit revision b offset v off t a = 0 c ? 713 ? mv slope m ? 2.67 ? mv/c revision c offset v off t a = 0 c ? 757 ? mv slope m ? 2.85 ? mv/c
287 rev. 1.0
rev. 1.0 287 29. c2 interface c8051f85x/86x devices include an on -chip silicon labs 2-wire (c2) debug interface to allow flash programming and in-system debugging with the producti on part installed in the end application. the c2 interface uses a clock sig nal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. details on t he c2 protocol can be found in the c2 interface specification. 29.1. c2 pin sharing the c2 protocol allows the c2 pins to be shared with user functions so that in-system debugging and flash programming may be performed. c2ck is shared with the rst pin, while the c2d si gnal is shared with a port i/o pin. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user softwa re are stalled. in this halted state, the c2 interface can safely ?borrow? the c2ck and c2d pins. in most ap plications, external resistors are required to isolate c2 interface traffic from the user application. a typi cal isolation configuration is shown in figure 29.1. figure 29.1. typical c2 pin sharing the configuration in figure 29.1 assumes the following: 1. the user input (b) cannot change state while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx
288 rev. 1.0 29.2. c2 interface registers the following describes the c2 registers necessar y to perform flash programming through the c2 interface. all c2 registers are accessed through the c2 interface, and are not available in the sfr map for firmware access. register 29.1. c2add: c2 address bit 7 6 5 4 3 2 1 0 name c2add ty pe rw r e s e t00000000 this register is part of the c2 protocol. table 29.1. c2add register bit descriptions bit name function 7:0 c2add c2 address. the c2add register is accessed via the c2 interface. the valu e written to c2add selects the target data register for c2 data read and data write commands. 0x00: c2devid 0x01: c2revid 0x02: c2fpctl 0xb4: c2fpdat
rev. 1.0 289 register 29.2. c2devid: c2 device id bit 7 6 5 4 3 2 1 0 name c2devid ty pe r r e s e t00110000 c2 address: 0x00 table 29.2. c2devid register bit descriptions bit name function 7:0 c2devid device id. this read-only register returns the 8 -bit device id: 0x30 (c8051f85x/86x).
290 rev. 1.0 register 29.3. c2revid: c2 revision id bit 7 6 5 4 3 2 1 0 name c2revid ty pe r r e s e txxxxxxxx c2 address: 0x01 table 29.3. c2revid register bit descriptions bit name function 7:0 c2revid revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a, 0 x01 = revision b and 0x02 = revision c.
rev. 1.0 291 register 29.4. c2fpctl: c2 flash programming control bit 7 6 5 4 3 2 1 0 name c2fpctl ty pe rw r e s e t00000000 c2 address: 0x02 table 29.4. c2fpctl register bit descriptions bit name function 7:0 c2fpctl flash programming control register. this register is used to enable flash programm ing via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset must be issued to resume normal operation.
292 rev. 1.0 register 29.5. c2fpdat: c2 flash programming data bit 7 6 5 4 3 2 1 0 name c2fpdat ty pe rw r e s e t00000000 c2 address: 0xb4 table 29.5. c2fpdat register bit descriptions bit name function 7:0 c2fpdat c2 flash programming data register. this register is used to pass flash comm an ds, addresses, and data during c2 flash accesses. valid commands are listed below. 0x03: device erase 0x06: flash block read 0x07: flash block write 0x08: flash page erase
rev. 1.0 293 d ocument c hange l ist revision 0.5 to revision 0.6 ? updated front page block diagram. ? updated adc supply current parameters in table 1.2, ?power consumption,? on page 8. ? corrected flash programming voltage range in "table 1.4. flash memory" on page 11. ? added adc power-on time specification in table 1.7, ?adc,? on page 13. ? added section "1.2. typical performance curves" on page 19. ? corrected derivid information in table 11.3, ?derivid register bit descriptions,? on page 66. ? updated adc chapter ("14. analog-to-digital converter (adc0)" on page 79) and expanded section "14.5. power considerations" on page 85 wit h recommended power configuration settings. ? updated figure 21.1, ?port i/o functional block diagram,? on page 176. ? corrected reset value in regist er 24.5, ?smb0adm: smbus0 slave address mask,? on page 246. ? corrected description of ie0 in "table 25.4. tcon register bit descriptions" on page 259. revision 0.6 to revision 0.7 ? added mention of the uid to the front page. ? updated some tbd values in the "1. electrical specifications" on page 8 section. ? updated power-on reset (por) threshold maxi mum falling voltage on v dd specification in table 1.3. ? updated reset delay from non-por source typical s pecification in table 1.3. ? removed v dd ramp time maximum specification in table 1.3. ? updated flash memory erase time specification and added note 2 to table 1.4. ? updated maximum adc dc performanc e specifications in table 1.7. ? updated minimum and maximum adc offset error and slope error specifications in table 1.7. ? updated conditions on internal fast settling refe rence output voltage (full temperature and supply range) in table 1.8. ? added a new section "1.2.3. port i/o output drive" on page 21. ? updated pinout figure 3.1, figure 3.2, figure 3.3, table 3.1, table 3.2, and table 3.3 titles to the correct part numbers. ? updated the ordering information ("4. ordering information" on page 40.) for revision c devices. ? added mention of the unique identifier to "8. memory organization" on page 49. ? added unique identifier information to "11. devi ce identification and unique identifier" on page 64. ? updated device part numbers listed in table 11.3, ?d erivid register bit descriptions,? on page 66 to include the revision. ? added "28. revision-specific behavior" on page 284. revision 0.7 to revision 1.0 ? updated digital core, adc, and temperature sensor electrical specifications information for -i devices. ? updated -i part number information in "4. ordering information" on page 40. ? replaced reference to amx0p an d amx0n with adc0mx in table 21.1, ?port i/o assignment for analog functions,? on page 178. ? added a note to table 1.13, ?absolute maximum ratings,? on page 22 and added a link to the quality and reliability monitor report. ? added operating junction temperature to table 1.13, ?absolute maximum ratings,? on page 22. ? updated all tbds in "1. electric al specifications" on page 8.
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