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o1911hkim 20100216-s00003 no.a1935-1/28 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 ver.0.21 lc87f2c64a overview the lc87f2c64a is an 8-bit microcom puter that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 64k-byte flash rom (onboard programmable), 2048-byte ram, an on-chip debugger, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), four 8-bit timers with a prescaler, a calendar function (rtc), high-speed cl ock counter, a synchronous sio interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous sio inte rface, two channels of uart interface (full duplex), four 12bit-pwms, a 12/8-bit 16-channel ad converter, a system clock frequency divider, an internal reset function and a 28-source 10-vector interrupt feature. features ? flash rom ? on-board-programmable with wide range (3.0 to 5.5v) of voltage source ? block-erasable in 128 byte units ? writable in 2-byte units ? 65536 8 bits ? ram ? 2048 9 bits ? minimum bus cycle ? 83.3ns (12mhz at v dd =3.0v to 5.5v) ? 250ns (4mhz at v dd =2.4v to 5.5v) note: the bus cycle time here refers to the rom read speed. ordering number : ENA1935 cmos ic 64k-byte from and 2048-byte ram integrated 8-bit 1-chip microcontroller * this product is licensed from silicon storage technology, inc. (usa).
lc87f2c64a no.a1935-2/28 ? minimum instruction cycle time ? 250ns (12mhz at v dd =3.0 to 5.5v) ? 750ns (4mhz at v dd =2.4 to 5.5v) ? temperature range ? -30 to +70 degree celsius ? ports ? normal withstand voltage i/o ports ports i/o direction can be designated in 1-bit units 71 (p0n, p1n, p2n, p30 to p34, p70 to p73, p8n, pan, pbn, pcn, pen, xt2, cf2) ? normal withstand voltage input port (oscillator) 2 (xt1, cf1) ? reset pin 1 (res ) ? power pins 6 (v ss 1 to v ss 3, v dd 1 to v dd 3) ? timers ? timer 0: 16-bit timer/counter with a capture register mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with a 8-bit capture register) mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer 1) the clock is selectable from the sub-clock (32.768khz crystal oscillation/slow rc oscillation), system clock, and prescaler output from timer 0. 2) interrupts are programmable in 5 different time schemes. ? real time clock (rtc) 1) used with a base timer, it can be used as a century + year + month + day + hour + minute + second counter. 2) calendar counts up to december 31, 2 799 with automatic l eap-year calculation. ? high-speed clock counter ? count clocks with a maximum clock rate of 24mhz (when main clock is 12mhz) ? real-time output
lc87f2c64a no.a1935-3/28 ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baud rate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) 4) hold/x?tal hold mode release func tion by receiving 1-byte (8-bit clock) ? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baud rates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? uart: 2 channels ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? remote control receiver circuit ? noise rejection function on p73/int3/t0in pin (noise rejec tion filter?s time constant can be selected from 1, 32 or 128 tcyc.) ? ad converter: 12 bits 16 channels ? 12 bits/8 bits ad converter resolution selectable ? pwm: 4 channels ? multi frequency 12-bit pwm ? clock output function ? output clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of the source clock of the system clock. ? output clock of the sub-clock. ? buzzer output ? 2khz or 4khz buzzer output can be generated using base timer. ? watchdog timer ? watchdog timer can generate interrupt or system reset. ? two types of watchdog timers are available: (1) external rc watchdog timer (2) base timer watchdog timer ? watchdog timer with base timer can select only one period (1, 2, 4 or 8s) by the user option. once set the watchdog timer period and start the watchdog timer, the period is not changeable.
lc87f2c64a no.a1935-4/28 ? interrupts ? 28 sources, 10 vector addresses (1) provides three levels (low (l), hi gh (h), and highest (x)) of multiplex inte rrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. (2) when interrupt requests to two or more vector addresse s occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/int4/t0l 4 0001bh h or l int3/int5/base timer0/ base timer1/rtc 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1 receive/uart2 receive 8 0003bh h or l sio1/uart1 transmit/uart2 transmit 9 00043h h or l adc/t6/t7/pwm4, 5/spi 10 0004bh h or l port0/t4/t5/pwm0, 1 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? iflg (list of interrupt source flag function) (1) shows a list of interrupt source flags that cause d a branching to a particular vector address (shown in the table above). ? subroutine stack levels ? 1024 levels (stack is allocated in ram) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits8 bits (8 tcyc execution time) ? 24 bits16 bits (12 tcyc execution time) ? oscillation circuits ? on-chip fast rc oscillation circuit : for system clock ? on-chip slow rc oscillation circuit : for system clock ? cf oscillation circuit : for system clock, with built in rf ? crystal oscillation circuit : for low-speed system clock ? on-chip frequency variable rc oscillation circuit : for system clock (1) adjustable by 4% (typical) st ep from selected center frequency (2) frequency measurable by referencing input signal from xt1 ? system clock divider function ? enables low power consumption operation ? the minimum instruction cycle selectable from 250ns, 500ns, 1.0 s, 2.0 s, 4.0 s, 8.0 s, 16.0 s, 32.0 s, and 64 s (at a main clock rate of 12mhz). ? internal reset function ? power-on reset (por) function (1) por reset is generated only at power-on. (2) the por release level can be sel ected through option configuration. ? low-voltage detection reset (lvd) function (1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. (2) the use/no-use of the lvd function and the low voltage threshold level can be selected through option configuration.
lc87f2c64a no.a1935-5/28 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. (1) oscillation is not halted automatically. (2) there are three ways of resetting the halt mode. 1) setting the reset pin to the lower level 2) system resetting by watchdog timer 3) occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. (1) the cf, rc, crystal, and frequency variable rc oscillators automatically stop operation. (2) there are five ways of resetting the hold mode. 1) setting the reset pin to the lower level 2) system resetting by watchdog timer 3) setting at least one of the int0, int1, int2, int3, int4, int5 pins to the specified level 4) having an interrupt source established at port 0 5) having an interrupt source establishe d in spi receiving 1-byte (8-bit clock) ? x?'tal hold mode: suspends instruction execution and the oper ation of the peripheral circ uits except the base timer. (1) the cf, rc, and frequency variable rc oscillators automatically stop operation. (2) the state of crystal oscillation established when the x?tal hold mode is entered is retained. (3) power-save mode is available for even lower current consumption. (4) there are seven ways of resetting the x?tal hold mode. 1) setting the reset pin to the low level 2) system resetting by watchdog timer 3) setting at least one of the int0, int1, int2, int3, int4, int5 pins to the specified level 4) having an interrupt source established at port0 5) having an interrupt source established in the base timer circuit 6) having an interrupt source established in the rtc 7) having an interrupt source establishe d in spi receiving 1-byte (8-bit clock) ? on-chip debugging function (flash rom version) ? supports software debugging with the test device installed on the target board. ? data security function (flash rom version) ? protects the program data stored in flash memory from unauthorized read or copy. note: the data security function does not nece ssarily provide an absolute data security. ? shipping form ? qfp80 (1414): lead-free type ? tqfp80j (1212): lead-free type ? development tools ? on-chip-debugger: tcb87 typeb + lc87f2c64a
lc87f2c64a no.a1935-6/28 package dimensions unit : mm (typ) 3255 package dimensions unit : mm (typ) 3290 sanyo : qfp80(14x14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.25 0.65 (0.83) (2.7) 0.8 1 20 21 40 41 60 80 61 120 21 40 41 60 80 61 (1.25) 0.2 0.5 0.125 12.0 12.0 14.0 14.0 0.5 (1.0) 0.1 1.2max sanyo : tqfp80j(12x12)
lc87f2c64a no.a1935-7/28 pin assignment qfp80 (1414) ?lead-free type? tqfp80j (1212) ?lead-free type? p02/utx2 p01/urx1 p00/utx1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p27/int5/t1in/t0lcp/t0hcp p26/int5/t1in/t0lcp/t0hcp p25/int5/t1in/t0lcp/t0hcp p24/int5/t1in/t0lcp/t0hcp p23/int4/t1in/t0lcp/t0hcp p22/int4/t1in/t0lcp/t0hcp p21/int4/t1in/t0lcp/t0hcp p20/int4/t1in/t0lcp/t0hcp pe3 p70/int0/t0lcp p71/int1/t0hcp p72/int2/t0in/nkin p73/int3/t0in res xt1 xt2 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 pb0/an8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v ss 2 v dd 2 pe2 pe1 pe0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pb7/an15 pb6/an14 pb5/an13 pb4/an12 pb3/an11 pb2/an10 pb1/an9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p03/urx2 p04 p05/cko p06/t6o p07/t7o v ss 3 v dd 3 pa0/pwm0 pa1/pwm0 pa2/pwm0 pa3/pwm0 pa4/pwm1 pa5/pwm1 pa6/pwm1 pa7/pwm1 p30/pwm4 p31/pwm5 p32/dbgp0 p33/dbgp1 p34/dbgp2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 lc87f2c64a to p view
lc87f2c64a no.a1935-8/28 system block diagram res interrupt control stand-by control flash rom ir pla rc 2 vmrc x?tal cf clock generato r reset control wdt reset circuit (por/lvd) pc acc b register psw alu rar ram stack pointer watchdog timer on-chip-debugger sio0 sio1 c register bus interface port 0 uart1 uart2 timer 0 (high-speed clock counter) timer 1 timer 4 timer 5 timer 6 timer 7 base timer rtc pwm0/1 port 1 port 2 port 3 port 7 port 8 adc port a port b port c pwm4/5 int0 to 5 noise rejection filter port e
lc87f2c64a no.a1935-9/28 pin description pin name i/o description option v ss 1 to v ss 3 - - power supply pin no v dd 1 to v dd 3 - + power supply pin no v1 - open no vdc - open no cup1, cup2 - open no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. ? hold release input ? port 0 interrupt input other functions: p00: uart1 transmit p01: uart1 receive p02: uart2 transmit p03: uart2 receive p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. other functions: p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output/beeper output yes port 2 p20 to p27 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. other functions: p20 to p23: int4 input/hold re lease input/timer 1 event input /timer 0l capture input/timer 0h capture input p24 to p27: int5 input/hold re lease input/timer 1 event input /timer 0l capture input/timer 0h capture input ? interrupt acknowledge type rising falling rising & falling h level l level int4 int5 yes yes yes yes yes yes no no no no yes port 3 p30 to p34 i/o ? 5-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. other functions: p30: pwm4 output p31: pwm5 output p32 (dbgp0) to p34 (dbgp2): on-chip-debugger port (only on flash version) yes continued on next page.
lc87f2c64a no.a1935-10/28 continued from preceding page. pin name i/o description option port 7 p70 to p73 i/o ? 4-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. other functions: p70: int0 input/hold release input/timer 0l capture input /watchdog timer output p71: int1 input/hold release input/timer 0h capture input p72: int2 input/hold release input/timer 0 event input /timer 0l capture input/high speed clock counter input p73: int3 input (with noise filter)/ hold release input /timer 0 event input/timer 0h capture input ? interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int2 int3 yes yes yes yes yes yes yes yes no no yes yes yes yes no no yes yes no no no port 8 p80 to p87 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units other functions: p80 to p87(an0 to an7): ad converter input no port a pa0 to pa7 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. other functions: pa0 to pa3: pwm0 output pa4 to pa7: pwm1 output yes port b pb0 to pb7 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. other functions: pb0 to pb7 (an8 to an15): ad converter input yes port c pc0 to pc7 i/o ? 8-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. yes port e pe0 to pe3 i/o ? 4-bit i/o port ? i/o specifiable in 1 bit units ? pull-up resistors can be turned on and off in 1 bit units. yes res i/o external reset input pin/internal reset output pin no xt1 i ? input for 32.768khz crystal oscillation other functions: ? general purpose input port *connect to v dd 1 when the port is not used. no xt2 i/o ? output for 32.768khz crystal oscillation other functions: ? general-purpose i/o port *must be set for oscilla tion mode and kept open if not to be used. no cf1 i ? input for ceramic resonator other functions: ? general purpose input port *connect to v dd 1 when the port is not used. no cf2 i/o ? output for ceramic resonator other functions: ? general-purpose i/o port *must be set for oscilla tion mode and kept open if not to be used. no
lc87f2c64a no.a1935-11/28 port output types the table below lists the types of port outputs and the presence/absence of a pull-up/down resistor. data can be read into any input port even if it is in the output mode. port name option selected iin units of option type output type pull-up resistor p00 to p07 1bit 1 cmos programmable 2 nch-open drain programmable p10 to p17 1bit 1 cmos programmable 2 nch-open drain programmable p20 to p27 1bit 1 cmos programmable 2 nch-open drain programmable p30 to p34 1bit 1 cmos programmable 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no nch-open drain no pa0 to pa7 1bit 1 cmos programmable 2 nch-open drain programmable pb0 to pc7 1bit 1 cmos programmable 2 nch-open drain programmable pc0 to pc7 1bit 1 cmos programmable 2 nch-open drain programmable pe0 to pe3 1bit 1 cmos programmable 2 nch-open drain programmable xt2 - no 32.768khz crystal oscillator output or nch-open drain when selected as normal port no cf2 - no ceramic resonator output or nch-open drain when selected as normal port no
lc87f2c64a no.a1935-12/28 user option table option name option to be applied on mask-rom version*1 flash-rom version option selected in units of option selection port output type p00 to p07 yes yes 1 bit cmos nch-open drain p10 to p17 yes yes 1 bit cmos nch-open drain p20 to p27 yes yes 1 bit cmos nch-open drain p30 to p34 yes yes 1 bit cmos nch-open drain pa0 to pa7 yes yes 1 bit cmos nch-open drain pb0 to pb7 yes yes 1 bit cmos nch-open drain pc0 to pc7 yes yes 1 bit cmos nch-open drain pe0 to pe3 yes yes 1 bit cmos nch-open drain program start address - no*2 yes - 0000h fe00h base timer watchdog timer watchdog timer period yes yes - 1s 2s 4s 8s low-voltage detect function detection level (enable) - yes - power-on reset level (disable) - yes - * 1: the option selection cannot to be changed after the mask is created. * 2: program start address for the mask-rom version is 0000h.
lc87f2c64a no.a1935-13/28 *note1: connect the ic as shown below to minimize the noise input to the v dd 1. be sure to electrically short the v ss 1, v ss 2 and v ss 3 pins. *note2: the internal memory is sustained by v dd 1. if none of v dd 2 and v dd 3 are backed up, the high level output at the ports are unstable in the hold backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. make sure that the port outputs are held at the low level in the hold backup mode. example of power connection wh en power-save mode is used power supply v dd 1 back-up capacitors v dd 2 v dd 3 v ss 3 v ss 2 v ss 1 lsi
lc87f2c64a no.a1935-14/28 absolute maximum ratings at ta=25c, v ss 1=v ss 2=v ss 3=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 ? v dd 1=v dd 2=v dd 3 -0.3 +6.5 v input voltage vi xt1, cf1, res -0.3 v dd +0.3 input/output voltage vio ports 0, 1, 2, 3, 7, 8, a, b, c, e, xt2, cf2 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1, 2, 3, a, b, c, e ? cmos output select ? per 1 applicable pin -10 ma ioph(2) p71, p72, p73 ? per 1 applicable pin -5 mean output current (note 1-1) iomh(1) ports 0, 1, 2, 3, a, b, c, e ? cmos output select ? per 1 applicable pin -7.5 iomh(2) p71, p72, p73 ? per 1 applicable pin -3 total output current ? ioah(1) port 0, p14 to p17 ? total of all applicable pins -25 ? ioah(2) port 3, a ? total of all applicable pins -25 ? ioah(3) port 0, 3, a p14 to p17 ? total of all applicable pins -45 ? ioah(4) port 2 p10 to p13,pe3 ? total of all applicable pins -25 ? ioah(5) port b, c, pe0 to pe2 ? total of all applicable pins -25 ? ioah(6) port 2, b, c, e p10 to p13 ? total of all applicable pins -45 ? ioah(7) p71, p72, p73 ? total of all applicable pins -5 low level output current peak output current iopl(1) ports 0, 1, 2, 3, a, b, c, e ? per 1 applicable pin 20 iopl(2) port 7, 8 xt2, cf2 ? per 1 applicable pin 10 mean output current (note 1-1) ioml(1) ports 0, 1, 2, 3, a, b, c, e ? per 1 applicable pin 15 ioml(2) port 7, 8 xt2, cf2 ? per 1 applicable pin 7.5 total output current ? ioal(1) port 0, p14 to p17 ? total of all applicable pins 45 ? ioal(2) port 3, a ? total of all applicable pins 45 ? ioal(3) port 0, 3, a p14 to p17 ? total of all applicable pins 80 ? ioal(4) port 2 p10 to p13, pe3 ? total of all applicable pins 45 ? ioal(5) port b, c, pe0 to pe2 ? total of all applicable pins 45 ? ioal(6) port 2, b, c,e p10 to p13 ? total of all applicable pins 80 ? ioal(7) port 7, xt2 ? total of all applicable pins 15 ? ioal(8) port 8, cf2 ? total of all applicable pins 15 ? ioal(9) port 7, 8, xt2, cf2 ? total of all applicable pins 20 power dissipation pd max(1) qfp80 ? ta=-30 to +70 c ? package only t.b.d mw ? ta=-30 to +70 c ? package with thermal resistance board (note 1-2) t.b.d pd max(2) tqfp80j ? ta=-30 to +70 c ? package only t.b.d ? ta=-30 to +70 c ? package with thermal resistance board (note 1-2) t.b.d operating ambient temperature topr -30 +70 c storage ambient temperature tstg -55 +125 note 1-1: the mean output current is a mean value measured over 100ms. note 1-2: semi standards ther mal resistance board (size: 76.1 114.3 1.6tmm, glass epoxy) is used. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lc87f2c64a no.a1935-15/28 allowable operating conditions at ta=-30 to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2 =v dd 3 ? 0.245 s tcyc 200 s 3.0 5.5 v v dd (2) ? 0.735 s tcyc 200 s 2.4 5.5 memory sustaining supply voltage vhd v dd 1 ? ram and register contents sustained in hold mode. 2.2 5.5 high level input voltage v ih (1) ports 0, 1, 2, 3, 8, a, b, c, e, p71, p72, p73 p70 port input /interrupt side ? output disabled 2.4 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side ? output disabled 2.4 to 5.5 0.9v dd v dd v ih (3) xt1, xt2, cf1, cf2, res 2.4 to 5.5 0.75v dd v dd low level input voltage v il (1) ports 0, 1, 2, 3, 8, a, b, c, e, p71, p72, p73 p70 port input /interrupt side ? output disabled 2.4 to 5.5 v ss 0.1v dd +0.4 v il (2) port 70 watchdog timer side ? output disabled 2.4 to 5.5 v ss 0.8v dd -1.0 v il (3) xt1, xt2, cf1, cf2, res 2.4 to 5.5 v ss 0.25v dd instruction cycle time (note 2-1) tcyc (note 2-2) 3.0 to 5.5 0.245 200 s 2.4 to 5.5 0.735 200 external system clock frequency fexcf cf1 ? cf2 pin open ? system clock frequency division ratio = 1/1 ? external system clock duty = 505% 3.0 to 5.5 0.1 12 mhz 2.4 to 5.5 0.1 4 ? cf2 pin open ? system clock frequency division ratio = 1/2 ? external system clock duty = 505% 3.0 to 5.5 0.2 24 2.4 to 5.5 0.2 8 oscillation frequency range (note 2-3) fmcf(1) cf1, cf2 ? 12mhz ceramic oscillation ? see fig. 1. 3.0 to 5.5 12 mhz fmcf(2) cf1, cf2 ? 4mhz ceramic oscillation ? see fig. 1. 2.4 to 5.5 4 fmvmrc(1) ? frequency variable rc source oscillation ? vmraj2 to 0 = 4 ? vmfaj2 to 0 = 0 ? vmsl4m = 0 3.0 to 5.5 10 fmvmrc(2) ? frequency variable rc source oscillation ? vmraj2 to 0 = 4 ? vmfaj2 to 0 = 0 ? vmsl4m=1 2.4 to 5.5 4 fmrc ? internal fast rc oscillation 2.4 to 5.5 500 khz fsrc ? internal slow rc oscillation 2.4 to 5.5 50 fsx?tal xt1, xt2 ? 32.768khz crystal oscillation ? see fig. 2. 2.4 to 5.5 32.768 note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see table 1, 2 for the oscillation constants continued on next page.
lc87f2c64a no.a1935-16/28 continued from preceding page. parameter symbol pin/remarks conditions specification v dd [v] min typ max unit frequency variable rc oscillation usable range opvmrc(1) ? vmsl4m=0 3.0 to 5.5 8 10 12 mhz opvmrc(2) ? vmsl4m=1 2.4 to 5.5 3.5 4 4.5 frequency variable rc oscillation adjustment range vmadj(1) ? 1 step of vmrajn (large range) 2.4 to 5.5 8 24 64 % vmadj(2) ? 1 step of vmfajn (small range) 2.4 to 5.5 1 4 8 electrical characteristics at ta=-30 to +70c, v ss 1=v ss 2=v ss 3=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2, 3, 7, 8, a, b, c, e ? output disabled ? pull-up resistor off ? v in =v dd (including output tr's off leakage current) 2.4 to 5.5 1 a i ih (3) res ? v in =v dd 2.4 to 5.5 1 i ih (4) xt1, xt2 cf1, cf2 ? configured as input ports ? v in =v dd 2.4 to 5.5 1 i ih (5) cf1 ? v in =v dd 2.4 to 5.5 15 low level input current i il (1) ports 0, 1, 2, 3, 7, 8, a, b, c, e ? output disabled ? pull-up resistor off ? v in =v ss (including output tr's off leakage current) 2.4 to 5.5 -1 i il (2) res ? v in =v ss 2.4 to 5.5 -1 i il (3) xt1, xt2 cf1, cf2 ? configured as input ports ? v in =v ss 2.4 to 5.5 -1 i il (4) cf1 ? v in =v ss 2.4 to 5.5 -15 high level output voltage v oh (1) ports 0, 1, 2, 3, a, b, c ? i oh =-1.0ma 4.5 to 5.5 v dd -1 v v oh (2) ? i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ? i oh =-0.2ma 2.4 to 5.5 v dd -0.4 v oh (4) p71, p72, p73 ? i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) ? i oh =-0.2ma 2.4 to 5.5 v dd -0.4 v oh (6) p30, p31, port a (using as pwm) ? i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (7) ? i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (8) ? i oh =-1.0ma 2.4 to 5.5 v dd -0.4 low level output voltage v ol (1) ports 0, 1, 2, 3, a, b, c, e ? i ol =10ma 4.5 to 5.5 1.5 v ol (2) ? i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ? i ol =1.0ma 2.4 to 5.5 0.4 v ol (4) port 7, 8 xt2, cf2 ? i ol =1.6ma 3.0 to 5.5 0.4 v ol (5) ? i ol =1.0ma 2.4 to 5.5 0.4 pull-up resistance rpu ports 0, 1, 2, 3, 7, a, b, c, e ? v oh =0.9v dd 4.5 to 5.5 15 40 70 k 2.4 to 4.5 25 70 150 hysteresis voltage vhys ports 0, 1, 2, 3, 7, a, res 2.4 to 5.5 0.1v dd v pin capacitance cp all pins ? f=1mhz ? ta=25c ? for pins other than that under test: v in =v ss 2.4 to 5.5 10 pf
lc87f2c64a no.a1935-17/28 serial i/o characteristics at ta=-30 to +70 c, v ss 1=v ss 2=v ss 3=0v 1. sio0 serial i/o characteristics (note 4-1-1) parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck0(p12) ? see fig. 6. 2.4 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 tsckha(1) ? continuous data transmission/reception mode ? see fig. 6. (note 4-1-2) 4 output clock frequency tsck(2) sck0(p12) ? cmos output selected ? see fig. 6. 2.4 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 tsckha(2) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc serial input data setup time tsdi sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.4 to 5.5 0.03 s data hold time thdi 0.03 serial output input clock output delay time tdd0(1) so0(p10), sb0(p11) ? continuous data transmission/reception mode (note 4-1-3) 2.4 to 5.5 (1/3)tcyc +0.05 tdd0(2) ? synchronous 8-bit mode (note 4-1-3) 1tcyc +0.05 output clock tdd0(3) (note 4-1-3) (1/3)tcyc +0.05 note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: when using serial clock input under continuous data transmission/reception mode, the time from si0run is set while serial clock is ?h? to the first falling edge of serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc87f2c64a no.a1935-18/28 2. sio1 serial i/o characteristics (note 4-2-1) parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) ? see fig. 6. 2.4 to 5.5 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.4 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.4 to 5.5 0.03 s data hold time thdi(2) 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.4 to 5.5 (1/3)tcyc +0.05 note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta=-30 to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p70) int1(p71) int2(p72) int3(p73) int4(p20 to p23) int5(p24 to p27) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.4 to 5.5 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.4 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.4 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.4 to 5.5 256 tpih(5) tpil(5) nkin(p72) ? high speed clock counter countable 2.4 to 5.5 1/12 tpil(6) res ? external reset input mode ? resetting is enabled 2.4 to 5.5 200 s
lc87f2c64a no.a1935-19/28 ad converter characteristics at v ss 1=v ss 2=v ss 3=0v <12bits ad converter mode / ta=-30 to +70 c> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p80) to an7(p87) an8(pb0) to an15(pb7) 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 16 lsb conversion time tcad ? see conversion time calculation formulas. (note 6-2) 4.0 to 5.5 32 115 s 3.0 to 5.5 64 115 analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh ? vain=v dd 3.0 to 5.5 1 a iainl ? vain=v ss 3.0 to 5.5 -1 <8bits ad converter mode / ta=-30 to +70 c> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p80) to an7(p87) an8(pb0) to an15(pb7) 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb conversion time tcad ? see conversion time calculation formulas. (note 6-2) 4.0 to 5.5 20 95 s 3.0 to 5.5 40 95 analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh ? vain=v dd 3.0 to 5.5 1 a iainl ? vain=v ss 3.0 to 5.5 -1 conversion time cal culation formulas: 12bits ad converter mode : tcad(conversion time) = ((52/(ad division ratio))+2) (1/3) tcyc 8bits ad converter mode : tcad(conversion time) = ((32/(ad division ratio))+2) (1/3) tcyc external oscillation (fmcf) operating supply voltage range (v dd ) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) ad conversion time (tcad) 12bit ad 8bit ad cf-12mhz 4.0v to 5.5v 1/1 250ns 1/8 34.8 s 21.5 s 3.0v to 5.5v 1/1 250ns 1/16 69.5 s 42.8 s cf-4mhz 3.0v to 5.5v 1/1 750ns 1/8 104.5 s 64.5 s note 6-1: the quantization error (1/2l sb) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from th e time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12-bit ad conversion mode after a system reset. ? the first ad conversion is performe d after the ad conversion mode is switc hed from 8-bit to 12-bit conversion mode.
lc87f2c64a no.a1935-20/28 power-on reset (por) characteristics at ta=-30 to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit por release voltage porrl ? select from option. (note 7-1) 1.67v 1.67 v 1.97v 1.97 2.07v 2.07 2.37v 2.37 2.57v 2.57 2.87v 2.87 3.86v 3.86 4.35v 4.35 detection voltage unknown state pouks ? see fig. 8. (note 7-2) 0.7 0.95 power supply rise time poris ? power supply rise time from 0v to x v. 100 ms note7-1: the por release level can be selected out of 7 levels only when the lvd reset function is disabled. note7-2: por is in an unknown state before transistors start operation. low voltage detection reset (lvd) characteristics at ta=-30 to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit lvd reset voltage (note 8-2) lvdet ? select from option. (note 8-1) (note 8-3) ? see fig. 9. 1.91v 1.91 v 2.01v 2.01 2.31v 2.31 2.51v 2.51 2.81v 2.81 3.79v 3.79 4.28v 4.28 lvd hysteresis width lvhys 1.91v 55 mv 2.01v 55 2.31v 55 2.51v 55 2.81v 60 3.79v 65 4.28v 65 detection voltage unknown state lvuks ? see fig. 9. (note 8-4) 0.7 0.95 v low voltage detection minimum width (reply sensitivity) tlvdw ? lvdet-0.5v ? see fig. 10. 0.2 ms note8-1: the lvd reset level can be selected out of 7 levels only when the lvd reset function is enabled. note8-2: lvd reset voltage specification values do not include hysteresis voltage. note8-3: lvd reset voltage may exceed its specification valu es when port output state changes and/or when a large current flows through port. note8-4: lvd is in an unknown state before transistors start operation.
lc87f2c64a no.a1935-21/28 consumption current characteristics at ta = -30 c to +70 c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit current consumption during normal operation (note 9-1) iddop(1) v dd 1 =v dd 2 =v dd 3 ? fmcf=12mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation stopped. ? system clock: cf oscillation 12mhz ? divider : 1/1 4.5 to 5.5 8.4 22.1 ma 3.0 to 3.6 4.9 12.1 iddop(2) ? fmcf=4mhz cera mic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation stopped. ? system clock: cf oscillation 4mhz ? divider : 1/1 4.5 to 5.5 3.5 10.0 2.4 to 3.6 2.8 6.3 iddop(3) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? fmvmrc=10mhz frequency variable rc oscillation ? internal rc oscillation stopped. ? system clock: frequency variable rc oscillation 10mhz ? divider :1/1 4.5 to 5.5 6.9 16.6 2.4 to 3.6 4.2 101 iddop(4) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? fmvmrc=4mhz frequency variable rc oscillation ? internal rc oscillation stopped. ? system clock: frequency variable rc oscillation 4mhz ? divider :1/1 4.5 to 5.5 2.8 8.5 2.4 to 3.6 2.5 5.4 iddop(5) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation=fast rc oscillation ? system clock: fast rc oscillation ? divider :1/1 4.5 to 5.5 400 1000 a 2.4 to 3.6 300 600 iddop(6) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation stopped. ? system clock: 32.768khz ? divider :1/1 4.5 to 5.5 74 269.4 2.4 to 3.6 26.1 110.1 note 9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. continued on next page.
lc87f2c64a no.a1935-22/28 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit current consumption during halt mode (note 9-1) iddhalt(1) v dd 1 = v dd 2 = v dd 3 halt mode ? fmcf=12mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation stopped. ? system clock: cf oscillation 12mhz ? divider : 1/1 4.5 to 5.5 3.3 8.4 ma 3.0 to 3.6 1.7 4.3 iddhalt(2) halt mode ? fmcf=4mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation stopped. ? system clock: cf oscillation 4mhz ? divider : 1/1 4.5 to 5.5 0.3 4.1 2.4 to 3.6 0.1 1.8 iddhalt(3) halt mode ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? fmvmrc=10mhz frequency variable rc oscillation ? internal rc oscillation stopped. ? system clock: frequency variable rc oscillation 10mhz ? divider :1/1 4.5 to 5.5 2.3 5.8 2.4 to 3.6 1.3 3.2 iddhalt(4) halt mode ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? fmvmrc=4mhz frequency variable rc oscillation ? internal rc oscillation stopped. ? system clock: frequency variable rc oscillation 4mhz ? divider :1/1 4.5 to 5.5 1.0 2.5 2.4 to 3.6 0.5 1.3 iddhalt(5) halt mode ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation=fast rc oscillation ? system clock: fast rc oscillation ? divider :1/1 4.5 to 5.5 200 500 a 2.4 to 3.6 100 200 iddhalt(6) halt mode ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? frequency variable rc oscillation stopped. ? internal rc oscillation stopped. ? system clock: 32.768khz ? divider :1/1 4.5 to 5.5 57.2 230.9 2.4 to 3.6 13.6 83.2 note 9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. continued on next page.
lc87f2c64a no.a1935-23/28 continued from preceding page parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit current consumption during hold mode (note 9-1) iddhold(1) v dd 1 = v dd 2 = v dd 3 hold mode ? cf1=v dd or open (when using external clock) 4.5 to 5.5 0.1 52 a 2.4 to 3.6 0.04 22 current consumption during date/time clock hold mode (note 9-1) iddhold(3) date/time clock hold mode ? cf1=v dd or open (when using external clock) ? fmx?tal=32.768khz crystal oscillation ? normal mode 4.5 to 5.5 49.9 213 2.4 to 3.6 9.6 73.4 iddhold(4) date/time clock hold mode ? cf1=v dd or open (when using external clock) ? fmx?tal=32.768khz crystal oscillation ? power save mode 4.5 to 5.5 1.0 94.3 2.4 to 3.6 0.76 39.3 note9-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw v dd 1 ? current of the flash module 3.0 to 5.5 5 10 ma programming time tfw(1) ? erase time 3.0 to 5.5 20 30 ms tfw(2) ? program time 40 60 s uart (full duplex) operating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit transfer rate ubr utx1(p00), urx1(p01) utx2(p02), urx2(p03) 2.4 to 5.5 16/3 8192/3 tcyc data length: 7, 8, and 9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: none example of continuous 8-bit data transmission mode processing (first transmit data=55h) example of continuous 8-bit da ta reception mode processing (first receive data=55h) transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit stop bit end of reception ubr receive data (lsb first) start of reception start bit
lc87f2c64a no.a1935-24/28 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a our designated oscillation characteristics eval uation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table1. characteristics of a sample main system clock oscillator circuit with a ceramic oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ] rd [ ] typ [ms] max [ms] the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics eval uation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table2. characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ] rd [ ] typ [s] max [s] 32.768khz the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
lc87f2c64a no.a1935-25/28 reset time and oscillation stable time hold release signal and os cillation stable time figure 4 oscillation stabilization times internal rc oscillation cf1, cf2 xt1, xt2 operation mode hold release signal without hold release signal hold release signal valid tmscf tmsxtal hold halt power suppl y res internal rc oscillation cf1, cf2 xt1, xt2 reset time tmscf tmsxtal operating mode unfixed reset instruction execution v dd v dd limit 0v
lc87f2c64a no.a1935-26/28 figure 5 reset circuit figure 6 serial i/o output waveforms figure 7 pulse input timing signal waveform c res v dd r res res note: external circuits for reset may vary depending on the usage of por and lvd. please refer to the user?s manual for more information. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transmission period (sio0) data ram transmission period (sio0)
lc87f2c64a no.a1935-27/28 figure 8 waveform observed when only por is used (lvd not used) (reset pin: pull-up resistor r res only) ? the por function generates a reset only wh en power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. figure 9 waveform observed when both por and lvd functions are used (reset pin: pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level. por release voltage(porrl) v dd res unknown-state (pouks) (a) (b) reset period reset period 100
lc87f2c64a no.a1935-28/28 figure 10 low voltage detection minimum width (example of momentary power loss/voltage variation waveform) ps ps v dd lvd reset volta g e tlvdw v ss lvd release voltage lvdet-0.5v on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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