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this is information on a product in full production. october 2015 docid028553 rev 1 1/45 L5963 dual monolithic switching regulator with ldo and hsd datasheet - production data features ? two step-down synchronous switching voltage regulators with internal power switches: ? wide input voltage range (from 3.5 v to 26 v) ? internal high-side/ low-side ndmos ? 1 v minimum output ? 3.0 a load current ? 250 khz free-run frequency ? 250 khz < f < 2 mhz synchronization range ? integrated soft-start ? independent hardware enable pins ? independent power supply ? 180 pwm output phase shift ? programmable switching frequency divider by 1, 2, 4 or 8 between the two dc/dc regulators ? power good function ? one standby / linear regulator ? output voltage programmable with external resistor divider ? 250 ma maximum current capability ? backup function ? power good function ? one high side driver ? 0.5 v max drop @ 0.5 a ? protected against short to ground and battery, loss of ground and battery, unsupplied short to battery ? programmable under voltage battery detector ? under voltage threshold adjustable through dedicated pin (vdin) ? load dump protection ? independent thermal protection on all regulators ? independent current limit on all regulators ? extremely low quiescent current in standby conditions ? power good / adjustable voltage detector outputs to realize customized power up/down sequences description L5963 is a dual step-down switching regulator with internal power switches, high side driver and a low drop-out linear regulator that can operate as standby regulator or normal ldo. all the regulators can be connected directly to the vehicle battery. in addition to an adjustable voltage detector, voltage supervisors are available. the two dc-dc converters can work in free-run condition or synchronize themselves to an external clock. dc/dcs' pwm outputs have a 180 phase shift. the high operating frequency allowed by the synchronization input helps to reduce am and fm interferences and grants the use of small and low cost inductors and capacitors. this ic finds application in the automotive segment, where load dump protection and wide input voltage range are mandatory. a slug-up package option is available for applications which require heatsink use. in standby condition the device guarantees extremely low quiescent current (25 a typical @ -40 c < t < 85 c) '!0'03 '!0'03 powersso-36 (exposed pad) powersso-36 (slug-up) table 1. device summary order code package packing L5963d-ehx powersso36 (exposed pad) tube L5963d-eht tape & reel L5963u-kbx powersso36 (slug-up) tube L5963u-kbt tape & reel www.st.com
contents L5963 2/45 docid028553 rev 1 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 operative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 blocks functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.1 unregulated supply input voltage (vinldo) . . . . . . . . . . . . . . . . . . . . . 17 6.2.2 low voltage warning monitor (related pins: vdin, vdout, vddly) . . . 17 6.2.3 power-good reset (related pins: ldook, ldookdly) . . . . . . . . . . . . . 18 6.2.4 power-good function of dc/dc1 (related pins: sw1ok, sw1okdly) . 18 6.2.5 over voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2.6 power ground (pgnd1 and pgnd2) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.7 signal ground (sgnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.8 pwm signal ground (swgnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.9 tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.10 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.11 high-side driver (hsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.12 switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 output inductor (lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 output capacitors (cout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 input capacitors (c in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4 bootstrap capacitor (cboot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
docid028553 rev 1 3/45 L5963 contents 3 7.5 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 package variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 powersso-36 (exposed pad) package information . . . . . . . . . . . . . . . . . 38 9.3 powersso-36 (slug-up) package information . . . . . . . . . . . . . . . . . . . . . 41 9.4 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
list of tables L5963 4/45 docid028553 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. thermal data (slug-down configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. components value for different output voltage cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. maximum suggested power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. powersso-36 exposed pad package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. powersso-36 slug-up package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
docid028553 rev 1 5/45 L5963 list of figures 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. example of a typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. example of usage of two regulators in the same application . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. pinout configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. pssr ldo 50 ma load vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. efficiency vs. output current (vin = 14 v, fsw = 2 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. efficiency vs. output current (vin = 14 v, fsw = 250 khz) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. low voltage warning monitor & delay schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. linear regulator diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. enable timing for standby regulator (enldo pin connect to supply directly) . . . . . . . . . . . 20 figure 11. enable timing for linear regulator (pin enldo isn't connected to vinldo) . . . . . . . . . . . . 21 figure 12. switching regulators diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. closed loop system with type iii network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14. type iii compensated network diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. layout configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. powersso-36 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17. powersso-36 (slug-up) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 18. powersso-36 (exp. pad) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. powersso-36 (slug up) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
overview L5963 6/45 docid028553 rev 1 1 overview the L5963 integrates two switching mode synchronous step down converters, a linearly regulated power supply, a protected high side driver and voltage detectors. to guarantee a robust operation, all the outputs have independent thermal protection and current limitation. the two switching mode synchronous step-down converters employ voltage mode control and feed forward functions to provide good load regulation and line regulation. each converter has its own enable. the users can adjust the output voltage of the two converters by an external resistor divider. if the converters need to work with a frequency different from the free running frequency, in order to consider emc performance in system level, they can be synchronized to an external clock by applying it on the syncin pin. the frequency should be higher than half of the free running frequency. if there are more than one L5963 in the system they can work in master-slave configuration, to make sure all the L5963 have the same operating frequency of the master device. this master-slave function is implemented by a dedicated pin syncout which always gives the operating frequency of dc/dc1 (for details, see the next chapter) a dedicated voltage detector is integrated in the first switching converter to monitor dc/dc1 output. when the output voltage of dc/dc1 goes above the threshold, sw1ok is released and goes back to high with configurable delay set by a capacitor on the sw1okdly pin. the linear regulator can work as standby regulator with low i q or as a non-standby regulator. connecting its enable enldo to its supply vinldo the regulator works as a standby regulator, while connecting enldo to signal lower than 5 v the regulator works as non- standby regulator, with higher load capability but also higher quiescent current. in standby state, i.e. only the linear regulator is powered and works as a standby regulator, with a load below 100 a the device has a quiescent current of just 25 a. the small drop-out voltage of the linear regulator allows its use with low operating supply voltage. in many cases, the linear regulator has to provide voltages to devices which need the reset function, like a mcu: this is provided by the ldook output, that is pulled low when voutldo goes below a threshold. once voutldo returns above that threshold, with a specified hysteresis, ldook goes back to high with a configurable delay set by a capacitor on pin ldookdly. the high side driver is enabled by a dedicated pin and has a very low drop-out voltage. protection circuits, like independent thermal protection, ocp, ovp and some special protections (loss of gnd, spu, short to supply and so on), are implemented to make it very robust (see next chapter for details). L5963 also embeds a voltage monitor (vdout), adjustable by means of an external resistor divider, that can be used to sense the battery or other voltages in the system. sensing voltage is fed to pin vdin. for instance, vdout might be used to monitor the output of dc/dc2, realizing in this way the power good function for that block. vdout is pulled low when voltage on vdin goes below the specified threshold. once vdin returns above that threshold, with a specified hysteresis, vdout goes back to high with a configurable delay set by a capacitor on pin ldookdly two different packages are available. the powersso-36 slug-down allows to dissipate the heat on the board and reduce the application size. the slug has to be connected to the ground plane. this is the package suggested for standard applications. when this is not enough, because the L5963 is used as pre-regulator for high consuming applications and both the 2 dc-dc are working at high currents, the psso36 slug-up allows the use of a heat-sink to make easier power dissipation.
docid028553 rev 1 7/45 L5963 block diagram 44 2 block diagram figure 1. block diagram '!0'03 "andgap 2ef )nternalregulator 6).,$/ ,inearregulator &",$/ 6/54,$/ 2eset$elay ,$//+ ,$//+$,9 6oltagesupervisory with0/2delay 6$). 6$/54 6$$,9 6"!4 )nternalregulator /scillator &req,ogic 3ync,ogic #,/#+ 39.#). 39.#/54 &2$)6 #,+ #,+ %.,$/ %.(3$ %.37 %.37 3witching2egulator 6).37 "3 07- &"37 0ower'ood $elay07- 37/+ 37/+$,9 #/-0 3witching2egulator 6).37 "3 07- &"37 #/-0 ,ogic #ontrol #,+ #,+ (igh3idedriver (3$ 6).(3$ 0'.$ 0'.$ 37'.$ 3'.$ 4!" '.$ 2ef?6 2ef?6 2ef?6 6bg 6bg 2ef?6
application diagrams L5963 8/45 docid028553 rev 1 3 application diagrams figure 2. example of a typical application diagram 287b6: (1b/'2 (1b6: (1b6: 6,1.b&/.b,1 9',1b2. +6'b,1 (1b+6' 6,1.b&/.b287 287b/'2 /'2b9287b2. 6:b9287b2. 9',1 +6'b287 9,1b6: 287b6: 9,1b/'2 & s9 & q & q & q)9 5 . ' 5 5 . & q 5 . & x9 & q)9 5 5 & q 5 . & x)9 & q & q)9 5 . & q & x9 5 . 5 . & q) & x9 & q9 & q & x9 & s / x+ & q 5 733 & q9 & q / x+ & s9 5 & s 5 . & x)9 & x)9 & x9 9%dww 9%dww 9%dww & x)9 5 & x)9 9%$7 9,1/'2 (1/'2 9,16: 7$% 9,16: )%6: )%6: 3:0 3:0 %6 %6 (16: (16: 3*1' 3*1' &203 &203 6<1&b,1 6<1&b287 )5',9 6:2. 6:2.'/< )%/'2 9287/'2 /'22. /'22.'/< 9'287 9',1 9''/< ,1+6' 287+6' (1+6' 1& 6*1' 6:*1' 7$% 8 /
docid028553 rev 1 9/45 L5963 application diagrams 44 figure 3. example of usage of two regulators in the same application 287b6:b 287b/'2b 287b6:b & s9 & q 5 . 5 . & x9 & q)9 5 5 & q & x9 5 . 5 . & x9 & q & x9 / x+ & q 5 & q / x+ & s9 5 & x9 9%$7 7$% 1& 6*1' 6:*1' 7$% 287b6: 287b/'2 287b6: & s9 & q 5 . 5 5 . & x9 5 5 & q & x9 5 . 5 . & x9 & q & x9 / x+ & q 5 & q / x+ & s9 5 & x9 w & 9%$7 7$% 1& 6*1' 6:*1' 7$% *$3*36 287/'2 5. x)9 & 9%dww 9%dww x)9 & 9,1b6: x)9 & q)9 & q)9 & ' x)9 & 9%dww 9,1b6: x)9 & q)9 & 9%dww x)9 & q)9 & x)9 5 x)9 & q & q & q & 6:b9287b2. /'2b9287b2. 6,1.b&/.b287 (1b+6' +6'b,1 9',1b2. 6,1.b&/.b,1 (1b6: (1b6: (1b/'2 & 9%dww 733 q)9 & x)9 5 q & q & q & 9,1b/'2 6:b9287b2. /'2b9287b2. 6,1.b&/.b287 (1b+6' +6'b,1 9',1b2. 6,1.b&/.b,1 (1b6: (1b6: (1b/'2 9%dw x)9 & 733 q)9 & (1+6' ,1+6' 9''/< 9'287 /'22.'/< /'22. 6:2.'/< 6:2. )5',9 6<1&b287 6<1&b,1 (16: (16: 9,16: 9,16: (1/'2 9,1/'2 (1+6' ,1+6' 9''/< 9'287 /'22.'/< /'22. 6:2.'/< 6:2. )5',9 6<1&b287 6<1&b,1 (16: (16: 9,16: 9,16: (1/'2 9,1/'2 287+6' 9',1 9287/'2 )%/'2 &203 &203 3*1' 3*1' %6 %6 3:0 3:0 )%6: )%6: 287+6' 9',1 9287/'2 )%/'2 &203 &203 3*1' 3*1' %6 %6 3:0 3:0 )%6: )%6: / 8 5. s & q9 & s & q9 & q) & 5. 5. 5. q & +6'b287 9',1 / 8 5. s & q9 & s & q9 & q) & 5. 5. 5. q & +6'b287 9',1
pins description L5963 10/45 docid028553 rev 1 4 pins description figure 4. pinout configuration 4! " 0'.$ %.37 "3 07- %.(3$ 6).37 39.#/54 39.#). &2$)6 6$/54 &"37 #/-0 3'.$ 6$). 6).(3$ 6$$,9 (3$ 0'.$ %.37 "3 07- %.,$/ 6).37 37/+ 4%34 37/+$,9 6"!4 37'.$ &"37 #/-0 6).,$/ ,$//+$,9 ,$//+ 6/54,$/ &",$/ '!0'03 3lug down '!0'03 4!" 0'.$ %.37 "3 07- %.(3$ 6).37 39.#/54 39.#). &2$)6 6$/54 &"37 #/-0 3'.$ 6$). 6).(3$ (3$ 6$$,9 0'.$ %.37 "3 07- %.,$/ 6).37 37/+ 4%34 37/+$,9 6"!4 37'.$ &"37 #/-0 6).,$/ ,$//+$,9 ,$//+ 6/54,$/ &",$/ 3lug up
docid028553 rev 1 11/45 L5963 pins description 44 table 2. pins description pin # name type function 1 tab n.a. device slug terminal. to be connected to ground 2 pgnd1 ground switching regulator 1 power ground 3 ensw1 input switching regulator 1 enable. 1.8/3.3 v compatible 4 bs1 supply switching regulator 1 boosted supply 5 pwm1 output switching regulator 1 switching output 6 enhsd input enable for high side driver. 1.8/3.3 v compatible 7 vinsw1 supply switching regulator 1 supply voltage 8 syncout output external synchronization output (push-pull) 9 syncin input external synchronization input draft 10 frdiv input/output switching frequency divider setting 11 vdout output voltage detector output (open drain) 12 fbsw1 input/output switching regulator 1 feedback voltage 13 comp1 input/output switching regulator 1 compensation 14 sgnd ground ground for linear blocks 15 vdin input voltage detector threshold setting 16 vinhsd supply high side driver supply 17 hsd output high side driver output 18 vddly input/output voltage detector delay setting 19 fbldo input/output ldo feedback voltage 20 voutldo output ldo output 21 ldook output ldo voltage detector output (open drain) 22 ldookdly input/output ldook delay setting 23 vinldo supply ldo supply 24 comp2 input/output switching regulator 2 compensation 25 fbsw2 input/output switching regulator 2 feedback voltage 26 swgnd ground low-power switching ground 27 vbat supply common linear blocks supply voltage 28 sw1okdly input/output sw1ok delay setting 29 test n.a. pin for testing purposes. to be left unconnected 30 sw1ok output switching regulator 1 voltage detector output (open drain) 31 vinsw2 supply switching regulator 2 supply voltage 32 enldo input ldo enable. 1.8/3.3 v compatible 33 pwm2 output switching regulator 2 switching output 34 bs2 supply switching regulator 2 boosted supply 35 ensw2 input switching regulator 2 enable. 1.8/3.3 v compatible 36 pgnd2 ground switching regulator 2 power ground
electrical specifications L5963 12/45 docid028553 rev 1 5 electrical specifications 5.1 absolute maximum ratings 5.2 thermal data table 3. absolute maximum ratings pin name / symbol parameter value unit vbat op vin op operating input voltage -0.3 to +26 v vbat max vin max maximum transient supply voltage -0.3 to +40 v pgnd1/2, sgnd, swgnd, tab ground pins voltage -0.3 to +0.3 v enldo ldo enable pin voltage -0.3 to +40 v v pinop other pins operating voltage -0.3 to +3.6 v v pinmax other pins voltage -0.3 to +4.6 v t op operating ambient temperature range -40 to +105 c t stg storage temperature range -55 to +150 c t j junction temperature 150 c table 4. thermal data (slug-down configuration) symbol parameter board value unit r th j-a-2s thermal resistance junction-to-ambient 2s 53 c/w r th j-a-2s2p 2s2p 27 c/w r th j-a-2s2pv 2s2p+vias 22 c/w table 5. thermal data symbol parameter value unit r th j-case thermal resistance junction-to-case 1.5 c/w
docid028553 rev 1 13/45 L5963 electrical specifications 44 5.3 electrical characteristics vbat = vin = 14.4 v, t amb = 25 c unless otherwise specified. table 6. electrical characteristics symbol parameter test conditions min typ max unit inputs and controls vbat op vbat operating range standby mode voutldo = 1.2 v/100 ma voutldo = 3.3 v/100 ma 3.5 4 - - 26 26 v v i q total quiescent current shutdown mode - 1.5 2 a standby mode; iload ldo = 100 a - 23 28 ov vbat overvoltage shut-down threshold on vbat vbat rising 27 29 31 v uv vbat undervoltage shut-down threshold on vbat vbat falling vdout forced to 0 v 2.7 3 3.3 v hys uv hysteresis on uv vbat - - 0.1 0.5 v enmin min voltage for enable pins high level - 1.6 - - v enmax max voltage for enable pins low level ---1v r frdiv thresholds of value of resistor connected between frdiv pin and ground fsw sw2 = fsw sw1 0-30 k fsw sw2 = fsw sw1 /2 60 - 70 fsw sw2 = fsw sw1 /4 110 - 115 fsw sw2 = fsw sw1 /8 180 - ? voltage detector thr vdin voltage detector input voltage threshold - 0.9 0.94 0.98 v hys vdin voltage detector input voltage hysteresis - - 30 40 mv vmax vdout vdout saturation voltage i = 1 ma in vdout pin - - 0.1 v i vddly vddly output current - 6 9 12 a thr vddly vddly threshold - 2.1 2.3 2.5 v linear regulator v fbldo feedback voltage i load = 100 ma 990 1000 1010 mv uv ldo undervoltage shut-down threshold on ldo vinldo decreasing - 2.2 2.4 v hys ldo hysteresis on uvldo - - - 100 mv ldr ldo fbldo load regulation 10 ma < i load < 250 ma - 5 - mv lnr ldo fbldo line regulation 3.5 < vinldo < 26 v iload = 100 ma - 1 - mv
electrical specifications L5963 14/45 docid028553 rev 1 v fbldo / v fbldo fbldo undershoot/overshoot (3) 5 ma ? 250 ma iload transition -5 - 5 % 8 ? 18 v vinldo transition -5 - 5 vdo ldo drop-out voltage voutldo = 3.3 v iload = 250 ma voutldo decreasing of 100 mv - 270 320 mv ishort ldo short circuit current limit voutldo shorted to ground - 350 420 ma ishort st-by voutldo (st-by) shorted to ground -6580ma psrr ldo power supply rejection ratio iload = 50 ma, 10 hz < f < 10 khz 1 vac pp on vinldo -70-db n ldo output noise 20 hz < f < 20 khz iload = 5 ma - 100 - v tsd ldo thermal shut-down temperature temperature rising 150 160 - c hys tsdldo hysteresis on thermal shutdown temperature -5-15c co output capacitance - 3 - - f esr output capacitor esr - - - 0.2 ? voltage detector on ldo thr ldook / v fbldo ldook threshold as percentage of fbldo voltage - 919497 % hys ldook hysteresis on ldook - - 90 - mv vmax ldook ldook saturation voltage i = 1 ma in ldook pin - - 0.2 v tglitch ldook glitch filter time for ldo-ok - 5 12 20 s i ldookdly ldookdly output current - 7 10 13 a thr ldookdly ldookdly threshold - 2 2.2 2.4 v switching regulators (1) , (2) v fbswx feedback voltage i load = 100 ma 980 1000 1020 mv ldr swx fbswx load regulation 50 ma < i load < 1 a - 1 - mv lnr swx fbswx line regulation 3.5 v < vinswx < 26 v - 1 - mv uv sw1 undervoltage shut-down threshold on sw1 vinswx decreasing - 2.8 3 v hys sw1 hysteresis on uv sw1 - - 0.15 - v uv sw2 undervoltage shut-down threshold on sw2 vinswx decreasing - 2.8 3 v hys sw2 hysteresis on uv sw2 - - 0.15 - v v fbswx / v fbswx fbswx pin undershoot/overshoot (3) 500 ma ? 1.5 a iload transition -5 - 5 % 8 ? 18 v vinswx transition -5 - 5 % table 6. electrical characteristics (continued) symbol parameter test conditions min typ max unit
docid028553 rev 1 15/45 L5963 electrical specifications 44 ilim sw1 peak current limitation on sw1 - 2.5 3 3.5 a ilim sw2 peak current limitation on sw2 - 3 3.5 4 a fsw free-run switching frequency - 225 250 275 khz fsync switching frequency range 50% duty-cycle wave on sync pin 250 - 2000 khz ron hs high side mos on resistance vinswx > 3.5 v; including bonding wires -85-m ron ls low side mos on resistance including bonding wires - 105 - m ? efficiency free run frequency voutsw1/2 = 5 v; iload = 2.5 a voutsw1/2 = 5 v; iload = 1 a -90 93 -% v fbswx / t fb pin slope at turn-on including bonding wires - 0.95 - v/ms tsd swx thermal shutdown temperature temperature rising 150 160 - c hys tsdswx hysteresis on thermal shutdown temperature - 5 - 15 c thr sw1ok / v fbsw1 sw1ok threshold as percentage of fbsw1 voltage - 919497 % hys sw1ok hysteresis on sw1ok - - 35 50 mv vmax sw1ok sw1ok saturation voltage i = 1 ma in sw1ok pin - - 0.2 v tglitch sw1ok glitch filter time for sw1-ok - 9 13 17 s i sw1okdly sw1okdly output current - 6 10 13 a thr sw1okdly sw1okdly threshold - 2 2.2 2.4 v t on-min (3) minimum on time - - 20 - ns high side driver vdrop hsd output saturation i load = 0.5 a - 140 170 mv ishort hsd short circuit current limit - 0.7 1 1.3 a tsd hsd thermal shut-down temperature temperature rising 150 160 - c hys tsdhsd hysteresis on thermal shutdown temperature - 5 - 15 c 1. test guaranteed by application measurements. 2. tests involving switching frequencies higher than 1 mhz are guaranteed by design. 3. not tested at ate. table 6. electrical characteristics (continued) symbol parameter test conditions min typ max unit
electrical specifications L5963 16/45 docid028553 rev 1 figure 5. pssr ldo 50 ma load vs. frequency figure 6. efficiency vs. output current (vin = 14 v, fsw = 2 mhz) figure 7. efficiency vs. output current (vin = 14 v, fsw = 250 khz) n +] g% n n n n *$3*36 (iilflhqf\ /rdg p$ 9 9 *$3*36 (iil f l hqf\ /rdg p$ 9 9 *$3*36
docid028553 rev 1 17/45 L5963 functional description 44 6 functional description 6.1 operative modes L5963 has three main operative modes: ? shutdown mode: all enable pins are low and the device is completely off. in this condition the quiescent current is typically 1.5 a. ? standby mode: the linear regulator is configured as stand-by regulator by connecting enldo directly to vinldo. in this condition the quiescent current is typically 25 a. ? normal mode: the linear regulator works as ldo and/or other blocks (dc/dc or hsd) are turned on. 6.2 blocks functional description 6.2.1 unregulated supply input voltage (vinldo) this terminal provides the power for internal circuitry to bias band-gap reference, standby regulator and other circuitry in the device. if backup function is needed, an external capacitor connected to this pin shall be charged through an external diode which is used to block reverse discharging. with backup function, when the system battery is removed or drops too low suddenly, the internal bias and regulator can operate correctly for a certain time, which avoids mcu to work abnormally and allows mcu to have enough time to turn-off. 6.2.2 low voltage warning monitor (related pins: vdin, vdout, vddly) an external voltage can be sensed through the vdin pin. this voltage is scaled using an external resistor network and compared with an internal threshold to detect a low voltage condition ( figure 8. ). once the input voltage is below the threshold, the low voltage warning output terminal (vdout) is pulled low after the designed glitch-filtering (~12 s). vdout is an open drain output. if the input returns above the threshold with the specified hysteresis, vdout is released after a defined delay, it is determined by the capacitor on pin vddly. the threshold is fixed to 0.95 v typ. the capacitor on the vddly pin sets the vdout delay. a current source (~9 a) on this pin charges the external capacitor to generate the required delay, programmable by adjusting the value of the capacitor. this voltage monitor can also be used to monitor dc/dc2 output. changing the ratio of the external resistor divider the low voltage warning threshold can be adjusted.
functional description L5963 18/45 docid028553 rev 1 figure 8. low voltage warning monitor & delay schematic 6.2.3 power-good reset (related pins: ldook, ldookdly) ldook monitors the regulator output voutldo. its circuit topology is the same as the voltage detector one ( figure 8 ). its threshold is fixed to 95% typ of the feedback voltage, and the hysteresis is always ~2% typ. pin ldook is an open drain output, and pin ldookdly is used to adjust the delay in the release of ldook output. 6.2.4 power-good function of dc/dc1 (related pins: sw1ok, sw1okdly) sw1ok monitors dc/dc1 output. its circuit topology is the same as the voltage detector one ( figure 8 ). its threshold can't be adjusted, it is always 95% typ of the feedback voltage, and the hysteresis is ~35mv typ. pin sw1ok is an open drain output, and pin sw1okdly is used to adjust its delay. 6.2.5 over voltage shutdown two internal over voltage shutdown (ov) blocks are included in L5963. one (ov1) senses vbat pin, the other (ov2) detects vinldo pin. if vbat gets too high, to prevent any damage, dc/dc1, dc/dc2 and the high-side driver are disabled by ov1. they will be turned on once vbat returns below the detection threshold with the specified hysteresis. if linear regulator works as a non-standby regulator and vinldo gets too high, to prevent any damage the ldo is disabled by ov2. it is turned on once vinldo returns below the detection threshold with the specified hysteresis. on the contrary, the linear regulator works as a standby regulator, ov2 doesn't intervene and the regulator continues to work even if vinldo increases. *$3*36 6 5 4 4 6 5 4 4 %dwwhu\ )%6:slq jrrgixqfwlrq szpsrzhu rswlrqdo 9',1 97+ &203 ghjolwfk ygg 54 64 odwfk odwfk :lqgrzfrps odwfk ygg ([whuqdofdsdflwru 9y .([whuqdouhvlvwru 9'287'/< 9'287
docid028553 rev 1 19/45 L5963 functional description 44 6.2.6 power ground (pgnd1 and pgnd2) pgnd1 pin and pgnd2 pin are power ground references for the dc/dc1 and dc/dc2 respectively. all switching nodes are referred to these two pins. 6.2.7 signal ground (sgnd) this pin is the ground reference for standby regulator, hsd and internal bias. 6.2.8 pwm signal ground (swgnd) this pin is the ground reference for signal part of dc/dc1 and dc/dc2. 6.2.9 tab tab is connected to the device substrate. this pin must be connected to gnd to guarantee the substrate is always at the lowest potential to avoid parasitic activation. 6.2.10 linear regulator figure 9. linear regulator diagram the linear regulator has two operative modes: standby mode and non-standby mode. its output voltage is set by an external resistor divider through the feedback pin fbldo. as a standby regulator, the current capability is reduced to 50 ma and the quiescent current minimized. in this case, the external resistor divider should be in the mega ohm order to reduce total quiescent current. as a non standby regulator, it has higher load capability (up to 250 ma). *$3*36 (1/'2 5() 5() (1 (1 (1b&rqwuro c (1 (1 &rpprq/'2 ($ 6wdqge\uhjxodwru ($ 5 5 ([whuqdouhvlvwru 9,1/'2 'ulyhu 9287/'2 9,1/'2 )%/'2 'ulyhu
functional description L5963 20/45 docid028553 rev 1 connecting enldo pin directly to its supply vinldo (it should be higher than 5 v), the regulator works as a standby regulator. once enldo is ever higher than 5 v, the regulator works as a standby regulator till vinldo is powered down, to reset a flag stored in an internal register. figure 10. enable timing for standby regulator (enldo pin connect to supply directly) the linear regulator works as a non-standby regulator if enldo is <5 v. '!0'03 %. t %. t 64( 64( %nable common,$/ 6).,$/%.,$/ t %nblepinthreshold 6threshold 64( 56,/threshold %nablestand by regulator 3hut down .ormalmode 3tandbymode .ormalmode 3tandbymode .ormalmode 3hutdown
docid028553 rev 1 21/45 L5963 functional description 44 figure 11. enable timing for linear regulator (pin enldo isn't connected to vinldo) the linear regulator operates with output voltages down to 1.2 v, and offers a maximum dropout voltage of 500 mv at rated load current. this regulator has an independent thermal protection and a current-limiting circuit. it should be always supplied (by vinldo) with a voltage not lower than 3.5 v because, even if not used, it gives the common supply to all internal blocks which have to stay alive when the battery drops too low (backup functionality). 6.2.11 high-side driver (hsd) the hsd pin is the output of the high side driver. it has a dedicated enable pin enhsd. following protections are implemented: ? over-current protection ? short to supply ? short to ground ? short through the load to -1 v ? unpowered short to supply ? loss of ground ? over voltage protection '!0'03 %.,$/ t %. t %. t 64( 64( %nablestandby regulator %nable common,$/ 6).,$/ t .ormalmode 3tandbymode 3hutdown 3hutdown
functional description L5963 22/45 docid028553 rev 1 thermal protection the hsd has an independent thermal shutdown protection. if the local die temperature exceeds the thermal shutdown detection threshold, the hsd is disabled. it is enabled once the local die temperature falls below the detection threshold with the specified hysteresis. the invoking of thermal shut down on hsd does not directly affect any other outputs or circuitry in the ic. short to ground the high side driver output is protected against shorts to ground. the faulted output returns to its pre-fault operating condition once the fault is removed. short to supply the high-side driver is protected against shorts to battery. in such an event, the ic is not damaged. external components connected directly to the ic are not damaged by such exposure. loss of ground protection the high side driver is protected against excessive leakage current to an external ground during a loss of supply ground (i.e. ground is open). during this event, the hsd is disabled and the ic is not damaged. loss of battery protection (unpowered shorts to battery, spu) the high-side driver is protected against unpowered shorts to battery. in such an event, in typical applicative conditions, the ic will not suffer any damage. below-ground protection the hsd output can be brought below ground by the inductive load. in this case, power pmos is turned on to charge the output, protecting itself.
docid028553 rev 1 23/45 L5963 functional description 44 6.2.12 switching regulators figure 12. switching regulators diagram L5963 embeds two synchronous dc/dc converters that incorporate all the control and necessary protection circuitries to satisfy a wide range of applications. dc/dc1 and dc/dc2 are enabled by pin ensw1 and pin ensw2 respectively. the two switching converters employ voltage mode control and feed forward function to provide good load regulation and line regulation. '!0'03 %22/2 !-0 62%& 07- #/-0 2 3 /#0!mp 6&"37 1 3oft 3tart 6# $river $river ? 1 $-$!mp "3 )2%& p p m : /3# 39.#). 39.# 07-#,+ &requency$ivider by &2$)6 07-#,+ ?phaseshift 6).37 3awtoothgenerator withfeedforward 07- &"37 #/-0 6).37 6"!4 2egulator 6607- %.37 %22/2 !-0 62%& 07- #/-0 2 3 /#0!mp 6&"37 1 3oft 3tart 6# $river $river ? 1 $-$!mp "3 )2%& m : 07-#,+ 6).37 3awtoothgenerator withfeedforward 07- &"37 #/-0 6).37 2egulator 6607- %.37 39.#/54 0'.$ 0'.$ 37'.$ 6607- 6607- 0rotect"locks 56,/ $ump34'/40 0rotect"locks 56,/ $ump34'/40 39.#
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functional description L5963 24/45 docid028553 rev 1 both switching regulators can operate up to a 100% duty cycle. once every four switching periods, the pwm output is forced low for 100ns typ to refresh the bootstrap capacitor. their features include: ? wide input voltage range (from 3.5 v to 26 v) ? min output of 1 v ? 250 khz free-run frequency and synchronization range from 250 khz to 2 mhz. the voltage feed forward is implemented in all frequency range ? internal 85 m high-side and 105 m low-side switching mosfet ? up to 3 a load current capability ? power ok (sw1ok) output ? internal soft start function to minimize startup inrush current ? pulse-by-pulse current limiting (ocp) ? discontinuous mode detection (dmc) ? over temperature protection (otp) ? uvlo with stop threshold at 2.8 v (typ) ? load dump protection ? externally adjustable compensation ? stable with ceramic output capacitors oscillator/switching frequency the internal oscillator provides a constant frequency clock of 250 khz. the switching frequency of dc/dc1 and dc/dc2 are determined by the internal frequency clock and the external synchronization clock. when no clock is applied to the syncin pin or the synchronization clock is lower than 125 khz (half of the internal clock), the two switching regulators work both with the internal 250 khz clock. when the syncin pin has a synchronization clock larger than 125 khz, the external synchronization clock is adopted. there is a phase shift of 180 between pwm1 and pwm2, and the frequency of pwm2 can be the same, 1/2, 1/4, 1/8 of pwm1 one. the division factor is programmed by frdiv pin. the switching clock of dc/dc1 can be sent out by pin syncout to synchronize another device, in view of reducing em disturbance. internal high-side and low-side power mosfet / bootstrap structure the two synchronous switching regulators don't need the external schottky diode. each of them integrates a high-side and a low-side n-channel power mosfet, which allows a very low drop voltage under high load current operation (up to 3 a). the bootstrap structure is used to drive the high-side n-channel power mosfet. a bootstrap capacitor of about 47 nf is needed. internal soft start function (ss) to reduce the inrush current during startup, an internal soft start is implemented. the total soft start time is about 400 s and it doesn't change with operating frequency.
docid028553 rev 1 25/45 L5963 functional description 44 pulse-by-pulse current limiting (ocp) the current in the upper mosfet is monitored and if it exceeds the pulse-by-pulse over- current threshold (ilim) then the upper mosfet is turned off. normal pwm operation resumes on the next oscillator clock pulse. dc/dcs? embed leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the upper mosfet is turned on. the blanking time is about 100 ns, so the minimum switching on time should be bigger than 100 ns: equation 1 from the above equation, when the input and output voltage are already known, the switching frequency should be within the range of the above equation, otherwise the ocp function is not guaranteed. pulse-by-pulse current limiting is always active. the threshold of ocp is about 3.7 a. low-side over current protection (ls ocp) ls ocp protects dc/dcs by limiting inductor current, when either the load is too high at high frequency or when the output of the converter is shorted to ground. the current in the low-side mosfet is monitored and, if it exceeds the pulse-by-pulse overcurrent threshold (ilim), it prevents the turning on of the high-side mosfet in the successive switching period. in high frequency and high load conditions, the inductor current cannot decrease even if hs ocp is triggered due to the blanking time, which results in the inductor current getting higher and higher every switching period. if inductor current reaches ls ocp threshold, that is set to a level higher than hs ocp one, pwm switching is stopped, waiting for the inductor current to decrease to a lower value. pwm switching will recover as soon as ls ocp is released. if high load and high frequency conditions remain, for instance in case of a short circuit being present on the regulator output, another ls ocp will occur. upon removal of the short circuit pwm switching will immediately recover, bringing the regulator back to normal operation. discontinuous mode detection (dmd) in order to save quiescent current when switching regulators are working in light load condition, L5963 embeds a discontinuous mode detection (dmd) circuit: dmd prevents inductor current to continuously flow to ground during t off by turning off ls mosfet and leaving pwm in tristate. over temperature protection (otp) each dc/dc has its own otp, which detects the local temperature and shuts down the regulator when temperature reaches the specified threshold. dump protection if the voltage on vbat supply exceeds the over-voltage shut-down threshold, dc/dcs are disabled. once vbat returns to working conditions, the output recovers to the normal state. $ i ns i $ ns 6 6ns 37 37 /54 ). !? ?
functional description L5963 26/45 docid028553 rev 1 under voltage lock out (uvlo) the uvlo circuit generates the shutdown signal to turn off dc/dcs when vbat is lower than the specified threshold. they are turned back on once vbat goes above the detection threshold with the specified hysteresis.
docid028553 rev 1 27/45 L5963 application information 44 7 application information 7.1 output inductor (lo) the value of the output inductor (lo) is usually calculated to satisfy the peak-to-peak ripple current requirement. for the best compromise of cost, size and performance, it is suggested to keep the inductor current ripple between 20% and 40% of the maximum current. for example, if ? i l = i ripple = 0.3 x i out(max) . where, i out(max) is the maximum output current. then, the inductor value can be estimated by the following equation: equation 2 where, f sw is the switching frequency, v in(max) is the maximum input voltage. if v out = 3.3 v, v in(max) = 26 v, f sw = 250 khz, ? i l = 0.3 x 3 a = 0.9 a equation 3 the next higher available value should be used, so l = 15 h. the peak current flowing in inductor is i l(peak) = i out(max) + ? i l / 2. if the inductor value decreases, the peak current increases. the peak current has to be lower than the current limit of the device. an inductor having saturation current higher than the device current limit has to be chosen. , 6 i ) 6 6 /54 37 , /54 ). t u ? 1 ? ' max ,?( ?( t uu u ? 1 ?
application information L5963 28/45 docid028553 rev 1 7.2 output capacitors (cout) output capacitors are selected to support load transients and output ripple current, as well as to get loop stability. the amount of voltage ripple can be calculated by the output ripple current flowing in the inductor: equation 4 usually the first term is dominant. however, if a ceramic capacitor (which is recommended) is adopted, the first term on the above equation can be neglected as the esr value is very low. for example, in case v out = 3.3 v, v in = 14 v, f sw = 250 khz, ? i l = 0.3 x 3 a = 0.9 a, in order to have a ? v out = 5%* v out =0.165 v, a 4.7 f ceramic capacitor is needed. in case of not negligible esr (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its esr value. in the above example, if a 100 f with esr = 100 m electrolytic capacitor is chosen, the voltage drop on esr dominates and the voltage ripple is 90 mv. the output capacitor is also important to sustain the output voltage during a load transient. in general, minimizing the esr value and increasing the output capacitance results in a better transient response. the esr can be minimized by simply adding more capacitors in parallel, or by using higher quality capacitors. if ceramic capacitors are chosen, in presence of a fast load transient the output voltage will change by the amount. equation 5 where: i out(max) , i out(min) refer to the worst case load in the system and ? v out is the tolerance of the regulated output voltage, 5% of v out . for example, v out = 5 v, v in = 14 v, i out(max) =1.5 a, i out(min) = 0.5 a, l = 22 h equation 6 so two 10 f ceramic capacitors in parallel are needed. the output capacitor is also important for loop stability: it fixes the double lc filter pole and the zero due to its esr. in section 7.5: compensation network , it will be illustrated how to consider its effect in the system stability. '' ' 6%32) ) # f out , , out sw u uu ' 6 )) out out max out min out u u , #6 out # out , 6 out ?& u u ) outmax ) outmin 6 out '
docid028553 rev 1 29/45 L5963 application information 44 7.3 input capacitors (c in ) the input capacitors must be chosen to support the maximum input operating voltage and the maximum rms input current required by the device. the input capacitors must deliver the rms current according to below equation: equation 7 where io is the maximum dc output current and d is the duty cycle. this function has a maximum at d = 0.5 and it is equal to i o /2. equation 8 v dl is the voltage drop across the low side dmos, and v dh is the voltage drop across the high side dmos. for example, with 20% duty cycle, the input/output current multiplier is 0.400. therefore, if the regulator is delivering 3 a of steady-state load current, the input capacitor(s) must support 0.400 3 a or 1.2 arms. ceramic capacitors can deliver quite a bit of current but their total capacitance is relatively low. electrolytic capacitors typically offer much more capacitance than ceramic capacitors, but can typically deliver a current of 100 to 500 marms. so a good design will employ both types of capacitors with the ceramic capacitors placed closest to the input pins of the device. as a result, ceramic capacitors which have very low esr and inductance are the best for filtering the high frequency switching noise, and electrolytic capacitors are typically able to provide more current over extended periods of time where vin would otherwise droop. 7.4 bootstrap capacitor (cboot) a bootstrap capacitor must be connected between the boot and sw pins to provide floating gate drive to the high-side mosfet. for most applications 47 nf is sufficient. this should be a ceramic capacitor with a voltage rating of at least 6 v. 7.5 compensation network the compensation network has to assure stability and good dynamic performance. the loop of the device is based on the voltage mode control, compatible with type iii compensation network ( figure 13 ). the error amplifier is a voltage operational amplifier with large bandwidth, which is much larger than the closed-loop one. ) rms ) o $$ u $ 6 dh 6 out 6 dl 6 in 6 dl
application information L5963 30/45 docid028553 rev 1 figure 13. closed loop system with type iii network the above figure shows the closed loop system with a type iii compensation network and presents the closed loop transfer function. see the guidelines for calculation of type iii network below: 1. choose a value for r 1 , usually between 2 k and 5 k . 2. choose a gain (r 2 /r 1 ) that shifts the open loop gain up to give the desired bandwidth. this allows the 0 db crossover to occur in the frequency range where the type iii network has its second plateau in the gain. the following equation calculates an r 2 that accomplishes this, given the system parameters and a chosen r 1 . equation 9 3. c2 is calculated by placing the zero at 50% of the output filter double pole frequency: equation 10 4. c1 can be calculated by placing the first pole at the esr zero frequency: equation 11 5. set the second pole at half the switching frequency and also set the second zero at the output filter double pole. this combination brings the following equation: 0(!3% $2)6%2 $2)6%2 2%&%2%.#% 2%&%2%.#% 07- #/-0!2!4/2 /3# ' 6 /3# $#2 %32 , o # o v out 6 in # # # # 6 #/-0 6 #/-0 # # 2 2 2 2 2 2 2 '!0'03 uu '!). 22 22# s 2# s 22 # 3934%- u uu u ? 1 ? u u ? 1 ? ? u uu ? 1 ? u u ? 1 ? u u ss ## 2## s 2# 6 6 s%32 in /3# ' # s %32 $#2 # s , # /54 /54 /54 /54 u u u u 2 $7 " & 6 6 2 ,# osc ). uu ' # 2& ,# uu s # # 2#& %32 uu u u s
docid028553 rev 1 31/45 L5963 application information 44 equation 12 the figure below shows the asymptotic bode gain plot for the type iii compensated system and the gain and phase equations for the compensated system figure 14. type iii compensated network diagram here an example of calculating the external components network step by step. suppose the requirements for a dc-dc regulator are the following: input voltage minimum v in(min) 8 v input voltage maximum v in(max) 26 v input voltage typical v in(typ) 14 v output voltage buck regulator 1- vbuck 1 min = 4.75 v, max = 5.25 v converter switching frequency, fsw 250 khz maximum output current on buck regulator 1-vbuck 1 3 a maximum ripple current i ripple 0.3* i out load transition requirement 500 ma < 1.5 a in ? t = tbd assume type iii compensation network. step 1 - calculate the inductor value using equation 13 , to find the inductor value, assume inductor ripple current of 0.9 a. equation 13 2 2 & & 37 ,# u # 2& 37 uu s '!0'03 %22/2!-0 $#'!). #/.6%24%2'!). /0%.,//0 %22/2!-0'!). #/-0%.3!4)/. '!). & ,# & ,# & : & 37 & 0 & ,# & : & %32 & 0 & %32 '!). $" &2%15%.#9 -/$5,!4/2 &),4%2'!). "!.$7)$4( d"$%# '!)."!.$7)$4( 02/$5#4 , 6 &) 6 6 out 37 , out in t u ? 1 ? uu ? 1 ? ' max ?( | ?(
application information L5963 32/45 docid028553 rev 1 the next higher available value should be used, so l = 22 h. step 2 -inductor peak current using equation 14 , the peak inductor current is: equation 14 step 3 - calculate the output capacitance using equation 15 , the output capacitance is: equation 15 so choose two 10 f ceramic capacitors in parallel, and the voltage ripple is within the spec. equation 16 (esr can be neglect due to ceramic cap) i l(peak) = i out(max) + ? i l /2 = 3 a + (0.9/2) a= 3.45 a # out , 6 out x u u u ) outmax ) outmin 6 out ' xx ?& ' ' 6 %32 u' ) out , uu ) # f xx xx m6 , out sw
docid028553 rev 1 33/45 L5963 application information 44 step 4 -calculate loop compensation values. using equation 17 to determine the "double pole": equation 17 using equation 18 to determine the zero due to the esr of the output capacitor c out with esr = 10 m ? : equation 18 dbw = f c = 0.14 x f sw = 35khz choose r1 = 5 k ? , using equation 19 : equation 19 r4 =1.24 k pwm modulator gain. equation 20 where v in is the typical input operating voltage, ? v osc is the saw-tooth peak-to-peak value. using equation 21 : equation 21 r2 = 2.4 k using equation 22 : equation 22 choose c2 = 16 nf using equation 23 : equation 23 f ,# ,# out u? uuuuu k(z s f # %32 k(z %32 out uu uuuuu s 2 2 6 6 k k out 2%& : 'ain 6 6 ulator ). /3# mod ' 2 $"7 f 6 6 2 k k ,# /3# ). k k uu u u ' # 2f & ,# uuu u u s # 2#f %32 u uuuuuuu s u &
application information L5963 34/45 docid028553 rev 1 choose c1= 82 nf. using equation 24 : equation 24 choose r3 = 330 . using equation 25 : equation 25 choose c3 = 3.9 nf. this is a table to summarize components value for different output voltage cases: 2 2 f f k 37 ,# u uu : # 2 & 37 f uuu u s table 7. components value for different output voltage cases v out (v) fsw (hz) lo ( h) co ( f) r1 (k ) r2 (k ) r3 ( ) r4 (k ) c1 (pf) c2 (nf) c3 (nf) 5 2m 2.7 4.7 4.99 1.2 220 1.24 33 5.6 0.68 250k 22 2x10 4.99 2.4 390 1.24 82 16 3.9 3.3 2m 2.2 10 4.99 1.5 180 2.15 56 6.2 0.82 250k 15 2x10 4.99 2 470 2.15 100 16 3.3 1.2 2m 1.5 2x10 4.99 1.8 160 24.9 100 5.6 1 250k 6.8 2x10 4.99 1.2 680 24.9 150 16 2.2
docid028553 rev 1 35/45 L5963 thermal design 44 8 thermal design the system design and maximum power that can be managed should take into account the ic thermal resistance junction to ambient which depends on the pcb design. the temperature inside the ic (junction temperature) should not exceed 150 c or one or more of the thermal shut-down protections will intervene. the total power dissipation is approximately given by the sum of the power dissipation of the two dc-dc regulators and the linear regulators: pd = pdpwm1 + pdpwm2 + pdldo where: pd issdc/dc = iload dc/dc x vout dc/dc x (1- ? )/ ? ; ? is the efficiency, as shown in figure 6 and 7 . p dissldo = iload ldo x (vinldo-voutldo) the junction temperature is estimated in this way: t j = t a + pd x r thj-a where: t a is the maximum ambient temperature; r thj-amb is the junction to ambient thermal resistance, as defined in table 4: thermal data (slug-down configuration) . L5963 comes in two different package options, slug-up and slug-down, to meet power management requirements and give flexibility in different board configurations (see section 9: package information ). the slug has to be connected to the ground plane, whenever possible. according to below formula and considering tsd_th thermal shutdown minimum threshold at 150 c, maximum suggested power dissipation, for a slug-down configuration, can be easily retrieved: p diss_suggested = (t shd - t amb ) / r thj-a table 8. maximum suggested power symbol t amb 105 c t amb 80 c r th j-a-2s 0.85 w 1.32 w r th j-a-2s2p 1.66 w 2.6 w r th j-a-2s2pvias 2.05 w 3.2 w
thermal design L5963 36/45 docid028553 rev 1 it is possible to improve performance and application thermal behavior, adopting some expedients: ? use the bottom layer as heat-sink ? inner layer tracks are sunk to the ground plane ? use large paths for ground connections, instead of narrow and long paths with sharp corners, and transfer all ground connections to other layers by a proper number of vias ? place compensation network very close to the chip to reduce noise ? put coils and capacitors close to the pins, and build output path with large and short tracks with the layout configuration shown in figure 15 , a r th of 13c/w has been reached. figure 15. layout configuration example
docid028553 rev 1 37/45 L5963 package information 44 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 9.1 package variation this device use package variations option b to define exposed pad (see table 9 ) or slug-up (see table 10 ) dimensions.
package information L5963 38/45 docid028553 rev 1 9.2 powersso-36 (exposed pad) package information figure 16. powersso-36 (exposed pad) package outline table 9. powersso-36 exposed pad package mechanical data ref dimensions millimeters inches (1) min. typ. max. min. typ. max. ? 0 - 8 0 - 8 ? 1 5 - 10 5 - 10 ? 20- -0- - a 2.15 - 2.45 0.0846 - 0.0965 b,b(+ e f f e %$6(0(7$/ :,7+3/$7,1* + ( ' jjj & $% ' jjj & $% ' *$8*(3/$1( / 6 / / % % k k ( ' $ $ $ h e ggg & ' & fff & 6($7,1*3/$1( hhh & ' iii & $% [ $ ( ' eee & [17,36 ( $ $ 1 1 % ddd & ' [ ( ' lqgh[duhd '[( slqlqglfdwru 5 5 *[ * * * * %rwwrpylhz 7rsylhz *$3*36 6hfwlrq$$ 6hfwlrq%% vhh6hfwlrq$$ vhh6hfwlrq%% 0 0 0
docid028553 rev 1 39/45 L5963 package information 44 a1 0.0 - 0.1 0.0 - 0.0039 a2 2.15 - 2.35 0.0846 - 0.0925 b 0.18 - 0.32 0.0071 - 0.0126 b1 0.13 0.25 0.3 0.0051 0.0098 0.0118 c 0.23 - 0.32 0.0091 - 0.0126 c1 0.2 0.2 0.3 0.0079 0.0079 0.0118 d (2) 10.30 bsc 0.4055 bsc d1 variation d2 - 3.65 - - 0.1437 - d3 - 4.3 - - 0.1693 - e 0.50 bsc 0.0197 bsc e 10.30 bsc 0.4055 bsc e1 (2) 7.50 bsc 0.2953 bsc e2 variation e3 - 2.3 - - 0.0906 - e4 - 2.9 - - 0.1142 - g1 - 1.2 - - 0.0472 - g2 - 1 - - 0.0394 - g3 - 0.8 - - 0.0315 - h 0.3 - 0.4 0.0118 - 0.0157 l 0.55 0.7 0.85 0.0217 - 0.0335 l1 1.40 ref 0.0551 ref l2 0.25 bsc 0.0098 bsc n 36 1.4173 r 0.3 - - 0.0118 - - r1 0.2 - - 0.0079 - - s 0.25 - - 0.0098 - - table 9. powersso-36 exposed pad package mechanical data (continued) ref dimensions millimeters inches (1) min. typ. max. min. typ. max.
package information L5963 40/45 docid028553 rev 1 tolerance of form and position aaa 0.2 0.0079 bbb 0.2 0.0079 ccc 0.1 0.0039 ddd 0.2 0.0079 eee 0.1 0.0039 ffff 0.2 0.0079 ggg 0.15 0.0059 variations option a d1 6.5 - 7.1 0.2559 - 0.2795 e2 4.1 - 4.7 0.1614 - 0.1850 option b d1 4.9 - 5.5 0.1929 - 0.2165 e2 4.1 - 4.7 0.1614 - 0.1850 option c d1 6.9 - 7.5 0.2717 - 0.2953 e2 4.3 - 5.2 0.1693 - 0.2047 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. dimensions d and e1 do not include mold flash or protrusions. allowable mold flash or protrusions is ?0.25 mm? per side d and ?0.15 mm? per side e1. d and e1 are maximum plastic body size dimensions including mold mismatch. table 9. powersso-36 exposed pad package mechanical data (continued) ref dimensions millimeters inches (1) min. typ. max. min. typ. max.
docid028553 rev 1 41/45 L5963 package information 44 9.3 powersso-36 (slug-up) package information figure 17. powersso-36 (slug-up) package outline table 10. powersso-36 slug-up package mechanical data ref dimensions millimeters inches (1) min. typ. max. min. typ. max. a 2.15 - 2.45 0.0846 - 0.0965 a2 2.15 - 2.35 0.0846 - 0.0925 a1 0 - 0.10 - 0.0039 b 0.18 - 0.36 0.0071 - 0.0142 c 0.23 - 0.32 0.0091 - 0.0126 d (2) 10.10 - 10.50 0.3976 - 0.4134 e (2) 7.4 - 7.6 0.2913 - 0.2992 e - 0.5 - - 0.0197 - e3 - 8.5 - - 0.3346 - b(b.% $ $ & & $ % % $ 0 & /($'&203/$1$5,7< 7239,(: < 0 / n 1 1 dvwdqgrii *dxjhsodqh '%rg\ohqjwk (%rg\zlgwk h 7 ) h e + 6 ; 8 8 2 * *$3*36
package information L5963 42/45 docid028553 rev 1 f - 2.3 - - 0.0906 - g - - 0.10 - - 0.0039 h 10.10 - 10.50 0.3976 - 0.4134 h - - 0.40 - - 0.0157 k 0 - 8 0 - 8 l 0.55 - 0.85 0.0217 - 0.0335 m - 4.3 - - 0.1693 - n - - 10 - - 10 o - 1.2 - - 0.0472 - q - 0.8 - - 0.0315 - s - 2.9 - - 0.1142 - t - 3.65 - - 0.1437 - u - 1.0 - - 0.0394 - x see variations y see variations variations option a x 4.1 - 4.7 0.1614 - 0.1850 y 6.5 - 7.1 0.2559 - 0.2795 option b x 4.1 - 4.7 0.1614 - 0.1850 y 4.9 - 5.5 0.1929 - 0.2165 option c x 4.3 - 5.2 0.1693 - 0.2047 y 6.9 - 7.5 0.2717 - 0.2953 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. "d? and ?e" do not include mold flash or protrusions mold flash or protrusions shall not exceed 0.15 mm per side (0.006?) table 10. powersso-36 slug-up package mechanical data (continued) ref dimensions millimeters inches (1) min. typ. max. min. typ. max.
docid028553 rev 1 43/45 L5963 package information 44 9.4 package marking information figure 18. powersso-36 (exp. pad) marking information figure 19. powersso-36 (slug up) marking information note: engineering samples: these samples are clearly identified by last two digits ?es? in the marking of each unit. these samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by st. st is not liable for any customer usage in production and/or in reliability qualification trials. commercial samples: fully qualified parts from st standard production with no usage restrictions. 3rzhu6627239,(: qrwlqvfdoh /dvwwzrgljlwv (6(qjlqhhulqjvdpsoh eodqn!&rpphufldovdpsoh 0dunlqjduhd *$3*36b(6 3rzhu6627239,(: qrwlqvfdoh 0dunlqjduhd /dvwwzrgljlwv (6(qjlqhhulqjvdpsoh eodqn!&rpphufldovdpsoh *$3*36b(6
revision history L5963 44/45 docid028553 rev 1 10 revision history . table 11. document revision history date revision changes 29-oct-2015 1 initial release.
docid028553 rev 1 45/45 L5963 45 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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