1 standard products ut54acs193/UT54ACTS193 synchronous 4-bit up-dow n dual clock counters datasheet november 2010 www.aeroflex.com/logic features ? look-ahead circuitry enhances cascaded counters ? fully synchronous in count modes ? parallel asynchronous load for modulo-n count lengths ? asynchronous clear ? 1.2 cmos (acts193) and .6 m crh cmos process (acs193) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 16-pin dip - 16-lead flatpack ? ut54acs193 - smd 5962-96566 ? UT54ACTS193 - smd 5962-96567 description the ut54acs193 and the UT54ACTS193 are synchronous 4- bit, binary reversible up-down binary counters. synchronous operation is provided by having all flip-flops clocked simultaneously so that the output s change coinci dent with each other when instructed. synchr onous operation eliminates the output counting spikes normally associated with asynchronous counters. the outputs of the four flip-flops are triggered on a low-to-high- level transition of either count input (up or down). the direc- tion of the counting is determined by which count input is pulsed while the other count input is high. the counters are fully programmable. the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. the output will change to agree with the data inputs independently of the count pulses. asynchronous loading allows the counters to be used as modulo- n dividers by simply modifying the count length with the preset inputs. a clear input has been provided th at forces all outputs to the low level when a high level is applied. the clear function is inde- pendent of the count and the load inputs. the counter is designed for efficient cascading without the need for external circuitry. the borrow output (bo ) produces a low- level pulse while the count is zero and the down input is low. similarly, the carry output (co ) produces a low-level pulse while the count is maximum pinouts 16-pin dip top view 16-lead flatpack top view function table function clock up clock down clr load count up h l h count down h l h reset x x h x load preset input x x l l 1 2 3 4 5 7 6 16 15 14 13 12 10 11 b q b q a down up q c q d v dd a clr bo co c 8 9 v ss d load 1 2 3 4 5 7 6 16 15 14 13 12 10 11 v dd 89 b q b q a down up q c q d a clr bo co load c v ss d
2 logic symbol logic diagram (14) clr (5) up g1 ct=0 ctrdiv 16 (4) down (15) a (1) b (10) c (9) d (12) (3) q a (7) q d (6) q c (2) q b 3d (1) (2) (4) (8) 2+ g2 (11) load c3 (13) bo 2 ct=0 1- co 1ct=15 note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publi- cation 617-12. a down up clr load (15) (4) (5) (1) (10) (9) (14) (11) q (7) (6) (2) (3) (12) (13) b c d bo co d c b a q q q c q r s q c q r s q c q r s q c q r s q
3 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 2.1 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buff er) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acts specifications are valid for radiation dose 1e6 rads(si) and all acs specifications are valid for radiation dose 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
6 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. notes: 1. maximum allowable relative shift equals 50mv. 2. all acts specifications are valid for radiation dose 1e6 rads(si) and all acs specifica tions are valid fo r radiation dose 5e5 rads(si). 3. based on characterization, data hold time (t h3 ) of 0ns can be assumed if data setup time (t su3 ) is > 10ns. this is guaranteed, but not tested. symbol parameter minimum maximum unit t plh up to q n 2 20 ns t phl up to q n 2 24 ns t plh up to co 2 13 ns t phl up to co 2 16 ns t plh down to bo 2 13 ns t phl down to bo 2 16 ns t plh down to q n 2 20 ns t phl down to q n 2 24 ns t plh load to q n 2 22 ns t phl load to q n 2 23 ns t phl clr to q n 2 22 ns f max maximum clock frequency 56 mhz t su1 load inactive setup time before up or down 3 ns t su2 clr inactive setup time before up or down 3 ns t su3 a, b, c, d setup time before load 6 ns t h1 up high hold time after down 20 ns t h2 down high hold time after up 20 ns t h3 3 a, b, c, d hold time after load 2 ns t w minimum pulse width up high or low down high or low load low clr high 9 ns
7 packaging side-brazed packages
8 flatpack packages
9 ut54acs193/UT54ACTS193: smd 5962 ***** ** * * * * lead finish: (notes 1 & 2) a = solder c = gold x = optional package type: x = 16-lead ceramic botto m-brazed dual-in-line flatpack c = 16-lead ceramic side-brazed dip class designator: q = qml class q v = qml class v device type: 01 drawing number : 96566 = ut54acs193 96567 = UT54ACTS193 total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, pa rt marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2 . device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-883 test method 1019 condition a.
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