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? 2015 exar corporation XR22802 hi-speed usb to 10/100 ethernet bridge exar.com/XR22802 rev 1b 1 / 46 general description the XR22802 is a hi-speed usb 2.0 compound device with an embed- ded hub and 5 downstream usb functions: 10/100 ethernet mac and phy, 2 uarts, multi-master capable i 2 c controller, and an enhanced dedicated gpio entity (edge) controller. the upstream usb interface has an integrated usb 2.0 phy and device controller that is compliant with both hi-speed (480mbps) and full-speed (12mbps) usb 2.0. the vendor id, product id, power mode, remote wakeup support and maximum power consumption are amongst the val- ues that can be programmed using the on-chip one-time programmable (otp) memory. the 10/100 ethernet mac and phy is compliant with ieee 802.3 and supports auto-negotiation, auto-mdix, checksum offload, auto-polarity correction in 10base-t and remote wakeup capabilities. the enhanced uart has a maximum data rate of 15 mbps. using a frac- tional baud rate generator, any baud rate between 300 bps and 15 mbps can be accurately generated. in addition, the uart has a large 1024-byte tx fifo and rx fifo to optimize the overall data throughput for various applications. the automatic rs485 control feature simplifies both the hardware and software for half-duplex rs-485 applications. if required, the multidrop (9-bit) mode feature furt her simplifies typical multidrop appli- cations by enabling / disabling the uart receiver depending on the address byte received. the multi-master capable i 2 c controller and edge controller (up to 32 gpios) can be accessed via the usb hid interface. the edge pins or i 2 c interface can be used for controlling and monitoring other peripherals. up to 2 edge pins can be configured as a pwm generator. features ? usb 2.0 compliant interface ? 10/100 ethernet mac and phy ? enhanced uart ? i 2 c multi-master ? enhanced dedicated gpio entity (edge) ? single +5.0v power supply input ? regulated +3.3v output power ? single 25mhz crystal ? 15kv hbm esd protection on usb data pins ? 8kv hbm esd protection on all other pins ? usb cdc-acm, cdc-ecm and hid compliant ? custom software drivers applications ? usb to ethernet dongles ? pos terminals ? test instrumentation ? networking ? factory automation and process controls ? industrial applications ordering information C back page block diagram upstream usb phy usb 2.0 hub 10/100 ethernet mac ethernet phy i 2 c multimaster otp memory edge controller usb ethernet i 2 c uart ch. a, b / edge 25 mhz xo uart ch a / modem io
? 2015 exar corporation XR22802 2 / 46 exar.com/XR22802 rev 1b extended features ? usb 2.0 compliant interface ? integrated usb 2.0 phy ? supports 480 mbps usb hi-speed and 12 mbps usb full-speed data rate ? supports usb suspend, resume and remote wakeup operations ? compatible with usb cdc-ecm and cdc-acm ? 10/100 ethernet mac and phy ? compliant with ieee 802.3 ? integrated 10/100 ethernet mac and phy ? 10base-t and 100base-tx support ? full-duplex and half-duplex support ? full-duplex and half-duplex flow control ? preamble generation and removal ? automatic 32-bit crc generation and checking ? automatic payload padding and pad removal ? diagnostic loop-back modes ? tcp/udp/ip/icmp checksum offload support ? flexible address filtering modes ? wakeup packet support ? support for 2 status leds ? enhanced uart features ? data rates up to 15 mbps ? fractional baud rate generator ? 1024 byte tx and rx fifos ? 7, 8 or 9 data bits, 1 or 2 stop bits ? automatic hardware flow control ? automatic software flow control ? multidrop (9-bit) mode ? auto rs-485 half-duplex control ? i 2 c multi-master ? up to 400 kbps transfers ? multi-master capable ? enhanced dedicated gpio entity (edge) ? parallel gpio access ? two pwm generators ? custom software drivers ? windows 2000, xp, vista, win 7 and win 8 ? windows ce 5.0, 6.0, 7.0 ? linux ? os x
? 2015 exar corporation XR22802 3 / 46 exar.com/XR22802 rev 1b absolute maximum ratings stresses beyond the limits listed below may cause perma- nent damage to the device. exposure to any absolute max- imum rating condition for extended periods may affect device reliability and lifetime. v cc supply voltage........ .............. .............. ........... ........... ...+5.75v input voltage (all pins except scl, sda, usbd+, usbdC)..............-0.3 to +4.0v input voltage (usbd+ and usbdC).......................-0.3v to +5.75v input voltage (scl and sda)......... ............... ........... -0.3v to +6.0v junction temperature............................................................125c operating conditions operating temperature range................................-40c to +85c v cc supply voltage...............................................+4.4v to +5.25v electrical characteristics unless otherwise noted: t a = -40c to +85c, v cc = 4.4v to 5.25v symbol parameter conditions min typ max units power consumption i cc operating current no load on gpio pins or 3v3_out 185 250 ma i susp suspend mode current no load on gpio pins or 3v3_out 3 4.5 ma uart, vbus_sense, low_pwr# and edge pins v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 3.6 v v ol output low voltage i ol = 4ma 0.3 v v oh output high voltage i ol = -4ma 2.2 v i il input low leakage current 10 a i ih input high leakage current 10 a c in input pin capacitance 5pf usb i/o pins v ol output low voltage full-speed usb. external 15k to gnd on usbd+ and usbd- pins 00.3v v oh output high voltage full-speed usb. external 15k to gnd on usbd+ and usbd- pins 2.8 3.6 v v ol output low voltage hi-speed usb. external 45 to gnd on usbd+ and usbd- pins -300 300 mv v oh output high voltage hi-speed usb. external 45 to gnd on usbd+ and usbd- pins 360 440 mv v drvz driver output impedance 45 i osc output short circuit current 1.5v on usbd+ and usbd- pins 52 ma
? 2015 exar corporation XR22802 4 / 46 exar.com/XR22802 rev 1b ethernet i/o pins - 100base-tx transmit mode v pph peak differential output voltage high measured at line side of transformer, line replaced by differential resistance of 100 ohms. 950 1050 mv v ppl peak differential output voltage low -950 -1050 mv v sas signal amplitude symmetry 98 102 % t rf signal rise and fall time 3 5 ns d cd duty cycle distortion 00.5ns v os overshoot and undershoot 0 5 % - transmit jitter measured differentially 0 1.4 ns ethernet i/o pins - 10base-t transmit mode v pph peak differential output voltage high m easured at line side of transformer, line replaced by differential resistance of 100 ohms. 2.2 2.8 v 3.3v regulated power output v out output voltage max load current 50 ma 3.0 3.3 3.6 v symbol parameter conditions min typ max units
? 2015 exar corporation XR22802 5 / 46 exar.com/XR22802 rev 1b pin configuration to p v i ew pin assignments pin no. pin name type description 1 e30 i/o enhanced general purpose io 2 e31 i/o enhanced general purpose io 3 vbus_sense i vbus sense input. in self-powered mode, the vbus from the usb connector needs to be connected to this pin through a voltage divide r circuit (vbus = 5v, vbus_sense = 3.3v input) using large resistance va lues to minimize power. it should also be decoupled by a 0.1uf capacitor. this feature may be enabled via the otp whenever the hub function is con- figured for self-powered mode. the vbus_sense input is used to disable the pull-up resis- tor on the usbd+ signal when vbus is not present. in bus-powered mode, this pin is ignored. 4 rext i connect externally using short trace to 226 ohm 1% resistor to ground 5 e29 i/o enhanced general purpose io 6 e28 i/o enhanced general purpose io 7 cap1 i connect externally to cap2 and 3v3_out using short trace 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 14 13 12 11 10 9 8 7 6 5 4 3 2 1 29 30 31 32 33 34 35 36 37 38 39 40 41 42 exar xr22b802/4 e30 e31 vbus_sense rext e29 e28 cap1 gnd usbd- usbd+ vcc e26 eth_spd e27 e7/txa e6/rxa/rwka# gnd e9/cdb#/gb1 e8/rib#/rwkb#/gb0 e18 gnd cap2 e19 eth_link e16 e17 e1/cda#/ga1 e0/ria#/rwka#/ga0 e_pad exar XR22802 sda scl e3/dtra#/ga3 e2/dsra#/ga2 e11/dtrb#/gb3 e10/dsrb#/gb2 gnd low_pwr# e12/ctsb#/gb4 e13/rtsb#/rs485b/gb5 e15/txb e14/rxb/rwkb# e4/ctsa#/ga4 e5/rtsa#/rs485a/ga5 xtalout xtalin e24 e25 3v3_out gnd eth_tx- eth_tx+ eth_rx+ eth_rx- e22 e23 e21 e20 e_pad
? 2015 exar corporation XR22802 6 / 46 exar.com/XR22802 rev 1b 8 gnd pwr power supply common, ground 9 usbdC i/o usb port differential data negative 10 usbd+ i/o usb port differential data positive 11 vcc pwr 5.0v power supply input 12 e26 i/o enhanced general purpose io 13 eth_spd o ethernet 100 mbps speed indicator. asserted high for 100 mbps. 14 e27 i/o enhanced general purpose io 15 xtalout o crystal or buffered clock output 16 xtalin i 25 mhz +/- 50 ppm crystal or external clock input 17 e24 i/o enhanced general purpose io 18 e25 i/o enhanced general purpose io 19 3v3_out pwr 3.3 v output power. connect externally to cap1 and cap2 using short trace and decouple with minimum of 4.7uf capacitor 20 gnd pwr power supply common, ground 21 eth_txC o ethernet transmit data out negative 22 eth_tx+ o ethernet transmit data out positive 23 eth_rx+ i ethernet receive data in positive 24 eth_rxC i ethernet receive data in negative 25 e22 i/o enhanced general purpose io 26 e23 i/o enhanced general purpose io 27 e21 i/o enhanced general purpose io 28 e20 i/o enhanced general purpose io 29 e0/ria#/rwka#/ga0 i/o enhanced general purpose io, or uart channel a ring indicator, or remote wakeup, or gen- eral purpose io. defaults to uart gpio input. refer to remote wakeup section on page 10 . 30 e1/cda#/ga1 i/o enhanced general purpose io, or uart channel a carrier detect, or general purpose io. defaults to uart gpio input. 31 e17 i/o enhanced general purpose io, or uart c hannel c carrier detect, or general purpose io. defaults to uart gpio input. 32 e16 i/o enhanced general purpose io 33 eth_link o ethernet 10/100 activity indicator. toggles with activity 34 e19 i/o enhanced general purpose io 35 cap2 i connect externally to cap1 and 3v3_out using short trace 36 gnd pwr power supply common, ground 37 e18 i/o enhanced general purpose io 38 e8/rib#/rwkb#/gb0 i/o enhanced general purpose io, or uart channel b ring indicator, or remote wakeup, or gen- eral purpose io. defaults to uart gpio input. refer to remote wakeup section on page 10 . 39 e9/cdb#/gb1 i/o enhanced general purpose io, or uart channel b carrier detect, or general purpose io. defaults to uart gpio input. pin no. pin name type description
? 2015 exar corporation XR22802 7 / 46 exar.com/XR22802 rev 1b type: i = input, o = output, i/o = input/output, pwr = power, od = open-drain 40 gnd pwr power supply common, ground 41 e6/rxa/rwka# i/o enhanced general purpose io, or uart c hannel a rx data, or remote wakeup. defaults to uart rx data. 42 e7/txa i/o enhanced general purpose io, or uart c hannel a tx data. defaults to uart tx data. 43 e5/rtsa#/rs485a/ga5 i/o enhanced general purpose io, or uart channel a request to send, or auto-rs485 half- duplex enable, or general purpose io. defaults to uart gpio input except when XR22802 is used with cdc-acm driver. refer to automatic rts/cts hardware flow control section on page 14 or auto rs-485 half-duplex control on page 15 . 44 e4/ctsa#/ga4 i/o enhanced general purpose io, or uart channel a clear to send, or general purpose io. defaults to uart gpio input except when XR22802 is used with cdc-acm driver. refer to automatic rts/cts hardware flow control section on page 14 . 45 e14/rxb/rwkb# i/o enhanced general purpose io, or uart channel b rx data, or remote wakeup. defaults to uart rx data. 46 e15/txb i/o enhanced general purpose io, or uart channel b tx data. defaults to uart tx data. 47 e13/rtsb#/rs485b/gb5 i/o enhanced general purpose io, or uart channel b request to send, or channel b auto- rs485 half-duplex enable, or general purpose io. de faults to uart gpio input except when XR22802 is used with cdc-acm driver. refer to automatic rts/cts hardware flow control section on page 14 or auto rs-485 half-duplex control on page 15 . 48 e12/ctsb#/gb4 i/o enhanced general purpose io, or uart channel b clear to send, or general purpose io. defaults to uart gpio input except when XR22802 is used with cdc-acm driver. refer to automatic rts/cts hardware flow control section on page 14 . 49 low_pwr# o the low_pwr# pin will be asserted whenever it is not safe to draw the amount of current requested from vbus in the device maximum power field of the configuration descriptor. the low_pwr# pin is asserted when the XR22802 is in suspend mode or when it is not yet configured. the low_pwr# pin will be de-asserted whenever it is safe to draw the amount of current requested in the device maximum powe r field. note that the XR22802 device is a high power device. the default polarity of the low_pwr# output pin is active low and is pro- grammable via the otp. 50 gnd pwr power supply common, ground 51 e10/dsrb#/gb2 i/o enhanced general purpose io, or uart channel b data set ready, or general purpose io. defaults to uart gpio input. refer to automatic dtr/dsr hardware flow control section on page 14 . 52 e11/dtrb#/gb3 i/o enhanced general purpose io, or uart channel b data terminal ready, or general purpose io. defaults to uart gpio input. refer to automatic dtr/dsr hardware flow control sec- tion on page 14 53 e2/dsra#/ga2 i/o enhanced general purpose io, or uart channel a data set ready, or general purpose io. defaults to uart gpio input. refer to automatic dtr/dsr hardware flow control section on page 14 . 54 e3/dtra#/ga3 i/o enhanced general purpose io, or uart channel a data terminal ready, or general purpose io. defaults to uart gpio input. refer to automatic dtr/dsr hardware flow control sec- tion on page 14 . 55 scl i/o od i 2 c master controller serial cloc k (open-drain) external pull-up resistor required on this pin. 56 sda i/o od i 2 c master controller data (open- drain). external pull-up re sistor required on this pin. pin no. pin name type description
? 2015 exar corporation XR22802 8 / 46 exar.com/XR22802 rev 1b functional block diagram usb 2.0 phy usbd+ usbd- 5.0v vcc 5.0v vcc gnd gnd otp 10/100 ethernet mac usb 2.0 hub 10/100 ethernet phy uart channel a uart channel b eth_tx+ eth_tx- eth_rx+ eth_rx- 25 mhz xtal xtalin xtalout i2c master sda scl edge controller pin mux eth_link eth_spd e7/txa e6/rxa/rwka# e5/rtsa#/rs485a/ga5 e4/ctsa#/ga4 e3/dtra#/ga3 e2/dsra#/ga2 e1/cda#/ga1 e0/ria#/rwka#/ga0 e15/txb e14/rxb/rwkb# e13/rtsb#/rs485b/gb5 e12/ctsb#/gb4 e11/dtrb#/gb3 e10/dsrb#/gb2 e9/cdb#/gb1 e8/rib#/rwkb#/gb0 vbus_sense low_pwr# usb descriptors e[31:16]
? 2015 exar corporation XR22802 9 / 46 exar.com/XR22802 rev 1b functional description usb interface the XR22802 is a usb compound device with an embedded hub and 5 downstream functions. the downstream functions of the XR22802 are 10/100 ethernet, two uart functions, an i 2 c function, and an enhanced dedicated gpio entity (edge) function. the upstream usb interface of the XR22802 is compliant with both usb 2.0 full and hi-speed specifica- tions. all functions downstream of the hub are hi-speed functions. the XR22802 will have a single vendor id and vendor string. each func tion in the XR22802 will have an individual product string and serial string. the default seri al number strings will be based upon the uniquely assigned ethernet mac address for each XR22802 device. the serial strings for multiple functions within the same de vice will differ only by a single charac- ter which will be assigned a value betw een 0 and 7. all string and id va lues can be overridden via otp. the XR22802 can be placed into a low power or suspended state by the usb host. by default the XR22802 hub is config- ured for bus powered mode with a maximum power of 250 ma. all other functions in the XR22802 are configured for self- powered mode. in bus powered mode, the ethernet phy must be powered down during suspended state to meet usb sus- pend power requirements. the ethernet phy may remain enabled to support ethernet remote wakeup during suspend if the device is self-powered and the otp is modified to report the hub function as self-powered in the usb descriptors. see ethernet remote wakeup section on page 11 . each function of the XR22802 su pports one configurat ion and utilizes the following usb endpoints: ? usb hub ? control endpoint ? interrupt-in endpoint ? ethernet function ? control endpoint ? interrupt-in endpoint ? bulk-in and bulk-out endpoints ? i 2 c function ? control endpoint ? interrupt-in and interrupt-out endpoints ? edge controller function ? control endpoint ? interrupt-in and interrupt-out endpoints ? uart function ? control endpoint ? interrupt-in endpoint ? bulk-in and bulk-out endpoints usb vendor id exars usb vendor id is 0x04e2. this is the default vendor id that is used for the XR22802. companies may obtain their own vendor id, by becoming members of usb.org. the XR22802 otp can then be modified to report this vendor id in the usb descriptors. usb product id each function in the XR22802 has an individual usb product id. the default product ids for each of the functions are shown in table?1. these values can be modified by programming the otp. companies using their own vendor id may also select their own product ids. additionally , upon request exar will provide a select ion of different product ids for use with exars vendor id for companies that do not wish to become members of usb.org, but wish to use their own product id.
? 2015 exar corporation XR22802 10 / 46 exar.com/XR22802 rev 1b usb suspend all usb peripheral devices must support the usb suspend mode. per usb standard, the XR22802 device will begin to enter the suspend state if it does not detect any activity, (including start of frame or sof packets) on its usb data lines for 3 ms. the peripheral device must then reduce power consumption from vbus power within the next 7 ms to the allowed limit of 2.5 ma per function for the suspended state. because the XR22802 is a compound device with 6 functions, the sus- pend state power limit is 15 ma for the device. note that in th is context, the "device" is all circuitry (including the XR22802 ) that draws power from the host vbus. remote wakeup when the XR22802 is suspended, the e0/ria#/rwka#/ga0 or the e8/rib#/rwkb#/gb0 pins may be used to request that the host exit the suspend state if configured as an input. a high to low transition on either pin may be used to signal a remote wakeup request to the host via exars custom driver. however, because the two pins are internally logically anded, a logic 0 on either input will prevent th e resume signaling. note that the cdc-acm driver does not support the remote wakeup feature. the e0/ria#/rwka#/ga0 or the e8/rib#/rwkb#/gb0 pins may be used to signal remote wakeup by default. additionally, the e6/rxa/rwka# or e14/rxb/rwkb# pins, if configured as an input, may also be used for remote wakeup if enabled using the remote_wakeup register. the ethernet function in the XR22802 can also be used for remote wakeup under certain conditions. refer to ethernet remote wakeup on page 11 . usb strings usb specifies three character string descriptors that are provided to the usb host during enumeration in string descriptors: the manufacturer, product and serial strings. in a compound device such as the XR22802, each function provides these strings to the usb host. the default manufacturer string for th e XR22802 device is "exar corp.". the default product strings for the hub, ethernet function, uart functions, i 2 c function and edge function are shown in ta b l e 2 . the serial number string is a unique alpha-numeric ascii string programmed into the device at the factory. the otp may be used to override these strings. however, to ensure unique serial numbers for each device, it is recom- mended that the factory pre-programmed serial number string be used and not be overwritten via otp. table 1: default XR22802 product ids XR22802 function default product id hub 0x0802 ethernet 10/100 0x1300 uart channel a 0x1400 uart channel b 0x1401 i 2 c 0x1100 edge 0x1200 table 2: default XR22802 product strings XR22802 function default product string hub exars XR22802 hub ethernet 10/100 exar usb ethernet uarts exar usb uart i 2 c exar usb i2c edge exar usb edge
? 2015 exar corporation XR22802 11 / 46 exar.com/XR22802 rev 1b usb device drivers each of the functions in the XR22802 require a usb device driver for operation. both the i 2 c and edge functions conform to the hid device class and as such, ut ilize the embedded hid driver that is native to each operating system. the embed- ded hub also uses the native h ub driver. the ethernet function conforms to the cdc device class and as such can utilize an embedded cdc-ecm driver. however, at the time of this writ ing, none of the microsoft os provide support for cdc-ecm embedded drivers. both linux and mac os-x platforms do support cdc-ecm drivers. the cdc-ecm is a "standard" driver which implements functionality on a specific cl ass of devices. they operate without any ability to access device specific register sets. in some ca ses, this can limit the functiona lity and / or th roughput capabi l- ity of the XR22802. exar provides a custom ethernet device driver which has been optimized for the best possible data through-put in windows and linux platforms. this custom driver also allows for access to the device register set and thus full control of the XR22802 device functionality. refer to 10/100 ethernet section on page 11 for more details. the uart function can be used with either a standard cdc-acm driver or a custom driver. when the cdc-acm driver is used, the driver has no ability to read or write the XR22802 device registers. because of this, the XR22802 device is initial- ized to the settings in table?3. with a custom driver, all gpios default in hardware to inputs but these settings may be mod- ified by a custom driver. these default settings can be overridden by programming the otp. if a custom driver is used, the custom_driver_active bit sh ould be immediately set to 1 by the usb uart driver. once the custom_driver_active bit is set, the custom driver can use standard cdc-acm commands without config- uring the device to the default register settings used with the cdc-acm driver. any changes to the register settings for the gpios and flow control will specifically ne ed to be configured by the driver / applic ation software. althoug h there is no abili ty to read / write registers when using the cdc-acm driver, basic uart functions, including setting baud rate, character for- mat and sending line break is supported by the cdc driver. refer to the 4 cdc_acm_if usb control commands listed in ta bl e 4 . 10/100 ethernet the ethernet port is a 10/100 ethernet mac and phy compliant with ieee 802.3. the ethernet port supports speed / duplex auto-negotiation, auto-mdix, 10 mbps data auto-polarity, full and half duplex data rates at 10 and 100 mbps, gener- ates and validates the 32-bit fcs, and performs unicast and multicast filtering. the XR22802 also performs tcp, udp and icmp checksum offload over ipv4 and ipv6 as well as header checksum offload in ipv4. on chip ram provides all required packet buffering. in windows os, using the exar custom ethernet driver, the properties dialog, advanced properties can be used to set the pause frame flow control, speed and duplex, auto-negotiation, checksum offload, and ethernet remote wakeup settings. by default, the ethernet mac will honor incomi ng pause frames sent by a peer ethe rnet device, but will not generate pause frames. auto-mdix is always enabled. ethernet remote wakeup if the XR22802 hub is configured as a self-powered device and has ethernet remote wakeup enabled, the XR22802 will request the usb host to resume in response to a magic packet or a link state change on the ethernet port. when the usb table 3: XR22802 register defaults with cdc-acm driver register value notes flow control 0x001 hardware flow control gpio_mode 0x001 rts / cts flow control gpio_direction 0x008 e3/dtra#/ga3 and e11/dtrb #/gb3 are configured as outputs. all other gpios as inputs. gpio_int_mask 0x030 e[n]/ri#/rwk#/g[n], e[n]/cd#/g[n] and e[n]/dsr#/g[n] for both uart chan- nels are interrupt sensitive, i.e. can cause a usb interrupt to be generated
? 2015 exar corporation XR22802 12 / 46 exar.com/XR22802 rev 1b host is suspended, the ethernet phy remains active and the XR22802 is able to both meet usb suspend mode power requirements as well as respond to magic packet and link state changes. the magic packet is an ethernet packet with specific content, i.e. 6 bytes of 0xff, followed by 16 repetitions of the target mac address (mac address of the XR22802 device). this content can occur anywhere in the incoming packet payload. the link state change will wake the usb host if the link is down when the usb host is suspended and then the link goes up, or if the link is up when the usb host is suspended and then the link goes down. uart the uart can be configured via usb control transfers from the usb host. the uart transmitter and receiver sections are described separately in the following sections. at power-up, th e XR22802 will default to 9600 bps, 8 data bits, no parity bit, 1 stop bit, and no flow control. if a standard cdc-acm dr iver accesses the XR22802, defaults will change. see remote wakeup section on page 10 . uart transmitter the transmitter consists of a 1024-byte tx fifo and a transmit shift register (tsr). once a bulk-out packet has been received and the crc has been validated, the data bytes in that packet are written into the tx fifo of the specified uart channel. data from the tx fifo is transferred to the tsr when the tsr is idle or has completed sending the previous data byte. the transmitter sends the start bit followed by the data bits (starting with the lsb), inserts the proper parity-bit if enabled, and adds the stop-bit(s). the transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity. if 9 bit data is selected with out wide mode, the 9th bit will always be 0. uart transmitter - wide mode when both 9 bit data and wide mode are enabled, two bytes of data must be written. the first byte that is loaded into the tx fifo are the first 8 bits (data bits 7-0) of the 9-bit data. bit-0 of the second byte that is loaded into the tx fifo is bit-8 of the 9-bit data. the data that is transmitted on the tx pin is as follows: start bit, 9-bit data, stop bit. use the tx_wide_mode register to enable transmit wide mode. uart receiver the receiver consists of a 1024-byte rx fifo and a receive shift register (rsr). data that is received in the rsr via the rx pin is transferred into the rx fifo. data from the rx fifo is sent to the usb host in response to a bulk-in request. depending on the mode, error / status information for that data character may or may not be stored in the rx fifo with the data. uart receiver - normal mode with 7 or 8-bit data data that is received is stored in the rx fifo. any parity, framing or overrun error or break status information related to the data is discarded. receive data format is shown in figure 1 . uart receiver - normal mode with 9-bit data the first 8 bits of data received is stored in the rx fifo. the 9th bit as well as any parity, framing or overrun error or brea k status information related to the data is discarded. figure 1: uart normal receive data format with 7 or 8-bit data 1 st byte 7, 8 or 9-bit data 7 6 5 4 3 2 1 0 7 = ?0? in 7 bit mode
? 2015 exar corporation XR22802 13 / 46 exar.com/XR22802 rev 1b uart receiver - wide mode with 7 or 8-bit data two bytes of data are loaded into the rx fifo for each byte of data received. the first byte is the received data. the sec- ond byte consists of the error bits and break status. wide mode receive data format is shown in figure 2 . use the rx_wide_mode register to enable receive wide mode. use the rx_wide_mode register to enable receive wide mode. uart receiver - wide mode with 9-bit data two bytes of data are loaded into the rx fifo for each byte of data received. the first byte is the first 8 bits of the receive d data. the 9th bit received is stored in the bit 0 of the second byte. the parity bit is not received / checked. the remainder o f the 2nd byte consists of the framing and overrun error bits and break status. figure 2: uart receive wide mode data format with 7, 8 or 9-bit data error flags are also available from the error_status register and the interrupt packet, however these flags are historical flags indicating that an error has occurred since the previous request. therefore, no conclusion can be drawn as to which specific byte(s) may have contained an actual error in this manner. rx fifo low latency in normal operation all bulk-in transfers will be of maxpacketsize bytes (512 byte s in hi-speed mode an d 64 bytes in full- speed mode) to improve throughput and to minimize host processing. when there are 512 / 64 bytes of data in the rx fifo, the XR22802 will acknowledge a bulk-in reques t from the host and transfer the data packet. if there is less than 512 bytes in the rx fifo, the XR22802 may nak the bulk-in request indicating that data is not ready to transfer at that time. however, if there is less than 512 bytes in the rx fifo and no data has been received for more than 3 character times, the XR22802 will acknowledge the bulk-in request and transfer any data in the rx fifo to the usb host. in some cases, especially when the baud rate is low, this increases latency unacceptably. the XR22802 has a low latency register bit that will cause the XR22802 to immediately transfer any received data in the rx fifo to the usb host, i.e. it will not wait for 3 character times. the custom driver may automatically set the rx_control register to force the XR22802 to be in the low latency mode, or the user may manually set this bit. with the cdc-acm driver, the low latency mode is auto- matically set whenever the baud rate is set to a value of less than 46921 bps using the cdc_acm_if_set_line_cod- ing command. 1st byte 2nd byte 9 bit mode 7 6 5 4 3 2 1 0 x x x x o f b p 1st byte b = break f = framing error o = overrun error 2nd byte 7 or 8 bit mode p = parity error (= ?0? if not enabled) 7 = ?0? in 7 bit mode x = ?0? 7 6 5 4 3 2 1 0 x x x x o f b 8b = break f = framing error o = overrun error x = ?0?
? 2015 exar corporation XR22802 14 / 46 exar.com/XR22802 rev 1b gpio there can be up to 8 gpio pins in the XR22802 uart includ ing the uart rx and tx pins. these gpio pins may be con- figured as uart gpio, or for other uart functions, e.g. rts# function, or be assigned to the edge. refer to enhanced dedicated gpio entity section on page 15 . automatic rts / cts hardware flow control e[n]/rts#/rs485/g[n] and e[n]/cts#/g[n] of the uart channel may be enabled as the rts# and cts# signals for auto rts/cts flow control when gpio_mode[2:0] = 001 and fl ow_control[2:0] = 001. automatic rts flow control is used to prevent data overrun errors in local rx fifo by de-asserting the rts signal to the remote uart. when there is room in the rx fifo, the rts pin will be re-asserted. automatic cts flow control is used to prevent data overrun to the remote rx fifo. the cts# input is monitored to suspend / restart the local transmitter (see figure 3 ): figure 3: auto rts / cts hardware flow control automatic dtr / dsr hardware flow control auto dtr/dsr hardware flow control behaves the same as the auto rts/cts hardware flow control described above except that it uses the dtr# and dsr# signals. for auto hardware flow control, flow_control[2:0] = 001. e[n]/dtr#/ g[n] and e[n]/dsr#/g[n] become dtr# and dsr# , respectively, when gpio_mode[2:0] = 010. automatic xon / xoff software flow control when software flow control is enabled, the XR22802 compares the receive data characters with the programmed xon or xoff characters. if the received charac ter matches the programmed xoff characte r, the XR22802 will halt transmission as soon as the current character has completed transmission. data transmission is resumed when a received character matches the xon character. software flow control is enabled when flow_control[2:0] = 010. transm itter auto cts monitor receiver fifo trigger reached auto rts trigger level remote uart uartb rtsa# ctsb# txb rxa on on off on on off 1 2 3 4 1) com port opened, rx fifo empty, rtsa# output is asserted 2) signal propagated to ctsb# input 3) data bytes enter tx fifo, begin transmitting on txb 4) data propagates to receiving device rxa 5) rx fifo reaches threshold 6) rtsa# de-asserts 7) signal propagates to ctsb# input 8) transmission stops on txb 9) usb bulk-in empties rx fifo below threshold, rtsa# is asserted 10) signal propagated to ctsb# input 11) data bytes resume transmitting on txb 5 6 7 8 9 10 11 rtsa# ctsb# txb rxa ctsa# txa rtsb# rxb receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor local uart uarta
? 2015 exar corporation XR22802 15 / 46 exar.com/XR22802 rev 1b automatic rs-485 half duplex control the auto rs-485 half-duplex control feature changes the behavior of the e5/rts#/rs485/g5 pin when enabled by the gpio_mode register bits 2-0. see gpio_mode register description on page 23 . the flow_control register must also be set appropriately for use in multidrop applications. see flow_control register description on page 21 . if enabled, the transmitter automatically asserts the e5/rts#/rs485/g5 output prior to sending the data. by default, it de- asserts e[n]/rts#/rs485/g[n] following the last stop bit of the last character that has been transmitted, but the rs485_de- lay register may be used to delay the deassertion. the polarity of the e[n]/rts#/rs485/g[n] signal can also be modified using the gpio_mode register bit 3. multidrop mode with address matching the XR22802 device has two address matching modes which are also set by the flow control register using modes 3 and 4. these modes are intended for a multi-drop network application. in these modes, the xon_char register holds a unicast address and the xoff_char holds a multicast address. a unicast address is used by a transmitting master to broadcast an address to all attached slave devices that is intended for only one slave device. a multicast address is used to broadcast an address intended for more than one recipient device. each attached slave device should have a unique unicast address value stored in the xon_char register, while multiple slav es may have the same multicast adderss stored in the xoff_char register. an address match occurs when an address byte (9th bit or parity bit is 1) is received that matches the value stored in either the xon_char or xoff_char register. multidrop mode receiver if an address match occurs in either flow control mode 3 or 4, the uart receiver will automatically be enabled and all sub- sequent data bytes will be loaded into th e rx fifo. the uart receiver will automatically be disabled when an address byte is received that does not match the values in the xon_char or xoff_char register. multidrop mode transmitter in flow control mode 3, the uart transmitter is always enabled, irrespective of the rx address match. in flow control mode 4, the uart transmitter will only be enabled if there is an rx address match. programmable turn-around delay by default, the e5/rts#/rs485/g5 pin will be de-asserted immediately after the stop bit of the last byte has been shifted. however, this may not be ideal for systems where the signal needs to propagate over long cables. therefore, the de-asser- tion of e5/rts#/rs485/g5 pin can be delayed from 1 to 15 bit times via the rs485_delay register to allow for the data to reach distant uarts. half-duplex mode half-duplex mode is enabled when flow_control[3] = 1. in this mode, t he uart will ignore any data on the rx input when the uart is transmitting data. edge - enhanced dedicated gpio entity the XR22802 has 32 io pins that may be assigned to the edge . by default, 16 of these pins are assigned to the uart channel a and channel b functions, either to the uart data and / or flow control pins or to the uart gpio. the remaining 16 pins are dedicated edge pins. note that uart gpio and edge have separate register controls. pins assigned to the uart function cannot be controlled by the edge registers and vice versa. to assign pins to the edge, use the edge_- func_sel_0 register. see edge_func_ sel_0 register description on page 37 . the edge controller allows for gpio signals to be individually set or cleared or to be grouped, such that the all pins in the group can be simultaneously accessed for reads or writes. no te that on write accesses, outpu t pins will change in 4-bit sub- groups on core clock (60 mhz) boundaries. for example, if an 8 bit data group is defined and the data value is written from 0x00 to 0xff, 4 bits would change from 0 to 1 followed by the next 4 bits one clock cycle (~ 17 ns) later. edge ios can be configured as inputs or outputs. outputs can be configured as push-pull or open drain and can be tri- stated. inputs can be configured to generate interrupts to the usb host on either negative or postive edge transitions.
? 2015 exar corporation XR22802 16 / 46 exar.com/XR22802 rev 1b another feature of the edge controller is that up to 2 gpio pins within the edge can be assigned to pulse width modu- lated (pwm) outputs. each of the pwm outputs can be used to generate an output clock or pulse of varying duty cycle. both low and high cycles can be configured in steps of 267 ns up to 1.092 ms. the output can be controlled to generate a single "one-shot" pulse or to free run. refer to the edge_pwm0_ctrl and edge_pwm1_ctrl registers on page 42 and page 44 for control of pwm outputs. i 2 c the XR22802 implements an i 2 c multi-master using the control endpoint of the full-speed usb function to transfer data to and from the i 2 c interface. the i 2 c master supports both standard (100 kbps) and fast (400 kbps) modes and supports mul- tiple master configurations to allow other devices to access slave devices on the i 2 c. the i 2 c function is an hid function and uses the native hid driver. it supports both 7 and 10 bit addressing modes. regulated 3.3v power output the XR22802 internal volt age regulator provides 3.3 vdc output power whic h can be utilized by other circuitry. refer to electrical characteristics on page 3 for maximum power capability. for bus powe red devices, significant utilization of the 3v3 output power may require increasing the maximum power request above the 250 ma default value from the usb host by programming the otp. otp the otp is an on-chip non-volatile memory, that is one-time programmable via the usb interface. bit locations within the memory may be programmed at various times allowing for customization of the XR22802. some bits are pre-programmed at the factory and caution must be taken not to program any locations except user defined addresses. contact the factory uarttechsupport@exar.com for information and assistance in programming the XR22802 otp.
? 2015 exar corporation XR22802 17 / 46 exar.com/XR22802 rev 1b usb control commands the following table shows all of the usb control commands that are supported by the XR22802. commands include stan- dard usb commands, usb class specific cdc-acm co mmands and usb vendor specific exar commands. table 4: supported usb control commands name request type request value index length description lsb msb lsb msb lsb msb usb standard requests dev get_status 0x80 0x0 0x0 0x0 0x0 0x0 0x2 0x0 device: remote wake-up + self-powered if get_status 0x81 0x0 0x0 0x0 0x0 0x0 0x2 0x0 interface: zero ep get_status 0x82 0x0 0x0 0x0 0x0, 0x4, 0x84 0x0 0x2 0x0 endpoint: halted dev clear_feature 0x00 0x1 0x1 0x0 0x0 0x0 0x0 0x0 device remote wake-up ep clear_feature 0x02 0x1 0x0 0x0 0x0, 0x4, 0x84 0x0 0x0 0x0 endpoint halt dev set_feature 0x00 0x3 0x1 0x0 0x0 0x0 0x0 0x0 device remote wake-up ep set_feature 0x02 0x3 0x0 0x0 0x0, 0x4, 0x84 0x0 0x0 0x0 endpoint halt set_address 0x00 0x5 addr 0x0 0x0 0x0 0x0 0x0 addr = 1 to 127 get_descriptor 0x80 0x6 0x0 0x1 0x0 0x0 len msb len msb device descriptor get_descriptor 0x80 0x6 0x0 0x2 langid langid len msb len msb configuration descriptor get_descriptor 0x80 0x6 0x0 0x3 0x0 0x0 len msb len msb string descriptor get_configuration 0x80 0x8 0x0 0x0 0x0 0x0 0x1 0x0 set_configuration 0x00 0x9 n 0x0 0x0 0x0 0x0 0x0 n = 0, 1 usb class specific requests cdc_acm_if set_line_coding 0x21 0x20 0x0 0x0 0x0 0x0 0x7 0x0 set the uart baud rate, parity, stop bits, etc. cdc_acm_if get_line_coding 0xa1 0x21 0x0 0x0 0x0 0x0 0x7 0x0 get the uart baud rate, parity, stop bits, etc. cdc_acm_if set_control_ line_state 0x21 0x22 0x0 0x0 0x0 0x0 0x7 0x0 set/clear dtr in cdc- acm mode. cdc_acm_if send_break 0x21 0x23 val lsb val msb 0x0 0x0 0x0 0x0 send a break for the specified duration.
? 2015 exar corporation XR22802 18 / 46 exar.com/XR22802 rev 1b note 1: set_eth_packet_filters bitmap definition: d15..d5: reserved d4: multicast if 1, packets with multicast addre sses set by setethernetmulticastfilter are forwarded to the host. 0 = disabled. d3: broadcast if 1, broadcast packets are forwarded to the host. 0 = disabled. d2: directed if 1, unicast packets with a matching address are forwarded to the host. 0 = disabled. d1: all_multicast if 1, all multicast packets are forwarded to the host. 0 = disabled. d0: promiscuous if 1, all packets are forwarded to the host, regardless of address. 0 = disbled. note 2: set_eth_packet_filte rs selector definition: 0x01 = xmit_ok 0x02 = rcv_ok 0x03 = xmit_error 0x04 = rcv_error 0x05 = rcv_no_buffer 0x0d = directed_frame_rcv 0x0f = multicast_frame_rcv 0x11 = broadcast_frame_rcv 0x12 = rcv_crc_error 0x13 = xmit_queue_length 0x14 = rcv_err_alignment 0x19 = rcv_overrun cdc_ecm_if_ set_eth_mcast_fil- ters 0x21 0x40 num- ber (n) of filters lsb num- ber (n) of filters msb 0x0 0x0 n*6 lsb n*6 msb cdc_ecm_if_ set_eth_packet_- filters 0x21 0x43 *bit- map lsb *bit- map msb 0x0 0x0 0x0 0x0 see bitmap definition in note 1 below cdc_ecm_if_ get_eth_statistic 0xa1 0x44 selec tor 0x0 0x0 0x0 0x4 0x0 see selector definition in note 2 below usb vendor specific requests xr_get_chip_id 0xc0 0xff 0x0 0x0 0x0 0x0 0x6 0x0 get exar vid (2 bytes), pid (2 bytes) and bcdde- vice (2 bytes) xr_set_reg see ta b l e 5 0x40 0x5 write- data lsb write- data msb write addr 0x0 0x0 0x0 vendor specific register access. xr_get_reg see ta b l e 5 0xc0 0x5 0x0 0x0 read addr 0x0 0x2 0x0 vendor specific register access. table 4: supported usb control commands name request type request value index length description lsb msb lsb msb lsb msb
? 2015 exar corporation XR22802 19 / 46 exar.com/XR22802 rev 1b uart registers uart registers are accessible via the usb interface us ing the xr_set_reg and xr_get_reg usb commands. note that all addresses not listed in this table are reserved or undefined. upper byte (bits 15:8) not shown in table are also reserved and should remain 0x00. writing to any register other than those defined in table?5 may result in undefined behav- ior of the device. the addresses for each of uarts in the XR22802 are the same. because each uart is assigned a unique usb address during enumer ation by the usb host, a gui connected to a specific com port will be directed via the driver to the appropriate uart channel. uart register map table 5: XR22802 register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8) 0x040 uart_enable 0 0 0 0 0 0 rx tx 0x045 format stop parity data_bits 0x046 flow_control 0 0 0 0 auto_ rs485 mode 0x047 xon_char char 0x048 xoff_char char 0x049 error_status break _ac- tive over- run parity frame break 0 0 0 0x04a tx_break (msb) value [msb] tx_break (lsb) value [lsb] 0x04b rs485_delay 0 0 0 0 value 0x04c gpio_mode 0 0 0 0 rs485_ pol mode 0x04d gpio_direction 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x04e gpio_set 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x04f gpio_clear 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x050 gpio_status 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x051 gpio_int_mask 0 0 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x052 customized_int 0 0 0 0 0 0 0 en 0x054 pin_pullup_en tx rx gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x055 pin_pulldown_en tx rx gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x056 loopback 0 0 0 0 0 dtr_ dsr rts_ cts tx_rx 0x057 ir_mode 0 0 0 0 0 tx_ pulse rx_ inver t en 0x05f remote_wakeup 0 0 0 0 rx_en ri_en 0 0
? 2015 exar corporation XR22802 20 / 46 exar.com/XR22802 rev 1b uart register descriptions note that all register reset default values are 0 unless otherwise specified. all registers are 16 bits. uart_enable (0x040) - read/write format (0x045) - read/write note that the cdc_set_line_codi ng command may be used to set the uart da ta format in addition to this registers . 0x060 tx_fifo_reset 0 0 0 0 0 0 0 rst 0x061 tx_fifo_fill (msb) 0 0 0 0 fill[10:8] tx_fifo_fill (lsb) fill[7:0] 0x062 tx_wide_mode 0 0 0 0 0 0 0 en 0x063 rx_fifo_reset 0 0 0 0 0 0 0 rst 0x064 rx_fifo_fill (msb) 0 0 0 0 0 fill[10:8] rx_fifo_fill (lsb) fill[7:0] 0x065 rx_wide_mode 0 0 0 0 0 0 0 en 0x066 rx_control 0 0 0 0 0 0 max_ pkt_- size low_ laten cy 0x067 flow_threshold (msb) 0 0 0 0 0 thresh [10:8] flow_threshold (l sb) thresh [7:0] miscellaneous registers 0x081 custom_driver 0 0 0 0 0 0 0 active bit default description 15:2 0x0000 reserved these bits are reserved and should be written as 0. 10 rx 0: disable uart rx 1: enable uart rx 00 tx 0: disable uart tx 1: enable uart tx bit default description 15:8 0x00 reserved these bits are reserved and should be written as 0. table 5: XR22802 register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8)
? 2015 exar corporation XR22802 21 / 46 exar.com/XR22802 rev 1b flow_control (0x046) - read/write xon_char (0x047) - read/write 70 stop 0: 1 stop bit 1: 2 stop bits 6:4 0 parity 000: no parity 001: odd parity 010: even parity 011: mark parity 100: space parity all other values undefined, do not use. 3:0 0x8 data_bits 0111: 7-bit characters 1000: 8-bit characters 1001: 9-bit characters all other values undefined, do not use. bit default description 15:4 0x000 reserved these bits are reserved and should be written as 0. 30 half-duplex mode 0: uart rx received data irrespective of uart tx 1: uart rx is disabled when uart tx is transmitting data 2:0 0 mode 000: none 001: hardware 010: soft ware 011: address match rx 100: address match rx and tx all other values undefined, do not use. bit default description 15:8 0x00 reserved these bits are reserved and should be written as 0. 7:0 0x11 char xon ascii character received in hexadecimal format bit default description
? 2015 exar corporation XR22802 22 / 46 exar.com/XR22802 rev 1b xoff_char (0x048) - read/write error_status (0x049) - read only tx_break (0x04a) - read/write bit default description 15:8 0x00 reserved these bits are reserved and should be written as 0. 7:0 0x13 char xoff ascii character received in hexadecimal format bit default description 15:8 0x00 reserved these bits are reserved and should be written as 0. 70 break_active 0: no break condition currently active 1: break condition currently active 60 overrun 0: no overrun error detected 1: overrun error detected since last register read 50 parity 0: no parity error detected 1: parity error detected since last register read 40 frame 0: no frame error detected 1: frame error detected since last register read 30 break 0: no break error detected 1: break error detected since last register read 2:0 0 reserved these bits are reserved and should be written as 0. bit default description 15:0 0x0000 value this register controls transmission of break signal. wr iting a non-zero value "n" to this registers causes the XR22802 to send a break signal on the uart tx pin for "n" ms, for 0 < n < 0xffff. a counter will decrement this value at 1 ms intervals until the count reaches 0x0 at which time the break signal will stop being sent. writ- ing a value of 0xffff causes a cont inuous break signal to be sent, until either a value of 0x0 is written or another non-zero value other than 0xffff which will again cause break signal to stop after the counter expires.
? 2015 exar corporation XR22802 23 / 46 exar.com/XR22802 rev 1b rs485_delay (0x04b) - read/write gpio_mode (0x04c) - read/write gpio_direction (0x04d) - read/write note that when setting direction of a uart gpio to output, the pin_pullup_en for that io pin should also be disabled and when setting a uart gpio pin to input, the pin_pullup_en for that io pin should also be enabled. gpio_set (0x04e) - write only bit default description 15:4 0x000 reserved these bits are reserved and should be written as 0. 3:0 000 value this value is the number of bit times the XR22802 wa its before de-asserting the e5/rts#/rs485/g5 pin when it is configured for automatic rs-485 half-duplex control. bit default description 15:4 0x000 reserved these bits are reserved and should be written as 0. 30 rs485 polarity 0: active low auto. rs-485 half-duplex enable 1: active high auto. rs-485 half-duplex enable 2:0 0x0 gpio mode 000: mode 0 - all gpio are used for general purpose i/o. 001: mode 1 - e5/rts#/rs485/g5 and e4/cts #/g4 used for auto rts/cts hw flow control 010: mode 2 - e3/dtr#/g3 and e2/dsr#/g2 used for auto dtr/dsr hw flow control 011: mode 3 - e5/rts#/rs485/g5 pin used for auto rs-485 half-duplex enable during transmit 100: mode 4 - e5/rts#/rs485/g5 pin used for au to rs-485 half-duplex enable after address match. 101 to 111: reserved values, do not use. bit default description 15:6 0x000 reserved these bits are reserved and should be written as 0. 5:0 0x00 gpio[n] direction 0: gpio[n] is an input 1: gpio[n] is an output bit default description 15:6 0x000 reserved these bits are reserved and should be written as 0.
? 2015 exar corporation XR22802 24 / 46 exar.com/XR22802 rev 1b gpio_clear (0x04f) - write only gpio_status (0x050) - read only gpio_int_mask (0x051) - read/write customized_int (0x052) - read/write 5:0 0x00 gpio[n] set 0: no effect 1: set gpio[n] if configured as an output to a logic 1 bit default description 15:6 0x000 reserved these bits are reserved and should be written as 0. 5:0 0x00 gpio[n] clear 0: no effect 1: clear gpio[n] if configured as an output to a logic 0 bit default description 15:6 0x000 reserved these bits are reserved and should be written as 0. 5:0 0x00 gpio[n] status reading returns the current state of gpio[n]. bit default description 15:6 0x000 reserved these bits are reserved and should be written as 0. 5:0 0x00 gpio[n] mask dictates whether a change in gpio pin state causes the device to generate a usb interrupt packet. in either case, the gpio status register will still report the pin's state when read, and if an interrupt packet is formed due to other interrupt trigger, the interrupt packet will contain the current state of the pin. 0: a change in the pin's state causes the device to generate an interrupt packet. 1: a change in the pin's state does not cause the device to generate an interrupt packet. bit default description 15:1 0x0000 reserved these bits are reserved and should be written as 0. bit default description
? 2015 exar corporation XR22802 25 / 46 exar.com/XR22802 rev 1b 00 enable enables the customized interrupt packet format to report all gpio status in the interrupt packet. 0: use standard interrupt packet. see ta b l e 6 and ta bl e 7 . 1: use customized interrupt packet. see ta b l e 8 . table 6: interrupt packet format offset field size (bytes) value description 0 bmrequesttype 1 8b10100001 d7 = device-to-host direction d6:5 = class type d4-0: = interface recipient 1 bnotification 1 8h20 defined encoding for serial_state 2 wvalue 2 16h0000 4 windex 2 16h0000 d15-8 = reserved (0) d7-0 = interface number, 8h00 for the cdc command interface 6 wlength 2 16h0002 2 bytes of transferred data 8 data 2 standard int_status (see ) for customized int_status size = 4 bytes (see ta bl e 7 and ) ta b l e 8 d15-7 = reserved (0) d6 = boverrun d5 = bparity d4 = bframing d3 = bringsignal (ri) d2 = bbreak d1 = btxcarrier (dsr) d0 = brxcarrier (cd) table 7: data field of standard interrupt packet bits field description d15..d7 reserved (future use) d6 boverrun received data has been disc arded due to overrun in the device. d5 bparity a parity error has occured. d4 bframing a framing error has occured. d3 bringsignal state of ring signal detection of the device. d2 bbreak state of break detection mechanism of the device. d1 btxcarrier state of transmission carrier. this signal corresponds to v.24 signal 106 and rs-232 signal dsr. d0 brxcarrier state of receiver carrier det ection mechanism of device. this signal corresponds to v.24 signal 109 and rs-232 signal dcd. bit default description
? 2015 exar corporation XR22802 26 / 46 exar.com/XR22802 rev 1b overrun, parity error, frame error, and break all indicate that at least one event has occurred since the last interrupt mes- sage. "state" reflects the high/low state of the pin at the ti me the interrupt data in packet was generated. "change" indi- cates whether the level on the pin changed at least once since the last interrupt message. pin_pullup_en (0x054) - read/write table 8: data field of customized interrupt packet - exar vendor specific bit(s) description 31-20 reserved (0) 19 overrun 18 parity error 17 frame error 16 break status 15-14 reserved (0) 13 rts state 12 cts state 11 dtr state 10 dsr state 9cd state 8ri state 7-6 reserved (0) 5 rts change 4 cts change 3 dtr change 2 dsr change 1 cd change 0 ri change bit default description 15:8 0 reserved these bits are reserved and should be written as 0. 71 uart tx 0: disable internal pull-up resistor on the uart tx pin 1: enable internal pull-up resistor on the uart tx pin 61 uart rx 0: disable internal pull-up resistor on the uart rx pin 1: enable internal pull-up resistor on the uart rx pin 5:0 0x3f gpio[n] 0: disable internal pull-up resistor on the corresponding gpio[n] pin 1: enable internal pull-up resistor on the corresponding gpio[n] pin
? 2015 exar corporation XR22802 27 / 46 exar.com/XR22802 rev 1b pin_pulldown_en (0x055) - read/write loopback (0x056) - read/write ir_mode (0x057) - read/write bit default description 15:10 0 reserved these bits are reserved and should be written as 0. 70 uart tx 0: disable internal pull-down resistor on the uart tx pin 1: enable internal pull-down resistor on the uart tx pin. (will not be enabled if pull-up is already enabled.) 60 uart rx 0: disable internal pull-down resistor on the uart rx pin 1: enable internal pull-down resistor on the uart rx pin. (will not be enabled if pull-up is already enabled.) 5:0 0 gpio[n] 0: disable internal pull-down resistor on the corresponding gpio[n] pin 1: enable internal pull-down resistor on the corresponding gpio[n] pin. (will not be enabled if pull-up is already enabled.) bit default description 15:3 0 reserved these bits are reserved and should be written as 0. 20 dtr_dsr 0: disable dtr to dsr internal loopback 1: enable dtr to dsr internal loopback 10 rts_cts 0: disable rts to cts internal loopback 1: enable rts to cts internal loopback 00 tx_rx when this bit is set all transmitted uart data is looped back to the uart receiver. note that when the internal loopback is enabled, the tx data will be disabled and rx data will be ignored. 0: disable tx to rx internal loopback 1: enable tx to rx internal loopback bit default description 15:3 0 reserved these bits are reserved and should be written as 0. 20 tx_pulse 0: tx pulse width is 3/16 of the bit period 1: tx pulse width is 4/16 of the bit period 10 rx_invert 0: rx input is not inverted before sampling 1: rx input is inverted before sampling
? 2015 exar corporation XR22802 28 / 46 exar.com/XR22802 rev 1b remote_wakeup (0x05f) - read/write tx_fifo_reset (0x060) - write only tx_fifo_fill (0x061) - read only 00 en 0: disable ir mode 1: enable ir mode bit default description 15:4 0x000 reserved these bits are reserved and should be written as 0. 30 rx_en 0: rx pin remote wakeup is disabled 1: a high to low transition on the rx pin will ca use a resume request to be sent to the usb host 21 ri_en 0: ri# pin remote wakeup is disabled 1: a high to low transition on the ri# pin will ca use a resume request to be sent to the usb host 1:0 0x0 reserved these bits are reserved and should be written as 0. bit default description 15:1 0x0000 reserved these bits are reserved and should be written as 0. 0 000 reset 0: no effect 1: resets the tx fifo to empty bit default description 15:11 0x00 reserved these bits are reserved and should be written as 0. 10:0 0x000 fill number of bytes in the tx fifo bit default description
? 2015 exar corporation XR22802 29 / 46 exar.com/XR22802 rev 1b tx_wide_mode (0x062) - read/write rx_fifo_reset (0x063) - write only rx_fifo_fill (0x064) - read only rx_wide_mode (0x065) - read/write bit default description 15:1 0x0000 reserved these bits are reserved and should be written as 0. 00 en in wide mode, 2 bytes of data are used to transfer one ch aracter. this requires 2 bytes of fifo space, therefore the fifo can hold half as many characters in wide mode . in the tx direction bit 0 of the second byte will be used as bit 9 of the character, if 9-bit mode is enabled. bits 7:1 of the second byte are not used. 0: disable tx wide mode 1: enable tx wide mode bit default description 15:1 0x0000 reserved these bits are reserved and should be written as 0. 0 000 reset 0: no effect 1: resets the rx fifo to empty bit default description 15:11 0x00 reserved these bits are reserved and should be written as 0. 10:0 0x000 fill number of bytes in the rx fifo bit default description 15:1 0x0000 reserved these bits are reserved and should be written as 0. 00 en in wide mode, 2 bytes of bulk data are used to transfer one character. this requires 2 bytes of fifo space, therefore the fifo can hold half as many characters in wi de mode. in the rx direction, bits 3:0 of the second byte contain the error flags associated with the character. bits 7:4 of the second byte are not used. 0: disable rx wide mode 1: enable rx wide mode
? 2015 exar corporation XR22802 30 / 46 exar.com/XR22802 rev 1b rx_control (0x066) - read/write flow_threshold (0x067) - read/write custom_driver (0x081) - read/write bit default description 15:2 0 reserved these bits are reserved and should be written as 0. 10 max_pkt_size 0: maximum bulk-in packet size is 512 / 64 bytes in hi-speed / full-speed mode respectively (normal operation) 1: maximum bulk-in packet size is 508 / 60 bytes in hi-speed / full-speed mode respectively (workaround for known windows os cdc-acm driver issue) 00 low_latency 0: disable low latency mode 1: enable low latency mode bit default description 15:11 0x0 reserved these bits are reserved and should be written as 0. 10:0 0x2e0 thresh if enabled, flow control (either hardware or software), will be asserted when the rx fifo fill level exceeds the threshold value. bit default description 15:1 0x0000 reserved these bits are reserved and should be written as 0. 00 active a custom driver should immediately enable this bit pr ior to using any cdc-acm commands from the usb host, to ensure that the XR22802 does not enter cdc mode and default to the values listed in ta bl e 3 .
? 2015 exar corporation XR22802 31 / 46 exar.com/XR22802 rev 1b hid reports the i 2 c and edge functions in the XR22802 are hid functions. i 2 c data may be read or written to / from the slave device using the interrupt in and interrupt out endpoints via hid input and output reports. additionally, XR22802 device register access using the control endpoint for both i 2 c and edge functions is performed via hi d feature reports. reading uses indi- rect addressing such that for register reads, the register address must first be written and the register value may then be read. both types of reports are described below. input and output reports input and output reports using the interrupt in and interrupt out endpoints follow the following format. for more information on reading and writing on the i 2 c interface refer to an220, programming applications using the xr2280x i 2 c interface. i2c_slave_out transfer type: interrupt out transfer size: 37 bytes the i2c_slave_out report writes and / or reads up to 32 bytes of data on the i 2 c interface. note that all interrupt out transfers will be automatically followed by an interrupt in trans fer. for write only transfers, the interrupt in packet will c ontain the status of the interrupt out transfer. for read only or write and read transfers, the interrupt in packet will contain the read data, as well as the status of the interrupt out transfer. the format of the interrupt out packet is given below. * note: to support 10-bit addressing the standard 7-bit address must be set to 1111 0 x x b w h e re x x a re t h e m o s t s i g n i fi c a n t b i t s o f t h e 10 - bit address. all 4 of these 7-bit addresses are reserved and will not be used by any slaves with 7-bit only addresses. the leas t significant bit of the address byte still specifies the direction. for writes, the first data byte which was previously unformatted is now reserved for the least significant 8 bits of the 10-bit address. additional data bytes remain unformatted. for reads, the write-then-read combi ned transfer format is always used. during the write portion of the combined transfer the master must send at least one data byte which cont ains the least significant 8 bits of the 10-bit address. after all of the write data is sent the master then sends a restart bit. this i s followed with an address byte which has the same 7-bit address 1111 0 x x b a s i n t h e w ri te p o r t i o n . h o w eve r, t h e d i re c t i o n b i t i s n o w 1 fo r re a d i n g. t h e s l a ve then sends the read data as usual. the le ast significant 8 bits of the 10-bit address are not sent again after the restart bit. field offset size value description report id 0 1 0x00 write, read, or write and read i 2 c data flags 1 1 bitmap transfer options d0: prefix transfer with a start bit. d1: append a stop bit to the transfer. d2: ack last read to extend a read transfer (e.g. if more than 32 bytes need to be read). the default is to nak the last read in the transfer. this bit has no effect if rdsize is 0. d3: reserved d7..d4: sequence number. this can help the host to correlate an in response with a prior out command. this field is optional. wrsize 2 1 number number of data bytes to write. valid values are 0 to 32. the 7-bit slave address should not be included in this total. rdsize 3 1 number number of bytes to read. valid values are 0 to 32. slaveaddr 4 1 number the 7-bit slave address * to send. the XR22802 will automatically set the i2 c read/write bit, so bit d0 of this field is ignored. data 5 32 data data to be written to the slave. hid uses a fixed report size for each specific report id so this field will always be 32 bytes long. however, only the number of bytes specified in wrsize will be written. other bytes will be ignored.
? 2015 exar corporation XR22802 32 / 46 exar.com/XR22802 rev 1b i2c_slave_in transfer type: interrupt in transfer size: 37 bytes interrupt in packet status only, or status and read data from the i2c interface. feature reports access to XR22802 registers via hid feature reports along with the register descriptions are given in the following sections. write_hid_register transfer type: control transfer size: 5 bytes the write_hid_register report writes 2 bytes of data to the specified register address. field offset size value description report id 0 1 0x00 i 2 c response packet flags 1 1 bitmap status of the requested transfer. d0: request error. if 1, the out request had an error (e.g. invalid size) and was not executed. d1: a byte sent to a slave received an i2c nak response. the transfer was aborted. d2: arbitration was lost. the transfer was aborted. d3: timeout. bus free condition was not observed within 256 ms or an individual byte transfer extended longer than 10ms. d7..d4: sequence number. this number matches the value provided in the corresponding out command packet. wrsize 2 1 number number of bytes written, 0 to 32. rdsize 3 1 number number of bytes read, 0 to 32. reserved 4 1 0x00 this field is reserved and should always return a value of 0x00. data 5 32 data the read data that was received from the slave. hid uses a fixed report size for each specific report id, so this field will always be 32 bytes long. however, only the number of bytes specified in rdsize are valid. other bytes should be ignored. field offset size value description report id 0 1 0x3c write hid register write address lsb 1 1 write address write address msb 2 1 write data lsb 3 1 write data write data msb 4 1
? 2015 exar corporation XR22802 33 / 46 exar.com/XR22802 rev 1b set_hid_read_address transfer type: control transfer size: 3 bytes the set_hid_read_address report sets the address for the read_hid_register report. read_hid_register transfer type: control transfer size: 3 bytes the read_hid_register report reads register data fr om the address set by the set_hid_read_address report. field offset size value description report id 0 1 0x4b set address for hid register read read address lsb 1 1 read address read address msb 2 1 field offset size value description report id 0 1 0x5a read hid register read data lsb 1 1 read data read data msb 2 1
? 2015 exar corporation XR22802 34 / 46 exar.com/XR22802 rev 1b hid register map table 9: XR22802 hid register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8) i 2 c registers 0x341 i 2 c_scl_low msb [15:8] value (msb) i 2 c_scl_low lsb [7:0] value (lsb) 0x342 i 2 c_scl_high msb [15:8] value (msb) i 2 c_scl_high lsb [7:0] value (lsb) edge registers 0x3c0 edge_func_sel_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_func_sel_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c1 edge_dir_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_dir_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c2 edge_set_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_set_0 [7:0] e7e6e5e4e3e2e1e0 0x3c3 edge_clear_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_clear_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c4 edge_state_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_state_0 [7:0] e7e6e5e4e3e2e1e0 0x3c5 edge_tri_state_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_tri_state_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c6 edge_open_drain_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_open_drain_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c7 edge_pull_up_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_pull_up_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c8 edge_pull_down_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_pull_down_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3c9 edge_intr_mask_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_intr_mask_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0
? 2015 exar corporation XR22802 35 / 46 exar.com/XR22802 rev 1b 0x3ca edge_intr_pos_ edge_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_intr_pos_ edge_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3cb edge_intr_neg_ edge_0 [15:8] e15 e14 e13 e12 e11 e10 e9 e8 edge_intr_neg_ edge_0 [7:0] e7 e6 e5 e4 e3 e2 e1 e0 0x3cd edge_dir_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_dir_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3ce edge_set_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_set_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3cf edge_clear_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_clear_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d0 edge_state_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_state_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d1 edge_tri_state_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_tri_state_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d2 edge_open_drain_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_open_drain_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d3 edge_pull_up_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_pull_up_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d4 edge_pull_down_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_pull_down_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d5 edge_intr_mask_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_intr_mask_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d6 edge_intr_pos_ edge_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_intr_pos_ edge_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 table 9: XR22802 hid register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8)
? 2015 exar corporation XR22802 36 / 46 exar.com/XR22802 rev 1b 0x3d7 edge_intr_neg_ edge_1 [31:24] e31 e30 e29 e28 e27 e26 e25 e24 edge_intr_neg_ edge_1 [23:16] e23 e22 e21 e20 e19 e18 e17 e16 0x3d8 edge_pwm0_ctrl msb [15:8] 0000000cmd[2] edge_pwm0_ctrl lsb [7:0] cmd[1:0] en pin[4:0] 0x3d9 edge_pwm0_high msb [15:8] 0000 value[11:8] edge_pwm0_high lsb [7:0] value [7:0] 0x3da edge_pwm0_low msb [15:8] 0000 value[11:8] edge_pwm0_low lsb [7:0] value [7:0] 0x3db edge_pwm1_ctrl msb [15:8] 0000000cmd[2] edge_pwm1_ctrl lsb [7:0] cmd[1:0] en pin[4:0] 0x3dc edge_pwm1_high msb [15:8] 0000 value[11:8] edge_pwm1_high lsb [7:0] value [7:0] 0x3dd edge_pwm1_low msb [15:8] 0000 value[11:8] edge_pwm1_low lsb [7:0] value [7:0] table 9: XR22802 hid register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8)
? 2015 exar corporation XR22802 37 / 46 exar.com/XR22802 rev 1b hid register descriptions note that all register reset default values are 0 unless otherwise specified. all registers are 16 bits. i 2 c_scl_low (0x341) - read/write i 2 c_scl_high (0x342) - read/write edge_func_sel_0 (0x3c0) - read/write edge_dir_0 (0x3c1) - read/write note that when setting direction of an edge io to output, the edge_pull_up for that io pin should also be disabled and when setting an edge io pin to input, the edge_pull_up for that io pin should also be enabled. bit default description 15:0 0x0144 value specifies the number of periods that scl will be asserted low by the XR22802 i 2 c master. note that in clock stretching, the i 2 c slave may extend the scl low period to delay the next transaction. for 100 kbps transfer rate this value must be at least 252 (0x00fc) and the sum of high and low periods must be at least 600 (0x0258). for 400kbps transfer rate this value must be at least 78 (0x004e) and the sum of the high and low periods must be at least 150 (0x0096). measured in 60 mhz core clock periods, i.e. approximately 16.7 ns. bit default description 15:0 0x0114 value specifies the number of periods that sc l will be asserted high by the XR22802 i 2 c master. note that another multi-master may assert scl low before the XR22802 high pe riod is completed. for 100 kbps transfer rate this value must be at least 240 (0x00f0) and the sum of t he high and low periods must be at least 600 (0x0258). for 400 kbps transfer rate this value must be at least 36 (0x0024) and the sum of the high and low periods must be at least 150 (0x0096). measured in 60 mhz core clock periods, i.e. approximately 16.7 ns bit default description 15:0 0x0000 e[15:0] 0: io is assigned to the uart / gpio function. io pin controlled using uart registers. 1: io is assigned to the edge function . io pin controlled using edge registers. bit default description 15:0 0x0000 e[15:0] 0: io pin assigned to edge function is configured as an input 1: io pin assigned to edge f unction is configured as an output.
? 2015 exar corporation XR22802 38 / 46 exar.com/XR22802 rev 1b edge_set_0 (0x3c2) - write only edge_clear_0 (0x3c3) - write only edge_state_0 (0x3c4) - read/write edge_tri_state_0 (0x3c5) - read/write edge_open_drain_0 (0x3c6) - read/write bit default description 15:0 0x0000 e[15:0] 0: no effect 1: set io pin assigned to edge function and configured as an output to a logic 1 bit default description 15:0 0x0000 e[15:0] 0: no effect 1: clear io pin assigned to edge function and configured as an output to a logic 0 bit default description 15:0 0x0000 e[15:0] writing in this register sets or clears the edge io pin( s) configured as an output. writing to an edge pin con- figured as an input has no effect. reading this register re turns the state of each io pin configured as an edge pin irrespective of whether it is conf igured as an input or output. note that output transitions across multiple io pins may be slightly staggered. refer to edge section on page 15 . 0: write clears the corresponding bit to a 0. read returns the current state. 1: write sets the corresponding bit to a 1. read returns the current state. bit default description 15:0 0x0000 e[15:0] 0: io pin assigned to edge function and configured as an output is actively driven 1: io pin assigned to edge function and configured as an output is tri-stated bit default description 15:0 0x0000 e[15:0] note that XR22802 open drain outputs have a weak internal pull-up. 0: io pin assigned to edge function and configured as an output is a push-pull output 1: io pin assigned to edge function and configured as an output is an open drain output
? 2015 exar corporation XR22802 39 / 46 exar.com/XR22802 rev 1b edge_pull_up_0 (0x3c7) - read/write edge_pull_down_0 (0x3c8) - read/write edge_intr_mask_0 (0x3c9) - read/write edge_intr_pos_edge_0 (0x3ca) - read/write bit default description 15:0 0xffff e[15:0] 0: disable internal pull-up resistor on io pin assigned to edge function and configured as an input 1: enable internal pull-up resistor on io pin assigned to edge function and configured as an input bit default description 15:0 0x0000 e[15:0] 0: disable internal pull-down resistor on io pin a ssigned to edge function and configured as an input 1: enable internal pull-down resistor on io pin assigned to edge function and configured as an input bit default description 15:0 0x0000 e[15:0] writing a 1 in this register enables an input pin for the corresponding bit position edge io pin(s) configured as an input to generate an interrupt if either edge_i ntr_pos_edge and / or edge _intr_neg_edge regis- ters has also been enabled. an edge pin configured as an output has no effect. 0: io pin will not generate an interrupt 1: io pin assigned to edge function and configured as an input will generate an interrupt bit default description 15:0 0xffff e[15:0] writing a 1 in this register enables an interrupt to be generated on the rising edge of the corresponding bit posi- tion edge io pin(s) configured as an input if the edge _intr_mask register is enabled for that pin. if the edge_intr_neg_edge register is also enabled, inte rrupts will be generated on both edges. writing to an edge pin configured as an output has no effect. 0: io pin will not generate an interrupt on rising edge 1: io pin assigned to edge function and configured as an input will generate an interrupt on rising edge if cor- responding edge_intr_mask bit is set
? 2015 exar corporation XR22802 40 / 46 exar.com/XR22802 rev 1b edge_intr_neg_edge_0 (0x3cb) - read/write edge_dir_1 (0x3cd) - read/write note that when setting direction of an edge io to output, the edge_pull_up for that io pin should also be disabled and when setting an edge io pin to input, the edge_pull_up for that io pin should also be enabled. edge_set_1 (0x3ce) - write only edge_clear_1 (0x3cf) - write only bit default description 15:0 0xffff e[15:0] writing a 1 in this register enables an interrupt to be generated on the falling edge of the corresponding bit position edge io pin(s) configured as an input if the edge _intr_mask register is enabled for that pin. if the edge_intr_pos_edge register is also enabled, interr upts will be generated on both edges. writing to an edge pin configured as an output has no effect. 0: io pin will not generate an interrupt on falling edge 1: io pin assigned to edge function and configured as an input will generate an interrupt on falling edge if cor- responding edge_intr_mask bit is set bit default description 31:16 0x0000 e[31:16] 0: io pin assigned to edge function is configured as an input 1: io pin assigned to edge f unction is configured as an output. bit default description 31:16 0x0000 e[31:16] 0: no effect 1: set io pin assigned to edge function and configured as an output to a logic 1 bit default description 31:16 0x0000 e[31:16] 0: no effect 1: clear io pin assigned to edge function and configured as an output to a logic 0
? 2015 exar corporation XR22802 41 / 46 exar.com/XR22802 rev 1b edge_state_1 (0x3d0) - read/write edge_tri_state_1 (0x3d1) - read/write edge_open_drain_1 (0x3d2) - read/write edge_pull_up_1 (0x3d3) - read/write edge_pull_down_1 (0x3d4) - read/write bit default description 31:16 0x0000 e[31:16] writing in this register sets or clears the edge io pin( s) configured as an output. writing to an edge pin con- figured as an input has no effect. reading this register re turns the state of each io pin configured as an edge pin irrespective of whether it is conf igured as an input or output. note that output transitions across multiple io pins may be slightly staggered. refer to edge section on page 15 . 0: write clears the corresponding bit to a 0. read returns the current state. 1: write sets the corresponding bit to a 1. read returns the current state. bit default description 31:16 0x0000 e[31:16] 0: io pin assigned to edge function and configured as an output is actively driven 1: io pin assigned to edge function and configured as an output is tri-stated bit default description 31:16 0x0000 e[31:16] note that XR22802 open drain outputs have a weak internal pull-up. 0: io pin assigned to edge function and configured as an output is a push-pull output 1: io pin assigned to edge function and configured as an output is an open drain output bit default description 31:16 0xffff e[31:16] 0: disable internal pull-up resistor on io pin assigned to edge function and configured as an input 1: enable internal pull-up resistor on io pin assigned to edge function and configured as an input bit default description 31:16 0x0000 e[31:16] 0: disable internal pull-down resistor on io pin a ssigned to edge function and configured as an input 1: enable internal pull-down resistor on io pin assigned to edge function and configured as an input
? 2015 exar corporation XR22802 42 / 46 exar.com/XR22802 rev 1b edge_intr_mask_1 (0x3d5) - read/write edge_intr_pos_edge_1 (0x3d6) - read/write edge_intr_neg_edge_1 (0x3d7) - read/write edge_pwm0_ctrl (0x3d8) - read/write bit default description 31:16 0x0000 e[31:16] writing a 1 in this register enables an input pin for the corresponding bit position edge io pin(s) configured as an input to generate an interrupt if either edge_i ntr_pos_edge and / or edge _intr_neg_edge regis- ters has also been enabled. an edge pin configured as an output has no effect. 0: io pin will not generate an interrupt 1: io pin assigned to edge function and configured as an input will generate an interrupt bit default description 31:16 0xffff e[31:16] writing a 1 in this register enables an interrupt to be generated on the rising edge of the corresponding bit posi- tion edge io pin(s) configured as an input if the edge _intr_mask register is enabled for that pin. if the edge_intr_neg_edge register is also enabled, inte rrupts will be generated on both edges. writing to an edge pin configured as an output has no effect. 0: io pin will not generate an interrupt on rising edge 1: io pin assigned to edge function and configured as an input will generate an interrupt on rising edge if cor- responding edge_intr_mask bit is set bit default description 31:16 0xffff e[31:16] writing a 1 in this register enables an interrupt to be generated on the falling edge of the corresponding bit position edge io pin(s) configured as an input if the edge _intr_mask register is enabled for that pin. if the edge_intr_pos_edge register is also enabled, interr upts will be generated on both edges. writing to an edge pin configured as an output has no effect. 0: io pin will not generate an interrupt on falling edge 1: io pin assigned to edge function and configured as an input will generate an interrupt on falling edge if cor- responding edge_intr_mask bit is set bit default description 15:9 0x00 reserved these bits are reserved and should be written as 0.
? 2015 exar corporation XR22802 43 / 46 exar.com/XR22802 rev 1b edge_pwm0_high (0x3d9) - read/write edge_pwm0_low (0x3da) - read/write 8:6 0x0 cmd 000: idle. output pin remains at same state 001: undefined, do not use 010: undefined, do not use 011: undefined, do not use 100: assert logic 0 101: one-shot -if previous state was assert 0, one-shot pulse will be high, if previous state was assert 1, one- shot pulse will be low 110: free run output 111: assert logic 0 50 enable 0: pwm0 output is not enabled 1: pwm0 output is enabled on pin specified in pin field using mode specified in cmd field 4:0 0x00 pin specifies which pin (e31 - e0) will be assigned to pwm0 output. bit default description 15:12 0x0 reserved these bits are reserved and should be written as 0. 11:0 0x001 value this register specifies the high period for pwm0 in increments of 266.667ns. high period must be in the range of 1 to 4095 (266.667 ns to 1.092 ms) bit default description 15:12 0x0 reserved these bits are reserved and should be written as 0. 11:0 0x001 value this register specifies the low period for pwm0 in increments of 266.667ns. low period must be in the range of 1 to 4095 (266.667 ns to 1.092 ms) bit default description
? 2015 exar corporation XR22802 44 / 46 exar.com/XR22802 rev 1b edge_pwm1_ctrl (0x3db) - read/write edge_pwm1_high (0x3dc) - read/write edge_pwm1_low (0x3dd) - read/write bit default description 15:9 0x00 reserved these bits are reserved and should be written as 0. 8:6 0x0 cmd 000: idle. output pin remains at same state 001: undefined, do not use 010: undefined, do not use 011: undefined, do not use 100: assert logic 0 101: one-shot -if previous state was assert 0, one-shot pulse will be high, if previous state was assert 1, one- shot pulse will be low 110: free run output 111: assert logic 0 4:0 0x00 pin specifies which pin (e31 - e0) will be assigned to pwm1 output. bit default description 15:12 0x0 reserved these bits are reserved and should be written as 0. 11:0 0x001 value this register specifies the high period for pwm1 in increments of 266.667ns. high period must be in the range of 1 to 4095 (266.667 ns to 1.092 ms) bit default description 15:12 0x0 reserved these bits are reserved and should be written as 0. 11:0 0x001 value this register specifies the low period for pwm1 in increments of 266.667ns. low period must be in the range of 1 to 4095 (266.667 ns to 1.092 ms)
? 2015 exar corporation XR22802 45 / 46 exar.com/XR22802 rev 1b mechanical dimensions 56-pin qfn ? ?
? 2015 exar corporation XR22802 46 / 46 exar.com/XR22802 rev 1b notice exar corporation reserves the right to make changes to the produc ts contained in this publication in order to improve design, p erformance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no re sponsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its product s in life support applications where the failure or malfunctio n of the product can reasonably be expected to cause failure of the life support system or to significantly af fect its safety or effectiveness. products are not authorized fo r use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user as sumes all such risks; (c) potential liability of exar cor- poration is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. for further assistance: technical support: techsupport.exar.com technical documentation: www.exar.com/techdoc exar corporation headquarters and sales offices 48720 kato road tel.: +1 (510) 668-7000 fremont, ca 95438 - usa fax: +1 (510) 668-7001 ordering information revision history part number package green operating temperature range packaging quantity marking XR22802il56-f 56-pin qfn yes -40c to +85c 260 / tray XR22802 XR22802il56tr-f 56-pin qfn yes -40c to +85c 2500 / reel XR22802 revision date description 1a july 2014 initial release 1b april 2015 corrected vbus_sense pin definition and ta b l e 1 hub pid. corrected request values for cdc_acm_if and added 3 cdc_ecm_if commands to ta bl e 4 usb commands. added descriptions of feature and input and output reports for hid functions. added hid register access feature reports. [ ecn ? 1518 \ 03 ? apr ? 28 ? 2015]

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