View TMP91C829FG_8588899.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

toshiba original cmos 16-bit microcontroller tlcs-900/l1 series tmp91c829 semiconductor company
preface thank you very much for making us e of toshiba microcomputer lsis. before use this lsi, refer the section, ?points of note and restrictions?. especially, take care below cautions. ** caution ** how to release the halt mode usually, interrupts can release all halts status. however, the interrupts = ( nmi , int0 to int4), which can release the ha lt mode may not be able to do so if they are input during the period cpu is shifting to the halt mode (for about 5 clocks of f fph ) with idle1 or stop mode (idle2 is not applicable to this case). (in this case, an interrupt request is kept on hold internally.) if another interrupt is generated after it has shifted to halt mode completely, halt status can be released without difficultly. the priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first fo llowed by the other interrupt.
tmp91c829 91c829-1 2006-03-15 cmos 16-bit microcontroller TMP91C829FG 1. outline and features tmp91c829 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment.with 2 kbytes of boot rom included, it allows your programs to be erased and rewritten on board. TMP91C829FG comes in a 100-pin flat package. listed below are the features. (1) high-speed 16-bit cpu (900/l1 cpu) ? instruction mnemonics are upward compatible with tlcs-90/900 ? 16 mbytes of linear address space ? general-purpose registers and register banks ? 16-bit multiplication and division instructions; bit transfer and arithmetic instructions ? micro dma: 4 channels (444 ns/2 bytes at 36 mhz) (2) minimum instruction execution time: 111 ns (at 36 mhz) (3) built-in ram: 8 kbytes built-in rom: none built-in boot rom: 2 kbytes
tmp91c829 91c829-2 2006-03-15 (4) external memory expansion ? expandable up to 16 mbytes (shared program/data area) ? can simultaneously support 8-/16-bit width external data bus ? dynamic data bus sizing (5) 8-bit timers: 6 channels (6) 16-bit timer/event counter: 1 channel (7) serial bus interface: 2 channels (8) 10-bit ad converter: 8 channels (9) watchdog timer (10) chip select/wait controller: 4 blocks (11) interrupts: 35 interrupts ? 9 cpu interrupts: software interrupt instruction and illegal instruction ? 19 internal interrupts: 7 priority levels are selectable ? 7 external interrupts: 7 priority levels are selectable (level mode, rising edge mode and falling edge mode are selectable.) (12) input/output ports: 46 pins (except data bus (8bit), address bus (16bit) and rd pin) (13) standby function three halt modes: idle2 (programmable), idle1, stop (14) operating voltage ? vcc (5 v) = 4.75 v to 5.25 v (fc max = 36 mhz) ? vcc (3 v) = 3.0 v to 3.6 v (fc max = 36 mhz) (15) package ? 100-pin qfp: p-lqfp100-1414-0.50f power on and power off the supply power on and power off of the supply require the simu ltaneous execution of the 5 v power supply and 3.3 v power supply. if the both power supplies cannot be turned on or off simultaneously, turn on or off each power supply within the specifications shown in figure 3. 1.2 and 3.1.2 ?power on and power off of the supply?. when power on and power off of the supply is performed on eigher of them, overlap current may run into the internal logic. leaving overlap current running results in increase of power dissipation and short lsi life. please avoid leaving either of power supplies on.
tmp91c829 91c829-3 2006-03-15 ( ): initial function after reset figure 1.1 tmp91c829 block diagram adtrg (an3/pa3) an0 to an7 (pa0 to pa7) vrefh vrefl avcc avss rd wr pz2 ( hwr ) pz3 txd0 (p80) rxd0 (p81) sclk0/ cts0 (p82) 0sts (p83) txd1 (p84) rxd1 (p85) sck1/ 1cts (p86) 1sts (p87) ta0in/int1 (p70) ta1out (p71) ta3out/int2 (p72) ta4in/int3 (p73) ta5out (p74) int4 (p75) lvcc 3v hvcc 5v vss boot a m0/am1 reset x1 x2 emu0 emu1 (p10 to p17) d8 to d15 (p20 to p27) a16 to a23 d0 to d7 a 0 to a7 a 8 to a15 busrq (p53) busak (p54) wait (p55) cs0 (p60) cs1 (p61) cs2 (p62) 3cs (p63) nmi int0 (p56) tb0in0 (p93) tb0in1 (p94) tb0out0 (p95) tb0out1 (p96) int5 (p90) 10-bit 8-ch ad converter port a 8-bit timer (timer 0) port z 8-bit timer (timer 1) 8-bit timer (timer 2) 8-bit timer (timer 3) serial i/o (channel 0) osc clock gear port 1 cs/wait controller (4 blocks) address bus interrupt controller 16-bit timer (tmrb0) data bus port 9 8-kbyte ram watchdog timer (wdt) xwa xbc xde xhl xix xiy xiz xsp w a b c d e h l ix iy iz sp 32 bits sr pc f f cpu ( tlcs-900l1 ) port 2 2-kbyte boot rom port 5 serial i/o (channel 1) port 8 8-bit timer (timer 4) 8-bit timer (timer 5) port 7
tmp91c829 91c829-4 2006-03-15 2. pin assignment and pin functions the assignment of input/output pins for the TMP91C829FG, their names and functions are as follows: 2.1 pin assignment diagram figure 2.1.1 shows the pin assignment of the TMP91C829FG. pin pin no. pin name pin name no. 63 hvcc (5 v) p27/a23 64 62 boot p26/a22 65 61 vss p25/a21 66 60 p17/d15 p24/a20 67 59 p16/d14 p23/a19 68 58 p15/d13 p22/a18 69 57 p14/d12 p21/a17 70 56 p13/d11 p20/a16 71 55 p12/d10 a15 72 54 p11/d9 a14 73 53 p10/d8 a13 74 52 d7 a12 75 51 d6 a11 76 50 d5 a10 77 49 d4 a9 78 48 d3 a8 79 47 d2 a7 80 46 d1 a6 81 45 d0 a5 82 44 p96/tb0out1 a4 83 43 p95/tb0out0 a3 84 42 p94/tb0in1 a2 85 41 p93/tb0in0 a1 86 40 p90/int5 a0 87 39 p75/int4 rd 88 38 p74/ta5out wr 89 37 p73/ta4in/int3 lvcc (3 v) 90 36 p72/ta3out/int2 pz2/ hwr 91 35 p71/ta1out vss 92 34 p70/ta0in/int1 pa0/an0 93 33 reset pa1/an1 94 32 am1 pa2/an2 95 31 x1 adtrg / pa3/an3 96 30 dvss pa4/an4 97 29 x2 pa5/an5 98 28 lvcc (oscillator) pa6/an6 99 27 am0 pa7/an7 100 26 p63/ cs3 vrefh 1 25 p62/ cs2 vrefl 2 24 p61/ cs1 avss 3 23 p60/ cs0 avcc 4 22 emu1 nmi 5 21 emu0 vss 6 20 p87/ sts1 p53/ busrq 7 19 p86/sclk0/ cts1 hvcc (5 v) 8 18 p85/rxd1 p54/ busak 9 17 p84/txd1 p55/ wait 10 16 p83/ sts0 p56/int0 11 15 p82/sclk0/ cts0 pz3 12 14 p81/rxd0 p80/txd0 13 figure 2.1.1 pin assignment diagram (100-pin lqfp) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p-lqfp100-1414-0.50f TMP91C829FG top view
tmp91c829 91c829-5 2006-03-15 2.2 pin names and functions the names of the input/output pins and their functions are described below. table 2.2.1 pin names and functions (1/3) pin name number of pins i/o functions d0 to d7 8 i/o data (lower): bits 0 to 7 of data bus p10 to p17 d8 to d15 8 i/o i/o port 1: i/o port that allows i/o to be selected at the bit level (when used to the external 8-bit bus) data (upper): bits 8 to15 of data bus p20 to p27 a16 to a23 8 output output port 2: output port address: bits 16 to 23 of address bus a8 to a15 8 output address: bits 8 to 15 of address bus a0 to a7 8 output address: bits 0 to 7 of address bus rd 1 output read: strobe signal for reading external memory wr 1 output write: strobe signal for writing data to pins d0 to d7 p53 busrq 1 i/o input port 53: i/o port (with pull-up resistor) bus request: signal used to reques t bus release (high impedance) p54 busak 1 i/o output port 54: i/o port (with pull-up resistor) bus acknowledge: signal used to acknowledge bus release (high impedance) p55 wait 1 i/o input port 55: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait. p56 int0 1 i/o input port 56: i/o port (with pull-up resistor) interrupt request pin0: interrupt reques t pin with programmable level/rising edge/falling edge p60 cs0 1 output output port 60: output port chip select 0: outputs 0 when address is within specified address area p61 cs1 1 output output port 61: output port chip select 1: outputs 0 when address is within specified address area p62 cs2 1 output output port 62: output port chip select 2: outputs 0 when address is within specified address area p63 3cs 1 output output port 63: output port chip select 3: outputs 0 when address is within specified address area p70 ta0in int1 1 i/o input input port 70: i/o port timer a0 input interrupt request pin2: interrupt reques t pin with programmable level/rising edge/falling edge p71 ta1out 1 i/o output port 71: i/o port timer a0 or timer a1 output p72 ta3out int2 1 i/o output input port 72: i/o port timer a2 or timer a3 output interrupt request pin2: interrupt reques t pin with programmable level/rising edge/falling edge
tmp91c829 91c829-6 2006-03-15 table 2.2.2 pin names and functions (2/3) pin name number of pins i/o functions p73 ta4in int3 1 i/o input input port 73: i/o port timer a4 input interrupt request pin 3: interrupt reques t pin with programmable level/rising edge/falling edge p74 ta5out 1 i/o output port 74: i/o port timer a4 or timer a5 output p75 int4 1 i/o input port 75: i/o port interrupt request pin 4: interrupt request pin with programmable p80 txd0 1 i/o output port 80: i/o port (with pull-up resistor) serial send data 0: programmable open-drain output pin p81 rxd0 1 i/o input port 81: i/o port (with pull-up resistor) serial receive data 0 p82 sclk0 cts0 1 i/o input i/o port 82: i/o port: (with pull-up resistor) serial clock i/o 0 serial data send enable 0 (clear to send) p83 0sts 1 i/o port 83: i/o port (with pull-up resistor) serial data request signal 0 p84 txd1 1 i/o output port 84: i/o port (with pull-up resistor) serial send data 0: programmable open-drain output pin p85 rxd1 1 i/o input port 85: i/o port (with pull-up resistor) serial receive data 1 p86 sclk1 cts1 1 i/o input i/o port 86: i/o port: (with pull-up resistor) serial clock i/o 1 serial data send enable 1 (clear to send) p87 1sts 1 i/o port 87: i/o port (with pull-up resistor) serial data request signal 1 p90 int5 1 i/o input port 90: i/o port interrupt request pin 5: interrupt reques t pin with programmable level/rising edge/falling edge p93 tb0in0 1 i/o input port 93: i/o port timer b0 input 0 p94 tb0in1 1 i/o input port 94: i/o port timer b0 input 1 p95 tb0out0 1 i/o output port 95: i/o port timer b0 output 0 p96 tb0out1 1 i/o output port 96: i/o port timer b0 output 1 pa0 to pa7 an0 to an7 adtrg 8 input input input port a0 to a7: pin used to input port analog input 0 to 7: pins us ed to input to ad converter a/d trigger: signal used to request ad start (pa3) pz2 hwr 1 i/o output port z2: i/o port (with pull-up resistor) high write: strobe signal for writing data to pins d8 to d15 pz3 1 i/o port z3: i/o port (with pull-up resistor)
tmp91c829 91c829-7 2006-03-15 table 2.2.3 pin names and functions (3/3) pin name number of pins i/o functions boot 1 input this pin sets boot mode (with pull-up resistor) nmi 1 input non-maskable interrupt request pin: interrupt request pin with programmable falling edge level or with both edge levels programmable am0 to am1 2 input address mode : external data bus with select pin when external 16-bit bus is fixed or ex ternal 8- or 16-bit buses are mixed, am1 = 0 , am0 = 1 when external 8-bit bus is fixed, am1 = 0 , am0 = 0 reset 1 input reset: initializes tmp91c829 (with pull-up resistor) vrefh 1 input pin for reference voltage input to ad converter (h) vrefl 1 input pin for reference voltage input to ad converter (l) avcc 1 i/o power supply pin for ad converter avss 1 gnd supply pin for ad converter x1/x2 2 oscillator connection pins hvcc 2 power supply pins (5 v) lvcc 2 power supply pins (3 v) dvss 3 gnd pins (0 v) emu0 1 output open pin emu1 1 output open pin note 1: an external dma controller cannot access t he device?s built-in memory or built-in i/o devices using the busrq and busak signal. note 2: all pins which have a built-in pull-up resistor (other than the reset pin and the boot pin ) can be disconnected from the resistor in software.
tmp91c829 2006-03-15 91c829-8 3. operation this section describes the bas ic components, functions and operation of the tmp91c829. notes and restrictions which apply to the various items described here are outlined in section 7. ?points to note and restrictions? at the end of this databook. 3.1 cpu the tmp91c829 incorporates a high-perform ance 16-bit cpu (the 900/l1 cpu). for a description of this cpu?s operatio n, please refer to the section of this databook which describes the tlcs-900/l1 cpu. the following sub sections des cribe functions peculiar to the cpu used in the tmp91c829; these functions are not covered in the section devoted to the tlcs-900/l1 cpu. 3.1.1 reset when resetting the tmp91c829 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then set the reset input to low level at least for 10 system clocks (8.89 s at 36 mhz). thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then hold the reset input to low-level at least for 10 system clocks. clock gear is intitialized 1/16 mode by reset operation. it means that the system clock mode f sys is set to fc/32 ( = fc/16 1/2). when the reset is accept, the cpu: ? sets the program counter (pc) as follows in accordance with the reset vector stored at address ffff00h to ffff02h: pc<0:7> data in location ffff00h pc<8:15> data in location ffff01h pc<16:23> data in location ffff02h ? sets the stack pointer (xsp) to 100h. ? sets bits of the status register (sr) to 111. (thereby setting the interrupt level mask register to level 7.) ? sets the bit of the status register to 1 (max mode). (note: as this product does not support min mode, do not write a 0 to the bit.) ? clears bits of the status register to 000. (thereby selecting register bank 0.) when the reset is cleared, the cpu starts executing instructions according to the program counter settings. cpu internal regi sters not mentioned above do not change when the reset is cleared. when the reset is accepted, the cpu sets internal i/o, ports and ot her pins as follows. ? initializes the internal i/o registers. ? sets the port pins, including the pins that also act as internal i/o, to general-purpose input or output port mode. note: the cpu internal register (except to pc, sr, xsp) and internal ram data do not change by resetting. figure 3.1.1 shows the timing of a reset for the tmp91c829.
tmp91c829 2006-03-15 91c829-9 read write f fph a23 to a0 data-in d0 to d15 d0 to d15 sampling (after reset released, starting 2 waits read cycle) pull up (internal) high-z sampling 0ffff00h data-in d ata-in cs0 , cs1 , cs3 (pz2 input mode) reset cs2 rd w r hw r figure 3.1.1 tmp91c829 reset timing example
tmp91c829 2006-03-15 91c829-10 3.1.2 power on and power off of the supply figure 3.1.2 power supply on/off timing 3.2 outline of operation modes there are multi chip and multi boot modes. which mode is selected depends on the device?s pin state after a reset. ? multi chip mode: the device normally operations in this mode. after a reset, the device starts executing the external memory program. ? multi boot mode: this mode is used to rewrite the external flash memory by serial transfer (uart) or atapi transfer. after a reset, internal boot program starts up, executing a on-board rewrite program. table 3.2.1 operation mode setup table mode setup input pin operation mode reset boot multi chip mode h multi boot mode l vcc 5 vcc 3.3 max 1 [s] min 10 [ms] min 0 [s] max 1 [s] reset oscillator operation time + clock doubler stabilization time
tmp91c829 2006-03-15 91c829-11 3.3 memory map figure 3.3.1 is a memory map of the tmp91c829. multi chip mode multi boot mode 000000h 000100h internal i/o (4 kbytes) 000000h 000100h internal i/o (4 kbytes) direct area (n) 001000h internal ram (8 kbytes) 001000h internal ram (8 kbytes) 003000h external memory 003000h 01f800h 16-mbyte area 01ffffh internal boot rom (2 kbytes) (r32) ( ? r32) external memory external memory (r32 + ) (r32 + d8/16) (r32 + r8/16) (nnn) fff800h fffeffh internal boot rom (2 kbytes) ffff00h ffffffh vector table (256 bytes) ffff00h ffffffh vector table (256 bytes) ( = internal area) figure 3.3.1 tmp91c829 memory map
tmp91c829 2006-03-15 91c829-12 3.4 triple clock function and standby function the tmp91c829 contains (1) a clock gearing system, (2) a standby controller, and (3) a noise-reducing circuit. it is used for low-power, lo w-noise systems. the clock operating mode is as follows: (a) single clock mode (x1, x2 pins only). figure 3.4.1 shows a transition figure. reset (f osch /32) release reset instruction interrupt stop mode (stops all circuits) normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) clock mode transition figure instruction instruction interrupt interrupt figure 3.4.1 system clock block diagram the clock frequency input from the x1 and x2 pins is called fc. in case of tmp91c829, fc = f fph . the system clock f sys is defined as the divided clock of f fph , and one cycle of f sys is regarded as one state.
tmp91c829 2006-03-15 91c829-13 3.4.1 block diagram of system clock f osch fc/8 f fph clock gear tmra01 to tmra45 syscr0 warm-up timer (high-frequency oscillator) syscr0 syscr2 x1 x2 2 16 4 fc/16 fc/4 fc/2 fc syscr1 2 4 fc/16 f fph f sys 2 f sys cpu rom ram interrupt controller wdt i/o ports prescaler t0 tmrb0 sio0, sio1 t0 t high-frequency oscillator 8 prescaler prescaler figure 3.4.2 block diag ram of system clock
tmp91c829 2006-03-15 91c829-14 3.4.2 sfrs 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? wuef prck1 prck0 syscr0 (00e0h) read/write r/w after reset 1 0 1 0 0 0 0 0 function always write ?1?. always write ?0?. always write ?1?. always write ?0?. always write ?0?. warm-up timer write 0: don?t care write 1: start timer read 0: end warm-up read 1: do not end warm-up select prescaler clock 00: f fph 01: reserved 10: fc/16 11: reserved 7 6 5 4 3 2 1 0 bit symbol ? gear2 gear1 gear0 syscr1 (00e1h) read/write r/w after reset 0 0 0 0 function always write ?0?. select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (reserved) 110: (reserved) 111: (reserved) 7 6 5 4 3 2 1 0 bit symbol ? wuptm1 wuptm0 haltm1 haltm0 drve syscr2 (00e2h) read/write r/w r/w r/w r/w r/w r/w after reset 0 1 0 1 1 0 function always write ?0?. warm-up timer 00: reserved 01: 2 8 inputted frequency 10: 2 14 inputted frequency 11: 2 16 inputted frequency halt mode 00: reserved 01: stop mode 10: idle1 mode 11: idle2 mode 1: drive the pin during stop mode figure 3.4.3 sfr for system clock
tmp91c829 2006-03-15 91c829-15 7 6 5 4 3 2 1 0 bit symbol protect ? ? ? ? extin ? ? emccr0 (00e3h) read/write r r/w r/w r/w r/w r/w r/w r/w after reset 0 0 1 0 0 0 1 1 function protect flag 0: off 1: on always write ?0?. always write ?1?. always write ?0?. always write ?0?. 1: external clock always write ?1?. always write ?1?. bit symbol read/write after reset emccr1 (00e4h) function writing 1fh turns protections off. writing any value other than 1fh turns protection on. figure 3.4.4 sfr for noise reducing
tmp91c829 2006-03-15 91c829-16 3.4.3 system clock controller the system clock controller gene rates the system clock signal (f sys ) for the cpu core and internal i/o. it contains a clock gear circuit for high-frequency (fc) operation. the register syscr1 sets the high-freq uency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). these functions can reduce the power consumption of the equipment in which the device is installed. the initialization = 100 will cause the system clock (f sys ) to be set to fc/32 (fc/16 1/2) after a reset. for example, f sys is set to 1.125 mhz when the 36 mhz oscillator is connected to the x1 and x2 pins. clock gear controller the f fph is set according to the contents of the clock gear select register syscr1 to either fc, fc/2, fc/4, fc/8, or fc /16. using the clock gear to select a lower value of f fph reduces power consumption. example: changing to a high-frequency gear syscr1 equ 00e1h ld (syscr1), xxxx0000b ; changes f sys to fc/2. x: don?t care (changing to high-frequency clock gear) to change the clock gear, write the appropriate value to the syscr1 register. the value of f fph will not change until a period of time equal to the warm-up time has elapsed from the point at which the register is written to. there is a possibility that the instruction immediately following the instruction which changes the clock gear will be executed before the new clock setting comes into effect. to ensure that this does not happen, insert a dummy instruction (to execute a write cycle) as follows: example: syscr1 equ 00e1h ld (syscr1), xxxx0001b ; changes f sys to fc/4. ld (dummy), 00h ; dummy instruction. instruction to be executed after clock gear has changed.
tmp91c829 2006-03-15 91c829-17 3.4.4 prescaler clock controller for the internal i/o (tmra01:45, tmrb0 and sio0, sio1), there is a prescaler which can divide the clock. the t clock input to the prescaler is either the clock f fph divided by 2 or the clock fc/16 divided by 2. the setting of the syscr0 register determines which clock signal is input. the t0 clock input to the prescaler is either the clock f fph divided by 4 or the clock fc/16 divided by 4. the setting of the syscr0 register determines which clock signal is input. 3.4.5 noise reduction circuits noise reduction circuits are built in, allowing implementation of the following features. (1) single drive for high-frequency oscillator (2) protection of register contents the above functions are performed by making the appropriate settings in the emccr0 and emccr1 registers. (1) single drive for high-frequency oscillator (purpose) not need twin drive and protect mistake operation by inputted noise to x2 pin when the external oscillator is used. (block diagram) x1 pin x2 pin enable oscillation f osch (stop + emccr0) (setting method) when a 1 is written to the emccr0, the oscillator is disabled and is operated as a buffer. the x2 pin always outputs a 1. is initialized to 0 by a reset. note: do not write emccr0 = ?1? when using external resonator.
tmp91c829 2006-03-15 91c829-18 (2) protection of register contents (purpose) an item for mistake operation by inputted noise. to execute the program certainty which is occurred mistake operation, the protect-register can be disabled write operation for the specific sfr. write disabled sfrs 1. cs/wait controller b0cs, b1cs, b2cs, b3cs, bexcs, msar0, msar1, msar2, msar3, mamr0, mamr1, mamr2, mamr3 2. clock gear (only emccr1 can be written to.) syscr0, syscr1, syscr2, emccr0 (block diagram) protect register emccr0 to emccr1 write value other than 1fh write 1fh s q r write signal to the disabled sfr write signal to the other sfr write signal sf r (setting method) writing any value other than 1fh to the emccr1 register turns on protection, thereby preventing the cpu from writing to the specific sfr. writing 1fh to emccr1 turns off protection. the protection status is set in emccr0. resetting initializes the protection status to off.
tmp91c829 2006-03-15 91c829-19 3.4.6 standby controller (1) halt modes when the halt instruction is executed, the operating mode switches to idle2, idle1 or stop mode, depending on the contents of the syscr2 register. the subsequent actions performed in each mode are as follows: a. idle2: the cpu only is halted. in idle2 mode internal i/o operations can be performed by setting the following registers. table 3.4.1 shows the registers of setting operation during idle2 mode. table 3.4.1 the registers of setting operation during idle2 mode internal i/o sfr tmra01 ta01run tmra23 ta23run tmra45 ta45run tmrb0 tb0run sio0 sc0mod1 sio1 sc1mod1 ad converter admod1 wdt wdmod b. idle1: only the oscillator to operate. c. stop: all internal circuits stop operating. the operation of each of the different halt modes is described in table 3.4.2. table 3.4.2 i/o operation during halt modes halt mode idle2 idle1 stop syscr2 11 10 01 cpu stop i/o ports maintain same state as when halt instruction was executed. see table 3.4.5, table 3.4.6 tmra, tmrb sio ad converter wdt can be selected block interrupt controller operational stopped
tmp91c829 2006-03-15 91c829-20 (2) how to clear a halt mode the halt state can be cleared by a reset or by an interrupt request. the combination of the value in of the interrupt mask register and the current halt mode determine in which ways the halt mode may be cleared. the details associated with each type of halt state clearance are shown in table 3.4.3. ? clearance by interrupt request whether or not the halt mode is cleared and subsequent operation depends on the status of the generated interrupt. if the interrupt request level set before execution of the halt instruction is greater than or equal to the value in the interrupt mask register, the following sequence takes place: the halt mode is cleared, the interrupt is then processed, and the cpu then resumes execution starting from the instruction following the halt instruction. if the interrupt request level set before execution of the halt instruction is less than the value in the interrupt mask register, the halt mode is not cleared. (if a non-maskable interrupt is generated, the halt mode is cleared and the interrupt processed, regardless of the value in the interrupt mask register.) however, for int0 to int4 only, even if the interrupt request level set before execution of the halt instruction is less than the value in the interrupt mask register, the halt mode is cleared. in th is case, the interrupt is not processed and the cpu resumes execution starting from the instruction following the halt instruction. the interrupt request flag remains set to 1. note: usually, interrupts can release all halts status. however, the interrupts ( nmi , int0 to int4) which can release the halt mode may not be able to do so if they are input during the period cpu is shifting to the halt mode (for about 5 clocks of f fph ) with idle1 or stop mode (idle2 is not applicable to this case). (in this case, an interrupt request is kept on hold internally.) if another interrupt is generated after it has shifted to halt mode completely, halt status can be released without difficulty. the priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. ? clearance by reset any halt state can be cleared by a reset. when stop mode is cleared by a reset signal, sufficient time (at least 3 ms) must be allowed after the reset for the operation of the oscillator to stabilize. when a halt mode is cleared by resetti ng, the contents of the internal ram remain the same as they were before execution of the halt instruction. however, all other settings are reinitialized. (clearance by an interrupt affects neither the ram contents nor any other settings ? the state which existed before the halt instruction was executed is retained.)
tmp91c829 2006-03-15 91c829-21 table 3.4.3 source of halt state cl earance and halt clearance operation status of received interrupt interrupt enabled (interrupt level) (interrupt mask) interrupt disabled (interrupt level) < (interrupt mask) halt mode idle2 idle1 stop idle2 idle1 stop interrupt nmi intwdt int0 to int4 (note) int5 intta0 to intta5 inttb00, inttb01, inttbof0 intrx0, inttx0 intrx1, inttx1 intad ? ? ? ? ? ? ? ? ? ? ? ? * 1 ? * 1 ? ? ? ? ? ? * 1 source of halt state clearance reset reset initializes the lsi ? : after clearing the halt mode, cpu starts interrupt processing. : after clearing the halt mode, cpu resumes execut ing starting from instruction following the halt instruction. : cannot be used to clear the halt mode. ? : the priority level (interrupt request level) of non- maskable interrupts is fixed to 7, the highest priority level. there is not this combination type. * 1: the halt mode is cleared when the warm-up time has elapsed. note: when the halt mode is cleared by int0 to int4 interrupt of the level mode in the interrupt enabled status, hold the level until starting interrupt processi ng. changing level before holding level, interrupt processing is correctly started. (example: clearing idle1 mode) an int0 interrupt clears the halt stat e when the device is in idle1 mode. address 8200h ld (p5fc), 40h ; sets p56 to int0 8203h ld (iimc0), 00h ; sets int0 interrupt rising edge. 8206h ld (inte0ad), 06h ; sets int0 interrupt level to 6. 8209h ei 5 ; sets interrupt level to 5 for cpu. 820bh ld (syscr2), 28h ; sets halt mode to idle1 mode. 820eh halt ; halts cpu. int0 interrupt routine int0 reti 820fh ld xx, xx
tmp91c829 2006-03-15 91c829-22 (3) operation a. idle2 mode in idle2 mode only specific internal i/o operations, as designated by the idle2 setting register, can take place. instruction execution by the cpu stops. figure 3.4.5 illustrates an example of the timing for clearance of the idle2 mode halt state by an interrupt. x1 a0 to a23 rd wr d0 to d15 data data idle2 mode clearing interrup t figure 3.4.5 timing chart for idle2 mo de halt state cleared by interrupt b. idle1 mode in idle1 mode, only the internal oscillator and the rtc continue to operate. the system clock in the mcu stops. in the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. figure 3.4.6 illustrates the timing for clearance of the idle1 mode halt state by an int errupt. x1 a0 to a23 rd wr clearing interrup t idle1 mode d0 to d15 data data figure 3.4.6 timing chart for idle1 mo de halt state cleared by interrupt
tmp91c829 2006-03-15 91c829-23 c. stop mode when stop mode is selected, all internal circuits stop, including the internal oscillator pin status in stop mode depends on the settings in the syscr2 register. table 3.4.5, table 3.4.6 summarizes the state of these pins in stop mode. after stop mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. see the sample warm-up times in table 3.4.4. figure 3.4.7 illustrates the timing for clearance of the stop mode halt state by an int errupt. interrupt fo r release warm-up time stop mode x1 a0 to a23 rd wr d0 to d15 data data figure 3.4.7 timing chart for stop mo de halt state cleared by interrupt table 3.4.4 sample warm-up times after clearance of stop mode at f osch = 36 mhz syscr2 01 (2 8 ) 10 (2 14 ) 11 (2 16 ) 7.1 s 0.455 ms 1.820 ms
tmp91c829 2006-03-15 91c829-24 table 3.4.5 input buffer state table input buffer state in halt mode (stop) when the cpu is operating in halt mode (idle2/idle1) =1 =0 port name input function name during reset when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port when used as function pin when used as input port ? d0-d7 ? ? ? ? p10-17 d8-d15 off *1 off off off off p53(*6) busrq on on on on on on on off p54(*6) ? off ? *2 ? off ? off ? p55(*6) wait off off p56(*6) int0 on on ta0in *3 p70 int1 on on on on on on on p71 ? ? ? ? ? p72 int2 *2 off off on ta4in *3 p73 int3 on on on on on on on p74 ? ? *2 ? off ? off ? p75 int4 on on on on p80(*6) ? ? ? ? ? p81(*6) rxd0 sclk0 p82(*6) 0cts on on on off p83-p84(*6) ? ? ? ? ? p85(*6) rxd1 sclk1 p86(*6) 1cts on on on off p87(*6) ? ? ? ? ? p90 int5 p93 tb0in0 p94 tb0in1 on on on off p95-p96 ? on ? on ? on ? on ? pa0-pa2(*7) an0-an2 an3 *4 *4 *4 *4 pa3(*7) adtrg on on on on pa4-pa7(*7) an4-an7 *4 *5 *4 *4 *4 pz2-pz3(*6) ? off *2 off off off boot (*6) ? nmi ? reset (*6) ? am0,am1 ? on on x1 ? on ? on ? on ? off ? off on: the buffer is always turned on. a current flows the input buffer if the in put pin is not driven. *1: the buffer is turned on if read external. off: the buffer is always turned off. *2: the buffer is turned on if access port. -: no applicable *3: the buffer is turned off if fc register is ?0?. the buffer is turned on if fc register is ?1?. *4: the buffer is always enable to input. *5: the buffer is turned on if read port. *6: port having a pull-up resistor.(programmable) *7: ain input does not cause a current to flow through the buffer.
tmp91c829 2006-03-15 91c829-25 table 3.4.6 output buffer state table output buffer state in halt mode (stop) when the cpu is operating in halt mode (idle2/idle1) =1 =0 port name output function name during reset when used as function pin when used as output port when used as function pin when used as output port when used as function pin when used as output port when used as function pin when used as output port ? d0-d7 ? ? ? ? p10-p17 d8-d15 ? *1 off off p20-p27 a16-a23 on on on off ? a8-a15 ? a0-a7 ? rd ? wr on on ? on ? on ? off ? p53 ? ? ? ? ? p54 busak on on on off p55-p56 ? ? ? ? ? ? p60 0 cs on p61 1cs p62 2cs p63 3cs on on on on off p70 ? ? ? ? ? p71 ta1out p72 ta3out on on on off p73 ? ? ? ? ? p74 ta5out on on on off p75 ? ? ? ? ? p80 txd0 on on on off p81 ? ? ? ? ? p82 sclk0 p83 0sts p84 txd1 on on on off p85 ? ? ? ? ? p86 sclk1 p87 1sts on on on off p90 ? p93-p94 ? ? ? ? ? p95 tb0out0 on p96 tb0out1 pz2 hwr on on on off pz3 ? ? on off x2 ? on ? on ? on ? *3 ? *3 on: the buffer is always turned on. when the bus is released, however, output buffers for some pins are turned off. *1: the buffer is turned on if write external. off: the buffer is always turned off. *2: port having a pull-up resistor.(programmable) -: no applicable *3: the buffer output high level.
tmp91c829 2006-03-15 91c829-26 3.5 interrupts interrupts are controlled by the cpu interrupt mask register sr and by the built-in interrupt controller. the tmp91c829 has a total of 35 interrupts divided into the following five types: ? interrupts generated by cpu: 9 sources (software interrupts, illegal instruction interrupt) ? interrupts on external pins ( nmi and int0 to int5): 7 sources ? internal i/o interrupts: 19 sources a (fixed) individual interrupt vector number is assigned to each interrupt. one of seven (variable) priority level can be assigned to each maskable interrupt. the priority level of non-maskable interrupt s are fixed at 7 as the highest level. when an interrupt is generated, the interrupt co ntroller sends the piority of that interrupt to the cpu. if multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the cp u. (the highest priority is level 7 using for non-maskable interrupts.) the cpu compares the priority level of the interrupt with the value of the cpu interrupt mask register . if the priority level of the interrupt is higher than the value of the interrupt mask register, the cpu accepts the interrupt. the interrupt mask register value can be updated using the value of the ei instruction (ei num sets data to num). for example, specifying ?ei 3? enables the maskable interrupts which priority level set in the interrupt controller is 3 or higher, and also non-maskable interrupts. operationally, the di instruction ( = 7) is identical to the ei 7 instruction. di instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 0 to 6. the ei instruction is vaild immediately after execution. in addition to the above general-purpose interrupt processing mode, tlcs-900/l1 has a micro dma interrupt processing mode as well. the cpu can transfer the data (1 or 2 or 4 bytes) automatically in micro dma mode, therefore this mode is used for speed up interrupt processing, such as transferring data to the internal or external peripheral i/o. moreover, tmp91c829 has software start f unction for micro dma processing request by the software not by the hardware interrupt. figure 3.5.1 shows the overall interrupt processing flow.
tmp91c829 2006-03-15 91c829-27 count = 0 general-purpose interrupt processing interrupt specified by micro dma start vector? yes interrupt processing push pc push sr sr level of accepted interrupt + 1 intnest intnest + 1 pc (ffff00h + v) interrupt processing program count count ? 1 no yes data transfer by micro dma no micro dma processing reti instruction pop sr pop pc intnest intnest ? 1 clear vector register generating micro dma transfer end interrupt (inttc0 to inttc3) clear interrupt requenst flag interrupt vector value ?v? read interrupt request f/f clear end micro dma soft start request figure 3.5.1 interrupt and micro dma processing sequence
tmp91c829 2006-03-15 91c829-28 3.5.1 general-purpose interrupt processing when the cpu accepts an interrupt, it usually performs the following sequence of operations. that is also the same as tlcs-900/l and tlcs-900/h. (1) the cpu reads the interrupt vector from the interrupt controller. if the same level interrupts occur simultaneo usly, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (the default priority is alre ady fixed for each interrupt: the smaller vector value has the higher priority level.) (2) the cpu pushes the value of program counter (pc) and status register (sr) onto the stack area (indicated by xsp). (3) the cpu sets the value which is the priority level of the accepted interrupt plus 1 ( + 1) to the interrupt mask register . howe ver, if the priority level of the accepted interrupt is 7, the register?s value is set to 7. (4) the cpu increases the interrupt nesting counter intnest by 1 ( + 1). (5) the cpu jumps to the address indicated by the data at address ?ffff00h + interrupt vector? and starts the interrupt processing routine. the above processing time is 18 states (1.0 s at 36 mhz) as the best case (16-bit data bus width and 0 waits). when the cpu completed the interrupt pr ocessing, use the reti instruction to return to the main routine. reti restores the contents of program counter (pc) and status register (sr) from the stack an d decreases the interrupt nesting counter intnest by 1 ( ? 1). non-maskable interrupts ca nnot be disabled by a user program. maskable interrupts, however, can be enabled or dis abled by a user program. a program can set the priority level for each inte rrupt source. (a priority level setting of 0 or 7 will disable an interrupt request.) if an interrupt request which has a priority level equal to or greater than the value of the cpu interrupt mask register comes out, the cpu accepts its interrupt. then, the cpu interrupt mask register is set to the value of the priority level for the accepted interrupt plus 1 ( + 1). therefore, if an interrupt is generated with a higher level than the current interrupt during its processing, the cpu accepts the later interrupt and goes to the nesting status of interrupt processing. moreover, if the cpu receives another interrupt request while performing the said (1) to (5) processing steps of the current interrupt, the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine. specifying di as the start instruction disables maskable interrupt nesting. a reset initializes the interrupt mask register to 111, disabling all maskable interrupts. table 3.5.1 shows the tmp91c829 interrupt vectors and micro dma start vectors. the address ffff00h to ffffffh (256 bytes) is assigned for the interrupt vector area.
tmp91c829 2006-03-15 91c829-29 table 3.5.1 tmp91c829 interrupt ve ctors and micro dma start vectors default priority type interrupt source or source of micro dma request vector value vector reference address micro dma start vector 1 reset or ?swi0? instruction 0000h ffff00h ? 2 ?swi1? instruction 0004h ffff04h ? 3 illegal instruction or ?swi2? instruction 0008h ffff08h ? 4 ?swi3? instruction 000ch ffff0ch ? 5 ?swi4? instruction 0010h ffff10h ? 6 ?swi5? instruction 0014h ffff14h ? 7 ?swi6? instruction 0018h ffff18h ? 8 ?swi7? instruction 001ch ffff1ch ? 9 nmi : nmi pin input 0020h ffff20h ? 10 non-mask able intwd: watchdog timer 0024h ffff24h ? ? micro dma ? ? ? 11 int0: int0 pin input 0028h ffff28h 0ah 12 int1: int1 pin input 002ch ffff2ch 0bh 13 int2: int2 pin input 0030h ffff30h 0ch 14 int3: int3 pin input 0034h ffff34h 0dh 15 int4: int4 pin input 0038h ffff38h 0eh 16 int5: int5 pin input 003ch ffff3ch 0fh 17 (reserved) 0040h ffff40h 10h 18 (reserved) 0044h ffff44h 11h 19 (reserved) 0048h ffff48f 12h 20 intta0: 8-bit timer 0 004ch ffff4ch 13h 21 intta1: 8-bit timer 1 0050h ffff50h 14h 22 intta2: 8-bit timer 2 0054h ffff54h 15h 23 intta3: 8-bit timer 3 0058h ffff58h 16h 24 intta4: 8-bit timer 4 005ch ffff5ch 17h 25 intta5: 8-bit timer 5 0060h ffff60h 18h 26 (reserved) 0064h ffff64h 19h 27 (reserved) 0068h ffff68h 1ah 28 inttb00: 16-bit timer 0 (tb0rg0) 006ch ffff6ch 1bh 29 inttb01: 16-bit timer 0 (tb0rg1) 0070h ffff70h 1ch 30 (reserved) 0074h ffff74h 1dh 31 (reserved) 0078h ffff78h 1eh 32 inttbof0: 16-bit timer 0 (overflow) 007ch ffff7ch 1fh 33 (reserved) 0080h ffff80h 20h 34 intrx0: serial receive (channel 0) 0084h ffff84h 21h 35 inttx0: serial transmission (channel 0) 0088h ffff88h 22h 36 intrx1: serial receive (channel 1) 008ch ffff8ch 23h 37 inttx1: serial transmission (channel 1) 0090h ffff90h 24h 38 (reserved) 0094h ffff94h 25h 39 (reserved) 0098h ffff98h 26h 40 intad: ad conversion end 009ch ffff9ch 27h 41 inttc0: micro dma end (channel 0) 00a0h ffffa0h 28h 42 inttc1: micro dma end (channel 1) 00a4h ffffa4h 29h 43 inttc2: micro dma end (channel 2) 00a8h ffffa8h 2ah 44 inttc3: micro dma end (channel 3) 00ach ffffach 2bh ? to ? maskable (reserved) 00b0h to 00fch ffffb0h to fffffch ? to ?
tmp91c829 2006-03-15 91c829-30 3.5.2 micro dma processing in addition to general-purpose interrupt processing, the tmp91c829 supprots a micro dma function. interrupt requests set by micro dma perform micro dma processing at the highest priority level (level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. the micro dma has 4 channels and is possible continuous transmission by spec ifing the say later burst mode. because the micro dma function has been implemented with the cooperative operation of cpu, when cpu goes to a standby mode by halt instruction, the requirement of micro dma will be ignored (pending). (1) micro dma operation when an interrupt request specified by the micro dma start vector register is generated, the micro dma triggers a micro dma request to the cpu at interrupt priority level 6 and starts processing the requ est in spite of any interrupt source?s level. the micro dma is ignored on = ?7? the 4 micro dma channels allow micro dma processing to be set for up to 4 types of interrupts at any one time. when micro dma is accepted, the interrupt request flip-flop assigned to that channel is cleared. the data are automatically transferred once (1 or 2 or 4 bytes) from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decreased by 1 ( ? 1). if the decreased result is 0, the micro dma transfer end interrupt (inttc0 to inttc3) passes from the cpu to the interrupt controller. in addition, the micro dma start vector register dmanv is cleared to 0, the next micro dma is disabled and micro dma processing completes. if the decreased result is other than 0, the micro dma processing completes if it isn?t specified the say later burst mode. in this case, the micro dma transfer end interrupt (inttc0 to inttc3) aren?t generated. if an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro dma start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. therefore, if only using the interrupt for starting the micro dma (not using the interrupts as a general-purpose interrupt: level 1 to 6), firs t set the interrupts level to 0 (interrupt requests disabled). if using micro dma and general-purpose inte rrupts together, first set the level of the interrupt used to start micro dma processing lower than all the other interrupt levels (note). in this case, the cause of general interrupt is limited to the edge interrupt. the priority of the micro dma transfer end interrupt (inttc0 to inttc3) is defined by the interrupt level and the default priority as same as the other maskable interrupt. note: if the priority level of micro dma is set higher than that of other interrupts, cpu operates as follows. in case intxxx interrupt is generated first and then intyyy interrupt is generated between checking ?interrupt specified by micro dma start vector? (in the figure 3.5.1 ) and reading interrupt vector with setting below . the vector shifts to that of intyyy at the time. this is because the priority level of intyyy is higher than that of intxxx. in the interrupt routine, cpu reads the vector of intyyy because cheking of micro dma has finished. and intyyy is generated regardless of transfer counter of micro dma. intxxx: level 1 without micro dma intyyy: level 6 with micro dma
tmp91c829 2006-03-15 91c829-31 if a micro dma request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. the smaller channel number has the higher priori ty (channel 0 (high) > channel 3 (low)). while the register for setting the transfer source/transfer destin ation addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. accordingly, micro dma can access 16 mbytes (the upper eight bits of the 32 bits are not valid). three micro dma transfer modes are support ed: 1-byte transfer, 2-byte (one word) transfer, and 4-byte transfer. after a transfer in any mode, the transfer source/transfer destination addresses are increased, decreased, or remain unchanged. this simplifies the transfer of data from i/o to memory, from memory to i/o. for details of the transfer modes, see (4) ?detailed description of the transfer mode register?. as the transfer counter is a 16-bit counter, micro dma pr ocessing can be set for up to 65536 times per interrupt source. (the micro dma processing count is maximized when the transfer counter initial value is set to 0000h.) micro dma processing can be started by the 23 interrupts shown in the micro dma start vectors of figure 3.5.1 and by the micro dma soft start, making a total of 24 int errupts. figure 3.5.2 shows the word transfer mi cro dma cyc le in transfer destination address inc mode (except for counter mode, the same as for other modes). (the conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even numbered values.) output input transfer destination address 1 state d0 to d15 x1 a0 to a23 dm1 dm2 dm3 dm4 dm5 dm6 dm7 dm8 (note 1) (note 2) rd wr / hwr transfer source address figure 3.5.2 timing for micro dma cycle states 1 to 3: instruction fetch cycle (gets next address code). if 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. states 4 to 5: micro dma read cycle. state 6: dummy cycle (the address bus remains unchanged from state 5.) states 7 to 8: micro dma write cycle. note 1: if the source address area is an 8- bit bus, it is increased by 2 states. if the source address area is a 16-bit bus and the address starts from an odd number, it is increased by 2 states. note 2: if the destination address area is an 8-bit bus, it is increased by 2 states. if the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by 2 states.
tmp91c829 2006-03-15 91c829-32 (2) soft start function in addition to starting the micro dma function by interrupts, tmp91c829 includes a micro dma software start function that st arts micro dma on the generation of the write cycle to the dmar register. writing 1 to each bit of dmar register causes micro dma once (if write 0 to each bitm micro dma doesn?t operate). at the end of transfer, the corresponding bit of the dmar register is automatically cleared to 0. only one-channel can be set for micro dma at once. (do not write 1 to plural bits.) when writing again 1 to the dmar register, check whether the bit is 0 before writing 1. if read 1, micro dma transfer isn?t started yet. when a burst is specified by dmab register, data is continuously transferred until the value in the micro dma transfer counter is 0 after start up of the micro dma transfer counter doesn?t change. don?t use read-modify ?write instruction to avoid writing to other bits by mistake. symbol name address 7 6 5 4 3 2 1 0 dmar3 dmar2 dmar1 dmar0 r / w 0 0 0 0 dmar dma request register 89h (prohibit rmw) dma request (3) transfer control registers the transfer source address and the tran sfer destination address are set in the following registers. data setting for these registers is done by an ?ldc cr,r? instruction. channel 0 dmas0 dma source address register 0: only use lsb 24 bits. dmad0 dma destination address register 0: only use lsb 24 bits. dmac0 dma counter register 0: 1 to 65536. dmam0 dma mode register 0. channel 3 dmas3 dma source address register 3. dmad3 dma destination address register 3. dmac3 dma counter register 3. dmam3 dma mode register 3. 8 bits 16 bits 32 bits
tmp91c829 2006-03-15 91c829-33 (4) detailed description of the transfer mode register 8 bits 0 0 0 mode number of transfer bytes mode description number of execution states minimum execution time at fc = 36 mhz 000 (fixed) 000 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer transfer destination address inc mode .............. i/o to memory (dmadn + ) (dmasn) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 states 667 ns 001 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer transfer destination address dec mode .............. i/o to memory (dmadn ? ) (dmasn) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 states 667 ns 010 00 byte transfer 8 states 444ns 01 word transfer 10 4-byte transfer transfer source address inc mode .............. memory to i/o (dmadn) (dmasn + ) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 states 667 ns 011 00 byte transfer 8 states 444ns 01 word transfer 10 4-byte transfer transfer source address dec mode .............. memory to i/o (dmadn) (dmasn ? ) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 states 667 ns 100 00 byte transfer 8 states 444 ns 01 word transfer 10 4-byte transfer fixed address mode .............. i/o to i/o (dmadn) (dmasn ? ) dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 12 states 667 ns 101 00 counter mode ............. for c ounting number of times interrupt is generated. dmasn dmasn + 1 dmacn dmacn ? 1 if dmacn = 0, then inttcn is generated. 5 states 278 ns note: when setting a value in this register, write 0 to the upper 3 bits. dmam0 to dmam3 note 1: ?n? is the corresponding micro dma channels 0 to 3. dmadn + /dmasn + : post-increment (increment register value after transfer) dmadn ? /dmasn ? : post-decrement (decrement register value after transfer) the i/os in the table mean fixed address and t he memory means increment (inc) or decrement (dec) addresses. note 2: execution time is under the condition of: 16-bit bus width (both translation and destination address area)/0 waits/ fc = 36 mhz/selected high-frequency mode (fc 1) note 3: do not use an undefined code for the transfer mode register except for the defined codes listed in the above table.
tmp91c829 2006-03-15 91c829-34 3.5.3 interrupt controller operation the block diagram in figure 3.5.3 shows the interrupt circuits. the left-hand side of the diagram shows the int errupt controller ci rcuit. the right-hand side shows the cpu interrupt request signal circuit and the halt release circuit. for each of the 26 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro dma start vector register. the interrupt request flag latches interrupt requests from the peripherals. the flag is cleared to zero in the following cases: ? when reset occurs ? when the cpu reads the channel vector after accepted its interrupt ? when executing an instruction that clears the interrupt (write micro dma start vector to intclr register) ? when the cpu receives a micro dma request (when micro dma is set) ? when the micro dma burst transfer is terminated an interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting re gister (e.g., inte0ad or inte12). 6 interrupt priorities levels (1 to 6) are provided. setting an interrupt source?s priority level to 0 (or 7) disables interrupt requests from that source. the priority of non-maskable interrupts (nmi pin interrupts and watchdog timer interrupts) are fixed at 7. if interrupt request with the same level are generated at the same time, th e default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. the 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. the interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the cpu. the cpu compares the priority value in the status register by the interrupt request signal with the priority value set; if the latter is higher, the interrupt is accepted. then the cpu sets a value higher than the priority value by 1 ( + 1) in the cpu sr . interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. when interrupt processing is completed (after execution of the reti instruction), the cpu restores the priority value saved in the stack before the interrupt was generated to the cpu sr. the interrupt controller also has registers (4 channels) used to store the micro dma start vector. writing the start vector of the interrupt source for the micro dma processing (see table 3.5.1), enables the corresponding interrupt to be processed by micro dma processing. t he values must be set in the micro dma parameter register (e.g., dmas and dmad) prior to the micro dma processing.
tmp91c829 2006-03-15 91c829-35 interrupt request signal to cpu if iff = 7 then 0 micro dma start vector setting register intad inttc0 inttc1 inttc2 inttc3 v = 9ch v = a0h v = a4h v = a8h v = ach soft start micro dma counter 0 interrupt 6 inttc during idle1 26 3 3 3 1 6 1 7 2 2 4 6 34 4 input or int0 to int4 micro dma channel priority encoder priority encoder dma0v dma1v dma2v dma3v reset interrupt request f/f reset decoder reset priority setting register v = 20h v = 24h interrupt controller cpu s q r v = 28h v = 2ch v = 30h v = 34h v = 38h v = 3ch v = 4ch d q clr y1 y2 y3 y4 y5 y6 a b c dn dn + 1 dn + 2 interrupt request f/f interrupt vector read micro dma acknowledge interrupt request flag dn + 3 a b c interrupt vector read d2 d3 d4 d5 d6 d7 selector s q r 0 1 2 3 a b d0 d1 interrupt vector read interrupt mask f/f micro dma request halt release nmi intrq2 to 0 iff2:0 interrupt level detect reset ei1 to 7 di interrupt request signal during stop micro dma channel specification reset nmi intwd int0 int1 int2 int3 int4 int5 intta0 s interrupt vector generator highest priority interrupt level select 1 2 3 4 5 6 7 d5 d4 d3 d2 d1 d0 d q clr if intrq2 to 0 iff 2 to 0 then 1. figure 3.5.3 block diagram of interrupt controller
tmp91c829 2006-03-15 91c829-36 (1) interrupt priority setting registers symbol name address 7 6 5 4 3 2 1 0 intad int0 iadc iadm2 iadm1 iadm0 i0c i0m2 i0m1 i0m0 r r/w r r/w inte0ad inte0 & intad enable 90h 0 0 0 0 0 0 0 0 int2 int1 i2c i2m2 i2m1 i2m0 i1c i1m2 i1m1 i1m0 r r/w r r/w inte12 int1 & int2 enable 91h 0 0 0 0 0 0 0 0 int4 int3 i4c i4m2 i4m1 i4m0 i3c i3m2 i3m1 i3m0 r r/w r r/w inte34 int3 & int4 enable 92h 0 0 0 0 0 0 0 0 int5 i5c i5m2 i5m1 i5m0 r r/w inte5 int5 enable 93h 0 0 0 0 intta1 (tmra1) intta0 (tmra0) ita1c ita1m2 ita1m1 ita1m0 ita0c ita0m2 ita0m1 ita0m0 r r/w r r/w inteta01 intta0 & intta1 enable 95h 0 0 0 0 0 0 0 0 intta3 (tmra3) intta2 (tmra2) ita3c ita3m2 ita3m1 ita3m0 ita2c ita2m2 ita2m1 ita2m0 r r/w r r/w inteta23 intta2 & intta3 enable 96h 0 0 0 0 0 0 0 0 intta5 (tmra5) intta4 (tmra4) ita5c ita5m2 ita5m1 ita5m0 ita4c ita4m2 ita4m1 ita4m0 r r/w r r/w inteta45 intta4 & intta5 enable 97h 0 0 0 0 0 0 0 0 lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests interrupt request flag
tmp91c829 2006-03-15 91c829-37 symbol name address 7 6 5 4 3 2 1 0 inttb01 (tmrb0) inttb00 (tmrb0) itb01c itb01m2 itb01m1 itb01m0 itb00c itb00m2 itb00m1 itb00m0 r r/w r r/w intetb0 interrupt enable tmrb0 99h 0 0 0 0 0 0 0 0 (reserved) inttbof0 (overflow) itf0c itf0m2 itf0m1 itf0m0 r r/w intetb0v interrupt enable tmrb0v (overflow) 9bh 0 0 0 0 inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 r r/w r r/w intes0 interrupt enable serial 0 9ch 0 0 0 0 0 0 0 0 inttx1 intrx1 itx1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 r r/w r r/w intes1 interrupt enable serial 1 9dh 0 0 0 0 0 0 0 0 inttc1 inttc0 itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 r r/w r r/w intetc01 inttc0 & inttc1 enable a0h 0 0 0 0 0 0 0 0 inttc3 inttc2 itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 r r/w r r/w intetc23 inttc2 & inttc3 enable a1h 0 0 0 0 0 0 0 0 lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests interrupt request flag
tmp91c829 2006-03-15 91c829-38 (2) external interrupt control symbol name address 7 6 5 4 3 2 1 0 ? i2edge i2le i1dge i1le i0edge i0le nmiree w 0 0 0 0 0 0 0 0 iimc0 interrupt input mode control 0 8ch (prohibit rmw) write ?0?. int2edge 0: rising 1: falling int2edge 0: edge 1: level int1edge 0: rising 1: falling int1edge 0: edge 1: level int0edge 0: rising 1: falling int0 0: edge 1: level 1: operates even on rising + falling edge of nmi int2 level enable 0 edge detect int 1 h level int int1 level enable 0 edge detect int 1 h level int int0 level enable 0 edge detect int 1 h level int nmi rising edge enable 0 int request generat ion at falling edge 1 int request gen eration at rising/falling edge symbol name address 7 6 5 4 3 2 1 0 i5edge i5le i4edge i4le i3edge i3le w 0 0 0 0 0 0 iimc1 interrupt input mode control1 8dh (prohibit rmw) int5edge 0: rising 1: falling int5 0: edge 1: level int4edge 0: rising 1: falling int4 0: edge 1: level int3edge 0: rising 1: falling int3 0: edge 1: level int5 level enable 0 edge detect int 1 h level int int4 level enable 0 edge detect int 1 h level int int3 level enable 0 edge detect int 1 h level int when switching iimc0 and iimc1 register s, first every fc registers in port which built-in int function set to 0.
tmp91c829 2006-03-15 91c829-39 setting functions on external interrupt pins interrupt pin mode setting method falling edge = 0 nmi both falling and rising edges = 1 rising edge = 0, = 0 falling edge = 0, = 1 high level = 1, = 0 int0 low level = 1, = 1 rising edge = 0, = 0 falling edge = 0, = 1 high level = 1, = 0 int1 low level = 1, = 1 rising edge = 0, = 0 falling edge = 0, = 1 high level = 1, = 0 int2 low level = 1, = 1 rising edge = 0, = 0 falling edge = 0, = 1 high level = 1, = 0 int3 low level = 1, = 1 rising edge = 0, = 0 falling edge = 0, = 1 high level = 1, = 0 int4 low level = 1, = 1 rising edge = 0, = 0 falling edge = 0, = 1 high level = 1, = 0 int5 low level = 1, = 1 (3) interrupt request flag clear register the interrupt request flag is cleared by writing the appropriate micro dma start vector, as given in table 3.5.1, to the register intclr. f or example, to clear the interrupt flag int0, perform the following register operation after execution of the di instruction. intclr 0ah clears interrupt request flag int0. symbol name address 7 6 5 4 3 2 1 0 clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 w 0 0 0 0 0 0 intclr interrupt clear control 88h (prohibit rmw) interrupt vector
tmp91c829 2006-03-15 91c829-40 (4) micro dma start vector registers these registers assign micro dma processing to sets which source corresponds to dma. the interrupt source whose micro dma start vector value matches the vector set in one of these registers is designated as the micro dma start source. when the micro dma transfer counter value reaches zero, the micro dma transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro dma start vector register is cleared, and the micro dma start source for the channel is cleared. therefore, in order for micro dma processing to continue, the micro dma start vector register must be set again during proc essing of the micro dma transfer end interrupt. if the same vector is set in the micro dma start vector registers of more than one channel, the lowest numbered channel takes priority. accordingly, if the same vector is set in the micro dma start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro dma transfer is complete. if the micro dma start vector for this channel has not been set in the channel?s mi cro dma start vector register again, micro dma transfer for the higher-numbered chan nel will be commenced. (this process is known as micro dma chaining.) symbol name address 7 6 5 4 3 2 1 0 dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 r/w 0 0 0 0 0 0 dma0v dma0 start vector 80h dma0 start vector dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 r/w 0 0 0 0 0 0 dma1v dma1 start vector 81h dma1 start vector dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 r/w 0 0 0 0 0 0 dma2v dma2 start vector 82h dma2 start vector dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 r/w 0 0 0 0 0 0 dma3v dma3 start vector 83h dma3 start vector (5) specification of a micro dma burst specifying the micro dma burst function causes micro dma transfer, once started, to continue until the value in the transfer co unter register reaches zero. setting any of the bits in the register dmab which corre spond to a micro dma channel (as shown below) to 1 specifies that any micro dma transfer on that channel will be a burst transfer. symbol name address 7 6 5 4 3 2 1 0 dmar3 dmar2 dmar1 dmar0 r/w r/w r/w r/w 0 0 0 0 dmar dma software request register 89h (prohibit rmw) 1: dma software request dmab3 dmab2 dmab1 dmab0 r/w 0 0 0 0 dmab dma burst register 8ah 1:dma burst request
tmp91c829 2006-03-15 91c829-41 (6) notes the instruction execution unit and the bus interface unit in this cpu operate independently. therefore if, immediately before an interrupt is generated, the cpu fetches an instruction which clears the corre sponding interrupt request flag (note), the cpu may execute this instruction in between accepting the interrupt and reading the interrupt vector. in this case, the cpu will read the default vector 0008h and jump to interrupt vector address ffff08h. to avoid the avobe problem, place instruct ions that clear interrupt request flags after a di instruction. and in the case of setting an interrupt enable again by ei instruction after the execution of clearing instruction, execute ei instruction after clearing and more than 1 instructions (ex. ?nop? * 1 time). if placed ei instruction without waiting nop instruction after executio n of clearing instruction, interrupt will be enable before request flag is cleared. in the case of changing the value of the interrupt mask register by execution of pop sr instruction, disable an interrupt by di instruction before execution of pop sr instruction. in addition, take care as the following 2 circuits are exceptional and demand special attention. in level mode int0 is not an edge-triggered interrupt. hence, in level mode the interrupt request flip-flop for int0 does not function. the peripheral interrupt request passes through the s input of the flip-flop and becomes the q output. if the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. int0 to int5 level mode (for example: in case of int0) if the cpu enters the interrupt res ponse sequence as a result of int0 going from 0 to 1, int0 must then be held at 1 until the interrupt response sequence has been completed. if int0 is set to level mode so as to release a halt state, int0 must be held at 1 from the time int0 changes from 0 to 1 until the halt state is released. (hence, it is necessary to ensure that input noise is not interpreted as a 0, causing int0 to revert to 0 before the halt state has been released.) when the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. interrupt request flags must be cleared using the following sequence. di ld (iimc0), 00h; switches interrupt input mode from level mode to edge mode. ld (intclr), 0ah; clears interrupt request flag. nop ; wait ei instruction ei intrx the interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. it cannot be cleared by writing intclr register. note: the following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. int0 to int5: instructions which switch to level mode after an interrupt request has been generated in edge mode. the pin input changes from high to low after an interrupt request has been generated in level mode. (h l) intrx: instructions which read the receive buffer.
tmp91c829 2006-03-15 91c829-42 3.6 port functions the tmp91c829 features 53 bit settings which relate to the various i/o ports. as well as general-purpose i/o po rt functionality, the port pins also have i/o functions which relate to the built-in cpu and internal i/os. table 3.6.1 lists the functions of each port pin. table 3.6.2 lists the i/o regist ers and t heir specifications. table 3.6.1 port functions (r: = with programmable pull-up resistor) port name pin name number of pins direction r direction setting unit pin name for internal function port 1 p10 to p17 8 i/o ? bit d8 to d15 port 2 p20 to p27 8 output ? bit a16 to a23 port 5 p53 1 i/o bit busrq p54 1 i/o bit busak p55 1 i/o bit wait p56 1 i/o bit int0 port 6 p60 1 output ? bit cs0 p61 1 output ? bit cs1 p62 1 output ? bit cs2 p63 1 output ? bit cs3 port 7 p70 1 i/o ? bit ta0in/int1 p71 1 i/o ? bit ta1out p72 1 i/o ? bit ta3out/int2 p73 1 i/o ? bit ta4in/int3 p74 1 i/o ? bit ta5out p75 1 i/o ? bit int4 port 8 p80 1 i/o bit txd0 p81 1 i/o bit rxd0 p82 1 i/o bit sclk0/ cts0 p83 1 i/o bit 0sts p84 1 i/o bit txd1 p85 1 i/o bit rxd1 p86 1 i/o bit sclk1/ cts1 p87 1 i/o bit 1sts port 9 p90 1 i/o ? bit int5 p93 1 i/o ? bit tb0in0 p94 1 i/o ? bit tb0in1 p95 1 i/o ? bit tb0out0 p96 1 i/o ? bit tb0out1 port a pa3 pa0 to pa7 1 7 input input ? ? (fixed) (fixed) adtrg an0 to an7 port z pz2 1 i/o bit hwr pz3 1 i/o bit
tmp91c829 2006-03-15 91c829-43 table 3.6.2 i/o registers and their specifications (1/2) i/o registers port name specification pn pncr pnfc input port x 0 0 output port x 1 0 port 1 p10 to p17 d8 to d15 bus x 1 1 output port x 1 0 port 2 p20 to p27 a16 to a23 output x 1 1 input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 pz2 hwr output x 1 1 input port (without pu) 0 0 input port (with pu) 1 0 port z pz3 output port x 1 none input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 busrq input (without pu) 0 0 1 p53 busrq input (with pu) 1 0 1 input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 p54 busak output x 1 1 input port/wait input (without pu) 0 0 input port/wait input (with pu) 1 0 p55 output port x 1 none input port/int0 input (without pu) 0 0 1 input port/int0 input (with pu) 1 0 1 port 5 p56 output port x 1 0 p60 to p63 output port x 0 p60 cs0 output x 1 p61 cs1 output x 1 p62 cs2 output x 1 port 6 p63 cs3 output x none 1 input port x 0 0 p70 to p75 output port x 1 0 ta0in input x 0 none p70 int1 input x 0 1 p71 ta1out output x 1 1 ta3out output x 1 1 p72 int2 input x 0 1 ta4in input x 0 none p73 int3 input x 0 1 p74 ta5out output x 1 1 port 7 p75 int4 input x 0 1 x: don?t care
tmp91c829 2006-03-15 91c829-44 table 3.6.3 i/o registers and their specifications (2/2) i/o registers port name specification pn pncr pnfc input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 p80 txd0 output x 1 1 input port/rxd0 input (without pu) 0 0 input port/rxd0 input (with pu) 1 0 p81 output port x 1 none input port/sclk0/cts0 input (without pu) 0 0 0 input port/sclk0/cts0 input (with pu) 1 0 0 output port x 1 0 p82 sclk0 output x 1 1 input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 p83 0sts output x 1 1 input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 p84 txd1 output x 1 1 input port/rxd1 input (without pu) 0 0 input port/rxd1 input (with pu) 1 0 p85 output port x 1 none input port/sclk1/cts1 input (without pu) 0 0 0 input port/sclk1/cts1 input (with pu) 1 0 0 output port x 1 0 p86 sclk1 output x 1 1 input port (without pu) 0 0 0 input port (with pu) 1 0 0 output port x 1 0 port 8 p87 1sts output x 1 1 input port x 0 0 output port x 1 0 p90 int5 input x 0 1 input port x 0 p93 to p96 output port x 1 p93 tb0in0 input x 0 p94 tb0in1 input x 0 none p95 tb0out0 output x 1 1 port 9 p96 tb0out1 output x 1 1 input port x pa3 adtrg input x input port x port a pa0 to pa7 an0 to an7 x none x: don?t care note 1: when pa1 to pa4 are used as ad converte r input channels, a 3-bit field in the ad mode control register admod1 is used to select the channel. note 2: when pa0 is used as the adtrg input, admod1 is used to enable external trigger input.
tmp91c829 2006-03-15 91c829-45 after a reset the port pins listed below f unction as general-purpose i/o port pins. a reset sets i/o pins which can be programmed fo r either input or output to be input port pins. setting the port pins for internal func tion use must be done in software. note about bus release and programmable pull-up i/o port pins when the bus is released (e.g., when busak = 0), the output buffers for d0 to d15, a0 to a23, and the control signals ( rd , wr , hwr and cs0 to cs3 ) are off and are set to high-impedance. however, the output of built-in programmable pull-up resistors are kept before the bus is released. these programmable pull-up resistors can be selected on/off by programmable when they are used as the input ports. when they are used as output ports , they cannot be turned on/off in software. table 3.6.4 shows the pin states aft er the bus has been released. table 3.6.4 pin states (after bus release) pin state (after bus release) pin names used as port used for function p10 to p17 (d8 to d15) unchanged (e.g., not set to high-impedance (high-z)) high-impedance (high-z) p20 to p27 (a16 to 23) unchanged (e.g., not set to high-impedance (high-z)) first all bits are set high, then they are set to high-impedance (high-z). rd wr pz2 ( hwr ) the output buffer is set to off. the programmable pull-up resistor is set to on irrespective of the output latch. p60 ( cs0 ) p61 ( cs1 ) p62 ( cs2 ) p63 ( cs3 )
tmp91c829 2006-03-15 91c829-46 figure 3.6.1 shows an example external interf ac e circuit when the bus release function is used. when the bus is released, neither the internal memory nor the internal i/o can be accessed. however, the internal i/o continues to operate. as a result, the watchdog timer also continues to run. therefore, the bus release time must be taken into account and care must be taken when setting the detection time for the wdt. p20 (a16) to p27 (a23) rd wr pz2 ( hwr ) p60 ( cs0 ) p61 ( cs1 ) p62 ( cs2 ) p63 ( cs3 ) a ddress bus (a23 to a16) system control bus figure 3.6.1 interface circuit ex ample (using bus release function) the above circuit is necessary to set the signal level when the bus is released. a reset sets ( rd ) and ( wr ), p60 ( cs0 ), p61 ( cs1 ), p62 ( cs2 ), p63 ( cs3 ) to output, and pz2 ( hwr ) and p54 ( busak ) to input with pull-up resistor.
tmp91c829 2006-03-15 91c829-47 3.6.1 port 1 (p10 to p17) port 1 is an 8-bit general-purpose i/o port. ea ch bit can be set individually for input or output using the control register p1cr. resetting, the control register p1cr to 0 and sets port 1 to input mode. in addition to functioning as a general-purpos e i/o port, port 1 can also function as an address data bus (d8 to d15). in case of am1 = 0, and am = 1 (outside 16-bit data bus), port 1 always functions as the data bus (d8 to d15) irre spective of the setting in p1cr control register. internal data bus direction control (on bit basis) p1cr write p10 to p17 (d8 to d15) output buffer reset p1 read output latch p1 write port 1 figure 3.6.2 port 1 port 1 register 7 6 5 4 3 2 1 0 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w p1 (0001h) after reset data from external port (output latch register is cleared to 0.) port 1 control register 7 6 5 4 3 2 1 0 bit symbol p17c p16c p15c p14c p13c p12c p11c p10c read/write w after reset (note) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p1cr (0004h) function 0: input 1: output note1: read-modify-write is prohibited for p1cr. note2: it is set to ?port? or ?data bus? by am pins state. port 1 i/o setting 0 input 1 output figure 3.6.3 register for port 1
tmp91c829 2006-03-15 91c829-48 3.6.2 port 2 (p20 to p27) port 2 is an 8-bit output port. in addition to functioning as a output port, port 2 can also function as an address bus (a16 to a23). each bit can be set individually for address bus using the function register p2fc. resetting sets all bits of the function register p2fc to 1 and sets port 2 to address bus. internal data bus function control (on bits basis) p2fc write p20 to p27 (a16 to a23) output buffer reset p2 read output latch p2 write port 2 selector s a b s internal a16 to a23 figure 3.6.4 port 2 port 2 register 7 6 5 4 3 2 1 0 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w p2 (0006h) after reset 1 1 1 1 1 1 1 1 port 2 function register 7 6 5 4 3 2 1 0 bit symbol p27f p26f p25f p24f p23f p22f p21f p20f read/write w after reset 1 1 1 1 1 1 1 1 p2fc (0009h) function 0: port 1: address bus (a23 to a16) note: read-modify-write is prohibited for p2fc. figure 3.6.5 register for port 2
tmp91c829 2006-03-15 91c829-49 3.6.3 port 5 (p53 to p56) port 5 is an 4-bit general-purpose i/o port . i/o is set using control register p5cr and p5fc. resetting resets all bits of the output latch p5 to 1, the control register p5cr and the function register p5fc to 0 and sets p52 to p56 to input mode with pull-up register. in addition to functioning as a general-purpos e i/o port, port 5 also functions as i/o for the cpu?s control/status signal. function control (on bit basis) s output latch p5fc write p5 write p53 ( busrq ) p5 read internal data bus direction control (on bit basis) p5cr write p-ch (programmable pull up) reset internal busrq figure 3.6.6 port 53
tmp91c829 2006-03-15 91c829-50 function control (on bit basis) s output latch p54( busak ) selector internal data bus direction control (on bit basis) p5cr write p-ch (programmable pull up) reset p5fc write p5 write output buffer p5 read s a b busak figure 3.6.7 port 54 internal wait s output latch p5 write p5 read internal data bus direction control (on bit basis) p5cr write p-ch (programmable pull up) reset p55 ( wait ) output buffer figure 3.6.8 port 55
tmp91c829 2006-03-15 91c829-51 internal data bus selector a b s p56 (int0) p5 write direction control (on bit basis) p5cr write function control (on bit basis) p5 write reset level or edge and rising edge or falling edge int0 iimc0 p-ch (programmable pull up) output buffer p5fc write s output latch figure 3.6.9 port 56
tmp91c829 2006-03-15 91c829-52 port 5 register 7 6 5 4 3 2 1 0 bit symbol p56 p55 p54 p53 read/write r/w after reset data from external port (output latch register is set to 1.) p5 (000dh) function 0(output latch register): pull-up resistor off 1(output latch register): pull-up resistor on port 5 control register 7 6 5 4 3 2 1 0 bit symbol p56c p55c p54c p53c read/write w after reset 0 0 0 0 p5cr (0010h) function 0: input 1: output i/o setting 0 input 1 output port 5 function register 7 6 5 4 3 2 1 0 bit symbol p56f p54f p53f read/write w w after reset 0 0 0 p5fc (0011h) function 0: port 1: int0 input 0: port 1: busak 0: port 1: busrq note 1: read-modify-write is prohibited for register p5cr, p5fc. note 2: when port 5 is used in the input mode, p5 register controls the built-in pull-up resistor. read-modify-write is prohibited in the input mode or the i/o mode. setting the built-in pull-up resistor may be depended on the states of the input pin. note 3: when p55 pin is used as a wait pin, set p5cr to 0 and chip select/wait control register to 010. figure 3.6.10 register for port 5
tmp91c829 2006-03-15 91c829-53 3.6.4 port 6 (p60 to p63) port 6 is a 4-bit output port. when reset, the p62 latch is cleared to 0 while the p60 to p63 output latches are set to 1. in addition to functioning as an output port, this port can output standard chip select signals ( cs0 to cs3 ). these settings are made by using the p6fc register. when reset, the p6fc register has all of its bi ts cleared to 0, so that the port is set for output mode. funtion control (on bit basis) s output lacth p6 read reset p60 ( cs0 ), p61 ( cs1 ), p63 ( cs3 ) cs0 , cs1 , cs3 selector p6fc write p6 write s a b internal data bus output buffer figure 3.6.11 port 60, 61, 63 function control (on bit basis) r output latch p6 read internal data bus reset output buffer p6fc write p6 write s a b p62 ( cs2 ) cs2 selector figure 3.6.12 port 62
tmp91c829 2006-03-15 91c829-54 port 6 register 7 6 5 4 3 2 1 0 bit symbol p63 p62 p61 p60 read/write r/w p6 (0012h) after reset 1 0 1 1 port 6 function register 7 6 5 4 3 2 1 0 bit symbol p63f p62f p61f p60f read/write w after reset 0 0 0 0 p6fc (0015h) function 0: port 1 1: cs note: read-modify-write is prohibited for the registers p6fc. 0 port (p60) 1 cs0 0 port (p61) 1 cs1 0 port (p62) 1 cs2 0 port (p63) 1 cs3 figure 3.6.13 register for port 6
tmp91c829 2006-03-15 91c829-55 3.6.5 port 7 (p70 to p75) port 7 is a 6-bit general-purp ose i/o port. each bit can be set individually for input or output. resetting sets port 7 to be an input port. in addition to functioning as a general-purpose i/o port, the indi vidual port can also have the following functions: port 70 and 73 can function as the inputs ta0in and ta 4in to the 8-bit timer, and port 71, 72 and 74 can function as the 8-bit timer outputs ta 1out, ta3out and ta5out. for each of the output pins, timer output can be enabled by writing a 1 to the corresponding bit in the port 7 function register (p7fc). resetting resets all bits of the registers p7cr and p7fc to 0, and sets all bits to be input port pins. p7 read selector a bs p70 (ta0in/int1) p73 (ta4in/int3) p75 (int4) int1 int3 int4 direction control (on bit basis) s output latch p7cr write p7 write function control (on bit basis) p7fc write reset internal data bus level or edge and rising edge or falling edge iimc0 iimc1 iimc1 ta0in ta4in figure 3.6.14 port 70, 73, 75
tmp91c829 2006-03-15 91c829-56 p7 write ta1out: tmra1 ta5out: tmra5 reset p7 read selector a b s selector a b s p71 (ta1out) p74 (ta5out) timer f/f out direction control (on bit basis) p7cr write function control (on bit basis) p7fc write s output latch internal data bus figure 3.6.15 port 71, 74 p7 write (ta3out: tmra3) reset p7 read selector a b s selector a b s p72 (ta3out/int2) timer f/f out direction control (on bit basis) p7cr write function control (on bit basis) p7fc write s output latch internal data bus edge or level and rising edge or falling edge iimc0 int2 function control (on bit basis) p7fc write figure 3.6.16 port 72
tmp91c829 2006-03-15 91c829-57 port 7 register 7 6 5 4 3 2 1 0 bit symbol p75 p74 p73 p72 p71 p70 read/write r/w p7 (0013h) after reset data from external port (output latch register is set to 1.) port 7 control register 7 6 5 4 3 2 1 0 bit symbol p75c p74c p73c p72c p71c p70c read/write w after reset 0 0 0 0 0 0 p7cr (0016h) function 0: input 1: output port 7 i/o setting 0 input 1 output port 6 function register 7 6 5 4 3 2 1 0 bit symbol p72f2 p75f p74f p73f p72f1 p71f p70f read/write w w w w w after reset 0 0 0 0 0 0 0 p7fc (0017h) function 0: port 1: int2 input 0: port 1: int4 input 0: port 1: ta5out 0: port 1: int3 input 0: port 1: ta3out 0: port 1: ta1out 0: port 1: int1 input setting p71 as timer output 1 p7fc 1 p7cr 1 setting p72 as timer output 3 p7fc 1 p7cr 1 setting p74 as timer output 5 p7fc 1 p7cr 1 figure 3.6.17 register for port 7 note: read-modify-write is prohibited for the registers p7cr and p7fc.
tmp91c829 2006-03-15 91c829-58 3.6.6 port 8 (p80 to p87) port 80 to 87 constitute a 8-bit general- purpose i/o port. each bit can be set individually for input or output. resetting sets p80 to p87 to be an input port. it also sets all bits of the output latch register to 1. in addition to functioning as general-purp ose i/o port, p80 to p87 can also function as the i/o for serial channels 0. these functi on can be enabled for i/o by writing a 1 to the corresponding bit of the port 8 function register (p8fc). resetting resets all bits of the registers p8 cr and p8fc to 0 and sets all bits to be input port (with pull-up resistors). (1) port 80 (txd0), 84 (txd1) as well as functioning as i/o port, port 80, 84 can also function as serial channel txd output pins. these port feature a programmable open-drain function. p80 (txd0) p84 (txd1) open-drain possible ode output buffer selector a b s selector a bs txd0 or txd1 p8 read derection control (on bit basis) p8cr write function control (on bit basis) p8fc write s output latch p8 write reset internal data bus p-ch (programmable pul up) figure 3.6.18 port 80, 84
tmp91c829 2006-03-15 91c829-59 (2) port 81 (rxd0), 85 (rxd1) port 81, 85 are i/o port and can also be used as rxd input pin for the serial channels. rxd0 or rxd1 selector a bs p8 read p81 (rxd0) p85 (rxd1) derection control (on bit basis) p8cr write reset s output latch internal data bus p8 write p-ch (programmable pull up) out p ut buffe r figure 3.6.19 port 81, 85 (3) port 82 ( cts0 /sclk0), 86 ( cts1 /sclk1) port 82, 86 are i/o port and can also be used as the cts input pins or sclk i/o pins for the serial channels. selector a b s selector a bs p82 (sclk0/ cts0 ) p86 (sclk1/ cts1 ) sclk0 sclk1 p8 read direction control (on bit basis) p8cr write function contorl (on bit basis) p8fc write p8 write reset internal data bus s output latch sclk0, cts0 input sclk1, cts1 input p-ch (programmable pull up) figure 3.6.20 port 82, 86
tmp91c829 2006-03-15 91c829-60 (4) port 83 ( 0sts ), 87 ( 1sts ) port 83, 87 are i/o port and can also be used as sts output for the received data request signal. reset p8cr write p8 write p8 read function control (on bit basis) p8fc write 0sts or 1sts p83 ( 0sts ) p87 ( 1sts ) s b y a selector direction control (on bit basis) p-ch (programmable pull up) internal data bus s output latch s a y selector b figure 3.6.21 port 83, 87
tmp91c829 2006-03-15 91c829-61 port 8 register 7 6 5 4 3 2 1 0 bit symbol p87 p86 p85 p84 p83 p82 p81 p80 read/write r/w after reset data from external port (o utput latch register is set to 1.) p8 (0018h) function 0(output latch register) : pull-up resistor off 1(output latch register): pull-up resistor on port 8 control register 7 6 5 4 3 2 1 0 bit symbol p87c p86c p85c p84c p83c p82c p81c p80c read/write w after reset 0 0 0 0 0 0 0 0 p8cr (001ah) function 0: input 1: output port 8 i/o setting 0 input 1 output port 8 function register 7 6 5 4 3 2 1 0 bit symbol p87f p86f p84f p83f p82f p80f read/write w w w w w w after reset 0 0 0 0 0 0 p8fc (001bh) function 0: port 1: 1sts output 0: port 1: sclk1 output 0: port 1: txd1 output 0: port 1: 0sts output 0: port 1: sclk0 output 0: port 1: txd0 input to set p80, 84 for txd0, txd1 output p8fc 1 p8cr 1 to set p82, p86 for sclk0, sclk1 output p8fc 1 p8cr 1 to set p83, p87 for 0sts , 1sts output p8fc 1 p8cr 1 figure 3.6.22 register for port 8 note 1: read-modify-write is prohibited for the registers p8cr and p8fc. note 2: writing 1 to bit0 of the ode register sets the txd0, 1 pin to be open drain. no register is provided for switching between the i/o port and rxd input functions of the p81/rxd0, p85/rxd1 pin. hence, when port 8 is used as an input port, the serial data input signals received on those pins are also input to the sio.
tmp91c829 2006-03-15 91c829-62 3.6.7 port 9 (p90, p93 to p96) port 9 is an 8-bit general-purpose i/o port. ea ch bit can be set individually for input or output, resetting sets port 9 to be an input po rt, it also sets all bits in the output latch register p9 to 1. in addtion to functioning as a general-purpose i/o port, the various pins of port 9 can also function as the clock input for the 16-bit timer flipflop putput, on as input int5. these functions cn be enabled by writing a 1 to the corresponding bits in the port 9 function registers (p9fc). (1) p90 internal data bus direction control (on bit basis) reset s output latch p9 write p90 (int5) selector p9 read p9fc s b a y int5 level or edge and rising edge or falling edge iimc1 p9cr write figure 3.6.23 port 90
tmp91c829 2006-03-15 91c829-63 (2) p93 to p96 tb0in0 tb0in1 p95 (tb0out0) p96 (tb0out1) p9 read timer f/f out p9 read internal data bus selector a b s selector a b s selector a b s p93 (tb0in0) p94 (tb0in1) direction control (on bit basis) s output latch p9cr write p9 write direction control (on bit basis) p9cr write function control (on bit basis) p9fc write s output latch p9 write reset tb0out0: tmrb0 tb0out1: tmrb0 reset figure 3.6.24 port p93 to p96
tmp91c829 2006-03-15 91c829-64 port 9 register 7 6 5 4 3 2 1 0 bit symbol p96 p95 p94 p93 p90 read/write r/w r/w p9 (0019h) after reset data from external port (output latch register is set to 1.) data from external port (output latch register is set to 1.) port 9 control register 7 6 5 4 3 2 1 0 bit symbol p96c p95c p94c p93c p90c read/write w w after reset 0 0 0 0 0 p9cr (001ch) function 0: input 1: output 0: input 1: output port 9 i/o setting 0 input 1 output port 9 function register 7 6 5 4 3 2 1 0 bit symbol p96f p95f p90f read/write w w w after reset 0 0 0 p9fc (001dh) function 0: port 1: tb0out1 0: port 1: tb0out0 0: port 1: int5 input to set p95 for timer 8 output 1 p9fc 1 p9cr to set p96 for timer 9 output 1 p9fc 1 p9cr figure 3.6.25 register for port 9 note: read-modify-write is prohibited for the registers p9cr and p9fc.
tmp91c829 2006-03-15 91c829-65 3.6.8 port a (pa0 to pa7) port a is an 8-bit input port and can also be used as the analog input pins for the internal ad converter. internal data bus ad read conversion result register ad converter channel selector port a read pa0 to pa7 ( adtrg , an0 to an7) a dtrg (only pa3) figure 3.6.26 port a port a register 7 6 5 4 3 2 1 0 bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 read/write r pa (0019h) after reset data from external port. note: the input channel selection of ad converter and the permission of adtrg input are set by ad converter mode register admod1. figure 3.6.27 register for port a
tmp91c829 2006-03-15 91c829-66 3.6.9 port z (pz2, pz3) port z is a 4-bit general-purpose i/o port. i/o is set using control register pzcr and pzfc. resetting resets all bits of the output latch pz to 1, the control register pzcr and the function register pzfc to 0 and sets pz2 and pz3 to input mode with pull-up register. in addition to functioning as a general-purpos e i/o port. port z also functions as i/o for the cpu?s control/status signal. function control (on bit basis) s output latch pz2( hwr ) selector internal data bus direction control (on bit basis) pzcr write p-ch (programmable pull up) reset pzfc write pz write output buffer pz read s a b hwr figure 3.6.28 port z2 internal data bus selector a b s pz read direction control (on bit basis) pzcr write reset s output latch pz write pz3 p-ch (programmable pull up) output buffer figure 3.6.29 port z3
tmp91c829 2006-03-15 91c829-67 port z register 7 6 5 4 3 2 1 0 bit symbol pz3 pz2 read/write r/w pz (007dh) after reset data from external port (output latch register is set to 1.) port z control register 7 6 5 4 3 2 1 0 bit symbol pz3 pz2 read/write w after reset 0 0 pzcr (007eh) function 0: input 1: output setting port z as i/o 0 input 1 output port z control register 7 6 5 4 3 2 1 0 bit symbol pz2f read/write w after reset 0 pzfc (007fh) function 0: port 1: hwr note: read-modify ?write is prohibited for the registers pzcr and pzfc. figure 3.6.30 register for port z
tmp91c829 2006-03-15 91c829-68 3.7 chip select/wait controller on the tmp91c829, four user specifiable address areas (cs0 to cs3) can be set. the data bus width and the number of waits can be set independ ently for each address area (cs0 to cs3 plus any other). the pins cs0 to cs3 (which can also function as p60 to p63) are the respective output pins for the areas cs0 to cs3. when the cpu specifies an address in one of these areas, the corresponding cs0 to cs3 pin outputs the chip select signal for the specified address area (in rom or sram). however, in order for the chip se lect signal to be output, the port 6 function register p6fc must be set. external connection of rom and sram is supported. the areas cs0 to cs3 are defined by the values in the memory start address registers msar0 to msar3 and the memory addre ss mask registers mamr0 to mamr3. the chip select/wait control registers b0cs to b3cs and bexcs should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. the input pin which controls these states is the bus wait request pin ( wait ). 3.7.1 specifying an address area the address areas cs0 to cs3 are specified using the memory start address registers (msar0 to msar3) and the memory addre ss mask registers (m amr0 to mamr3). during each bus cycle, a compare operation is performed to determine whether or not the address specified on the bus corresponds to a location in one of the areas cs0 to cs3. if the result of the comparison is a match, it indicates that the corresponding cs area is to be accessed. if so, the corresponding cs0 to cs3 pin outputs the chip select signal and the bus cycle proceeds according to the settings in the corresponding b0cs to b3cs chip select/wait control register. (see 3.7.2 ? chip select/wait control registers?.)
tmp91c829 2006-03-15 91c829-69 (1) memory start address registers figure 3.7.1 shows the memory start addr ess registers. the m emory start address registers msar0 to msar3 determine the start addresses for the memory areas cs0 to cs3 respectively. the eight most significan t bits (a23 to a16) of the start address should be set in . the 16 least significant bits of the start address (a15 to a0) are fixed to 0. thus the start address can only be set to lie on a 64-kbyte boundary, starting from 000000h. figure 3.7.2 shows the relationship between the value set in the start address register and the start address. memory start address register s (for areas cs0 to cs3) 7 6 5 4 3 2 1 0 bit symbol s23 s22 s21 s20 s19 s18 s17 s16 read/write r/w after reset 1 1 1 1 1 1 1 1 msar0 (00c8h)/ msar1 (00cah) msar2 (00cch)/ msar3 (00ceh) function determines a23 to a16 of start address. sets start addresses for areas cs0 to cs3. figure 3.7.1 memory start address register 64 kbytes address 000000h ffffffh 000000h .................... 00h 010000h .................... 01h 020000h .................... 02h 030000h .................... 03h 040000h .................... 04h 050000h .................... 05h 060000h .................... 06h ff0000h .................... ffh start address value in start address register (msar0 to msar3) to to figure 3.7.2 relationship between start address and start address register value
tmp91c829 2006-03-15 91c829-70 (2) memory address mask registers figure 3.7.3 shows the memory address mask registers. the size of each of the areas cs0 to cs3 can be set by specifying a mask in the corresponding memory address mask register (mamr0 to mamr3). each bit in a memory address mask register (mamr0 to mamr3) which is set to 1 masks the co rresponding bit of the start address which has been set in the corresponding memory start address register (msar0 to msar3). the compare operation used to determine whether or not a bus address is in one of the areas cs0 to cs3 only compares address bits for which a 0 has been set in the corresponding bit position in the corres ponding memory address mask register. also, the address bits which each memory a ddress mask register can mask vary from register to register; hence, the possible si ze settings for the areas cs0 to cs3 differ accordingly. memory address mask regi ster (for cs0 area) 7 6 5 4 3 2 1 0 bit symbol v20 v19 v18 v17 v16 v15 v14 to 9 v8 read/write r/w after reset 1 1 1 1 1 1 1 1 mamr0 (00c9h) function sets size of cs0 area. 0: used for address compare range of possible settings for cs0 area size: 256 bytes to 2 mbytes. memory address mask register (cs1) 7 6 5 4 3 2 1 0 bit symbol v21 v20 v19 v18 v17 v16 v15 to 9 v8 read/write r/w after reset 1 1 1 1 1 1 1 1 mamr1 (00cbh) function sets size of cs1 area. 0: used for address compare range of possible settings for cs1 area size: 256 bytes to 4 mbytes. memory address mask register (cs2, cs3) 7 6 5 4 3 2 1 0 bit symbol v22 v21 v20 v19 v18 v17 v16 v15 read/write r/w after reset 1 1 1 1 1 1 1 1 mamr2 (00cdh)/ mamr3 (00cfh) function sets size of cs2 or cs3 area. 0: used for address compare range of possible settings for cs2 and cs3 area sizes: 32 kbytes to 8 mbytes. figure 3.7.3 memory address mask registers
tmp91c829 2006-03-15 91c829-71 (3) setting memory start ad dresses and address areas figure 3.7.4 shows an example in which cs 0 is spec ified to be a 64-kbyte address area starting at 010000h. first, msar0, the eight most signific ant bits of the start address register and which correspond to the memory start address, are set to 01h. next, based on the desired cs0 area size, the difference between the start address and the end address (01ffffh) is calculated. bits 20 to 8 of this result constitute the mask value for the desired cs0 area size. setting this value in mamr0 (bits 20 to 8 of the memory address mask re gister) sets the desired area size for cs0. in this example 07h is set in mamr0, specifying an area size of 64 kbytes. 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 f f f f s23 s22 s21 s20 s19 s18 s17 s16 0 0 0 0 0 0 0 1 0 1 h v20 v19 v18 v17 v16 v15 v14 to v9 v8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 7 h h memory end address memory start address cs0 area size (64 kbytes) memory address mask register setting msar0 msmr0 setting of 07h specifies a 64-kbyte area. figure 3.7.4 example showing how to set the cs0 area a reset sets msar0 to msar3, and mamr0 to mamr3 to ffh. in addition, b0cs, b1cs and b3cs are re set to 0, disabling the cs0, cs1, and cs3 areas. however, since a reset resets b2cs to 0 and sets b2cs to 1, cs2 is enabled with the address ra nge 003000h to 01f7ffh, 020000h to ffffffh. when addresses outside the areas specified as cs0 to cs3 are accessed, the bus width and number of waits specified in bexcs are used. (see 3.7.2 ? chip select/wait co ntroller?.)
tmp91c829 2006-03-15 91c829-72 (4) address area si ze specification table 3.7.1 shows the valid area sizes for each cs area and indicates which method can be used to make th e size setting. a ? ? indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register. if an area size for a cs area marked ? ? in the table is to be set, the start address must either be set to 000000h or to a value that is greater than 000000h by an integer multiple of the desired area size. if the cs2 area is set to 16 mbytes or if two or more areas overlap, the lowest-numbered cs area has highest priority (e.g., cs0 has a higher priority than any other area). example: to set the area size for cs0 to 128 kbytes: a. valid start addresses 000000h 020000h 040000h 060000h 128 kbytes 128 kbytes 128 kbytes any of these addresses may be set as the start address. b. invalid start addresses 000000h 010000h 030000h 050000h 64 kbytes 128 kbytes 128 kbytes this is not an integer multiple of the desired area size setting. hence, none of these addresses can be set as the start address. table 3.7.1 valid area sizes for each cs area size (bytes) cs area 256 512 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m cs0 cs1 cs2 cs3
tmp91c829 2006-03-15 91c829-73 3.7.2 chip select/wait control registers figure 3.7.5 lists the chip select/wait control registers. the master enable/disable, chip select outp ut waveform, data bus width, and number of wait states for each address area (cs0 to cs3 plus any other) are set in the respective chip select/wait control registers, b0cs to b3cs or bexcs. chip select/wait control register 7 6 5 4 3 2 1 0 bit symbol b0e b0om1 b0om0 b0bus b0w2 b0w1 b0w0 read/write w w after reset 0 0 0 0 0 0 0 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits bit symbol b1e b1om1 b1om0 b1bus b1w2 b1w1 b1w0 read/write w w after reset 0 0 0 0 0 0 0 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits bit symbol b2e b2m b2om1 b2om0 b2bus b2w2 b2w1 b2w0 read/write w after reset 1 0 0 0 0 0 0 0 function 0: disable 1: enable cs2 area selection 0: 16-mbyte area 1: cs area chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits bit symbol b3e b3om1 b3om0 b3bus b3w2 b3w1 b3w0 read/write w w after reset 0 0 0 0 0 0 0 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: 10: don?t care 11: data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits bit symbol bexbus bexw2 bexw1 bexw0 read/write w after reset 0 0 0 0 function data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits chip select output waveform selection 00 for rom/sram 01 10 11 don?t care master enable bit 0 cs area disable 1 cs area enable b0cs (00c0h) read- modify- write instructions are prohibited. b1cs (00c1h) read- modify- write instructions are prohibited. b2cs (00c2h) read- modify- write instructions are prohibited. b3cs (00c3h) read- modify- write instructions are prohibited. bexcs (00c7h) read- modify- write instructions are prohibited. cs2 area selection 0 16-mbyte area 1 specified address area data bus width selection 0 16-bit data bus 1 8-bit data bus number of address area waits (see 3.7.2 (3) ?wait control?.) figure 3.7.5 chip select/wait control registers
tmp91c829 2006-03-15 91c829-74 (1) master enable bits bit7 (, , , or ) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. writing 1 to this bit enables the se ttings. a reset disabl es , and (e.g., sets them to 0) and enables (e.g., sets it to 1). hence after a reset only the cs2 area is enabled. (2) data bus width selection bit3 (, , , , or ) of a chip select/wait control register spec ifies the width of the data bus. this bit should be set to 0 when memory is to be accessed using a 16-bi t data bus, and to 1 when an 8-bit data bus is to be used. this process of changing the data bus wi dth according to the address being accessed is known as dynamic bus sizing. for details of this bus operation see figure 3.7.2. t able 3.7.2 dynamic bus sizing cpu data operand data bus width operand start address memory data bus width cpu address d15 to d8 d7 to d0 8 bits 2n + 0 xxxxx b7 to b0 2n + 0 (even number) 16 bits 2n + 0 xxxxx b7 to b0 8 bits 2n + 1 xxxxx b7 to b0 8 bits 2n + 1 (odd number) 16 bits 2n + 1 b7 to b0 xxxxx 2n + 0 xxxxx b7 to b0 8 bits 2n + 1 xxxxx b15 to b8 2n + 0 (even number) 16 bits 2n + 0 b15 to b8 b7 to b0 2n + 1 xxxxx b7 to b0 8 bits 2n + 2 xxxxx b15 to b8 2n + 1 b7 to b0 xxxxx 16 bits 2n + 1 (odd number) 16 bits 2n + 2 xxxxx b15 to b8 2n + 0 xxxxx b7 to b0 2n + 1 xxxxx b15 to b8 2n + 2 xxxxx b23 to b16 8 bits 2n + 3 xxxxx b31 to b24 2n + 0 b15 to b8 b7 to b0 2n + 0 (even number) 16 bits 2n + 2 b31 to b24 b23 to b16 2n + 1 xxxxx b7 to b0 2n + 2 xxxxx b15 to b8 2n + 3 xxxxx b23 to b16 8 bits 2n + 4 xxxxx b31 to b24 2n + 1 b7 to b0 xxxxx 2n + 2 b23 to b16 b15 to b8 32 bits 2n + 1 (odd number) 16 bits 2n + 4 xxxxx b31 to b24 input data in bit positions marked xxxxx is ignored during a read. during a write, the bus lines corresponding to these bit positions go high-impedance and the write strobe signal for the bus remains inactive.
tmp91c829 2006-03-15 91c829-75 (3) wait control bits 0 to 2 (, , , , or ) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. the following types of wait operation can be specified using these bits. bit settings other than those listed in the table should not be made. table 3.7.3 wait operation settings number of waits wait operation 000 2 waits inserts a wait of two states, irrespective of the wait pin state. 001 1 wait inserts a wait of one state, irrespective of the wait pin state. 010 (1 + n) waits inserts one wait state, then continuously samples the state of the wait pin. while the wait pin remains low, the wait continues; the bus cycle is prolonged until the pin goes high. 011 0 waits ends the bus cycle without a wait, regardless of the wait pin state. 1xx reserved do not set. a reset sets these bits to 000 (2 waits). (4) bus width and wait control for an area other than cs0 to cs3 the chip select/wait control register bexcs controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (cs0 to cs3) are accessed. the bexcs register settings are always enabled for areas other than cs0 to cs3. (5) selecting 16-mbyte area/specified address area setting b2cs (bit6 of the chip select/wait control register for cs2) to 0 designates the 16-mbyte area 001800h to 01f7ffh, 020000h to ffffffh as the cs2 area. setting b2cs to 1 designates the address area specified by the start address register msar2 and the address mask register mamr2 as cs2 (e.g., if b2cs = 1, cs2 is specified in the same manner as cs0, cs1, and cs3). a reset clears this bit to 0, specifying cs2 as a 16-mbyte address area.
tmp91c829 2006-03-15 91c829-76 (6) procedure for setting chip select/wait control when using the chip select/wait control function, set the registers in the following order: a. set the memory start addre ss registers msar0 to msar3. set the start addresses for cs0 to cs3. b. set the memory address mask registers mamr0 to mamr3. set the sizes of cs0 to cs3. c. set the chip select/wait control registers b0cs to b3cs. set the chip select output waveform, data bus width, number of waits and master enable/disable status for cs0 to cs3 . the cs0 to cs3 pins can also function as pins p60 to p63. to output a chip select signal using one of these pins, set the corresponding bit in the port 6 function register p6fc to 1. if a cs0 to cs3 address is specified whic h is actually an internal i/o, ram or rom area address, the cpu a ccesses the internal address area and no chip select signal is output on any of the cs0 to cs3 pins. example: in this example cs0 is set to be the 64-kbyte area 010000h to 01ffffh. the bus width is set to 16 bits and the number of waits is set to 0. msar0 = 01h ............start address: 010000h mamr0 = 07h...........address area: 64 kbytes b0cs = 83h ...............rom/sram, 16-bit data bus, zero waits, cs0 area settings enabled.
tmp91c829 2006-03-15 91c829-77 3.7.3 connecting external memory figure 3.7.6 shows an example of how to connect external memory to the tmp91c829. in this example the rom is connected using a 16-bit bus. the ram and i/o are connected using an 8-bit bus. address bus cs 8-bit ram oe we tmp91c829 cs upper byte rom oe cs lower byte rom oe cs 8-bit i/o oe we cs0 cs1 cs2 a0 to a23 d8 to d15 d0 to d7 rd wr figure 3.7.6 example of external memory connection (rom uses 16-bit bus; ram and i/o use 8-bit bus.) a reset clears all bits of the port 4 control register p6cr and the port 6 function register p6fc to 0 and disables output of the cs signal. to output the cs signal, the appropriate bit must be set to 1.
tmp91c829 2006-03-15 91c829-78 3.8 8-bit timers (tmra) the tmp91c829 features six built-in 8-bit timers. these timers are paired into three modules: tmra01, tmra23 and tmra45. each module consists of two channels and can operate in any of the following four operating modes. ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable square wave puls e generation output mode (ppg ? variable duty cycle with variable period) ? 8-bit pulse width modulation output mode (pwm ? variable duty cycle with constant period) figure 3.8.1 to 3.8.3 show block diag ra ms for tmra01, tmra23 and tmra45. each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. in addition, a timer flip-flop and a prescale r are provided for each pair of channels. the operation mode and timer flip-flops are controlled by five control sfrs (special function registers). each of the four modules (tmra01, tmra23, and tmra45) can be operated independently. all modules operate in the same manner; hence only the operation of tmra01 is explained here. table 3.8.1 registers and pins for each module module tmra01 tmra23 tmra45 input pin for external clock ta0in (shared with p70) no ta4in (shared with p73) external pin output pin for timer flip-flop ta1out (shared with p71) ta3out (shared with p72) ta5out (shared with p74) timer run register ta01run (0100h) ta23run (0108h) ta45run (0110h) timer register ta0reg (0102h) ta1reg (0103h) ta2reg (010ah) ta3reg (010bh) ta4reg (0112h) ta5reg (0113h) timer mode register ta01mod (0104h) ta23mod (010ch) ta45mod (0114h) sfr (address) timer flip-flop control register ta1ffcr (0105h) ta3ffcr (010dh) ta5ffcr (0115h)
tmp91c829 2006-03-15 91c829-79 3.8.1 block diagrams run/clear prescaler clock: t0 ta0trg external input clock: ta0in ta01mod selector 8-bit up counter (uc1) 8-bit comparator (cp1) 8-bit up counter (uc0) 8-bit timer register ta1reg 8-bit up counter (cp0) match detect register buffer 0 8-bit timer register ta0reg ta01run ta01run t1 t4 t16 2 n overflow tmra0 interrupt output: intta0 ta01mod tmra0 match output: ta0trg selector t1 t16 t256 internal data bus ta01mod ta01mod match detect tmra1 interrupt output: intta1 ta01run timer flip-flop ta1ff ta1ffcr timer flip-flop output: ta1out 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 prescaler ta01run internal data bus figure 3.8.1 tmra01 block diagram
tmp91c829 2006-03-15 91c829-80 t1 t16 t256 run/clear prescale r clock: t0 ta2trg ta23mod selecto r 8-bit comparator register (cp3) 8-bit up counter (uc2) 8-bit timer register ta3reg 8-bit comparator (cp2) match detect register buffer 2 ta23run ta23run t1 t4 t16 2 n overflow tmra2 interrupt output: intta2 ta23mod tmra2 match output: ta2trg selector internal data bus ta23mod match detect tmra3 interrupt output: intta3 ta23run timer flip-flop ta3ff ta3ffcr timer flip-flop output: ta3out 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 prescaler ta23run internal data bus 8-bit up counter (uc3) 8-bit timer register ta2reg ta23mod figure 3.8.2 tmra23 block diagram
tmp91c829 2006-03-15 91c829-81 run/clear prescale r clock: t0 ta4trg external input clock: ta4in ta45mod selector 8-bit up counter (uc5) 8-bit comparator (cp5) 8-bit up counter (uc4) 8-bit timer register ta5reg 8-bit comparator (cp4) match detect register buffer 4 8-bit timer register ta4reg ta45run ta45run t1 t4 t16 2 n overflow tmra4 interrupt output: intta4 ta45mod tmra4 match output: ta4trg selector t1 t16 t256 internal data bus ta45mod ta45mod match detect tmra5 interrupt output: intta5 ta45run timer flip-flop ta5ff ta5ffcr timer flip-flop output: ta5out 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 prescale r ta45run internal data bus figure 3.8.3 tmra45 block diagram
tmp91c829 2006-03-15 91c829-82 3.8.2 operation of each circuit (1) prescalers a 9-bit prescaler generates the input clock to tmra01. the clock t0 is divided by 4 and input to this prescaler. t0 can be either f fph or fc/16 and is selected using the prescaler clock selection register syscr0. the prescaler?s operation can be controlled using ta01run in the timer control register. setting to 1 starts the count; setting to 0 clears the prescaler to zero and stops operation. table 3.8.2 shows the various prescaler output clock resolutions. table 3.8.2 prescaler output clock resolution at fc = 36 mhz prescaler output clock resolution prescaler clock selection gear value t1 t4 t16 t256 000 (fc) 2 3 /fc (0.22 s) 2 5 /fc (0.9 s) 2 7 /fc (3.6 s) 2 11 /fc (57 s) 001 (fc /2 ) 2 4 /fc (0.4 s) 2 6 /fc (1.8 s) 2 8 /fc (7.1 s) 2 12 /fc (114 s) 010 (fc /4 ) 2 5 /fc (0.9 s) 2 7 /fc (3.6 s) 2 9 /fc (14 s) 2 13 /fc (228 s) 011 (fc /8 ) 2 6 /fc (1.8 s) 2 8 /fc (7.1 s) 2 10 /fc (28 s) 2 14 /fc (455 s) (f fph ) 100 (fc /16 ) 2 7 /fc (3.6 s) 2 9 /fc (14 s) 2 11 /fc (57 s) 2 15 /fc (910 s) 10 (fc/16 clock) xxx 2 7 /fc (3.6 s) 2 9 /fc (14 s) 2 11 /fc (57 s) 2 15 /fc (910 s) xxx: don?t care (2) up counters (uc0 and uc1) these are 8-bit binary counters which count up the input clock pulses for the clock specified by ta01mod. the input clock for uc0 is selectable and ca n be either the external clock input via the ta0in pin or one of the three internal clocks t1, t4, or t16. the clock setting is specified by the value set in ta01mod. the input clock for uc1 depends on the operation mode. in 16-bit timer mode, the overflow output from uc0 is used as the input clock. in any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks t1, t16, or t256, or the comparator output (the match detection signal) from tmra0. for each interval timer the timer operation control register bits ta01run and ta01run can be used to stop and clear the up counters and to control their count. a reset clears both up counters, stopping the timers.
tmp91c829 2006-03-15 91c829-83 (3) timer registers (ta0reg and ta1reg) these are 8-bit registers which can be used to set a time interval. when the value set in the timer register ta0reg or ta1reg matches the value in the corresponding up counter, the comparator match detect signal goes active. if the value set in the timer register is 00h, the signal goes active when the up counter overflows. the ta0reg are double buffer structure, each of which makes a pair with register buffer. the setting of the bit ta01run determines whether ta0reg?s double buffer structure is enabled or disabled. it is disabled if = 0 and enabled if = 1. when the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2 n overflow occurs in pwm mode, or at the start of the ppg cycle in ppg mode. hence the double buffer cannot be used in timer mode. a reset initializes to 0, disabling the double buffer. to use the double buffer, write data to the timer register, se t to 1, and write the following data to the re gister buffer. figure 3.8.4 shows the configuration of ta0reg. figure 3.8.4 config uration of ta0reg note: the same memory address is allocated to th e timer register and the register buffer. when = 0, the same value is written to the r egister buffer and the timer register; when = 1, only the register buffer is written to. the address of each timer register is as follows. ta0reg: 000102h ta1reg: 000103h ta2reg: 00010ah ta3reg: 00010bh ta4reg: 000112h ta5reg: 000113h all these registers are write only and cannot be read. y b a selector write shift trigger write to ta0reg 2 n overflow of pwm ta01run timer registers 0 (ta0reg) register buffers 0 internal data bus matching detection in ppg cycle s
tmp91c829 2006-03-15 91c829-84 (4) comparator (cp0) the comparator compares the value in an up counter with the value set in a timer register. if they match, the up counter is cleared to zero and an interrupt signal (intta0 or intta1) is generated. if timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) timer flip-flop (ta1ff) the timer flip-flop (ta1ff) is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. whether inversion is enabled or disabled is determined by the setting of the bit ta1ffcr in the timer flip-flop control register. a reset clears the value of ta1ff to 0. writing 01 or 10 to ta1ffcr sets ta1ff to 0 or 1. writing 00 to these bits inverts the value of ta1ff (this is known as software inversion). the ta1ff signal is output via the ta1out pin (which can also be used as p71). when this pin is used as the timer output, the timer flip-flop should be set beforehand using the port 7 function register p7fc. note: when the double buffer is enabled for an 8-bit timer in pwm or ppg mode, caution is required as explained below. if new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and t he up-counter value, the timer flip-flop may output an unexpected value. for this reason, make sure that in pwm mode new data is written to the register buffer by six cycles (f sys 6) before the next overflow occurs by using an overflow interrupt. in the case of using ppg mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. example when using pwm mode ta1out 2 n overflow interrupt (intta0) t pwm (pwm cycle) match between ta0reg and up-counter desired pwm cycle change point write new data to the register buffer before the next overflow occurs by using an overflow interrupt
tmp91c829 2006-03-15 91c829-85 3.8.3 sfrs tmra01 run register 7 6 5 4 3 2 1 0 bit symbol ta0rde i2ta01 ta01prun ta1run ta0run read/write r/w r/w after reset 0 0 0 0 0 ta01run (0100h) function double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ta0reg double buffer control timer run/stop control 0 disable 0 stop and clear 1 enable 1 run (count up) i2ta01: operation in idle2 mode ta01prun: run prescaler ta1run: run tmra1 ta0run: run tmra0 note: the values of bits 4 to 6 of ta01run are undefined when read. tmra23 run register 7 6 5 4 3 2 1 0 bit symbol ta2rde i2ta23 ta23prun ta3run ta2run read/write r/w r/w after reset 0 0 0 0 0 ta23run (0108h) function double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ta2reg double buffer control timer run/stop control 0 disable 0 stop and clear 1 enable 1 run (count up) i2ta23: operation in idle2 mode ta23prun: run prescaler ta3run: runtmra3 ta2run: run tmra2 note: the values of bits 4 to 6 of ta23run are undefined when read. figure 3.8.5 tmra registers
tmp91c829 2006-03-15 91c829-86 tmra45 run register 7 6 5 4 3 2 1 0 bit symbol ta4rde i2ta45 ta45prun ta5run ta4run read/write r/w r/w after reset 0 0 0 0 0 ta45run (0110h) function double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ta4reg double buffer control timer run/stop control 0 disable 0 stop and clear 1 enable 1 run (count up) i2ta45: operation during idle2 mode ta45prun: run for prescaler ta5run: run tmra5 ta4run: run tmra4 note: the values of bits 4 to 6 of ta45run are undefined when read. figure 3.8.6 tmra registers
tmp91c829 2006-03-15 91c829-87 tmra01 mode register 7 6 5 4 3 2 1 0 bit symbol ta01m1 ta01m0 pwm01 pwm 00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 ta01mod (0104h) function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for tmra1 00: ta0trg 01: t1 10: t16 11: t256 source clock for tmra0 00: ta0in pin 01: t1 10: t4 11: t16 tmra0 source clock selection 00 ta0in (external input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmra1 source clock selection ta01mod 01 ta01mod = 01 00 comparator output from tmra0 01 t1 10 t16 11 t256 overflow output from tmra0 (16-bit timer mode) pwm cycle selection 00 reserved 01 2 6 source clock 10 2 7 source clock 11 2 8 source clock tmra01 operation mode selection 00 two 8-bit timers 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra0), 8-bit timer (tmra1) figure 3.8.7 tmra registers
tmp91c829 2006-03-15 91c829-88 tmra23 mode register 7 6 5 4 3 2 1 0 bit symbol ta23m1 ta23m0 pwm21 pwm 20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 ta23mod (010ch) function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 tmra3 clock for tmra3 00: ta2trg 01: t1 10: t16 11: t256 tmra2 clock for tmra2 00: reserved 01: t1 10: t4 11: t16 tmra2 source clock selection 00 do not set 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmra3 source clock selection ta23mod 01 ta23mod = 01 00 comparator output from tmra2 01 t1 10 t16 11 t256 overflow output from tmra2 (16-bit timer mode) pwm cycle selection 00 reserved 01 2 6 source clock 10 2 7 source clock 11 2 8 source clock tmra23 operation mode selection 00 two 8-bit timers 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra0), 8-bit timer (tmra3) figure 3.8.8 tmra registers
tmp91c829 2006-03-15 91c829-89 tmra45 mode register 7 6 5 4 3 2 1 0 bit symbol ta45m1 ta45m0 pwm41 pwm 40 ta5clk1 ta5clk0 ta4clk1 ta4clk0 read/write r/w after reset 0 0 0 0 0 0 0 0 ta45mod (0114h) function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for tmra5 00: ta4trg 01: t1 10: t16 11: t256 source clock for tmra4 00: ta4in pin 01: t1 10: t4 11: t16 source clock for tmra4 00 ta4in (external input) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) source clock for tmra5 ta45mod 01 ta45mod = 01 00 comparator output from tmra4 01 t1 10 t16 11 t256 overflow output from tmra4 (16-bit timer mode) pwm cycle 00 reserved 01 2 6 source clock 10 2 7 source clock 11 2 8 source clock operation mode for tmra45 00 two 8-bit timers 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra4), 8-bit timer (tmra5) figure 3.8.9 tmra registers
tmp91c829 2006-03-15 91c829-90 tmra1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta1ffc1 ta1ffc0 ta1ffie ta1ffis read/write r/w r/w after reset 1 1 0 0 ta1ffcr (0105h) read- modify-write instructions are prohibited. function 00: invert ta1ff 01: set ta1ff 10: clear ta1ff 11: don?t care ta1ff control for inversion 0: disable 1: enable ta1ff inversion select 0: tmra0 1: tmra1 inverse signal for timer flip-flop 1 (ta1ff) (don?t care except in 8-bit timer mode) 0 inversion by tmra0 1 inversion by tmra1 inversion of ta1ff 0 disabled 1 enabled control of ta1ff 00 inverts the value of ta1ff 01 sets ta1ff to 1 10 clears ta1ff to 0 11 don?t care figure 3.8.10 tmra registers
tmp91c829 2006-03-15 91c829-91 tmra3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta3ffc1 ta3ffc0 ta3ffie ta3ffis read/write r/w r/w after reset 1 1 0 0 ta3ffcr (010dh) read- modify-write instructions are prohibited. function 00: invert ta3ff 01: set ta3ff 10: clear ta3ff 11: don?t care ta3ff control for inversion 0: disable 1: enable ta3ff inversion select 0: tmra2 1: tmra3 inverse signal for timer flip-flop 3 (ta3ff) (don?t care except in 8-bit timer mode) 0 inversion by tmra2 1 inversion by tmra3 inversion of ta3ff 0 disabled 1 enabled control of ta3ff 00 inverts the value of ta3ff 01 sets ta3ff to 1 10 clears ta3ff to 0 11 don?t care figure 3.8.11 tmra registers
tmp91c829 2006-03-15 91c829-92 tmra5 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta5ffc1 ta5ffc0 ta5ffie ta5ffis read/write r/w r/w after reset 1 1 0 0 ta5ffcr (0115h) read- modify-write instructions are prohibited. function 00: invert ta5ff 01: set ta5ff 10: clear ta5ff 11: don?t care ta5ff control for inversion 0: disable 1: enable ta5ff inversion select 0: tmra4 1: tmra5 inverse signal for timer flip-flop 5 (ta5ff) (don?t care except in 8-bit timer mode) 0 inversion by tmra4 1 inversion by tmra5 inversion of ta5ff 0 disabled 1 enabled control of ta5ff 00 inverts the value of ta5ff 01 sets ta5ff to 1 10 clears ta5ff to 0 11 don?t care figure 3.8.12 tmra registers
tmp91c829 2006-03-15 91c829-93 tmra register 7 6 5 4 3 2 1 0 bit symbol ? read/write w ta0reg (0102h) after reset undefined bit symbol ? read/write w ta1reg (0103h) after reset undefined bit symbol ? read/write w ta2reg (010ah) after reset undefined bit symbol ? read/write w ta3reg (010bh) after reset undefined bit symbol ? read/write w ta4reg (0112h) after reset undefined bit symbol ? read/write w ta5reg (0113h) after reset undefined note: the above registers are prohibit ed read-modify-write instruction. figure 3.8.13 tmra registers
tmp91c829 2006-03-15 91c829-94 3.8.4 operation in each mode (1) 8-bit timer mode both tmra0 and tmra1 can be used independently as 8-bit interval timers. a. generating interrupts at a fixed interval (using tmra1) to generate interrupts at constant inte rvals using tmra1 (intta1), first stop tmra1 then set the operation mode, input clock and a cycle to ta01mod and ta1reg register, respecti vely. then, enable the interrupt intta1 and start tmra1 counting. example: to generate an intta1 interrupt every 8.8 s at fc = 36 mhz, set each register as follows: * clock state system clock: high frequency (fc) prescaler clock: f fph msb lsb 7 6 5 4 3 2 1 0 ta01run ? ? x x ? ? 0 ? stop tmra1 and clear it to 0. ta01mod 0 0 x x 1 0 x x select 8-bit timer mode and select t1 ((2 3 /fc) s at fc = 36 mhz) as the input clock. ta1reg 0 0 1 0 1 0 0 0 set ta1reg to 8.8 s t1 (2 3 /fc) = 40 = 28h inteta01 x 1 0 1 ? ? ? ? enable intta1 and set it to level 5. ta01run ? x x x ? 1 1 ? start tmra1 counting. x: don?t care, ? : no change select the input clock using table 3.8.4 note: the input clocks for tmra0 and tmra1 differ as follows: tmra0: uses ta0in input and can be selected from t1, t4, or t16. tmra1: match output of tmra 0 and can be selected from t1, t16, t256.
tmp91c829 2006-03-15 91c829-95 b. generating a 50% duty ratio square wave pulse the state of the timer flip-flop (ta1ff) is inverted at constant intervals and its status output via the timer output pin (ta1out). example: to output a 1.32 s square wave pulse from the ta1out pin at fc = 36 mhz, use the following procedure to make the appropriate register settings. this example uses tmra1; however, either tmra0 or tmra1 may be used. * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph 7 6 5 4 3 2 1 0 ta01run ? x x x ? ? 0 ? stop tmra1 and clear it to 0. ta01mod 0 0 x x 0 1 ? ? select 8-bit timer mode and select t1 ((2 3 /fc)s at fc = 36 mhz) as the input clock. ta1reg 0 0 0 0 0 0 1 1 set the timer register to 1.32 s t1(2 3 /fc)s 2 = 3 ta1ffcr x x x x 1 0 1 1 clear ta1ff to 0 and set it to invert on the match detect signal from tmra1. p7cr x x ? ? ? ? 1 ? p7fc x x ? ? x ? 1 x set p71 to function as the ta1out pin. ta01run ? x x x ? 1 1 ? start tmra1 counting. x: don?t care, ? : no change 0.67 s at fc = 36 mhz bit7 to 2 t1 intta1 uc1 clea r ta1ff bit0 bit1 ta01run up counte r comparato r timing comparator output (match detect) ta1out 0 1 1 1 2 2 2 3 3 3 0 00 figure 3.8.14 square wave output timing chart (50% duty)
tmp91c829 2006-03-15 91c829-96 c. making tmra1 count up on the match signal from the tmra0 comparator select 8-bit timer mode and set the comparator output from tmra0 to be the input clock to tmra1. tmra1 up counter (when ta1reg = 2) tmra0 up counter (when ta0reg = 5) 1 2 3 4 5 1 1 22 33 45 12 1 comparator output (tmra0 match) tmra1 match output figure 3.8.15 tmra1 count up on signal from tmra0 (2) 16-bit timer mode a 16-bit interval timer is configured by pairing the two 8-bit timers tmra0 and tmra1. to make a 16-bit interval timer in whic h tmra0 and tmra1 are cascaded together, set ta01mod to 01. in 16-bit timer mode, the overflow output from tmra0 is used as the input clock for tmra1, regardless of the value set in ta01mod. table 3.8.4 shows the re lationship between the timer (interrupt) cycle and the input clock selection. setting example: to generate an intta 1 interrupt every 0.22 seconds at fc = 36 mhz, set the timer registers ta0reg and ta1reg as follows: * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph if t16 ((2 7 /fc)s at 36 mhz) is used as the input clock for counting, set the following value in the registers: 0.22 s (2 7 /fc)s 62500 = f424h (e.g., set ta1reg to f4h and ta0reg to 24h). as a result, intta1 interrupt can be generated every 0.23 [s].
tmp91c829 2006-03-15 91c829-97 the comparator match signal is output from tmra0 each time the up counter uc0 matches ta0reg, where the up counter uc0 is not be cleared. in the case of the tmra1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter uc1 and ta1reg match. when the match detect signal is output simultaneously from both the comparators tmra0 and tmra1, the up counters uc0 and uc1 are cleared to 0 and the interrupt intta1 is generated. also, if inversion is enabled, the value of the timer flip-flop ta1ff is inverted. example: when ta1reg = 04h and ta0reg = 80h figure 3.8.16 timer output by 16-bit timer mode (3) 8-bit ppg (programmable pulse generation) output mode square wave pulses can be generated at any frequency and duty ratio by tmra0. the output pulses may be active-low or active-high. in this mode tmra1 cannot be used. tmra0 outputs pulses on the ta1out pin (which can also be used as p71). figure 3.8.17 8-bit ppg output waveforms t ta0reg and uc0 match (interrupt intta0) t h t l ta0reg ta1reg ta1reg and uc0 match ( interru p ut intta1 ) ta1out t t l t h when =?10? when =?01? example when =?01? 0080h 0180h 0280h 0380h 0480h value of up counte r (uc1, uc0) tmra0 comparator match detect signal intta0 0080h inversion ta1out tmra0 comparator match detect signal intta1
tmp91c829 2006-03-15 91c829-98 in this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (uc0) matches the value in one of the timer registers ta0reg or ta1reg. the value set in ta0reg must be smaller than the value set in ta1reg. although the up counter for tmra1 (u c1) is not used in this mode, ta01run should be set to 1 so that uc1 is set for counting. figure 3.8.18 shows a block diagram representing this mode. internal data bus selector t1 shift trigger t4 t16 ta01run 8-bit up counter (uc 0) comparator comparator ta0reg register buffer ta01run ta1reg ta1ff intta0 intta1 inversion ta01mod selector ta1ffcr ta0reg-wr ta1out ta0in figure 3.8.18 block diagram of 8-bit ppg output mode if the ta0reg double buffer is enabled in this mode, the value of the register buffer will be shifted into ta0reg each time ta1reg matches uc0. use of the double buffer facilitates the handling of low-duty waves (when duty is varied). q 3 shift from register buffer match with ta0reg and up counte r match with ta1reg ta0reg (value to be compared) register buffe r (up counter = q 1 ) q 1 ta0reg (register buffer) write (up countner = q 2 ) q 2 q 2 figure 3.8.19 operation of register buffer
tmp91c829 2006-03-15 91c829-99 example: to generate 1/4 duty 50khz pulses (at fc = 36 mhz): 20 s * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph calculate the value which should be set in the timer register. to obtain a frequency of 50khz, the pulse cycle t should be: t = 1/50 khz = 20 s t1 = (2 3 /fc)s (at 36 mhz); 20 s (2 3 /fc)s 90 therefore set ta1reg to 90 (5ah) the duty is to be set to 1/4: t 1/4 = 20 s 1/4 = 5 s 5 s (2 3 /fc)s 22 therefore, set ta0reg = 22 = 16h. 7 6 5 4 3210 ta01run 0 x x x ?000 stop tmra0 and tmra01 and clear it to 0. ta01mod 1 0 x x xx01 set the 8-bit ppg mode, and select t1 as input clock. ta0reg 0 0 0 1 0110 write 16h. ta1reg 0 1 0 1 1010 write 5ah. ta1ffcr x x x x 011x set ta1ff, enabling both inversion and the double buffer. 10 generates a negative logic pulse. p7cr x x ? ? ??1? p7fc x x ? ? x?1x set p71 as the ta1out pin. ta01run 1 x x x ?111 start tmra0 and tmra01 counting. x: don?t care, ? : no change
tmp91c829 2006-03-15 91c829-100 (4) 8-bit pwm output mode this mode is only valid for tmra0. in this mode, a pwm pulse with the maximum resolution of 8 bits can be output. when tmra0 is used the pwm pulse is output on the ta1out pin (which is also used as p71). tmra1 can also be used as an 8-bit timer. the timer output is inverted when the up counter (uc0) matches the value set in the timer register ta0reg or when 2 n counter overflow occurs (n = 6, 7, or 8 as specified by ta01mod). the up counter uc0 is cleared when 2 n counter overflow occurs. the following conditions must be satisfied before this pwm mode can be used. value set in ta0reg < value set for 2 n counter overflow value set in ta0reg 0 ta1out 2 n overflo w (intta0 interrupt) t pwm (pwm cycle) ta0reg and uc0 match figure 3.8.20 8-bit pwm waveforms figure 3.8.21 shows a block diagram representing this mode. ta01mod ta1ffcr internal data bus shift trigger clear 8-bit up counter (uc 0) ta01run selector ta0in t1 t4 t16 taff1 ta1out comparator ta0reg register buffer selector ta01run invert ta0reg-wr intta0 ta01mod overflow 2 n overflow control figure 3.8.21 block diagram of 8-bit pwm mode
tmp91c829 2006-03-15 91c829-101 in this mode the value of the register buffer will be shifted into ta0reg if 2 n overflow is detected when the ta0reg double buffer is enabled. use of the double buffer facilitates th e handling of low duty ratio waves. q 2 up counter = q 2 up counter = q 1 q 1 q 2 q 3 shift into ta0reg match with ta0reg 2 n overflow ta0reg (value to be compared) register buffe r ta0reg (register buffer) write figure 3.8.22 register buffer operation example: to output the following pwm waves on the ta1out pin at fc = 36 mhz: 16.0 s 28.4 s * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph to achieve a 28.4 s pwm cycle by setting t1 to (2 3 /fc)s (at fc = 36 mhz): 28.4 s (2 3 /fc)s 128 = 2 n therefore n should be set to 7. since the low-level period is 16.0 s when t1 = (2 3 /fc)s, set the following value for ta0reg: 16.0 s (2 3 /fc)s 72 = 48h msb lsb 7 6 5 4 3210 ta01run ? x x x ???0 stop tmra0 and clear it to 0. ta01mod 1 1 1 0 ??01 select 8-bit pwm mode (cycle: 2 7 ) and select t1 as the input clock. ta0reg 0 1 0 0 1000 write 48h. ta1ffcr x x x x 101x clear ta1ff to 0, enable the inversion and double buffer. p7cr x x ? ? ??1? p7fc x x ? ? x?1x set p71 and the ta1out pin. ta01run 1 x x x ?111 start tmra0 counting. x: don?t care, ? : no change
tmp91c829 2006-03-15 91c829-102 table 3.8.3 pwm cycle at fc = 36 mhz pwm cycle 2 6 2 2 8 select prescaler clock gear value t1 t4 t16 t1 t4 t16 t1 t4 t16 000 (fc) 14.2 s 56.8 s 227 s 28.4 s 113 s 455 s 56.8 s 227 s 910 s 001 (fc/2) 28.4 s 113 s 455 s 56.8 s 227 s 910 s 113 s 455 s 1820 s 10 (fc/4) 56.8 s 227 s 910 s 113 s 455 s 1820 s 227 s 910 s 3640 s 011 (fc/8) 113 s 455 s 1820 s 227 s 910 s 3640 s 455 s 1820 s 7281 s 00 (f fph ) 00 (fc/16) 227 s 910 s 3640 s 455 s 1820 s 7281 s 910 s 3640 s 14563 s 10 (fc/16 clock) xxx 227 s 910 s 3640 s 455 s 1820 s 7281 s 910 s 3640 s 14563 s xxx: don?t care (5) settings for each mode table 3.8.4 shows the sfr settings for each mode. t able 3.8.4 timer mode setting registers register name ta01mod ta1ffcr ta1ffis function timer mode pwm cycle upper timer input clock lower timer input clock timer f/f invert signal select 8-bit timer 2 channels 00 ? lower timer match t1, t16, t256 (00, 01, 10, 11) external clock t1, t4, t16 (00, 01, 10, 11) 0: lower timer output 1: upper timer output 16-bit timer mode 01 ? ? external clock t1, t4, t16 (00, 01, 10, 11) ? 8-bit ppg 1 channel 10 ? ? external clock t1, t4, t16 (00, 01, 10, 11) ? 8-bit pwm 1 channel 11 2 6 , 2 7 , 2 8 (01, 10, 11) ? external clock t1, t4, t16 (00, 01, 10, 11) ? 8-bit timer 1 channel 11 ? t1, t16, t256 (01, 10, 11) ? output disabled ? : don?t care
tmp91c829 2006-03-15 91c829-103 3.9 16-bit timer/event counters (tmrb) the tmp91c829 incorporates multifunctional 16-bit timer/event counter (tmrb0) which has the following operation modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable pulse generation (ppg) mode the timer/event counter channel consists of a 16-bit up counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. the timer/event counter is controlled by an 11-byte control sfr. this chapter consists of the following items: table 3.9.1 differences between tmrb0 channel spec tmrb0 tb0in0 (also used as p93) external clock/capture trigger input pins tb0in1 (also used as p94) tb0out0 (also used as p95) external pins timer flip-flop output pins tb0out1 (also used as p96) timer run register tb0run (0180h) timer mode register tb0mod (0182h) timer flip-flop control register tb0ffcr (0183h) tb0rg0l (0188h) tb0rg0h (0189h) tb0rg1l (018ah) timer register tb0rg1h (018bh) tb0cp0l (018ch) tb0cp0h (018dh) tb0cp1l (018eh) sfr (address) capture register tb0cp1h (018fh)
tmp91c829 2006-03-15 91c829-104 3.9.1 block diagrams intenal data bus internal data bus run/ clear match detection 16-bit comparator (cp0) 16-bit up counte r (uc0) 16-bit time register tb0rg1h/l match detection count clock tb0mod tb0run selector capture, external int input control tb0mod prescaler clock: t0 ta1out tb0in0 tb0in1 t1 t4 t16 tb0run tb0mod ( from tmra01) capture register 0 tb0cp0h/l tb0mod caputure register 1 tb0cp1h/l 32 16 8 4 2 t1 t4 t16 tb0run internal data bus internal data bus timer flip-flop control tb0ff0 tb0ff1 time r flip-flop tb0out0 tb0out1 over flow int inttbof1 time r flip-flop output register 0 inttb00 register 1 inttb01 int output 16-bit comparator (cp1) 16-bit timer register tb0rg0h/l register buffer 0 figure 3.9.1 block diagram of tmrb0
tmp91c829 2006-03-15 91c829-105 3.9.2 operation of each block (1) prescaler the 5-bit prescaler generates the source clock for tmrb0. the prescaler clock ( t0) is divided clock (divided by 4) from selected clock by the register syscr0 of clock gear. this prescaler can be started or stopped using tb0run. counting starts when is set to 1; the prescaler is cleared to zero and stops operation when is set to 0. table 3.9.2 prescaler clock resolution at fc = 36 mhz prescaler clock resolution prescaler clock selection clock gear value t1 t4 t16 000 (fc) 2 3 /fc (0.2 s) 2 5 /fc (0.9 s) 2 7 /fc (3.6 s) 001 (fc/2) 2 4 /fc (0.4 s) 2 6 /fc (1.8 s) 2 8 /fc (7.1 s) 010 (fc/4) 2 5 /fc (0.9 s) 2 7 /fc (3.6 s) 2 9 /fc (14.2 s) 011 (fc/8) 2 6 /fc (1.8 s) 2 8 /fc (7.1 s) 2 10 /fc (28.4 s) 00 (f fph ) 100 (fc/16) 2 7 /fc (3.6 s) 2 9 /fc (14.2 s) 2 11 /fc (56.9 s) 10 (fc/16 clock) xxx 2 7 /fc (3.6 s) 2 9 /fc (14.2 s) 2 11 /fc (56.9 s) xxx: don?t care (2) up counter (uc0) uc0 is a 16-bit binary counter which counts up pulses input from the clock specified by tb0mod. any one of the prescaler internal clocks t1, tb0 and t16 or an external clock input via the tb0in0 pin can be selected as the input clock. counting or stopping and clearing of the counter is controlled by tb0run. when clearing is enabled, the up counter uc 0 will be cleared to zero each time its value matches the value in the timer register tb0rg1h/l. clearing can be enabled or disabled using tb0mod. if clearing is disabled, the counter operates as a free-running counter. a timer overflow interrupt (inttbof0) is generated when uc0 overflow occurs.
tmp91c829 2006-03-15 91c829-106 (3) timer registers (tb0 rg0h/l and tb0rg1h/l) these two 16-bit registers are used to set the interval time. when the value in the up counter uc0 matches the value set in this ti mer register, the comparator match detect signal will go active. setting data for both upper and lower re gisters is always needed. for example, either using 2-byte data transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order. the tb0rg0 timer register has a double-b uffer structure, which is paired with register buffer. the value set in tb0run determines whether the double-buffer structure is enabled or disabled: it is disabled when = 0, and enabled when = 1. when the double buffer is enabled, data is transferred from the register buffer to the timer register when the values in the up counter (uc0) and the timer register tb0rg1 match. after a reset, tb0rg0 and tb0rg1 are undef ined. if the 16-bit timer is to be used after a reset, data should be written to it beforehand. on a reset tb0run is initialized to 0, disabling the double buffer. to use the double buffer, write data to the timer re gister, set to 1, then write data to the register buffer as shown below. tb0rg0 and the register buffer both ha ve the same memory addresses (000188h and 000189h) allocated to them. if = 0, the value is written to both the timer register and the register buffer. if = 1, the value is written to the register buffer only. the addresses of the timer registers are as follows: the timer registers are write-only registers and thus cannot be read. upper 8 bits (tb0rg0h) lower 8 bits (tb0rg0l) tb0rg0 000189h 000188h upper 8 bits (tb0rg1h) lower 8 bits (tb0rg1l) tb0rg1 00018bh 00018ah tmrb0 (4) capture registers (tb0 cp0h/l and tb0cp1h/l) these 16-bit registers are used to latch the values in the up counter uc0. data in the capture registers should be re ad all 16 bits. for example, using a 2-byte data load instruction or two 1-byte data load instructions. the least significant byte is read first, followed by the most significant byte. the addresses of the capture registers are as follows: upper 8 bits (tb0cp0h) lower 8 bits (tb0cp0l) tb0cp0 00018dh 00018ch upper 8 bits (tb0cp1h) lower 8 bits (tb0cp1l) tb0cp1 00018fh 00018eh tmrb0 the capture registers are read-only registers and thus cannot be written to.
tmp91c829 2006-03-15 91c829-107 (5) capture input control this circuit controls the timing to latch the value of up counter uc0 into tb0cp0, tb0cp1. the latch timing for the capture register is determined by tb0mod. in addition, the value in the up counter can be loaded into a capture register by software. whenever 0 is written to tb0mod, the current value in the up counter is loaded into capture register tb0cp0. it is necessary to keep the prescaler in run mode (e.g., tb0run mu st be held at a value of 1). note: as described above, whenever 0 is written to tb0mod, the current value in the up counter is loaded into capt ure register tb0cp0. however, note that the current value in the up counter is al so loaded into capture register tb0cp0 when 1 is written to tb0mod while this bit is holding 0. (6) comparators (cp0 and cp1) cp0 and cp1 are 16-bit comparators which co mpare the value in the up counter uc0 with the value set in tb0rg0 or tb0rg1 respectively, in order to detect a match. if a match is detected, the comparator generates an interrupt (inttb00 or inttb01 respectively). (7) timer flip-flops (tb0ff0 and tb0ff1) these flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers. inversion can be enabled and disabled for each element using tb0ffcr. after a reset the value of tb0ff0 is undefined. if 00 is written to tb0ffcr or , tb0ff0 will be inverted. if 01 is written to the capture registers, the value of tb0ff0 will be set to 1. if 10 is written to the capture registers, the value of tb0ff0 will be set to 0. the values of tb0 ff0 and tb0ff1 can be output via the timer output pins tb0out0 (which is shared with p95) and tb0out1 (which is shared with p96). timer output should be specifie d using the port 9 function register. ?0? wr ?0? wr ?1? wr ?1? wr capture capture capture nop write to tbnmod register tbnmod capture operation capture note
tmp91c829 2006-03-15 91c829-108 3.9.3 sfrs tmrb0 run register 7 6 5 4 3 2 1 0 bit symbol tb0rde ? i2tb0 tb0prun tb0run read/write r/w r/w r/w r/w r/w after reset 0 0 0 0 0 tb0run (0180h) function double buffer 0: disable 1: enable always write ?0?. idle2 0: stop 1: operate 16-bit timer run/stop control 0: stop and clear 1: run (count up) count operation 0 stop and clear 1 count i2tb0: operation during idle2 mode tb0prun: operation of prescaler note: the 1, 4 and 5 of tb0run are read as undefined value. tb0run: operation of tmrb0 figure 3.9.2 register for tmrb
tmp91c829 2006-03-15 91c829-109 tmrb0 run register 7 6 5 4 3 2 1 0 bit symbol tb0ct1 tb0et1 tb0cp0i t b0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 read/write r/w w * r/w after reset 0 0 1 0 0 0 0 0 tb0ff1 inversion 0: disable trigger 1: enable trigger tb0mod (0182h) read -modify -write instruction is prohibited function invert when the uc value is captured to tb0cp1. invert when the uc value matches the value in tb0rg1. execute software capture 0: execute 1: undefined capture timing 00: disable 01: tb0in0 tb0in1 10: tb0in0 tb0in1 11: ta1out ta1out control up counter 0: disable clearing 1: enable clearing tmrb0 source clock 00: tb0in0 pin 01: t1 10: t4 11: t16 tmrb0 source clock 00 tb0in0 pin 01 t1 10 t4 11 t16 up counter clear control 0 disable 1 tb0rg1 clearing on match with tb0rg1. capture capture control 00 disable 01 cap0 at tb0in0 rising cap1 at tb0in1 rising 10 cap0 at tb0in0 rising cap1 at tb0in1 rising 11 cap0 at ta1out rising cap1 at ta1out falling software capture 0 the value in the up counter is captured to tb0cp0. 1 undefined (note) note: whenever writing ?0? to tb0mod bit, present value of up counter is received to capture register tb0cp0. but write ?1? to tb0mod in c ondition of written ?0? to tb0mod bit, present value of up counter is received to capture register tb0cp0. therefore you must to regard. figure 3.9.3 register for tmrb
tmp91c829 2006-03-15 91c829-110 tmrb0 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol tb0ff1c1 tb0ff1c0 tb0c1t1 tb0c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 read/write w * r/w w * after reset 0 0 1 0 0 0 0 0 tb0ff0 inversion trigger 0: disable trigger 1: enable trigge r tb0ffcr (0183h) read -modify -write instruction is prohibited function control tb0ff1 00: invert 01: set 10: clear 11: don?t care * always read as ?11?. invert when the uc value is loaded in to tb0cp1. invert when the uc value is loaded in to tb0cp0. invert when the uc value matches the value in tb0rg1. invert when the uc value matches the value in tb0rg0. control tb0ff0 00: invert 01: set 10: clear 11: don?t care * always read as ?11?. tb0ff0 control 00 invert 01 set to 11 10 clear to 0 11 don?t care inverted when the uc value is loaded in to tb0cp1. 0 disable trigger 1 enable trigger inverted when the uc value is loaded in to tb0cp0. 0 disable trigger 1 enable trigger inverted when the uc value matches the valued in tb0rg1. 0 disable trigger 1 enable trigger inverted when the uc value matches the valued in tb0rg0. 0 disable trigger 1 enable trigger figure 3.9.4 register for tmrb
tmp91c829 2006-03-15 91c829-111 tmrb0 register 7 6 5 4 3 2 1 0 bit symbol ? read/write w tb0rg0l (0188h) after reset undefined bit symbol ? read/write w tb0rg0h (0189h) after reset undefined bit symbol ? read/write w tb0rg1l (018ah) after reset undefined bit symbol ? read/write w tb0rg1h (018bh) after reset undefined note: the above registers are prohibit ed read-modify-write instruction. figure 3.9.5 tmrb registers
tmp91c829 2006-03-15 91c829-112 3.9.4 operation in each mode (1) 16-bit interval timer mode generating interrupts at fixed intervals in this example, the interrupt inttb01 is se t to be generated at fixed intervals. the interval time is set in the timer register tb0rg1. 7 6 5 4 3210 tb0run 0 0 x x ?0x0 stop tmrb0. intetb01 x 1 0 0 x000 enable inttb01 and set interrupt level 4. disable inttb00. tb0ffcr 1 1 0 0 0011 disable the trigger. tb0mod 0 0 1 0 0 1 ** select internal clock for input and ( ** = 01, 10, 11) disable the capture function. tb0rg1 * * * * * * * * set the interval time (16 bits). * * * * * * * * tb0run 0 0 x x ?1x1 start tmrb0. x: don?t care, ? : no change (2) 16-bit event counter mode as described above, in 16-bit timer mode, if the external clock (tb0in0 pin input) is selected as the input clock, the timer can be used as an event counter. to read the value of the counter, first perform software capture once, then read the captured value. 7 6 5 4 3210 tb0run 0 0 x x ?0x0 stop tmrb0. p8cr ? ? ? ? 0??? set p93 input mode. intetb01 x 1 0 0 x000 enable inttb01 and set interrupt level 4. disable inttb00. tb0ffcr 1 1 0 0 0011 disable the trigger. tb0mod 0 0 1 0 0100 select tb0in0 as the input clock. tb0rg1 * * * * * * * * set the number of counts (16 bits). * * * * * * * * tb0run 0 0 x x ?1x1 start tmrb0. x: don?t care, ? : no change when the timer is used as an event counter, set the prescaler in run mode (e.g., with tb0run = 1).
tmp91c829 2006-03-15 91c829-113 (3) 16-bit programmable pulse generation (ppg) output mode square wave pulses can be generated at any frequency and duty ratio. the output pulse may be either low-active or high-active. the ppg mode is obtained by inversion of the timer flip-flop tb0ff0 that is to be enabled by the match of the up counter uc0 with timer register tb0rg0 or tb0rg1 and to be output to tb0out0. in this mode the following conditions must be satisfied. (value set in tb0rg0) < (value set in tb0rg1) match with tb0rg0 (inttb00 inerrupt) match with tb0rg1 (inttb01 interrupt) tb0out0 pin figure 3.9.5 programmable pulse generation (ppg) output waveforms when the tb0rg0 double buffer is enabled in this mode, the value of register buffer 0 will be shifted into tb0rg0 at match with tb0rg1. this feature facilitates the handling of low-duty waves. q 1 q 2 q 2 q 3 shift into thetb0rg1 up counter = q 1 up counter = q 2 match with tb0rg0 match with tb0rg1 tb0rg0 (value to be compared) register buffe r write into the tb0rg0 figure 3.9.6 operation of register buffer
tmp91c829 2006-03-15 91c829-114 the following block diagram illustrates this mode. selector selector tb0run match 16-bit up counter uc0 f/f (tb0ff0) 16-bit comparator internal data bus tb0rg1 tb0rg0-wr tb0in0 t1 t4 t16 tb0out0 (ppg output) tb0run clear register buffer 0 tb0rg0 16-bit comparator figure 3.9.7 block diagram of 16-bit mode the following example shows how to set 16-bit ppg output mode: 7 6 5 4 3210 tb0run 0 0 x x ?0x0 disable the tb0rg0 double buffer and stop tmrb0. tb0rg0 * * * * * * * * set the duty ratio (16 bits). tb0rg1 * * * * * * * * set the frequency (16 bits). tb0run 1 0 x x ?0x0 enable the tb0rg0 double buffer. (the duty and frequency are changed on an inttb01 interrupt.) tb0ffcr x x 0 0 1110 set the mode to invert tb0ff0 at the match with tb0rg0/tb0rg1. set tb0ff0 to 0. tb0mod 0 0 1 0 0 1 ** select the internal clock as the input clock and disable ( ** = 01, 10, 11) the capture function. p9cr ? ? 1 ? ?-?? p9fc x ? 1 x xxx- set p95 to function as tb0out0. tb0run 1 0 x x ?1x1 start tmrb0. x: don?t care, ? : no change
tmp91c829 2006-03-15 91c829-115 3.10 serial channel tmp91c829 includes one serial i/o chan nel. either uart mode (asynchronous transmission) or i/o interface mode (syn chronous transmission) can be selected. ? i/o interface mode mode 0: for transmit ting and receiving i/o data using the synchronizing signal sclk for extending i/o. mode 1: 7-bit data ? uart mode mode 2: 8-bit data mode 3: 9-bit data in mode 1 and mode 2 a parity bit can be added. mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (a multi-controller system). figure 3.10.2 and figure 3.10.3 are block diagrams. t able 3.10.1 channels 0 and 1 channel 0 channel 1 pin name txd0 (p80) rxd0 (p81) cts0 /sclk0 (p82) 0sts (p83) txd1 (p84) rxd1 (p85) cts0 /sclk1 (p86) 1sts (p87) figure 3.10.1 data formats bit0 1 2 3 4 5 6 start stop bit0 1 2 3 4 5 6 start stop parity bit0 1 2 3 4 5 6 bit0 1 2 3 4 5 6 start stop start stop parity 7 7 7 bit0 1 2 3 4 5 6 start 8 7 stop bit0 1 2 3 4 5 6 start stop bit8 7 when bit8 = 1, address (select code) is denoted. when bit8 = 0, data is denoted. ? mode 0 (i/o interface mode) transfer direction ? mode 1 (7-bit uart mode) ? mode 2 (8-bit uart mode) ? mode 3 (9-bit uart mode) no parity parity no parity parity 7 bit0 1 2 3 4 5 6 wakeup function
tmp91c829 2006-03-15 91c829-116 sts0 and sts1 pins are built in port p83 and p87. sts0 and sts1 are the request signal for the next data send to the cpu. p8cr sets port as output mode, p8fc sets sts using mode, and bit 0 of sc0mod1 (sc1mod1) register sets low leve l. then sts is enable to start to transfer the data. when sclk signal is exactly falling edge, sts is disable. and when it is ended to transfer 8-bits data, the sts can be set to enable and request the next data. in sclk output mode, the sts function can?t be used. d ck s q d ck s q d ck q iph resio iobus wr sclk input sts output sclk sts is h level, when sclk is falling edge timing. txd sclk sts reg wr by programming
tmp91c829 2006-03-15 91c829-117 3.10.1 block diagrams figure 3.10.2 is a block diagram representing serial channel 0. prescaler br0cr ta0trg (from tmra0) 16 32 64 8 4 2 t2 t8 t32 t0 br0cr br0add selector selector selector prescaler t0 t2 t8 t32 br0cr f sys i/o interface mode 2 selector sc0cr sc0mod0 receive counter (only uart 16) serial channel interrupt control transmision counter (only uart 16) transmission control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc0buf) error flag sioclk uart mode sc0mod0 sc0mod0 tb8 transmission buffer int request intrx0 inttx0 sc0cr cts0 shared with p82 sc0mod0 rxd0 shared with p81 sc0cr txdclk sc0mod0 parity control serial clock generation circuit sclk0 shared with p82 sclk0 shared with p82 baud rate generator rxdclk txd0 shared with p80 internal data bus i/o interface mode figure 3.10.2 block diagram of the serial channel 0
tmp91c829 2006-03-15 91c829-118 prescaler br1cr ta0trg (from tmra0) 16 32 64 8 4 2 t2 t8 t32 t0 br1cr br1add selector selector selector prescaler t0 t2 t8 t32 br1cr f sys i/o interface mode 2 selector sc1cr sc1mod0 receive counter (only uart 16) serial channel interrupt control transmision counter (only uart 16) transmission control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc1buf) error flag sioclk uart mode sc1mod0 sc1mod0 tb8 transmission buffer int request intrx1 inttx1 sc1cr cts1 shared with p86 sc1mod0 rxd1 shared with p85 sc1cr txdclk sc1mod0 parity control serial clock generation circuit sclk1 shared with p86 sclk1 shared with p86 baud rate generator rxdclk txd1 shared with p84 internal data bus i/o interface mode figure 3.10.3 block diagram of the serial channel 1
tmp91c829 2006-03-15 91c829-119 3.10.2 operation of each circuit (1) prescaler, prescaler clock select there is a 6-bit prescaler for waking se rial clock. the cl ock selected using syscr is divided by 4 and input to the prescaler as t0. the prescaler can be run by selecting the baud rate ge nerator as the waking serial clock. table 3.10.2 shows prescaler clock resolu tion into th e baud rate generator. table 3.10.2 prescaler clock resolution to baud rate generator prescaler output clock resolution select prescaler clock gear value t0 t2 t8 t32 000 (fc) 2 2 /fc 2 4 /fc 2 6 /fc 2 8 /fc 001 (fc/2) 2 3 /fc 2 5 /fc 2 7 /fc 2 9 /fc 010 (fc/4) 2 4 /fc 2 6 /fc 2 8 /fc 2 10 /fc 011 (fc/8) 2 5 /fc 2 7 /fc 2 9 /fc 2 11 /fc 00 (f fph ) 100 (fc/16) 2 6 /fc 2 8 /fc 2 10 /fc 2 12 /fc 10 (fc/16 clock) xxx ? 2 8 /fc 2 10 /fc 2 12 /fc x: don?t care, ? : cannot be used the baud rate generator sele cts between 4 clock inputs: t0, t2, t8, and t32 among the prescaler outputs.
tmp91c829 2006-03-15 91c829-120 (2) baud rate generator the baud rate generator is a circuit whic h generates transmi ssion and receiving clocks which determine the transfer rate of the serial channels. the input clock to the baud rate generator, t0, t2, t8 or t32, is generated by the 6-bit prescaler which is shared by the ti mers. one of these input clocks is selected using the br0cr field in the baud rate generator control register. the baud rate generator includes a frequency divider, which divides the frequency by 1 or 16 )k16( n ? + to 16 values, determin ing the transfer rate. the transfer rate is determined by the settings of br0cr and br0add. ? in uart mode (1) when br0cr = 0 the settings br0add are ignore d. the baud rate generator divides the selected prescaler clock by n, which is set in br0ck (n = 1, 2, 3 ? 16). (2) when br0cr = 1 the n + (16 ? k)/16 division function is enabled. the baud rate generator divides the selected prescaler clock by n + (16 ? k)/16 using the value of n set in br0cr (n = 2, 3 ? 15) and the value of k set in br0add (k = 1, 2, 3 ? 15). note: if n = 1 or n = 16, the n + (16 ? k)/16 division function is disabled. set br0cr to 0. ? in i/o interface mode the n + (16 ? k)/16 division function is no t available in i/o interface mode. set br0cr to 0 before dividing by n. the method for calculating the transfer rate when the baud rate generator is used is explained below. ? in uart mode baud rate = generator rate baudfor divider frequency generator rate baud of clock input 16 ? in i/o interface mode baud rate = generator rate baudfor divider frequency generator rate baud of clock input 2 ? integer divider (n divider) for example, when the source clock frequency (fc) = 12.288 mhz, the input clock frequency = t2 (fc/16), the frequency divider n (br0cr) = 5, and br0cr = 0, the baud rate in uart mode is as follows: * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: system clock baud rate = 5 fc/16 16 = 12.288 10 6 16 5 16 = 9600 (bps) note: the n + (16 ? k)/16 division function is disabled and setting br0add is invalid.
tmp91c829 2006-03-15 91c829-121 ? n + (16 ? k)/16 divider (only uart mode) accordingly, when the source clock frequency (fc) = 4.8 mhz, the input clock frequency = t0, the frequency divider n (br0cr) = 7, k (br0add) = 3, and br0cr = 1, the baud rate in uart mode is as follows: * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: system clock fc/4 baud rate = 7 + (16 ? 3)/16 16 = 4.8 10 6 4 (7 + 13/16) 16 = 9600 (bps) table 3.10.3 and 3.10.4 show examples o f uart mode transfer rates. additionally, the external clock input is available in the serial clock. (serial channels 0 and 1). the method for calculating the baud rate is explained below: ? in uart mode baud rate = external clock input frequency 16 it is necessary to satisfy (external clock input cycle) 4/fc ? in i/o interface mode baud rate = external clock input frequency it is necessary to satisfy (external clock input cycle) 16/fc
tmp91c829 2006-03-15 91c829-122 table 3.10.3 transfer rate selection (when ba ud rate generator is used and br0cr = 0) unit (kbps) fc [mhz] input clock frequency divider n (br0cr) t0 t2 t8 t32 9.830400 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 0 9.600 2.400 0.600 0.150 12.288000 5 38.400 9.600 2.400 0.600 a 19.200 4.800 1.200 0.300 14.745600 2 115.200 28.800 7.200 1.800 3 76.800 19.200 4.800 1.200 6 38.400 9.600 2.400 0.600 c 19.200 4.800 1.200 0.300 19.6608 1 307.200 76.800 19.200 4.800 2 153.600 38.400 93.600 2.400 4 76.800 19.10 4.800 1.200 8 38.400 9.600 2.400 0.600 10 19.200 4.800 1.200 0.300 22.1184 3 115.200 28.800 7.200 1.800 24.576 1 384.000 96.000 24.000 6.000 2 192.000 48.000 12.000 3.000 4 96.000 24.000 6.000 1.500 5 76.800 19.200 4.800 1.200 8 48.000 12.000 3.000 0.750 a 38.400 9.600 2.400 0.600 10 24.000 6.000 1.500 0.375 27.0336 b 38.400 9.600 2.400 0.600 29.4912 1 460.800 115.200 28.800 7.200 3 153.600 38.400 9.600 2.400 4 115.200 28.800 7.200 1.800 6 76.800 19.200 4.800 1.200 9 51.200 12.800 3.200 1.800 c 38.400 9.600 2.400 1.600 f 30.720 7.680 1.920 1.480 10 28.800 7.200 1.800 0.450 31.9488 d 38.400 9.600 2.400 0.600 34.4064 7 76.800 19.200 4.800 1.200 note 1: transfer rates in i/o interface mode are eight times faster than the values given above. note 2: the values in this table are calculated for when fc is selected as the system clock, the clock gear is set for fc and the system clock is the prescaler clock input. timer out clock (ta0trg) can be used fo r source clock of uart mode only. calculation method the frequency of ta0trg frequency of ta0trg = baud rate 16 note 1: the tmra0 match detects signal cannot be used as the transfer clock in i/o interface mode.
tmp91c829 2006-03-15 91c829-123 (3) serial clock generation circuit this circuit generates the basic clock for transmitting and receiving data. ? in i/o interface mode in sclk output mode with the setting sc0cr = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. in sclk input mode with the setting sc0cr = 1, the rising edge or falling edge will be detected according to the setting of the sc0cr register to generate the basic clock. ? in uart mode the sc0mod0 setting determines whether the baud rate generator clock, the internal system clock f sys , the match detect signal from timer tmra0 or the external clock (sclk0) is used to generate the basic clock sioclk. (4) receiving counter the receiving counter is a 4-bit binary counter used in uart mode which counts up the pulses of the sioclk clock. it takes 16 sioclk pulses to receive 1 bit of data; each data bit is sampled three times ? on the 7th, 8th, and 9th clock cycles. the value of the data bit is determined from these three samples using the majority rule. for example, if the data bit is sampled respec tively as 1, 0 and 1 on 7th, 8th, and 9th clock cycles, the received data bit is taken to be 1. a data bit sampled as 0, 0 and 1 is taken to be 0. (5) receiving control ? in i/o interface mode in sclk output mode with the setting sc0cr = 0, the rxd0 signal is sampled on the rising or falling edge of the shift clock which is output on the sclk0 pin, according to th e sc0cr setting. in sclk input mode with the setting sc0cr = 1, the rxd0 signal is sampled on the rising or falling edge of the sclk0 input, according to the sc0cr setting. ? in uart mode the receiving control block has a circui t which detects a start bit using the majority rule. received bits are sampled three times; when two or more out of three samples are 0, the bit is recogniz ed as the start bit and the receiving operation commences. the values of the data bits that are received are also determined using the majority rule.
tmp91c829 2006-03-15 91c829-124 (6) the receiving buffers to prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. received data is stored one bit at a time in receiving buffer 1 (which is a shift register). when 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (sc0buf); this causes an intrx0 interrupt to be generated. the cpu only reads receiving buffer 2 (sc0buf). even before the cpu has finished reading the contents of re ceiving buffer 2 (sc0buf), more data can be received and stored in receiving buffer 1. however, if receiv ing buffer 2 (sc0buf) has not been read completely before all the bits of the next data item are received by receiving buffer 1, an overrun error occurs. if an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and sc0cr will be preserved. sc0cr is used to store either the parity bit ? added in 8-bit uart mode ? or the most significant bit (msb) ? in 9-bit uart mode. in 9-bit uart mode the wakeup function for the slave controller is enabled by setting sc0mod0 to 1; in this mode intrx0 interrupts occur only when the value of sc0cr is 1. (7) transmission counter the transmission counter is a 4-bit binary counter which is used in uart mode and which, like the receiving counter, counts the sioclk clock pulses; a txdclk pulse is generated every 16 sioclk clock pulses. figure 3.10.4 generation of the transmission clock (8) transmission controller ? in i/o interface mode in sclk output mode with the setting sc0cr = 0, the data in the transmission buffer is output one bit at a time to the txd0 pin on the rising edge or falling edge of the shift clock which is output on the sclk0 pin, according to the sc0cr setting. in sclk input mode with the setting sc0cr = 1, the data in the transmission buffer is output one bit at a time on the txd0 pin on the rising or falling edge of the sclk0 input, according to the sc0cr setting. ? in uart mode when transmission data sent from the cpu is written to the transmission buffer, transmission starts on the rising edge of the next txdclk, generating a transmission shift clock txdsft. sioclk txdclk 15 16 1 2 4 5 67 8 910 11 12 13 14 15 16 3 1 2
tmp91c829 2006-03-15 91c829-125 handshake function use of cts0 pin allows data can be sent in units of one frame; thus, overrun errors can be avoided. the handshake functions is enabled or disabled by the sc0mod setting. when the cts0 pin goes high on completion of the current data send, data transmission is halted until the cts0 pin goes low again. however, the inttx0 interrupt is generated, it requests the next data send to the cpu. the next data is written in the transmission buff er and data sending is halted. although there is no rts pin, a handshake function ca n easily be configured by assigning any port to perform the rts function. the rts should be output high to request send data halt after data receiv e is completed by software in the rxd interrupt routine. rxd rts (any port) receiver txd cts0 tmp91c829 sender tmp91c829 figure 3.10.5 handshake function timing to writing to the transmission buffe r cts (1) (2) 13 14 15 16 1 2 3 14 15 16 1 2 3 sioclk txdclk txd bit0 start bit send is suspended from (1) and (2). note 1: if the cts signal goes high during transmission, no more data will be sent after completion of the current transmission. note 2: transmission starts on the first falling edge of the txdclk clock after the cts signal has fallen. figure 3.10.6 cts (clear to send) timing
tmp91c829 2006-03-15 91c829-126 (9) transmission buffer the transmission buffer (sc0buf) shifts out and sends the transmission data written from the cpu, in order one bit at a time starting with the least significant bit (lsb) and finishing with the mo st significant bit (msb). when all the bits have been shifted out, the empty transmission buffer generates an inttx0 interrupt. (10) parity control circuit when sc0cr in the serial channel control register is set to 1, it is possible to transmit and receive data with parity. howe ver, parity can be added only in 7-bit uart mode or 8-bit uart mode. the sc0cr field in the serial channel control register allows either even or odd parity to be selected. in the case of transmission, parity is automatically generated when data is written to the transmission buffer sc0buf. the data is transmitted after the parity bit has been stored in sc0buf in 7-bit ua rt mode or in sc0mod0 in 8-bit uart mode. sc0cr and sc0cr must be set before the transmission data is written to the transmission buffer. in the case of receiving, data is shifted into receiving buffer 1, and the parity is added after the data has been transferred to receiving buffer 2 (sc0buf), and then compared with sc0buf in 7-bit uart mode or with sc0cr in 8-bit uart mode. if they are not equal, a parity error is generated and the sc0cr flag is set. (11) error flags three error flags are provided to increase the reliability of data reception. 1. overrun error if all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 (sc0buf), an overrun error is generated. following shows the overrun generating process flow example. (receiving interrupts routine) (1) read of receiving buffer (2) read of error flag (3) if = ?1? then a) set to receiving enable write ?0? to b) wait end of now flame c) read of receiving buffer d) read of error flag e) set to receiving enable write ?1? to f) request transmission again (4) other process 2. parity error the parity generated for the data shifte d into receiving buffer 2 (sc0buf) is compared with the parity bit received via th e rxd pin. if they are not equal, a parity error is generated. 3. framing error the stop bit for the received data is sampled three times around the center. if the majority of the samples are 0, a framing error is generated.
tmp91c829 2006-03-15 91c829-127 (12) timing generation a. in uart mode receiving mode 9 bits (note) 8 bits + parity (note) 8 bits, 7 bits + parity, 7 bits interrupt timing center of last bit (bit8) center of last bit (parity bit) center of stop bit framing error timing center of stop bit center of stop bit center of stop bit parity error timing ? center of last bit (parity bit) center of stop bit overrun error timing center of last bit (bit8) center of last bit (parity bit) center of stop bit note: in 9-bit mode and 8 bits + parity mode, interrupts coincide with the 9th bit pulse. thus, when servicing the interrupt, it is necessary to allow a 1-bit period to elapse (so that the stop bit can be transferred) in orde r to allow proper framing error checking. transmitting mode 9 bits 8 bits + parity 8 bits, 7 bits + parity, 7 bits interrupt timing just before stop bit is transmitted just before last data bit is transmitted just before last data bit is transmitted b. i/o interface sclk output mode immediately after the last bit. (see figure 3.10.19) transmission interrupt timing sclk input mode immediately after rise of last sclk signal rising mode, or immediately after fall in falling mode. (see figure 3.10.20) sclk output mode timing used to transfer re ceived to data receive buffer 2 (sc0buf) (e.g., immediately after last sclk). (see figure 3.10.21) receiving interrupt timing sclk input mode timing used to transfer received data to receive buffer 2 (sc0buf) (e.g., immediately after last sclk). (see figure 3.10.22)
tmp91c829 2006-03-15 91c829-128 3.10.3 sfrs 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w after reset 0 0 0 0 0 0 0 0 sc0mod0 (0202h) function transfer data bit8 hand shake 0: cts disable 1: cts enable receive function 0: receive disable 1: receive enable wakeup function 0: disable 1: enable serial transmission mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial transmission clock (uart) 00: tmra0 trigger 01: baud rate generator 10: internal clock f sys 11: external clcok (sclk0 input) serial transmission clock source (uart) 00 timer tmra0 match detect signal 01 baud rate generator 10 internal clock f sys 11 external clock (sclk0 input) note: the clock selection for the i/o interface mode is controlled by the serial control register (sc0cr). serial transmission mode 00 i/o interface mode 01 7-bit mode 10 8-bit mode 11 uart 9-bit mode wakeup function 9-bit uart other modes 0 interrupt generated when data is received 1 interrupt generated only when sc0cr = 1 don?t care receiving function 0 receive disabled 1 receive enabled handshake function ( cts pin) 0 disabled (always transferable) 1 enabled transmission data bit8 figure 3.10.7 serial mode control register (channel 0, sc0mod0)
tmp91c829 2006-03-15 91c829-129 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w after reset 0 0 0 0 0 0 0 0 sc1mod0 (020ah) function transfer data bit8 hand shake 0: cts disable 1: cts enable receive function 0: receive disable 1: receive enable wakeup function 0: disable 1: enable serial transmission mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial transmission clock (uart) 00: tmra0 trigger 01: baud rate generator 10: internal clock f sys 11: external clcok (sclk1 input) serial transmission clock source (uart) 00 timer tmra0 match detect signal 01 baud rate generator 10 internal clock f sys 11 external clock (sclk1 input) note: the clock selection for the i/o interface mode is controlled by the serial control register (sc1cr). serial transmission mode 00 i/o interface mode 01 7-bit mode 10 8-bit mode 11 uart 9-bit mode wakeup function 9-bit uart other modes 0 interrupt generated when data is received 1 interrupt generated only when sc1cr = 1 don?t care receiving function 0 receive disabled 1 receive enabled handshake function ( cts pin) 0 disabled (always transferable) 1 enabled transmission data bit8 figure 3.10.8 serial mode control register (channel 1, sc1mod0)
tmp91c829 2006-03-15 91c829-130 7 6 5 4 3 2 1 0 bit symbol rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared to 0 when read.) r/w after reset undefined 0 0 0 0 0 0 0 1: error sc0cr (0201h) function received data bit8 parity 0: odd 1: even parity addition 0: disable 1: enable overrun parity framing 0: sclk0 1: sclk0 0: baud rate generator 1: sclk0 pin input i/o interface input clock selection 0 baud rate generator 1 sclk0 pin input edge selection for sclk pin 0 transmits and receivers data on rising edge of sclk0. 1 transmits and receivers data on falling edge sclk0. framing error flag parity error flag overrun error flag parity addition enable 0 disabled 1 enabled even parity addition/check 0 odd parity 1 even parity received data bit8 note: as all error flags are cleared after reading. do not test only a single bit with a bit testing instruction. figure 3.10.9 serial control register (channel 0, sc0cr) cleared to 0 when read.
tmp91c829 2006-03-15 91c829-131 7 6 5 4 3 2 1 0 bit symbol rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared to 0 when read.) r/w after reset undefined 0 0 0 0 0 0 0 sc1cr (0209h) 1: error function received data bit8 parity 0: odd 1: even parity addition 0: disable 1: enable overrun parity framing 0: sclk1 1: sclk1 0: baud rate generator 1: sclk1 pin input i/o interface input clock selection 0 baud rate generator 1 sclk0 pin input edge selection for sclk pin 0 transmits and receivers data on rising edge of sclk1. 1 transmits and receivers data on falling edge sclk1. framing error flag parity error flag overrun error flag parity addition enable 0 disabled 1 enabled even parity addition/check 0 odd parity 1 even parity received data bit8 note: as all error flags are cleared after reading. do not test only a single bit with a bit testing instruction. figure 3.10.10 serial control register (channel 1, sc1cr) cleared to 0 when read.
tmp91c829 2006-03-15 91c829-132 7 6 5 4 3 2 1 0 bit symbol ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 read/write r/w after reset 0 0 0 0 0 0 0 0 brocr (0203h) function received data bit8 + (16 ? k)/16 division 0: disable 1: enable 00: t0 01: t2 10: t8 11: t32 setting of the divided frequency + (16 ? k)/16 division enable setting the input clock of baud rate generator 0 disable 00 internal clock t0 1 enable 01 internal clock t2 10 internal clock t8 11 internal clock t32 7 6 5 4 3 2 1 0 bit symbol br0k3 br0k2 br0k1 br0k0 read/write r/w after reset 0 0 0 0 br0add (0204h) function sets frequency divisor k (divided by n = (16 ? k)/16) sets baud rate generator frequency divisor br0cr = 1 br0cr = 0 br0cr dr0add 0000 (n = 16) or 0001 (n = 1) 0000 (n = 2) or 1111 (n = 15) 0001 (n = 1) (only uart) to 1111 (n = 15) 0000 (n = 16) 0000 disable disable 0001 (k = 1) to 1111 (k = 15) disable divided by n + 16 k16 ? divided by n note1:availability of +(16-k)/16 division function n uart mode i/o mode 2 to 15 1 , 16 the baud rate generator can be set ?1? in uart mode and disable +(16-k)/16 division function.don?t use in i/o interface mode. note2:set br0cr to 1 after setting k (k = 1 to 15) to br0add when +(16-k)/16 division function is used. writes to unused bits in the br0add r egister do not affext operation, and undefined data is read from these unused bits. figure 3.10.11 baud rate generator control (channel 0, br0cr, br0add)
tmp91c829 2006-03-15 91c829-133 7 6 5 4 3 2 1 0 bit symbol ? br1adde br1ck1 br1ck0 br1s3 br1s2 br1s1 br1s0 read/write r/w after reset 0 0 0 0 0 0 0 0 br1cr (020bh) function received data bit8 + (16 ? k)/16 division 0: disable 1: enable 00: t0 01: t2 10: t8 11: t32 setting of the divided frequency + (16 ? k)/16 division enable setting the input clock of baud rate generator 0 disable 00 internal clock t0 1 enable 01 internal clock t2 10 internal clock t8 11 internal clock t32 7 6 5 4 3 2 1 0 bit symbol br1k3 br1k2 br1k1 br1k0 read/write r/w after reset 0 0 0 0 br1add (020ch) function sets frequency divisor k (divided by n = (16 ? k)/16) sets baud rate generator frequency divisor br0cr = 1 br1cr = 0 br1cr dr1add 0000 (n = 16) or 0001 (n = 1) 0000 (n = 2) or 1111 (n = 15) 0001 (n = 1) (only uart) to 1111 (n = 15) 0000 (n = 16) 0000 disable disable 0001 (k = 1) to 1111 (k = 15) disable divided by n + 16 k16 ? divided by n note1:availability of +(16-k)/16 division function n uart mode i/o mode 2 to 15 1 , 16 the baud rate generator can be set ?1? in uart mode and disable +(16-k)/16 division function.don?t use in i/o interface mode. note2:set br1cr to 1 after setting k (k = 1 to 15) to br1add when +(16-k)/16 division function is used. writes to unused bits in the br1add r egister do not affext operation, and undefined data is read from these unused bits. figure 3.10.12 baud rate generator control (channel 1, br1cr, br1add)
tmp91c829 2006-03-15 91c829-134 tb7 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 sc0buf (0200h) (transmission) (receiving) tb6 tb5 tb4 tb3 tb2 tb1 tb0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 note: prohibit read-modify-write for sc0buf. figure 3.10.13 serial transmission/receiv ing buffer registers (channel 0, sc0buf) 7 6 5 4 3 2 1 0 bit symbol i2s0 fdpx0 stsen0 read/write r/w r/w w after reset 0 0 1 sc0mod1 (0205h) function idle2 0: stop 1: run duplex 0: half 1: full sts0 0: enable 1: disable figure 3.10.14 serial mode control register 1 (channel 0, sc0mod1) tb7 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 sc1buf (0208h) (transmission) (receiving) tb6 tb5 tb4 tb3 tb2 tb1 tb0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 note: prohibit read-modify-write for sc1buf. figure 3.10.15 serial transmission/receiv ing buffer registers (channel 1, sc1buf) 7 6 5 4 3 2 1 0 bit symbol i2s1 fdpx1 stsen1 read/write r/w r/w w after reset 0 0 1 sc1mod1 (020dh) function idle2 0: stop 1: run duplex 0: half 1: full sts1 0:enable 1:disable figure 3.10.16 serial mode control register 1 (channel 1, sc1mod1)
tmp91c829 2006-03-15 91c829-135 3.10.4 operation in each mode (1) mode 0 (i/o interface mode) this mode allows an increase in the number of i/o pins available for transmitting data to or receiving data from an external shift register. this mode includes the sclk output mode to output synchronous clock sclk and sclk input external synchronous clock sclk. output extension tmp91c829 txd scl k por t input extension tc74hc595 or equivalent tc74hc165 or equivalent tmp91c829 a b c d e f g h rxd sclk port shift register a b c d e f g h si sck rck qh clock shift register s/ l figure 3.10.17 example of sclk output mode connection tmp91c829 txd scl k por t tmp91c829 a b c d e f g h rxd sclk port shift register a b c d e f g h si sck rck qh clock external clock output extension input extension tc74hc595 or equivalent tc74hc165 or equivalent external clock shift register s/ l figure 3.10.18 example of sclk input mode connection
tmp91c829 2006-03-15 91c829-136 a. transmission in sclk output mode 8-bit data and a synchronous clock are output on the txd0 and sclk0 pins respectively each time the cpu writes the data to the transmission buffer. when all the data has been output, intes0 is set to 1, causing an inttx0 interrupt to be generated. figure 3.10.19 transmitting operation in i/o interface mode (sclk0 output mode) (channel 0) in sclk input mode, 8-bit data is output on the txd0 pin when the sclk0 input becomes active after the data has been written to the transmission buffer by the cpu. when all the data has been output, intes0 is set to 1, causing an inttx0 interrupt to be generated. figure 3.10.20 transmitting operation in i/o interface mode (sclk0 input mode) (channel 0) sclk0input ( = 0 rising edge mode) sclk0 input ( = 1 falling edge mode) bit0 bit1 txd0 itx0c (inttx0 interrupt request) bit5 bit6 bit7 timing to write transmission data sclk0 output (=0 rising edge mode) bit0 bit6 bit7 bit1 txd0 itx0c (inttx0 interru p t re q uest ) sclk0 output (=1 falling edge mode) (internal clock timing)
tmp91c829 2006-03-15 91c829-137 b. receiving in sclk output mode the synchronous clock is output on the sclk0 pin and the data is shifted to receiving buffer 1. this is initiated when the receive interrupt flag intes0 is cleared as the received data is read. when 8-bit data is received, the data is transferred to receiving buffer 2 (sc0buf) following the timing shown below and intes0 is set to 1 again, causing an intrx0 interrupt to be generated. setting sc0mod0to 1 initiates sclk0 output. figure 3.10.21 receiving operation in i/o interface mode (sclk0 output mode) (channel 0) in sclk input mode the data is shifted to receiving buffer 1 when the sclk input goes active. the sclk input goes active when the receive interrupt flag intes0 is cleared as the received data is read. when 8-bit data is received, the data is shifted to receiving buffer 2 (sc0buf) following the timing shown below and intes0 is set to 1 again, causing an intrx0 interrupt to be generated. figure 3.10.22 receiving operation in i/o interface mode (sclk0 input mode) (channel 0) note: the system must be put in t he receive enable state (scmod0 = 1) before data can be received. sclk0 input ( = 0: rising edge mode) bit0 bit6 bit7 irx0c bit1 rxd0 (intrx0 ) bit5 sclk0 input ( = 1: falling edge mode) sclk0 output (=0 rising edge mode) rxd0 irx0c (intrx0 interrupt request) bit0 bit6 bit7 bit1 sclk0 output (=1 fallingf edge mode)
tmp91c829 2006-03-15 91c829-138 c. transmission and receiving (full duplex mode) when full duplex mode is used, set the receive interrupt level to 0 and set enable the level of transmit interrupt. ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. the following is an example of this: example: channel 0, sclk output baud rate = 9600 bps fc = 14.7456 mhz * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph main routine 7 6 5 43210 set the inttx0 level to 1. intes0 0 0 0 1 0000 set the intrx0 level to 0. p8cr ? ? ? ? ?101 set p80, p81, and p82 to function as the txd0, rxd0, and sclk0 pins respectively . p8fc ? ? ? ? ?1?1 sc0mod0 0 0 0 0 0000 select i/o interface mode. sc0mod1 1 1 0 0 0000 select full duplex mode. sc0cr 0 0 0 0 0000 sclk_out, transmit on negative edge, receive on positive edge. br0cr 0 0 1 1 0011 baud rate = 9600 bps. sc0mod0 0 0 1 0 0000 enable receiving. sc0buf * * * ***** set the transmit data and start . inttx0 interrupt routine acc sc0buf read the receiving buffer. sc0buf ? ? x x ?1xx set the next transmit data. x: don?t care, ? : no change
tmp91c829 2006-03-15 91c829-139 (2) mode 1 (7-bit uart mode) 7-bit uart mode is selected by setti ng the serial cha nnel mode register sc0mod0 field to 01. in this mode a parity bit can be added. use of a parity bit is enabled or disabled by the setting of the serial channel control re gister sc0cr bit; whether even parity or odd parity will be used is determined by the sc0cr setting when sc0cr is set to 1 (enabled). setting example: when transmitting data of the following format, the control registers should be set as described below. this explanation applies to channel 0. transmission direction (transmission rate: 2400 bps at fc = 12.288 mhz) start bit0 1 2 3 5 4 6 even parity stop * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: system clock 7 6 5 4 3 2 1 0 p8cr ? ? ? ? ? ? ? 1 p8fc ? ? ? ? ? ? ? 1 set p80 to function as the txd0 pin. sc0mod x 0 ? x 0 1 0 1 select 7-bit uart mode. sc0cr x 1 1 x x x 0 0 add even parity. br0cr 0 0 1 0 0 1 0 1 set the transfer rate to 2400 bps. intes0 1 1 0 0 ? ? ? ? enable the inttx0 interrupt and set it to interrupt level 4. sc0buf * * * * * * * * set data for transmission. x: don?t care, ? : no change (3) mode 2 (8-bit uart mode) 8-bit uart mode is selected by setting sc0mod0 to 10. in this mode a parity bit can be added (use of a parity bi t is enabled or disabled by the setting of sc0cr); whether even parity or odd pari ty will be used is determined by the sc0cr setting when sc0cr is set to 1 (enabled). setting example: when receiving data of the following format, the control registers should be set as described below. transmission direction (transmission rate: 9600 bps at fc = 12.288 mhz) start bit0 1 2 3 5 4 6 odd parity stop 7
tmp91c829 2006-03-15 91c829-140 * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: system clock main settings 7 6 5 4 3 2 1 0 p8cr ? ? ? ? ? ? 0 ? set p80 to function as the txd0 pin. sc0mod ? 0 1 x 1 0 0 1 enable receiving in 8-bit uart mode. sc0cr x 0 1 x x x 0 0 add even parity. br0cr 0 0 0 1 0 1 0 1 set the transfer rate to 9600 bps. intes0 ? ? ? ? 1 100 enable the inttx0 interrupt and set it to interrupt level 4. interrupt processing acc sc0cr and 00011100 if acc 0 then error check for errors. acc sc0buf read the received data. x: don?t care, ? : no change (4) mode 3 (9-bit uart mode) 9-bit uart mode is selected by setting sc0mod0 to 11. in this mode parity bit cannot be added. in the case of transmission the msb (9th bit) is written to sc0mod0. in the case of receiving it is stored in sc0cr. when the buffer is written and read, the msb is read or written first, before the rest of the sc0buf data. wakeup function in 9-bit uart mode, the wakeup function for slave controllers is enabled by setting sc0mod0 to 1. the interrupt intrx0 can only be generated when = 1. txd master slave 1 slave 2 slave 3 rxd txd rxd txd txd rxd rxd note: the txd pin of each slave controller must be in open-drain output mode. figure 3.10.23 serial link using wakeup function
tmp91c829 2006-03-15 91c829-141 protocol a. select 9-bit uart mode on the master and slave controllers. b. set the sc0mod0 bit on each slave controller to 1 to enable data receiving. c. the master controller transmits data one frame at a time. each frame includes an 8-bit select code which identifies a slave controller. the msb (bit8) of the data () is set to 1. select code of slave controller start bit0 1 2 3 5 4 6 stop 7 8 1 d. each slave controller receives the above frame. each controller checks the above select code against its own select code. the controller whose code matches clears its wu bit to 0. e. the master controller transmits data to the specified slave controller (the controller whose sc0mod bit has been cleared to 0). the msb (bit8) of the data () is cleared to 0. data 0 start bit0 1 2 3 5 4 6 stop 7 bit8 f. the other slave controllers (whose bi ts remain at 1) ignore the received data because their msbs (bit8 or ) are set to 0, disabling intrx0 interrupts. the slave controller whose wu bit = 0 can also transmit to the master controller. in this way it can signal the master controller that the data transmission from the master controller has been completed.
tmp91c829 2006-03-15 91c829-142 setting example: to link two slave controllers serially with the master controller using the internal clock f sys as the transfer clock. txd master slave 1 slave 2 select code 00000001 rxd txd rxd txd rxd select code 00001010 since serial channels 0 and 1 operate in exactly the same way, channel 0 only is used for the purposes of this explanation. ? setting the master controller main p8cr ? ? ? ? ? ? 01 p8fc ? ? ? ? ? ? x1 set p80 and p81 to function as the txd0 and rxd0 pins respectively. intes0 1 1 0 0 1 1 0 1 enable the inttx0 interrupt and set it to interrupt level 4. enable the intrx0 interrupt and set it to interrupt level 5. sc0mod0 1 0 1 0 1 1 1 0 set f sys as the transmission clock for 9-bit uart mode. sc0buf 0 0 0 0 0 0 0 1 set the select code for slave controller 1. inttx0 interrupt sc0mod0 0 ? ? ? ? ? ? ? set tb8 to tb0. sc0buf * * * * * * * * set data for transmission. ? setting the slave controller main p8cr ? ? ? ? ? ? 01 p8fc ? ? ? ? ? ? x1 ode x x x x x x ? 1 select p81 and p80 to function as the rxd0 and txd0 pins respectively (open-drain output). intes0 1 1 0 1 1 1 1 0 enable intrx0 and inttx0. sc0mod0 0 0 1 1 1 1 1 0 set to 1 in 9-bit uart transmission mode using f sys as the transfer clock. intrx0 interrupt acc sc0buf if acc = select code then sc0mod0 ? ? ? 0 ? ? ? ? clear to 0.
tmp91c829 2006-03-15 91c829-143 3.11 analog/digital converter the tmp91c829 incorporates a 10-bit successi ve approximation type analog/digital converter (ad converter) with 8-channel analog input. figure 3.11.1 is a block diagram of the ad converter. the 8-channel analog input pins (an0 to an7 ) are shared with the input-only port, port a and can thus be used as an input port. note: when idle2, idle1 or stop mode is selected , so as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled. therefore be sure to check that ad converter operations are halted before a halt instruction is executed. intad interrupt an7 (pa7) an6 (pa6) an5 (pa5) an4 (pa4) an3 (pa3) an2 (pa2) an1 (pa1) an0 (pa0) comparator vrefh vrefl multiplexer sample and hold a d mode control register 1 admod1 a dmod1 scan repeat interrupt busy end start + ? internal data bus decoder ad mode control register 0 admod0 adtrg ad conversion result register adreg04l to adreg37l adreg04h to adreg37h da converter ad converter control circuit channel select a nalog input adtrg (pa3) figure 3.11.1 block diagram of ad converter
tmp91c829 2006-03-15 91c829-144 3.11.1 analog/digital converter registers the ad converter is controlled by the two ad mode control registers: admod0 and admod1. the eight ad conversion data upper and lower regi sters (adreg04h/l, adreg15h/l, adreg26h/l, and adreg37h/l) store the results of ad conversion. figure 3.11.2 shows the registers related to the ad converter. ad mode control register 0 7 6 5 4 3 2 1 0 bit symbol eocf adbf ? ? itm0 repeat scan ads read/write r r/w after reset 0 0 0 0 0 0 0 0 admod0 (02b0h) function ad conversion end flag 0: conversion in progress 1: conversion complete ad conversion busy flag 0: conversion stopped 1: conversion in progress always write ?0?. always write ?0?. interrupt specification in conversion channel fixed repeat mode 0: every conversion 1: every fourth conversion repeat mode specification 0: single conversion 1: repeat conversion mode scan mode specification 0: conversion channel fixed mode 1: conversion channel scan mode ad conversion start 0: don?t care 1: start conversion always ?0? when read. ad conversion start 0 don?t care 1 start ad conversion note: always read as 0. ad scan mode setting 0 ad conversion channel fixed mode 1 ad conversion channel scan mode ad repeat mode setting 0 ad single conversion mode 1 ad repeat conversion mode specify ad conversion interrupt for channel fixed repeat conversion mode channel fixed repeat conversion mode = 0, = 1 0 generates interrupt every conversion. 1 generates interrupt every fourth conversion. ad conversion busy flag 0 ad conversion stopped 1 ad conversion in progress ad conversion end flag 0 before or during ad conversion 1 ad conversion complete figure 3.11.2 ad converter related register
tmp91c829 2006-03-15 91c829-145 ad mode control register 1 7 6 5 4 3 2 1 0 bit symbol vrefon i2ad adtrge adch2 adch1 adch0 read/write r/w r/w r/w after reset 0 0 0 0 0 0 admod1 (02b1h) function vref application control 0: off 1: on idle2 0: stop 1: operate ad external trigger start control 0: disable 1: enable analog input channel selection. analog input channel selection 0 channel fixed 1 channel scanned 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 an3 an0 an1 an2 an3 100 an4 an4 101 an5 an4 an5 110 an6 an4 an5 an6 111 an7 an4 an5 an6 an7 ad conversion start control by external trigger ( adtrg input) 0 disabled 1 enabled idle2 control 0 stopped 1 in operation control of application of reference voltage to ad converter 0 off 1 on before starting conversion (before writing 1 to admod0), set the bit to 1. ad mode control register 2 7 6 5 4 3 2 1 0 bit symbol adm27 adm26 adm25 adm24 adm23 adm22 adm21 adm20 read/write r/w after reset 0 0 0 1 0 0 0 1 admod2 (2b2h) function please write 1e ad mode control register 3 7 6 5 4 3 2 1 0 bit symbol adm37 adm36 adm35 adm34 adm33 adm32 adm31 adm30 read/write r/w after reset 1 1 0 0 1 1 1 1 admod3 (2b3h) function please write cf figure 3.11.3 ad converter related register
tmp91c829 2006-03-15 91c829-146 ad conversion data lower register 0/4 7 6 5 4 3 2 1 0 bit symbol adr01 adr00 adr0rf read/write r r after reset undefined 0 adreg04l (02a0h) function stores lower 2 bits of ad conversion result. ad conversion data storage flag 1: conversion result stored ad conversion data upper register 0/4 7 6 5 4 3 2 1 0 bit symbol adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 read/write r after reset undefined adreg04h (02a1h) function stores upper 8 bits ad conversion result. ad conversion data lower register 1/5 7 6 5 4 3 2 1 0 bit symbol adr11 adr10 adr1rf read/write r r after reset undefined 0 adreg15l (02a2h) function stores lower 2 bits of ad conversion result. ad conversion result flag 1: conversion result stored ad conversion data upper register 1/5 7 6 5 4 3 2 1 0 bit symbol adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 read/write r after reset undefined adreg15h (02a3h) function stores upper 8 bits ad conversion result. 9 8 76543210 channel x conversion result adregxh adregxl 7 6 543210 76543 2 1 0 ? bits 5 to 1 are always read as 1. ? bit0 is the ad conversion data storage flag . when the ad conversion result is stored, the fl ag is set to 1. when either of the registers (adregxh, adregxl) is read, the flag is cleared to 0. figure 3.11.4 ad converter related registers
tmp91c829 2006-03-15 91c829-147 ad conversion result lower register 2/6 7 6 5 4 3 2 1 0 bit symbol adr21 adr20 adr2rf read/write r r after reset undefined 0 adreg26l (02a4h) function stores lower 2 bits of ad conversion result. ad conversion data storage flag 1: conversion result stored ad conversion data upper register 2/6 7 6 5 4 3 2 1 0 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r after reset undefined adreg26h (02a5h) function stores upper 8 bits of ad conversion result. ad conversion data lower register 3/7 7 6 5 4 3 2 1 0 bit symbol adr31 adr30 adr3rf read/write r r after reset undefined 0 adreg37h (02a6h) function stores lower 2 bits of ad conversion result. ad date storage 1: conversion result stored ad conversion result upper register 3/7 7 6 5 4 3 2 1 0 bit symbol adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 read/write r after reset undefined adreg37h (02a7h) function stores upper 8 bits of ad conversion result. 9 8 76543210 channel x conversion result adregxh adregxl 7 6 543210 76543 2 1 0 ? bits 5 to 1 are always read as 1. ? bit0 is the ad conversion data storage flag . when the ad conversion result is stored, the fl ag is set to 1. when either of the registers (adregxh, adregxl) is read, the flag is cleared to 0. figure 3.11.5 ad converter related registers
tmp91c829 2006-03-15 91c829-148 3.11.2 description of operation (1) analog reference voltage a high-level analog reference voltage is applied to the vrefh pin; a low-level analog reference voltage is applied to the vrefl pin. to perform ad conversion, the reference voltage, the difference between vrefh and vrefl, is divided by 1024 using string resistance. the result of the division is then compared with the analog input voltage. to turn off the switch between vrefh and vrefl, write a 0 to admod1 in ad mode control register 1. to start ad conversion in the off state, first write a 1 to admod1, wait 3 s until the internal reference voltage stabilizes (this is not related to fc.), then set admod0 to 1. (2) analog input channel selection the analog input channel selection varies depends on the operation mode of the ad converter. ? in analog input channel fixed mode (admod0 = 0) setting admod1 selects one of the input pins an0 to an7 as the input channel. ? in analog input channel scan mode (admod0 = 1) setting admod1 selects one of the eight scan modes. table 3.11.1 illustrates analog input channel selection in each operation mode. on a reset, admod0 is set to 0 and admod1 is initialized to 000. thus pin an0 is selected as the fixed input channel. pi ns not used as analog input channels can be used as standard input port pins. table 3.11.1 analog input channel selection channel fixed = 0 channel scan = 1 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 an3 an0 an1 an2 an3 100 an4 an4 101 an5 an4 an5 110 an6 an4 an5 an6 111 an7 an4 an5 an6 an7 (3) starting ad conversion to start ad conversion, write a 1 to admod0 in ad mode control register 0 or admod1 in ad mode control register 1, pull the adtrg pin input from high to low. when ad conversion starts, the ad conversion busy flag admod0 will be set to 1, indicating that ad conversion is in progress. writing a 1 to admod0 during ad conversion restarts conversion. at that time, to determine whether the ad conversion results have been preserved, check the value of the conversion data storage flag adregxl. during ad conversion, a falling edge input on the adtrg pin will be ignored.
tmp91c829 2006-03-15 91c829-149 (4) ad conversion modes and the ad conversion end interrupt the four ad conversion modes are: ? channel fixed single conversion mode ? channel scan single conversion mode ? chanel fixed repeat conversion mode ? channel scan repeat conversion mode the admod0 and admod0 settings in ad mode control register 0 determine the ad mode setting. completion of ad coversion triggers an in tad ad conversion end interrupt request. also, admod0 will be set to 1 to indicate that ad conversion has been completed. a. channel fixed single conversion mode setting admod0 and admod0 to 00 selects conversion channel fixed single conversion mode. in this mode data on one specified channel is converted once only. when the conversion has been completed, the admod0 flag is set to 1, admod0 is cleared to 0, and an intad interrupt request is generated. b. channel scan single conversion mode setting admod0 and admod0 to 01 selects conversion channel scan single conversion mode. in this mode data on the specified scan channels is converted once only. when scan conversion has be en completed, admod0 is set to 1, admod0 is cleared to 0, and an intad interrupt request is generated. c. channel fixed repeat conversion mode setting admod0 and admod0 to 10 selects conversion channel fixed repeat conversion mode. in this mode data on one specified channel is converted repeatedly. when conversion has been completed, admod0 is set to 1 and admod0 is not cleared to 0 but held at 1. intad interrupt request generation timing is determined by the setting of admod0. setting to 0 generates an interrupt request every time an ad conversion is completed. setting to 1 generates an inte rrupt request on completion of every fourth conversion.
tmp91c829 2006-03-15 91c829-150 d. channel scan repeat conversion mode setting admod0 and admod0 to 11 selects conversion channel scan repeat conversion mode. in this mode data on the specified scan channels is converted repeatedly. when each scan conversion has been complete d, admod0 is set to 1 and an intad interrupt request is generated. admod0 is not cleared to 0 but held at 1. to stop conversion in a repeat conversion mode (e.g., in cases of c and d), write a 0 to admod0. after the current conversion has been completed, the repeat conversion mode terminates and admod0 is cleared to 0. switching to a halt state (idle2 mode with admod1 cleared to 0, idle1 mode or stop mode) immediately stops operation of the ad converter even when ad conversion is still in progress. in repeat conversion modes (e.g., in cases of c and d), when the halt is released, conversion restarts from the beginning. in single conversion modes (e.g., in cases of a and b), conversion does not restart when the halt is released (the converter remains stopped). table 3.11.2 shows the relationship between the ad conversion modes and interrupt requ ests. table 3.11.2 relationship between ad conversion modes and interrupt requests admod0 mode interrupt request generation channel fixed single conversion mode after completion of conversion x 0 0 channel scan single conversion mode after completion of scan conversion x 0 1 every conversion 0 channel fixed repeat conversion mode every forth conversion 1 1 0 channel scan repeat conversion mode after completion of every scan conversion x 1 1 x: don?t care (5) ad conversion time 84 states (4.7 s at f fph = 36 mhz) are required for the ad conversion of one channel. (6) storing and reading the results of ad conversion the ad conversion data upper and lowe r registers (adreg04 h/l to adreg37h/l) store the results of ad conversion. (adreg04h/l to adreg37h/l are read-only registers.) in channel fixed repeat conversion mo de, the conversion results are stored successively in registers adreg04h/l to adreg37h/l. in other modes the an0 and an4, an1 and an5, an2 and an6, an3 and an7 conversion results are stored in adreg04h/l, adreg15h/l, adreg26h/l , and adreg37h/l respectively. table 3.11.3 shows the correspondence between the analog input channels and the reg isters which are used to hold the results of ad conversion.
tmp91c829 2006-03-15 91c829-151 table 3.11.3 correspondence between analog inpu t channels and ad conversion result registers ad conversion result register a nalog input channel (port a) conversion modes other than at right channel fixed repeat conversion mode (every 4 th conversion) an0 adreg04h/l an4 an1 adreg15h/l an5 an2 adreg26h/l an6 an3 adreg37h/l an7 a dreg04h/l a dreg15h/l a dreg26h/l a dreg37h/l , bit0 of the ad conversion data lower register, is used as the ad conversion data storage flag. the storage flag indicates whether the ad conversion result register has been read or not. when a conversion result is stored in the ad conversion result register, the flag is set to 1. when either of the ad conversion result registers (adregxh or adregxl) is read, the flag is cleared to 0. reading the ad conversion result also clears the ad conversion end flag admod0 to 0. setting example: a. convert the analog input voltage on the an3 pin and write the result, to memory address 0800h using the ad interrupt (intad) processing routine. main routine: 7 6 5 4 3 2 1 0 inte0ad x 1 0 0 - - - - enable intad and set it to interrupt level 4. admod1 1 1 x x 0 0 1 1 set pin an3 to be the analog input channel. admod0 x x 0 0 0 0 0 1 start conversion in channel fixed single conversion mode. interrupt routine processing example: wa adreg37 read value of adreg37l and adreg37h into 16-bit general-purpose register wa. wa > > 6 shift contents read into wa six times to right and zero fill upper bits. (0800h) wa write contents of wa to memory address 0800h. b. this example repeatedly converts the analog input voltages on the three pins an0, an1, and an2, using channel scan repeat conversion mode. inte0ad x 0 0 0 - - - - disable intad. admod1 1 1 x x 0 0 1 0 set pins an0 to an2 to be the analog input channels. admod0 x x 0 0 0 1 1 1 start conversion in channel scan repeat conversion mode. x: don?t care, ? : no change
tmp91c829 2006-03-15 91c829-152 3.12 watchdog timer (runaway detection timer) the tmp91c829 features a watchdog timer for detecting runaway. the watchdog timer (wdt) is used to return the cpu to normal state when it detects that the cpu has started to malfunction (runaway) due to causes such as noise. when the watchdog timer detects a malfunction, it generates a non-maskable interrupt intwd to notify the cpu of the malfunction. connecting the watchdog timer output to the reset pin internally forces a reset. (the level of external reset pin is not changed.) 3.12.1 configuration figure 3.12.1 is a block diagram of the watchdog timer (wdt). internal reset wdmod wdmod reset wdt control register wdcr q r s 2 21 internal reset wdmod wdti interrupt f sys (f fph /2) selector 2 19 2 17 2 15 internal data bus write b1h write 4eh reset reset control binary counter (22 stage) figure 3.12.1 block diagram of watchdog timer note: the watchdog timer cannot operate by disturbance noise in some case. take care when design the device.
tmp91c829 2006-03-15 91c829-153 the watchdog timer consists of a 22-stage binary counter which uses the system clock (f sys ) as the input clock. the binary counter can output f sys /2 15 , f sys /2 17 , f sys /2 19 and f sys /2 21 . 0 wdt interrupt wdt clea r (soft ware) clear write code wdt counte r n overflow figure 3.12.2 normal mode the runaway is detected when an overflow occurs, and the watchdog timer can reset device. in this case, the reset time will be between 22 and 29 states (19.6 to 25.8 s at f fph = 36mhz, f osch = 2.25 state) is f fph /2, where f fph is generated by dividing the high-speed oscillator clock (f osch ) by sixteen through the clock gear function. overflow wdt counter n wdt interrupt 22 to 29 states (19.6 to 25.8 s at f osch = 36 mhz, f fph = 2.25 mhz) internal reset figure 3.12.3 reset mode
tmp91c829 2006-03-15 91c829-154 3.12.2 control registers the watchdog timer wdt is controlled by two control registers wdmod and wdcr. (1) watchdog timer mode register (wdmod) a. setting the detection time for the watchdog timer in this 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. on a reset this register is initialized to wdmod = 00. the detection times for wdt are shown in figure 3.12.4. b. watchdog timer enable/disable control register on a reset wdmod is initialized to 1, enabling the watchdog timer. to disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (b1h) to the watchdog timer control register . this makes it difficult for the watchdog timer to be disabled by runaway. however, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting to 1. c. watchdog timer out reset connection this register is used to connect the output of the watchdog timer with the reset terminal internally. since wdmodis initialized to 0 on a reset, a reset by the watchdog time r will not be performed. (2) watchdog timer control register (wdcr) this register is used to disable and clear the binary counter for the watchdog timer. ? disable control the watchdog timer can be disabled by clearing wdmod to 0 and then writing the disable code (b1h) to the wdcr register. wdmod 0 - - - - - - - clear wdmod to 0. wdcr 1 0 1 1 0 0 0 1 write the disable code (b1h). ? enable control set wdmod to 1. ? watchdog timer clear control to clear the binary counter and cause counting to resume, write the clear code (4eh) to the wdcr register. wdcr 0 1 0 0 1 1 1 0 write the clear code (4eh). note1: if it is used disable control, set the disable code (b1h) to wdcr after write the clear code (4eh) once. (please refer to setting example.) note2: if it is changed watchdog timer setting, change setting after set to disable condition once.
tmp91c829 2006-03-15 91c829-155 7 6 5 4 3 2 1 0 bit symbol wdte wdtp1 wdtp0 i2wdt rescr ? read/write r/w r/w r/w r/w after reset 1 0 0 0 0 0 wdmod (0300h) function wdt control 1: enable select detecting time 00: 2 15 /f sys 01: 2 17 /f sys 10: 2 19 /f sys 11: 2 21 /f sys idle2 0: stop 1: operate 1: internally connects wdl out to the reset pin always write ?0?. watchdog timer out control 0 ? 1 connects wdt out to a reset idle2 control 0 stop 1 operation watchdog timer detection time fc = 36 mhz watchdog timer detection time wdmod syscr1 gear value 00 01 10 11 000 (fc) 1.82 ms 7.28 ms 29.13 ms 116.51 ms 001 (fc/2) 3.64 ms 14.56 ms 58.25 ms 233.02 ms 010 (fc/4) 7.28 ms 29.13 ms 116.51 ms 466.03 ms 011 (fc/8) 14.56 ms 58.25 ms 232.02 ms 932.07 ms 100 (fc/16) 29.13 ms 116.51 ms 466.03 ms 1864.14 ms watchdog timer enable/disable control 0 disabled 1 enabled figure 3.12.4 watchdog timer mode register 7 6 5 4 3 2 1 0 bit symbol ? wdcr (0301h) read/write w after reset ? function b1h: wdt disable code 4eh: wdt clear code disable/clear wdt b1h disable code 4eh clear code others don?t care figure 3.12.5 watchdog timer control register read -modify -write instruction is prohibited
tmp91c829 2006-03-15 91c829-156 3.12.3 operation the watchdog timer generates an intwd interrupt when the detection time set in the wdmod has elapsed. the watchdog timer must be zero cleared in software before an intwd interrupt will be generated. if the cpu malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an intwd interrupt will be generated. the cpu will detect malfunction (runaway) due to the intwd interrupt and in this case it is possible to return to the cpu to normal operation by means of an anti-mulfunction program. by connecting the watchdog timer out pin to a peripheral device?s reset input, the occurrence of a cpu malfunction can also be relayed to other devices. the watch dog timer works immediately after reset. the watchdog timer does not operate in idle1 or stop mode, as the binary counter continues counting during bus release (when busak goes low). when the device is in idle2 mode, the operation of wdt depends on the wdmod setting. ensure that wdmod is set before the device enters idle2 mode. example: a. clear the binary counter. wdcr 0 1001110 write the clear code (4eh). b. set the watchdog timer detection time to 2 17 /f sys . wdmod 1 01----- c. disable the watchdog timer. wdmod 0 -----xx clear wdte to 0. wdcr 1 0110001 write the disable code (b1h).
tmp91c829 2006-03-15 91c829-157 3.13 multi vector control 3.13.1 multi vector controller (1) outline by rewriting the value of multi vector control register (mvec0 and mvec1), a vector table is arbitrarily movable. (2) control register the amount of 228 bytes become an interruption vector area from the value set as vector control register (mvec0 and mvec1). vector control register composition 7 6 5 4 3 2 1 0 bit symbol vec7 vec6 vec5 vec4 vec3 vec2 vec1 vec0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 1 1 1 1 1 1 1 1 mvec0 (00aeh) function vector address a15 to a8 7 6 5 4 3 2 1 0 bit symbol vec15 vec14 vec13 vec12 vec11 vec10 vec9 vec8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 1 1 1 1 1 1 1 1 mvec1 (00afh) function vector address a23 to a16 circuit composition note: write mvec1, mvec0 after making an interruption prohibition state. al23 cs al8 register (mvec0) cpu output address al23 to al8 internal address a 23 to a8 cs circuit from ffff28h to ffffffh a l23 to al8 a8 a23 s a y b register (mvec1)
tmp91c829 2006-03-15 91c829-158 3.13.2 multi boot mode (1) outline the tmp91c829 has multi boot mode available as an on-board programming operation mode. when in multi boot mode, the boot rom is mapped into memory space. this boot rom is a mask rom that contains a program to rewrite the flash memory on board. rewriting is accomplished by connecting the tmp91c829?s sio and the programming tool (controller) and then sending commands from the controller to the target board. the boot program included in the boot rom only has the function of a loader for transferring program data from an external source into the device?s internal ram. rewriting can be performed by uart. from 1000h to 105fh in device?s internal ram is work area of boot program. don?t transfer program data in this work area. figure 3.12.1 shows an example of how to connect the programming controller and the target board (when rom has 16-bit data bus). figure 3.13.1 example for connect ing units for on-board programming (2) mode setting to execute on-board programming, start the tmp91c829 in multi boot mode. settings necessary to start up in multi boot mode are shown below. boot = l reset = after setting the boot pin each to the above conditions and a reset , the tmp91c829 start up in multi boot mode. boot/normal programming controller uart 3 pin rom d0 to d15 a d0 to ad15 cs oe we tmp91c829 a1 to a16 d0 to d15 cs2 rd wr boot txd0 (output) rxd0 (input) rts0 (p83) (output)
tmp91c829 2006-03-15 91c829-159 (3) memory map figure 3.12.2 shows memory maps for multi chip and multi boot modes. when start up in multi boot mode, internal boot ro m is mapped in fff800h address, the boot program starts up. when start up in multi chip mode, internal boot rom is mapped in 1f800h address, it can be made to operate arbitrarily by the user. program starting address is 1f800h. multi chip mode multi boot mode 000000h 000100h internal i/o (4 kbytes) 000000h 000100h internal i/o (4 kbytes) 001000h internal ram (8 kbytes) 001000h internal ram (8 kbytes) 003000h external memory 003000h 01f800h 16-mbyte area 01ffffh internal boot rom (2 kbytes) (r32) ( ? r32) external memory external memory (r32 + ) (r32 + d8/16) (r32 + r8/16) (nnn) fff800h fffeffh internal boot rom (2 kbytes) ffff00h ffffffh vector table (256 bytes) ffff00h ffffffh vector table (256 bytes) ( = internal area) figure 3.13.2 tmp91c829 memory map direct area (n)
tmp91c829 2006-03-15 91c829-160 (4) sio interface specifications the following shows the sio communication format in multi boot mode. before on-board programming can be exec uted, the communication format on the programming controller side must also be setup in the same way as for the tmp91c829. note that although the default baud rate is 9600 bps, it can be changed to other values as shown in table 3.13.3. serial transfer mode: uart (asynchronous communication) mode, full-duplex communication. data length: 8 bits. parity bit: none. stop bit: 1 bit. handshake: microcontroller (p83) programming controller. baud rate (default): 9600 bps. (5) sio data transfer format table 3.13.1 through 3.13.6 show supported fr equencies, data transfer format, baud rate modification co mmands, operation commands, version management information, and frequency measurement result with data store location, respectively. also refer to the description of boot program operation in the latter pages of this manual as you read these tables. table 3.13.1 supported frequencies 16.000 mhz 20.000 mhz 22.579 mhz 25.000 mhz 32.000 mhz 33.868 mhz 36.000 mhz table 3.13.2 transfer format number of bytes transferred transfer data from controller to tmp91c829 baud rate transfer data from tmp91c829 to controller boot rom 1st byte 2nd byte matching data (5ah) ? 9600 bps 9600 bps ? (frequency measurement and baud rate auto set) ok: echo back data (5ah) error: nothing transmitted 3rd byte : 6th byte ? 9600 bps version management information (see table 3.13.5) 7th byte ? 9600 bps frequency information (see table 3.13.6) 8th byte 9th byte baud rate modification command (see table 3.13.3) ? 9600 bps 9600 bps ? ok: echo back data error: error code x 3 10th byte : n?th ? 4 byte user program extended intel hex format (binary) changed new baud rate error: operation stop by checksum error n?th ? 3 byte ? changed new baud rate ok: sum (high) (see (6) (iii) notes on sum) n?th ? 2 byte ? changed new baud rate ok: sum (low) n?th ? 1 byte n?th byte user program start command (c0h) (see table 3.13.4) ? changed new baud rate changed new baud rate ? ok: echo back data (c0h) error: error code x 3 ram ? jump to user program start address error code x 3 means sending an error code three times. ex ample, when error code is 62h, tmp91c829 sends 62h three times. about error code, see (6)(b) error code.
tmp91c829 2006-03-15 91c829-161 table 3.13.3 baud rate modification command baud rate (bps) 9600 19200 38400 57600 115200 modification command 28h 18h 07h 06h 03h table 3.13.4 operation command operation command operation c0h start user program table 3.13.5 version management information version information ascii code frm1 46h, 52h, 4dh, 31h table 3.13.6 frequency m easurement result data frequency of resonator (mhz) 16.000 20.000 22.579 25.000 32.000 33.868 36.000 1000h (ram store address) 00h 01h 02h 03h 04h 05h 06h (6) description of sio boot program operation when you start the tmp91c829 in multi boot mode, the boot program starts up. the boot program provides the ram loader function described below. ram loader the ram loader transfers the data sent from the controller in extended intel hex format into the internal ram. when the transfer has terminated normally, the ram loader calculates the sum and sends the result to the controller before it starts executing the user program. the execution start address is the first address received. this ram loader function provides the user?s own way to control on-board programming. to execute on-board programming in the user program, you need to use the flash memory command sequence to be connected. (must be matched to the flash memory addresses in multi boot mode.) a. operational procedure of ram loader 1. connect the serial cable. make sure to perform connection before resetting the microcontroller. 2. set the boot pin to ?boot? and reset the microcontroller. 3. the receive data in the 1st byte is the matching data. when the boot program starts in multi boot mode, it goes to a state in which it waits for the matching data to receive. upon receiving the matching data, it automatically adjusts the serial channels? initial baud rate to 9600 bps. the matching data is 5ah. 4. the 2nd byte is used to echo back 5ah to the controller upon completion of the automatic baud rate setting in the 1st byte. if the device fails in automatic baud rate setting, it goes to an idle state. 5. the 3rd byte through 6th byte are used to send the version management information of the boot program in ascii code. the controller should check that the correct version of the boot program is used.
tmp91c829 2006-03-15 91c829-162 6. the 7th byte is used to send information of the measured frequency. the controller should check that the frequency of the resonator is measured correctly. 7. the receive data in the 8th byte is the baud rate modification data. the five kinds of baud rate modification data shown in table 3.13.3 are available. even when you do n ot change the baud rate, be sure to send the initial baud rate data (28h; 9600 bps). baud rate modification becomes effective after the echo back transmission is completed. 8. the 9th byte is used to echo back the received data to the controller when the data received in the 8th byte is one of the baud rate modification data corresponding to the device?s operating frequency. then the baud rate is changed. if the received baud rate data does not correspond to the device?s operating frequency, the device goes to an idle state after sending 3 byte s of baud rate modi fication error code (62h). 9. the receive data in the 10th byte through n? th ? 4 byte is received as binary data in extended intel hex format. no received data is echoed back to the controller. the ram loader processing routine ignores the received data until it receives the start mark (3ah for ?:?) in extended inte l hex format. nor does it send error code to the controller. after receiving the start mark, the routine receives a range of data from the data length to checksum and writes the received data to the specified ram addr esses successively. after receiving one record of data from start mark to checksum, the routine goes to a start mark waiting state again. if a receive error or checksum error of extended intel hex format occurs, the device goes to an idle state without returning error code to the controller. because the ram loader processing routine executes a sum calculation routine upon detecting the end record, the controller should be placed in a sum waiting state after sending the end record to the device. 10. the n?th ? 3 byte and the n?th ? 2 byte are the sum value that is sent to the controller in order of upper byte and lo wer byte. for details on how to calculate the sum, refer to ?notes on sum? in the latter page of this manual. the sum calculation is performed only when no write error, receive error, or extended intel hex format error has been encountered af ter detecting the end record. soon after calculation of sum, the device sends the sum data to the controller. the controller should determine whether writing to the ram has terminated normally depending on whether the sum value is received after sending the end record to the device. 11. after sending the sum, the device goes to a state waiting for the user program start code. if the sum value is correct, the controller should send the user program start command to the n?th ? 1 by te. the user program start command is c0h. 12. the n?th byte is used to echo back the user program start code to the controller. after sending the echo back to the controll er, the stack pointer is set to 105fh and the boot program jumps to the first address that is received as data in extended intel hex format. 13. if the user program start code is wrong or a receive error occurs, the device goes to an idle state after returning three byte s of error code to the controller.
tmp91c829 2006-03-15 91c829-163 b. error code the boot program sends the processing status to the controller using various code. the error code is listed in the table below. table 3.13.7 error code error code meaning of error code 62h baud rate modification error occurred. 64h operation command error occurred. a1h framing error in received data occurred. a3h overrun error in received data occurred. * 1: when a receive error occurs when receiving the user program, the device does not send the error code to the controller. * 2: after sending the error code, the device goes to an idle state. c. notes on sum 1. calculation method sum consists of byte + byte ? + byte, the sum of which is returned in word as the result. namely, data is read out in byte and sum of which is calculated, with the result returned in word. example: if the data to be calculated consists of the four bytes a1h shown to the left, sum of the data is: b2h a1h + b2h + c3h + d4h = 02eah c3h sum (high) = 02h d4h sum (low) = eah 2. calculation data the data from which sum is calculated is the ram data from the first address received to the last address received. the received ram write data is not the only data to be calculated for sum. even when the received addresses are noncontiguous and there are some unwritten areas, data in the entire memory area is calculated. the user program should not contain unwritten gaps. d. notes on extended intel hex format (binary) 1. after receiving the checksum of a record, the device waits for the start mark (3ah for ?:?) of the next record. therefore, the device ignores all data received between records during that time unless the data is 3ah. 2. make sure that once the controller program has finished sending the checksum of the end record, it does not send anything and waits for two byes of data to be received (upper and lower bytes of sum). this is because after receiving the checksum of the end record, the boot program calculates the sum and returns the calculated sum in two bytes to the controller. 3. it becomes the cause of incorrect operation to write to areas out of device?s internal ram. therefore, when an extended record is transmitted, be sure to set a paragraph address to 0000h. 4. always make sure the first record type is an extended record. because the initial value of the address pointer is 00h.
tmp91c829 2006-03-15 91c829-164 5. transmit a user program not by the ascii code but by binary. however, start mark ?:? is 3ah (ascii code). example: transmit data in the case of writing in 16-byte data from address 1060h data record 3a 10 1060 00 0607f100030000f201030000b1f16010 77 data checksum record type address number of data ?:? (start mark) end record 3a 00 0000 01 ff checksum record type address number of data ?:? (start mark) e. error when receiving user program if the following errors occur in extended intel hex format when receiving the user program, the device goes to an idle state. ? when the record type is not 00h, 01h, 02h ? when a checksum error occurs f. error between frequency measurement and baud rate the boot program measures the resonator frequency when receiving matching data. if an error is under 3%, the boot program decides on that frequency. since there is an overlap between the margin of 3% for 32.000 mhz and 33.868 mhz, the boundary is set at the intermediate value between the two. the baud rate is set based on the measured frequency. each baud rate includes a set error shown in table 3.13.8. for example, in the case of 20.00 0 mhz and 9600 bps, the baud rate is actually set at 9615.38 bps with an e rror of 0.2%. to establish communication, the sum of the baud rate set error shown in table 3.13.8 and the frequency error nee d to be under 3%. table 3.13.8 set error of each baud rate (%) 9600 bps 19200 bps 38400 bps 57600 bps 115200 bps 16.000 mhz 0.2 0.2 0.2 ? 0.6 ? 0.8 20.000 mhz 0.2 0.2 0.2 ? 0.2 0.9 22.579 mhz 0 0.7 0 0 0 25.000 mhz ? 0.2 0.5 ? 0.1 0.5 0.5 32.000 mhz 0.1 0.2 0.2 0 0.6 33.868 mhz 0.2 0.2 0.2 0 0.7 36.000 mhz 0.2 0.2 ? 0.7 0.2 0.2
tmp91c829 2006-03-15 91c829-165 (7) ports setup of the boot program only ports shown in table 3.13.9 are setup in the boot pr ogram. at the time of boot program use, be careful of the influence on a user system. do not use cs0 space and p60 in the system which uses the boot program. other ports are not setting up, and are the reset state or the state of boot program starting. table 3.13.9 ports setting list ports function input/output high/low notes p60 cs0 output ? cs0 space is 20000h to 201ffh. p61 port output ? p62 port output high p63 port output ? p80 port input high not open-drain port. this port becomes txd0 after matching data reception. p81 rxd0 input high p82 port input ? p83 port input low this port is set as the output and becomes rts0 after matching data reception. p84 port input ? p85 port input ? p86 port input ? p87 port input ? ? : un-setting up (8) setting method of microcontroller peripherals although p83 has the rts0 function, it is initially in a high-impedance state and not set as rts0 . to establish serial communication, a ttach a pull-down resistor to p83.
tmp91c829 2006-03-15 91c829-166 4. electrical characteristics 4.1 maximum ratings parameter symbol rating unit power supply voltage (5 v) hvcc ? 0.5 to 5.75 power supply voltage (3 v) lvcc ? 0.5 to 4.0 input voltage vin ? 0.5 to vcc + 0.5 v output current (per pin) iol 2 output current (per pin) ioh ? 2 output current (total) iol 80 output current (total) ioh ? 80 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) tsolder 260 storage temperature tstg ? 65 to 150 operating temperature topr ? 20 to 70 c note: the maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exce eded. if any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. solderability of lead free products te s t parameter test condition note (1) use of sn-37pb solder bath solder bath temperature =230 c, dipping time = 5 seconds the number of times = one, use of r-type flux solderability (2) use of sn-3.0ag-0.5cu solder bath solder bath temperature =245 c, dipping time = 5 seconds the number of times = one, use of r-type flux (use of lead free) pass: solderability rate until forming 95%
tmp91c829 2006-03-15 91c829-167 4.2 dc characteristics (1/2) parameter symbol condition min typ. (note) max unit power supply voltage (5 v) (avcc = hvcc) (avss = dvss = 0 v) hvcc fc = 10 to 36 mhz 4.75 5.25 v power supply voltage (3 v) lvcc fc = 10 to 36 mhz 3.0 3.6 v d0 to d7, p10 to p17 (d8 to d15) hv il 0.8 other ports v il1 0.3 hvcc reset , nmi p56 (int0), p70 (int1) p72 (int2), p73 (int3) p75 (int4), p90 (int5) v il2 0.25 hvcc am0, am1 v il3 0.3 input low voltage x1 v il4 ? 0.3 0.2 lvcc d0 to d7, p10 to p17 (d8 to d15) v ih 2.2 other ports v ih1 0.7 hvcc reset , nmi p56 (int0), p70 (int1) p72 (int2), p73 (int3) p75 (int4), p90 (int5) v ih2 0.75 hvcc am0, am1 v ih3 hvcc ? 0.3 hvcc + 0.3 input low voltage x1 v ih4 0.8 lvcc lvcc + 0.3 v output low voltage v ol iol = 1.6 ma 0.45 output high voltage v oh ioh = ? 400 a 4.2 v input leakage current ili 0.02 5 0.0 vin hvcc output leakage current ilo 0.05 10 0.2 vin hvcc ? 0.2 a power down voltage (at stop, ram back up) vstop 2.0 3.6 vil2 = 0.2 hvcc, v ih2 = 0.8 hvcc v reset pull-up resistor rrst 40 200 hvcc = 5 v 5% k pin capacitance cio 10 fc = 1 mhz pf schmitt width reset , nmi , int0 to int5 vth 0.4 1.0 v programmable pull-up resistor rkh 40 200 hvcc = 5 v 5% k normal (note 2) icc 40 hvcc = 5 v 5% lvcc = 3.0 to 3.6 v fc = 36 mhz idle2 20 idle1 14 ma stop 100 hvcc = 5 v 5% lvcc = 3.0 to 3.6 v ta 70c a note 1: typical values are for when ta = 25c, hvcc = 5.0 v and lvcc = 3.3 v unless otherwise noted. note 2: icc measurement conditions (normal): all functions are operational; output pi ns are open and input pins are fixed.
tmp91c829 2006-03-15 91c829-168 4.3 ac characteristics (1) hvcc = 5.0 v 5%, lvcc = 3.0 to 3.6 v variable f fph = 36 mhz no. parameter symbol min max min max unit 1 f fph period ( = x ) t fph 27.6 100 27.6 ns 2 a0 to a23 valid rd / wr fall t ac x ? 26 1.6 ns 3 rd rise a0 to a23 hold t car 0.5x ? 13.8 0.0 ns 4 wr rise a0 to a23 hold t caw x ? 13 14.6 ns 5 a0 to a23 valid d0 to d15 input t ad 3.5x ? 40 56.6 ns 6 rd fall d0 to d15 input t rd 2.5x ? 34 35.0 ns 7 rd low width t rr 2.5x ? 25 44.0 ns 8 rd rise d0 to d15 hold t hr 0 0 ns 9 wr low width t ww 2.0x ? 25 30.2 ns 10 d0 to d15 valid wr rise t dw 1.5x ? 35 6.4 ns 11 wr rise d0 to d15 hold (1+n) waits t wd x ? 25 2.6 ns 12 a0 to a23 valid wait input (1+n) waits t aw 3.5x ? 60 36.6 ns 13 rd / wr fall wait hold t cw 2.5x + 0 69.0 ns 14 a0 to a23 valid port input t aph 3.5x ? 76 20.6 ns 15 a0 to a23 valid port hold t aph2 3.5x 96.6 ns 16 a0 to a23 valid port valid t apo 3.5x + 60 156.6 ns ac measuring conditions output level: high = 2.2 v, low = 0.8 vcc, cl = 50 pf input level: high = 2.4 v, low = 0.45 v (d0 to d15) high 0.8 vcc, low 0.2 vcc (except d0 to d15) note: symbol ?x? in the above ta ble means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting.
tmp91c829 2006-03-15 91c829-169 (2) read cycle t hr f fph a0 to a23 port input (note) rd d0 to d15 t fph t aw t ap t ad t ac t rr t ca r d0 to d15 t cw t aph2 csn wait t rd note: since the cpu accesses the internal area to read data from a port, the control signals of external pins such as rd and cs are not enabled. therefore, the above waveform diagram should be regarded as depicting internal operation. please also note that the timing and ac characteristics of port input/output shown above are typical repr esentation. for details, contact your local toshiba sales representative.
tmp91c829 2006-03-15 91c829-170 (3) write cycle d0 to d15 t wd t apo t ww t dw f fph a0 to a23 port output (note) d0 to d15 wait csn t caw wr , wait note: since the cpu accesses the internal area to wr ite data to a port, the cont rol signals of external pins such as wr and cs are not enabled. therefore, the above waveform diagram should be regarded as depicting internal operation. please also note that the timing and ac characteristics of port input/output shown above are typical repr esentation. for details, contact your local toshiba sales representative.
tmp91c829 2006-03-15 91c829-171 4.4 ad conversion characteristics avcc = hvcc, avss = vss parameter symbol min typ. max unit analog reference voltage ( + ) vrefh hv cc ? 0.2 v hv cc hv cc analog reference voltage ( ? ) vrefl dv ss dv ss dvss + 0.2 v analog input voltage range vain v refl v refh v analog current for analog reference voltage = 1 0.85 1.20 ma = 0 iref (vrefl = 0v) 0.02 5.0 a error (not including quantizing errors) ? 1.0 4.0 lsb note 1: 1 lsb = (vrefh ? vrefl)/1024 [v] note 2: the value for icc includes the current which flows through the avcc pin.
tmp91c829 2006-03-15 91c829-172 4.5 serial channel timi ng (i/o internal mode) note: symbol ?x? in the above t able means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting. (1) sclk input mode variable 36 mhz (note) parameter symbol min max min max unit sclk period t scy 16x 0.44 s output data sclk rising/falling edge * t oss t scy /2 ? 4x ? 85 25 ns sclk rising/falling edge * output data hold t ohs t scy /2 + 2x + 0 276 ns sclk rising/falling edge * input data hold t hsr 3x + 10 92 ns sclk rising/falling edge * valid data input t srd t scy ? 0 440 ns valid data input sclk rising/falling edge * t rds 0 0 ns * ) sclk rising/falling edge: the rising edge is used in sclk rising mode. the falling edge is used in sclk falling mode. note: at t scy = 16x (2) sclk output mode variable 36 mhz (note) parameter symbol min max min max unit sclk period (programable) t scy 16x 8192x 0.44 s output data sclk rising/falling edge * t oss t scy /2 ? 40 180 ns sclk rising/falling edge * output data hold t ohs t scy /2 ? 40 180 ns sclk rising/falling edge * input data hold t hsr 0 0 ns sclk rising/falling edge * valid data input t srd t scy /2 ? 1x ? 90 324 ns valid data input sclk rising/falling edge * t rds 1x + 90 117 ns * ) sclk rising/falling edge: the rising edge is used in sclk rising mode. the falling edge is used in sclk falling mode. note: at t scy = 16x t rds t srd t hsr t scy output data txd sclk scl k 0 t oss t ohs 1 3 01 3 2 2 valid input data rxd valid valid valid
tmp91c829 2006-03-15 91c829-173 4.6 event counter (ta0in, ta4in, tb0in0, tb0in1) variable 36 mhz parameter symbol min max min max unit clock perild t vck 8x + 100 320 ns clock low level width t vckl 4x + 40 150 ns clock high level width t vckh 4x + 40 150 ns note: symbol ?x? in the above ta ble means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting . 4.7 interrupts note: symbol ?x? in the above t able means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting. (1) nmi , int0 to int5 interrupts variable 36 mhz parameter symbol min max min max unit nmi , int0 to int5 low level width t intal 4x + 40 150 ns nmi , int0 to int5 high level width t intah 4x + 40 150 ns
tmp91c829 2006-03-15 91c829-174 4.8 bus request/bus acknowledge busak a 0 to a23, rd , wr cs0 to cs3 , hwr d0 to d15 t cbal t aba t baa (note 2) (note 2) (note 1) busrq variable f fph = 36 mhz parameter symbol min max min max unit output buffer to busak low t aba 0 80 0 80 ns busak high to output buffer on t baa 0 80 0 80 ns note 1: even if the busrq signal goes low, the bus will not be released while the wait signal is low. the bus will only be released when busrq goes low while wait is high. note 2: this line shows only that t he output buffer is in the off state. it does not indicate that the signal level is fixed. just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capa citance. therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. the internal programmable pull-up/pull-down re sistor is switched between the active and non-active states by the internal signal.
tmp91c829 2006-03-15 91c829-175 5. table of sfrs the special function registers (sfrs) include the i/o ports and peripheral control registers allocated to the 4-kbyte address space from 000000h to 000fffh. (1) i/o port (2) i/o port control (3) interrupt control (4) chip select/wait control (5) clock gear (6) 8-bit timer (7) 16-bit timer (8) uart/serial channel (9) ad converter (10) watchdog timer (11) multi vector controller symbol address name 7 6 1 0 bit symbol read/write initial value after reset remarks table layout note: ?prohibit rmw? in the a table means that y ou cannot use rmw instructions on these register. example: when setting bit0 only of the register px cr, the instruction ?set 0, (pxcr)? cannot be used. the ld (transfer) instruction must be used to write all eight bits. read/write r/w: both read and write are possible. r: only read is possible. w: only write is possible. w *: both read and write are possible (when this bit is read as 1). prohibit rmw: read-modify-write instructions are prohibited. (the ex, add, adc, bus, sbc, inc, dec, and, or, xor, st cf, res, set, chg, tset, rlc, rrc, rl, rr, sla, sra, sll, srl, rld, and rrd instruction are read-modify-write instructions.) r/w * : read-modify-write is prohibited when controlling the pull-up resistor.
tmp91c829 2006-03-15 91c829-176 table 5.1 address map sfrs [1] port address name address name address name 0000h 0010h p5cr 0020h 1h p1 1h p5fc 1h 2h 2h p6 2h 3h 3h p7 3h 4h p1cr 4h p6cr 4h 5h 5h p6fc 5h 6h p2 6h p7cr 6h 7h 7h p7fc 7h 8h 8h p8 8h 9h p2fc 9h p9 9h ah ah p8cr ah bh bh p8fc bh ch ch p9cr ch dh p5 dh p9fc dh eh eh pa eh fh fh fh ode address name 0070h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh pz eh pzcr fh pzfc [2] intc address name address name address name 0080h dma0v 0090h inte0ad 00a0h intetc01 1h dma1v 1h inte12 1h intetc23 2h dma2v 2h inte34 2h 3h dma3v 3h inte5 3h 4h 4h 4h 5h 5h inteta01 5h 6h 6h inteta23 6h 7h 7h inteta45 7h 8h intclr 8h 8h 9h dmar 9h intetb0 9h ah dmab ah ah bh bh intetb0v bh ch iimc0 ch intes0 ch dh iimc1 dh intes1 dh eh eh eh mvec0 fh fh fh mvec1 note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91c829 2006-03-15 91c829-177 [3] cs/wait [4] cgear, dfm address name address name 00c0h b0cs 00e0h syscr0 1h b1cs 1h syscr1 2h b2cs 2h syscr2 3h b3cs 3h emccr0 4h 4h emccr1 5h 5h 6h 6h 7h bexcs 7h 8h msar0 8h 9h mamr0 9h ah msar1 ah bh mamr1 bh ch msar2 ch dh mamr2 dh eh msar3 eh fh mamr3 fh [5] tmra address name address name 0100h ta01run 0110h ta45run 1h 1h 2h ta0reg 2h ta4reg 3h ta1reg 3h ta5reg 4h ta01mod 4h ta45mod 5h ta1ffcr 5h ta5ffcr 6h 6h 7h 7h 8h ta23run 8h 9h 9h ah ta2reg ah bh ta3reg bh ch ta23mod ch dh ta3ffcr dh eh eh fh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91c829 2006-03-15 91c829-178 [6] tmrb [7] uart/sio address name address name 0180h tb0run 0200h sc0buf 1h 1h sc0cr 2h tb0mod 2h sc0mod0 3h tb0ffcr 3h br0cr 4h 4h br0add 5h 5h sc0mod1 6h 6h 7h 7h 8h tb0rg0l 8h sc1buf 9h tb0rg0h 9h sc1cr ah tb0rg1l ah sc1mod0 bh tb0rg1h bh br1cr ch tb0cp0l ch br1add dh tb0cp0h dh sc1mod1 eh tb0cp1l eh fh tb0cp1h fh [8] 10-bit adc address name address name 02a0h adreg04l 02b0h admod0 1h adreg04h 1h admod1 2h adreg15l 2h 3h adreg15h 3h 4h adreg26l 4h 5h adreg26h 5h 6h adreg37l 6h 7h adreg37h 7h 8h 8h 9h 9h ah ah bh bh ch ch dh dh eh eh fh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). [9] wdt address name 0300h wdmod 1h wdcr 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
tmp91c829 2006-03-15 91c829-179 (1) i/o port symbol name address 7 6 5 4 3 2 1 0 p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 port 1 01h data from external port (output latch register is cleared to 0.) p27 p26 p25 p24 p23 p22 p21 p20 r/w p2 port 2 06h 1 1 1 1 1 1 1 1 p56 p55 p54 p53 r/w* data from external port (output latch register is set to 1.) p5 port 5 0dh 0(output latch register): pull-up resistor off 1(output latch register): pull-up resistor on p63 p62 p61 p60 r/w p6 port 6 12h 1 0 1 1 p75 p74 p73 p72 p71 p70 r/w p7 port 7 13h data from external port (output latch register is set to 1.) p87 p86 p85 p84 p83 p82 p81 p80 r/w data from external port (output latch register is set to 1.) p8 port 8 18h 0(output latch register): pull-up resistor off 1(output latch register): pull-up resistor on p96 p95 p94 p93 p90 r/w r/w p9 port 9 19h data from external port (output latch register is set to 1.) data from external port (output latch register is set to 1.) pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 r pa port a 1eh data from external port pz3 pz2 r/w pz port z 7dh data from external port (output latch register is set to 1.)
tmp91c829 2006-03-15 91c829-180 (2) i/o port control (1/2) symbol name address 7 6 5 4 3 2 1 0 p17c p16c p15c p14c p13c p12c p11c p10c w 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 p1cr port 1 control 04h (prohibit rmw) 0: input 1: output p27f p26f p25f p24f p23f p22f p21f p20f w 1 1 1 1 1 1 1 1 p2fc port 2 function 09h (prohibit rmw) 0: port 1: address bus (a23 to a16) p56c p55c p54c p53c w 0 0 0 0 p5cr port 5 control 10h (prohibit rmw) 0: input 1: output p56f p54f p53f w w 0 0 0 p5fc port 5 function 11h (prohibit rmw) 0: port 1: int0 0: port 1: busak 0: port 1: busrq p63f p62f p61f p60f w 0 0 0 0 p6fc port 6 function 15h (prohibit rmw) 0: port 1: cs3 0: port 1: cs2 0: port 1: cs1 0: port 1: cs0 p75c p74c p73c p72c p71c p70c w 0 0 0 0 0 0 p7cr port 7 control 16h (prohibit rmw) 0 : input 1 : output p72f2 p75f p74f p73f p72f1 p71f p70f w w w w w w w 0 0 0 0 0 0 0 p7fc port 7 function 17h (prohibit rmw) 0: port 1: int2 0: port 1: int4 0: port 1: ta5out 0: port 1: int3 0: port 1: ta3out 0: port 1: ta1out 0: port 1: int1 p87c p86c p85c p84c p83c p82c p81c p80c w 0 0 0 0 0 0 0 0 p8cr port 8 control 1ah (prohibit rmw ) 0: input 1: output p87f p86f p84f p83f p82f p80f w w w w w w 0 0 0 0 0 0 p8fc port 8 function 1bh (prohibit rmw) 0: port 1: 1sts 0: port 1: sclk1 0: port 1: txd1 0: port 1: 0sts 0: port 1: sclk0 0: port 1: txd0
tmp91c829 2006-03-15 91c829-181 i/o port control (2/2) symbol name address 7 6 5 4 3 2 1 0 p96c p95c p94c p93c p90c w w 0 0 0 0 0 p9cr port 9 control 1ch (prohibit rmw) 0: input 1: output 0: input 1: output p96f p95f p90f w w w 0 0 0 p9fc port 9 function 1dh (prohibit rmw) 0: port 1: tb0out1 0: port 1: tb0out0 0: port 1: int5 pz3c pz2c w 0 0 pzcr port z control 7eh (prohibit rmw) 0: input 1: output p z 2 f w 0 pzfc port z function 7fh (prohibit rmw) 0 : p o r t 1: hwr ode84 ode80 w w 0 0 ode serial open drain 2fh (prohibit rmw) 1: p84ode 1: p80ode
tmp91c829 2006-03-15 91c829-182 (3) interrupt control (1/3) symbol name address 7 6 5 4 3 2 1 0 intad int0 iadc iadm2 iadm1 iadm0 i0c i0m2 i0m1 i0m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte0ad interrupt enable 0 & ad 90h 1: intad interrpt request level 1: int0 interrpt request level int2 int1 i2c i2m2 i2m1 i2m0 i1c i1m2 i1m1 i1m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte12 interrupt enable 2/1 91h 1: int2 interrupt request level 1: int1 interrpt request level int4 int3 i4c i4m2 i4m1 i4m0 i3c i3m2 i3m1 i3m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte34 interrupt enable 4/3 92h 1: int4 interrupt request level 1: int3 interrpt request level i n t 5 i5c i5m2 i5m1 i5m0 r r/w 0 0 0 0 inte5 interrupt enable 5 93h 1 : i n t 5 interrpt request level intta1 (tmra1) intta0 (tmra0) ita1c ita1m2 ita1m1 ita1m0 ita0c ita0m2 ita0m1 ita0m0 r r/w r r/w 0 0 0 0 0 0 0 0 inteta01 interrupt enable timer a 1/0 95h 1: intta1 interrpt request level 1: intta0 interrpt request level intta3 (tmra3) intta2 (tmra2) ita3c ita3m2 ita3m1 ita3m0 ita2c ita2m2 ita2m1 ita2m0 r r/w r r/w 0 0 0 0 0 0 0 0 inteta23 interrupt enable timer a 3/2 96h 1: intta3 interrpt request level 1: intta2 interrpt request level intta5 (tmra5) intta4 (tmra4) ita5c ita5m2 ita5m1 ita5m0 ita4c ita4m2 ita4m1 ita4m0 r r/w r r/w 0 0 0 0 0 0 0 0 inteta45 interrupt enable timer a 5/4 97h 1: intta5 interrpt request level 1: intta4 interrpt request level inttb01 (tmrb0) inttb00 (tmrb0) itb01c itb01m2 itb01m1 itb01m0 i tb00c itb00m2 itb00m1 itb00m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetb0 interrupt enable timer b0 99h 1: inttb01 interrpt request level 1: inttb00 interrpt request level inttbof0 (tmrb0 overflow) itf0c itf0m2 itf0m1 itf0m0 r r/w 0 0 0 0 intetb0v interrupt enable timer b0 (overflow) 9bh 1: inttbof0 interrpt request level
tmp91c829 2006-03-15 91c829-183 interrupt control (2/3) symbol name address 7 6 5 4 3 2 1 0 inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 r r/w r r/w 0 0 0 0 0 0 0 0 intes0 interrupt enable serial 0 9ch 1: inttx0 interrpt request level 1: intrx0 interrpt request level inttx1 intrx1 itx1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 r r/w r r/w 0 0 0 0 0 0 0 0 intes1 interrupt enable serial 1 9dh 1: inttx1 interrpt request level 1: intrx1 interrpt request level inttc1 inttc0 itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 r r/w r r/w intetc01 interrupt enable tc0/1 a0h 0 0 0 0 0 0 0 0 inttc3 itc2m0 itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 r r/w r r/w intetc23 interrupt enable tc2/3 a1h 0 0 0 0 0 0 0 0
tmp91c829 2006-03-15 91c829-184 interrupt control (3/3) symbol name address 7 6 5 4 3 2 1 0 dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 r/w 0 0 0 0 0 0 dma0v dma 0 request vector 80h dma0 start vector dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 r/w 0 0 0 0 0 0 dma1v dma 1 request vector 81h dma1 start vector dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 r/w 0 0 0 0 0 0 dma2v dma 2 request vector 82h dma2 start vector dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 r/w 0 0 0 0 0 0 dma3v dma 3 request vector 83h dma3 start vector clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 w 0 0 0 0 0 0 intclr interrupt clear control 88h (prohibit rmw) clear interrupt request dma flag by writing to dma start vector. dmar3 dmar2 dmar1 dmar0 r/w r/w r/w r/w 0 0 0 0 dmar dma software request register 89h 1: dma request in software dmab3 dmab2 dmab1 dmab0 r/w r/w r/w r/w 0 0 0 0 dmab dma burst request register 8ah 1 : dma request on burst mode ? i2edge i2le i1edge i1le i0edge i0le nmiree w w w w w w w w 0 0 0 0 0 0 0 0 iimc0 interrupt input mode control 0 8ch (prohibit rmw) always write ?0?. int2 edge 0: rising 1: falling int2 0: edge 1: level int1 edge 0: rising 1: falling int1 0: edge 1: level int0 edge 0: rising 1: falling int0 0: edge 1: level 1: nmi operation even on nmi rising edge i5edge i5le i4edge i4le i3edge i3le w w w w w w 0 0 0 0 0 0 iimc1 interrupt input mode control 1 8dh (prohibit rmw) int5 edge 0: rising 1: falling int5 0: edge 1: level int4 edge 0: rising 1: falling int4 0: edge 1: level int3 edge 0: rising 1: falling int3 0: edge 1: level
tmp91c829 2006-03-15 91c829-185 (4) chip select/wait control (1/2) symbol name address 7 6 5 4 3 2 1 0 b0e b0om1 b0om0 b0bus b0w2 b0w1 b0w0 w w w w w w w 0 0 0 0 0 0 0 b0cs block 0 cs/wait control register c0h (prohibit rmw) 0: disable 1: enable 00: rom/sram 01: 10: reserved 11: data bus width 0: 16 bits 1: 8 bits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits b1e b1om1 b1om0 b1bus b1w2 b1w1 b1w0 w w w w w w w 0 0 0 0 0 0 0 b1cs block 1 cs/wait control register c1h (prohibit rmw) 0: disable 1: enable 00: rom/sram 01: 10: reserved 11: data bus width 0: 16 bits 1: 8 bits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits b2e b2m b2om1 b2om0 b2bus b2w2 b2w1 b2w0 w w w w w w w w 1 0 0 0 0 0 0 0 b2cs block 2 cs/wait control register c2h (prohibit rmw) 0: disable 1: enable 0: 16 m space 1: area setting 00: rom/sram 01: 10: reserved 11: data bus width 0: 16 bits 1: 8 bits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits b3e b3om1 b3om0 b3bus b3w2 b3w1 b3w0 w w w w w w w 0 0 0 0 0 0 0 b3cs block 3 cs/wait control register c3h (prohibit rmw) 0: disable 1: enable 00: rom/sram 01: 10: reserved 11: data bus width 0: 16 bits 1: 8 bits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits bexbus bexw2 bexw1 bexw0 w w w w 0 0 0 0 bexcs external cs/wait control register c7h (prohibit rmw) data bus width 0: 16 bits 1: 8 bits 000: 2 waits 001: 1 wait 010: (1 + n) waits 1xx: reserved 011: 0 waits s23 s22 s21 s20 s19 s18 s17 s16 r/w 1 1 1 1 1 1 1 1 msar0 memory start address register 0 c8h start address a23 to a16 v20 v19 v18 v17 v16 v15 v14~9 v8 r/w 1 1 1 1 1 1 1 1 mamr0 memory address mask register 0 c9h cs0 area size 0: enable to address comparision s23 s22 s21 s20 s19 s18 s17 s16 r/w 1 1 1 1 1 1 1 1 msar1 memory start address register 1 cah stat address a23 to a16 v21 v20 v19 v18 v17 v16 v15~9 v8 r/w 1 1 1 1 1 1 1 mamr1 memory address mask register 1 cbh cs1area size 0: enable to address comparsion
tmp91c829 2006-03-15 91c829-186 chip select/wait control (2/2) symbol name address 7 6 5 4 3 2 1 0 s23 s22 s21 s20 s19 s18 s17 s16 r/w 1 1 1 1 1 1 1 1 msar2 memory start address register 2 cch start address a23 to a16 v22 v21 v20 v19 v18 v17 v16 v15 r/w 1 1 1 1 1 1 1 1 mamr2 memory address mask register 2 cdh cs2 area size 0: enable address comparsion s23 s22 s21 s20 s19 s18 s17 s16 r/w 1 1 1 1 1 1 1 1 msar3 memory start address register 3 ceh start address a23 to a16 v22 v21 v20 v19 v18 v17 v16 v15 r/w 1 1 1 1 1 1 1 1 mamr3 memory address mask register 3 cfh cs3 area size 0: enable to address comparsion
tmp91c829 2006-03-15 91c829-187 (5) clock gear symbol name address 7 6 5 4 3 2 1 0 ? ? ? ? ? wuef prck1 prck0 r/w 1 0 1 0 0 0 0 0 syscr0 system clock control register 0 e0h always write ?1?. always write ?0?. always write ?1?. always write ?0?. always write ?0?. warm-up timer 0 write: don?t care write: start timer read: end warm-up read: not end warm-up prscaler clock seleciton 00: f fph 01: reserved 10: fc/16 11: reserved ? gear2 gear1 gear0 r/w 0 1 0 0 syscr1 system clock control register 1 e1h a l w a y s write ?0?. high-frequency gear value selection (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (reserved) 110: (reserved) 111: (reserved) ? wuptm1 wuptm0 haltm1 haltm0 drve r/w r/w r/w r/w r/w r/w 0 1 0 1 1 0 syscr2 system clock control register 2 e2h always write ?0?. warming-up time 00: reserved 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency 00: reserved 01: stop mode 10: idle1 mode 11: idle2 mode 1: drive the pin in stop mode protect ? ? ? ? extin ? ? r r/w r/w r/w r/w r/w r/w r/w 0 0 1 0 0 0 1 1 emccr0 emc control register 0 e3h protection flag 0: off 1: on always write ?0?. always write ?1?. always write ?0?. always wirte ?0?. 1: fc is external clock. always write ?1?. always write ?1?. emccr1 emc control register 1 e4h protection is turned off by writing 1fh. protection is turned on by writing any value other than 1fh. note: emccr1 if protection is on, write operations to the following sfrs are not possible. 1. cs/wait control b0cs, b1cs, b2cs, b3cs, bexcs, msar0, msar1, msar2, msar3, mamr0, mamr1, mamr2, and mamr3 2. clock gear (only emccr1 can be written to) syscr0, syscr1, syscr2 and emccr0
tmp91c829 2006-03-15 91c829-188 (6) 8-bit timer (1/2) (6 ? 1) tmra01 symbol name address 7 6 5 4 3 2 1 0 ta0rde i2ta01 ta01prun ta1run ta0run r/w r/w r/w r/w r/w 0 0 0 0 0 ta01run 8-bit timer run 100h double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ? w ta0reg 8-bit timer register 0 102h (prohibit rmw) undefined ? w ta1reg 8-bit timer register 1 103h (prohibit rmw) undefined ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 r/w 0 0 0 0 0 0 0 0 ta01mod 8-bit timer source clk & mode 104h 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm 00: reserved 01: 2 6 pwm cycle 10: 2 7 11: 2 8 00: ta0trg 01: t1 10: t16 11: t256 00: ta0in pin 01: t1 10: t4 11: t16 ta1ffc1 ta1ffc0 ta1ffie ta1ffis r/w r/w 1 1 0 0 ta1ffcr 8-bit timer flip-flop control 105h (prohibit rmw) 00: invert ta1ff 01: set ta1ff 10: clear ta1ff 11: don?t care 1: ta1ff invert enable 0: tmra0 1: tmra1 inversion (6 ? 2) tmra23 symbol name address 7 6 5 4 3 2 1 0 ta2rde i2ta23 ta23prun ta3run ta2run r/w r/w r/w r/w r/w 0 0 0 0 0 ta23run 8-bit timer run 108h double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ? w ta2reg 8-bit timer register 0 10ah (prohibit rmw) undefined ? w ta3reg 8-bit timer register 1 10bh (prohibit rmw) undefined ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 r/w 0 0 0 0 0 0 0 0 ta23mod 8-bit timer source clk & mode 10ch 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm 00: reserved 01: 2 6 pwm cycle 10: 2 7 11: 2 8 00: ta2trg 01: t1 10: t16 11: t256 00: reserved 01: t1 10: t4 11: t16 ta3ffc1 ta3ffc0 ta3ffie ta3ffis r/w r/w 1 1 0 0 ta3ffcr 8-bit timer flip-flop control 10dh (prohibit rmw) 00: invert ta3ff 01: set ta3ff 10: clear ta3ff 11: don?t care 1: ta3ff invert enable 0: tmra2 1: tmra3 inversion
tmp91c829 2006-03-15 91c829-189 8-bit timer (2/2) (6-3) tmra45 symbol name address 7 6 5 4 3 2 1 0 ta4rde i2ta45 ta45prun ta5run ta4run r/w r/w r/w r/w r/w 0 0 0 0 0 ta45run 8-bit timer run 110h double buffer 0: disable 1: enable idle2 0: stop 1: operate 8-bit timer run/stop control 0: stop and clear 1: run (count up) ? w ta4reg 8-bit timer register 0 112h (prohibit rmw) undefined ? w ta5reg 8-bit timer register 1 113h (prohibit rmw) undefined ta45m1 ta45m0 pwm41 pwm40 ta5clk1 ta5clk0 ta4clk1 ta4clk0 r/w 0 0 0 0 0 0 0 0 ta45mod 8-bit timer source clk & mode 114h 00: 8-bit timer 01: 16-bit timer 10: 8-bit ppg 11: 8-bit pwm 00: reserved 01: 2 6 pwm cycle 10: 2 7 11: 2 8 00: ta4trg 01: t1 10: t16 11: t256 00: ta4in pin 01: t1 10: t4 11: t16 ta5ffc1 ta5ffc0 ta5ffie ta5ffis r/w r/w 1 1 0 0 ta5ffcr 8-bit timer flip-flop control 115h (prohibit rmw) 00: invert ta5ff 01: set ta5ff 10: clear ta5ff 11: don?t care 1: ta5ff invert enable 0: timer4 1: timer5 inversion
tmp91c829 2006-03-15 91c829-190 (7) 16-bit timer (1/2) (7-1) tmrb0 symbol name address 7 6 5 4 3 2 1 0 tb0rde ? i2tb0 tb0prun tb0run r/w r/w r/w r/w r/w 0 0 0 0 0 tb0run 8-bit timer control 180h double buffer 0: disable 1: enable always write ?0?. idle2 0: stop 1: operate 16-bit timer run/stop control 0: stop and clear 1: run (count up) tb0ct1 tb0et1 tb0cp0i tb0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 r/w w * r/w 0 0 1 0 0 0 0 0 tb0ff1 inv trg 0: trg disable 1: trg enable tb0mod 16-bit timer source clk & mode 182h (prohibit rmw) invert when the uc value is captured to tb0cp1. invert when the uc value matches the value in tb0rg1. 0: soft capture 1: undefined capture timing (tb0in0, tb0in1) 00: disable 01: , 10: , 11: , (ta1out) 1: uc0 clear enable source clock 00: tb0in0 pin 01: t1 10: t4 11: t16 tb0ff1c1 tb0ff1c0 tb0c1t1 tb0c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 w * r/w w * 1 1 0 0 0 0 0 0 tb0ff0 invert trigger 0: trigger disable 1: trigger enable tb0ffcr 16-bit timer flip-flop control 183h (prohibit rmw) 00: invert tb0ff1 01: set 10: clear 11: don?t care always read as ?11?. invert when the uc value is loaded into tb0cp1. invert when the uc value is loaded into tb0cp0. invert when the uc value matches the value in tb0rg1. invert when the uc value matches the value in tb0rg0. 00: invert tb0ff0 01: set 10: clear 11: don?t care always read as ?11?. ? w tb0rg0l 16-bit timer register 0l 188h (prohibit rmw) undefined ? w tb0rg0h 16-bit timer register 0h 189h (prohibit rmw) undefined ? w tb0rg1l 16-bit timer register 1l 18ah (prohibit rmw) undefined ? w tb0rg1h 16-bit timer register 1h 18bh (prohibit rmw) undefined ? r tb0cp0l capture register 0l 18ch undefined ? r tb0cp0h capture register 0h 18dh undefined ? r tb0cp1l capture register 1l 18eh undefined ? r tb0cp1h capture register 1h 18fh undefined
tmp91c829 2006-03-15 91c829-191 (8) uart/serial channel (8-1) uart/sio channel 0 symbol name address 7 6 5 4 3 2 1 0 rb7/tb7 rb6/tb6 rb5/tb5 rb4/tb4 r b3/tb3 rb2/tb2 rb1/tb1 rb0/tb0 r (receiving)/w (transmission) sc0buf serial channel 0 buffer 200h (prohibit rmw) undefined rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to 0 by reading.) r/w undefined 0 0 0 0 0 0 0 1: error sc0cr serial channel 0 control 201h receiving data bit8 parity 0: odd 1: even 1: parity enable overrun parity framing 0:sclk0 1:sclk0 1: input sclk0 pin tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 0 0 0 0 0 0 0 0 sc0mod0 serial channel 0 mode 0 202h transmission data bit8 1: cts enable 1: receive enable 1: wakeup enable 00: i/o interface 01: uart 7 bits 10: uart 8 bits 11: uart 9 bits 00: ta0trg 01: baud rate generator 10: internal clock f sys 11: external clock sclk0 ? br0add br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 r/w 0 0 0 0 0 0 0 br0cr baud rate control 203h always write ?0?. 1: (16 ? k)/16 divided enable 00: t0 01: t2 10: t8 11: t32 set the frequency divisor n. 0 to f br0k3 br0k2 br0k1 br0k0 r/w 0 0 0 0 br0add serial channel 0 k setting register 204h baud rate 0 k. 1 to f i2s0 fdpx0 stsen0 r/w r/w w 0 0 1 sc0mod1 serial channel 0 mode 1 205h idle2 0: stop 1: operate i/o interface 0: half duplex 1: full duplex sts0 1: output 0: stop
tmp91c829 2006-03-15 91c829-192 (8-2) uart/sio channel 1 symbol name address 7 6 5 4 3 2 1 0 rb7/tb7 rb6/tb6 rb5/tb5 rb4/tb4 r b3/tb3 rb2/tb2 rb1/tb1 rb0/tb0 r (receiving)/w (transmission) sc1buf serial channel 1 buffer 208h (prohibit rmw) undefined rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to 0 by reading.) r/w undefined 0 0 0 0 0 0 0 1: error sc1cr serial channel 1 control 209h receiving data bit8 parity 0: odd 1: even 1: parity enable overrun parity framing 0:sclk1 1:sclk1 1: input sclk1 pin tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 0 0 0 0 0 0 0 0 sc1mod0 serial channel 1 mode 0 20ah transmission data bit8 1: cts enable 1: receive enable 1: wakeup enable 00: i/o interface 01: uart 7 bits 10: uart 8 bits 11: uart 9 bits 00: ta0trg 01: baud rate generator 10: internal clock f sys 11: external clock sclk1 ? br1add br1ck1 br1ck0 br1s3 br1s2 br1s1 br1s0 r/w 0 0 0 0 0 0 0 br1cr baud rate control 20bh always write ?0?. 1: (16 ? k)/16 divided enable 00: t0 01: t2 10: t8 11: t32 set the frequency divisor n. 0 to f br1k3 br1k2 br1k1 br1k0 r/w 0 0 0 0 br1add serial channel 1 k setting register 20ch baud rate 0 k. 1 to f i2s1 fdpx1 stsen1 r/w r/w w 0 0 1 sc1mod1 serial channel 1 mode 1 20dh idle2 0: stop 1: operate i/o interface 1: full duplex 0: half duplex sts1 1: output 0: stop
tmp91c829 2006-03-15 91c829-193 (9) ad converter symbol name address 7 6 5 4 3 2 1 0 eocf adbf ? ? itm0 repeat scan ads r r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 admod0 ad mode register 0 2b0h 1: end 1: busy always write ?0?. always write ?0?. interrupt in repeat mode. 1: repeat 1: scan 1: start vrefon i2ad adtrge adch2 adch1 adch0 r/w r/w r/w r/w 0 0 0 0 0 0 admod1 ad mode register 1 2b1h 1: vref on idle2 0: abort 1: operate 1: enable for external start input channel 000: an0 an0 001: an1 an0 an1 010: an2 an0 an1 an2 011: an3 an0 an1 an2 an3 100: an4 an4 101: an5 an4 an5 110: an6 an4 an5 an6 111: an7 an4 an5 an6 an7 adm27 adm26 adm25 adm24 adm23 adm22 adm21 adm20 r/w 0 0 0 1 0 0 0 1 admod2 ad mode register 2 2b2h please write ?1e?. adm37 adm36 adm35 adm34 adm33 adm32 adm31 adm30 r/w 1 1 0 0 1 1 1 1 admod3 ad mode register 3 2b3h please write ?cf?. adr01 adr00 a dr0rf r r adreg04l ad result register 0/4 low 2a0h undefined 0 adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 r adreg04h ad result register 0/4 high 2a1h undefined adr11 adr10 adr1rf r r adreg15l ad result register 1/5 low 2a2h undefined 0 adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 r adreg15h ad result register 1/5 high 2a3h undefined adr21 adr20 adr2rf r r adreg26l ad result register 2/6 low 2a4h undefined 0 adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 r adreg26h ad result register 2/6 high 2a5h undefined adr31 adr30 adr3rf r r adreg37l ad result register 3/7 low 2a6h undefined 0 adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 r adreg37h ad result register 3/7 high 2a7h undefined
tmp91c829 2006-03-15 91c829-194 (10) watchdog timer symbol name address 7 6 5 4 3 2 1 0 wdte wdtp1 wdtp0 i2wdt rescr ? r/w r/w r/w r/w r/w r/w 1 0 0 0 0 0 wdmod wdt mode register 300h 1: wdt enable 00: 2 15 /f sys 01: 2 17 /f sys 10: 2 19 /f sys 11: 2 21 /f sys idle2 0: abort 1: operate reset connect internally wdt out to reset pin always write ?0?. ? w ? wdcr wdt control 301h (prohibit rmw) b1h: wdt disable 4eh: wdt clear (11) multi vector controllor symbol name address 7 6 5 4 3 2 1 0 vec7 vec6 vec5 vec4 vec3 vec2 vec1 vec0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 mvec0 multi vector control 00aeh vector address a15 to a8 symbol name address 7 6 5 4 3 2 1 0 vec15 vec14 vec13 vec12 vec11 vec10 vec9 vec8 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 mvec1 multi vector control 00afh vector address a23 to a16 note: write mvec1, mvec0 after making an interruption prohibition state.
tmp91c829 2006-03-15 91c829-195 6. port section equivalent circuit diagrams ? reading the circuit diagrams the gate symbols used are essentially the same as those used for the standard cmos logic ic [74hcxx] series. the dedicated signal is described below. stop: this signal becomes active (1) when the halt mode setting register is set to stop mode (e.g., when syscr2 = 0, 1) and the cpu executes the halt instruction. when the drive enable bit syscr2 is set to 1, however, stop will remains at 0. ? the input protection resistances ranges from seve ral tens of ohms to several hundreds of ohms. ? d0 to d7, p10 to p17, p20 to p27, a0 to a15, p71, p74, p90, p93 to p96 vcc output data p-ch i/o input data output enable stop input enable n-ch ? rd , wr , p60 to p63 output vcc output data stop
tmp91c829 2006-03-15 91c829-196 ? p53 to p55, p80 to p87, pz2, pz3 i/o input enable vcc output data output enable stop input data vcc programmable pull-up resistor ? pa (an0 to an7) a nalog input channel select input input data analog input input enable ? p56 (int0), p70 (int1), p72 (int2), p73 (int3), p75 (int4), p90 (int5) i/o schmitt trigger vcc output data output enable stop input data ? p80 (txd0) i/o input enable vcc output data stop input data open-drain output enable ? nmi input nmi schmitt trigger
tmp91c829 2006-03-15 91c829-197 ? am0 to am1 input input data ? reset input wdtout reset reset enable schmitt trigger p-ch vcc ? x1 and x2 x 2 high-frequency oscillation enable oscillator p-ch n-ch clock x 1 ? vrefh and vrefl vrefh vrefon vrefl p-ch string resistor
tmp91c829 2006-03-15 91c829-198 7. points to note and restrictions (1) notation a. the notation for built-in/i/o registers is as follows register symbol (e.g., ta01run denotes bi t ta0run of register ta01run). b. read-modify-write instructions an instruction in which the cpu reads data from memory and writes the data to the same memory location in one instruction. example 1: set 3, (ta01run) ? set bit 3 of ta01run. example 2: inc 1, (100h) ? increment the data at 100h. ? examples of read-modify-write instructions on the tlcs-900 exchange instruction ex (mem), r arithmetic operations add (mem), r/# adc (mem), r/# sub (mem), r/# sbc (mem), r/# inc #3, (mem) dec #3, (mem) logic operations and (mem), r/# or (mem), r/# xor (mem), r/# bit manipulation operations stcf #3/a, (mem) res #3, (mem) set #3, (mem) chg #3, (mem) tset #3, (mem) rotate and shift operations rlc (mem) rrc (mem) rl (mem) rr (mem) sla (mem) sra (mem) sll (mem) srl (mem) rld (mem) rrd (mem) c. fc, f fph , f sys and one state the clock frequency input on pins x1 and 2 is called f osch . the clock selected by dfmcr0 is called fc. the clock selected by syscr1 is called f fph . the clock frequency give by f fph divided by 2 is called f sys . one cycle of f sys is referred to as one state.
tmp91c829 2006-03-15 91c829-199 (2) points to note a. am0 and am1 pins fix these pins to v cc unless changing voltage. b. emu0 and emu1 open pins. c. reserved address areas the tmp91c829 does not have any reserved areas. d. halt mode (idle1) when idle1 mode is used (in which oscillator operation only occurs), set rtccr to 0 stop the timer for the real time clock before the halt instructions is executed. e. warm-up counter the warm-up counter operates when stop mode is released, even if the system is using an external oscillator. as a result a time eq uivalent to the warm-up time elapses between input of the release request and output of the system clock. f. programmable pull-up resistance the programmable pull-up resistor can be turned on/off by a program when the ports are set for use as input ports. when the ports are set for use as output ports, they cannot be turned on/off by a program. the data registers (e.g., p3) are used to turn the pull-up/pull-down resistors on/off. consequently read-modify-write instructions are prohibited. g. bus releasing function please refer to the note about bus release in section 3.6 ?port functions?. the pin state is written when the bus is released. h. watchdog timer the watchdog timer starts operation immediately after a reset is released. when the watchdog timer is not to be used, disable it. i. watchdog timer when the bus is released, neither internal memory nor internal i/o can be accessed. however, the internal i/o continues to operate. hence the watchdog timer continues to run. therefore be careful about the bus releasing time and set the detection timer of watchdog timer. j. ad converter the string resistor between the vrefh and vrefl pins can be cut by a program so as to reduce power consumption. when stop mode is used, disable the resistor using the program before the halt instruction is executed. k. cpu (micro dma) only the ?ldc cr, r? and ?ldc r, cr? instructions can be used to access the control registers in the cpu. (e.g., the transf er source address register (dmasn).) l. undefined sfr the value of an undefined bit in an sfr is undefined when read. m. pop sr instruction please execute the pop sr instruction during di condition.
tmp91c829 2006-03-15 91c829-200 n. releasing the halt mode by requesting an interruption usually, interrupts can release all halts status. however, the interrupts ( nmi , int0 to int4) which can release the halt mode may not be able to do so if they are input during the period cpu is shifting to the halt mode (for about 5 clocks of f fph ) with idle1 or stop mode (idle2 is not applicable to this case ). (in this case, an interrupt request is kept on hold internally.) if another interrupt is generated after it has shifted to halt mode completely, halt status can be released without difficulty. the priority of this interrupt is compared with that of the interrupt kept on hold internally , and the interrupt with higher priority is handled first followed by the other interrupt.
tmp91c829 2006-03-15 91c829-201 8. package dimensions p-lqfp100-1414-0.50f unit: mm
tmp91c829 2006-03-15 91c829-202

▲Up To Search▲

Price & Availability of TMP91C829FG

	To Download TMP91C829FG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .