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1 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel features ? synchronous sram organized as 2meg words x 40bit ? cont inuous data transfer (cdt) architecture eliminates wait states between read and write op erations ? sup ports 40mhz to 80mhz bus operations ? int ernally self-timed output buffer control eliminates the need for sy nchronous output enable ? registered inp uts and out puts for flow-thru operation ? s ingle 2.5v to 3.3v supply ? cl ock-to-output time - clk to q = 12ns ? clock enable ( cen ) pin to enable clock and suspend operation ? syn chronous self-timed writes ? three chip enables ( cs0 , cs1, cs2 ) for simple depth expansion ? "zz" sl eep mode option for partial power-down ? "shu tdown" mode option for deep power-down ? four word burst capability--linear or interleaved ? operat ional environment - t otal dose: 100 krad(si) - sel immune: 100mev-cm 2 /mg - seu error rate: 1.7x10 -6 errors/bit-day ? package options: - 288-lead clga, ccga, and cbga ? s tandard microelectronics drawing (smd) 5962-tbd - qmlq and q+ pend ing introduction the ut8sf2m40 is a high performance 83,886,080-bit synchronous static random access memory (ssram) device that is organized as 2m words of 40 bits. this device is equipped with thr ee chip selects (cs0 , cs1, and cs2 ), a write enable (we ), and an output enable (oe ) pin, allowing for significant design flexibility without bus contention. the device supports a four word burst function using (adv_ld ). all synchronous inputs are registered on the rising edge of the clock provided the clock enable (cen ) input is enabled low. operations are suspended when cen is disabled high and the previous operation is extended. write operation control signals are we and six byte write enables bwe [4:0]. all write operations are performed by inte rnal self-timed circuitry. for easy bank selection, three synchronous chip enables (cs0 , cs1, cs2 ) and an asynchronous output enable (oe ) provide for output tri-state control. the output drivers are synchronously tri-stated during the data portion of a write sequence to avoid bus contention. standard products ut8sf2m40 80megabit flow-thru ssram preliminary datasheet www.aeroflex.com/memories april 2015
2 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel figure 1. ut8sf2m40 block diagram main memory array 2meg x 40 q out housekeeping, and fault logic write address and command queue user command interface logic addr cmd pipeline register write data queue write data steering logic stall cycle registers read data steering and fault logic clk write data coherency logic d in
3 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel table 1: pin definitions name description type cs0 chip enable 0, input, active low: sampled on the rising edge of clk. used in conjunction with cs1 and cs2 to select or deselect the device. input-synchronous cs1 chip enable 1 input, active high: sampled on the rising edge of clk. used in conjunction with cs0 and cs2 to select or deselect the device. input-synchronous cs2 chip enable 2 input, active low: sampled on the rising edge of clk. used in conjunction with cs0 and cs1 to select or deselect the device. input-synchronous a[20:0] address inputs: sampled at the rising edge of the clk. a[1:0] is fed to the two-bit burst counter. input-synchronous bwe [4:0] byte write enable, active low: qualified with we, allows writes to each of six bytes of memory when active, and masks input data when disabled. input-synchronous we write enable input, active low: sampled on the rising edge of clk if cen is active low. this signal must be enabled low to initiate a write sequence. input-synchronous adv_ld advance/load input: advances the on-chip address counter or loads a new address. when high (and cen is enabled low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after deselection, drive adv_ld low to load a new address. input-synchronous clk clock input: used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. input-clock oe output enable, asynchrono us input, active low: combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are en abled to behave as outputs. when disabled high, i/o pins are tri-stat ed, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected stat e and when the device is deselected. input-asynchronous cen clock enable input, active low: when enabled low, the clock signal is recognized by the ssram. when deasserted high, the clock signal is masked. because deasserting cen does not deselect the device, cen can be used to extend the prev ious cycle when required. input-synchronous dq[47:0] bidirectional data i/os: as inputs, dq[47:0] feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, dq[47:0] delivers the data contained in the memo ry location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is enabled low, the pins behave as outputs. when high, dqs are placed in a tri-state condition. the outputs are automatically tri-stated during th e data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . aeroflex recommends connecting all dq pins to either vddq or vss through a > 10k? resistor. i/o-synchronous reset reset input, active low: resets device to known configuration. reset is required at initial power-up, after exiting shutdown mode, or after any power interruption. input-asynchronous
4 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel note: 1. reference application note an-mem-004 for additional ready signal in formation. 2. dc inputs are established at power up and can not be switched while power is applied to the device. 3. reference application note an-mem-005 for jtag operations. jtag ope rations are intended for terrestrial use and not guarante ed in radiation environment. name description type zz zz ?sleep? input, active high: when high, places the device in a non- time critical ?sleep? condi tion with data integrity preserved. during normal operation, this pin must be low. input-synchronous shutdown shutdown input, active high : when high, places device in shutdown mode. system clock can be stopped. memory contents are not retained. input-asynchronous ready 1 device ready output: ready outputs a high when device is available for normal operations. ready outputs a low when requesting an idle cycle or during power up initialization. output-synchronous mode 2 mode input: established at power up. selects the burst order of the device. when tied to vss selects linear burst sequence. when tied to vddq selects interleaved burst sequence. input-dc extres 2 input current reference: provided for external pr ecision current reference resistor connection. input-dc v dd power supply inputs to the core of the device. power supply v ddq power supply for the i/o circuitry. i/o power supply v ss ground inputs to the core of the device. ground v ssq ground for i/o circuitry. i/o ground nuil not used input low: pins designated as nuil need to be externally connected by user to v ssq through a > 10k ? 10% resistor. -- nuih not used input high: pins designated as nuih need to be externally connected by user to v ddq through a > 10k? 10% resistor. -- nc no connects. not internally connected to the die. --- tdo 3 jtag circuit serial data output: package pin requires a pull-up through > 10k ? 10% resistor to v ddq . jtag serial output synchronous tdi 3 jtag circuit serial data input: device pin internally connected through a 75k ? 10% resistor to v ddq . jtag serial input synchronous tms 3 jtag controller test mode select: device pin internally connected through a 75k ? 10% resistor to v ddq . test mode select synchronous tck 3 jtag circuit clock input: package pin requires a pull-up through > 10k ? 10% resistor to v ddq . jtag clock table 1: pin definitions
5 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel device operation the ut8sf2m40 is synchronous flow-thru ssram designed specifically to eliminate wait stat es during write/read or read/ write transitions. all synchronous inputs and outputs are registered on the rising edge of clock. the clock signal is enabled by the clock enable input ( cen ). when cen is high, the clock signal is disregarded and all inte rnal states are maintained. all synchronous operations are qualified by cen . once power-up requirements have been satisfied, the input clock may only be stopped during sleep (zz is high) or shutdown mode (shutdown is high). maximum access delay from the rising edge of clock (t cqv ) is 12ns (80 mhz device). access is initiated by asserting all three chip enables ( cs0 , cs1, cs2 ) active at the rising edge of the clock with clock enable ( cen ) and adv_ ld asserted low. the address presented to the device will be registered. access can be either a read or write operation, depending on the status of the write enable ( we ). write operations are initia ted by the w rite enable ( we ) input. all write commands are controlled by built in synchronous self-timed circuitry. three synchronous chip enables ( cs0 , cs1, cs2 ) and an asynchronous output enable ( oe ) simplify memory depth expansion. all operations (read s, writes, and deselects) are pipelined. adv_ ld must be driven low once the device has been deselected in order to load a new address and command for the next operation. single read accesses a read access is initiated when the following device inputs are pres ent at rising clock edge: cen is enabled low, cs0 , cs1, and cs2 are all enabled, the write enable input signal we is disabled high and adv_ ld is asserted low. the addresses present at the address inputs a[20:0] are registered and presented to the memory. data propagates to the input of the output register. data will be available to the bus 12ns after the next rising clock edge provided oe is enabled low. after the first clock of the read access, th e output buffers are controlled by oe and the internal control logic. oe must be enabled low to drive requested data. during the next rising clock, any operation (read/write/deselect) may be initiated. burst read accesses the ut8sf2m40 has an internal burst counter allowing up to four read s to be perf ormed from a single address input. a new address can only be loaded when adv_ ld is driven low. new addresses are loaded into the ssram, as described by the single read access section. the burst counter operates in either linear or interleave and is controlled by the mode input at power up. when mode pin is low, the burst sequence is linear. the burst sequence is interleaved when mode is high. a0 and a1 are controll ed by the burst counter. the burst counter will wrap arou nd when needed. the burst counter increments anytime adv_ ld is high and cen is low. the operation selected by the state of we is latched at the beginning of the sequence and maintained throughout. single write accesses a write access is initiated when the following device inputs are present at ri sing clock edge: cen is enabled low, cs0 , cs1, and cs2 are all enabled, the write enable input signal we is enabled low and adv_ ld is asserted low. the addresses present at the address inputs a[20:0] are registered and presented to the memory core. da ta i/os are tri-stated at the next rising edge of clock regardless of state of oe . the write is completed after the next rising clock edge using data present on dq pins. each byte of data is individually qualified by its applicable byte write enable input (see table 2). when the input low, the applicable dq i nputs are registered to memory. when the input is high, the applicable dq pins are ignored. to avoid bus contention data should not be driven to dqs when outputs are active. the output enable ( oe ) may be disabled high before applying data to the dq lines. this will tri-state the dq output drivers. as an additional feature dq lines are automatically tri-stat ed during the data portion of a write cycle, regardless of the state of oe . burst write accesses the ut8sf2m40 has an internal burst counter allowing up to four writ es to be performed from a single address input. a new address can only be loaded when adv_ ld is driven low. new addresses are loaded into th e ssram, as described in the single write access section. when adv_ ld is driven high on the subsequent clock rise, where cen is low, the chip enables ( cs0 , cs1, cs2 ) and we inputs are ignored and the burst counter is incremented. the bwe [4:0] inputs must be low in each cycle of the burst write in order to qualify each respective byte of data.
6 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel ready status the ut8sf2m40 device operates as a synchronous sram device. data integrity housekeeping activities are performed in the background during normal user activity. these housekeeping activities are performed on a regular basis. however, when a housekeeping activity sequence cannot be completed due to user conflict for memory space, the ready pin asserts signifying to the user that an idle cycle is required. please reference applications note an-mem-004 for more information. byte write enables bwe [4:0] the ut8sf2m40 device employs six byte write enable inputs t o be used in conjunction with we to qualify each associated byte of data into the memory. when we is high, the device is in read mode where all bwe [4:0] are don?t cares. when we is low, each bwe [4:0] must also be low to write the associated data input pins into memory. data input pins whose associated byte write enable pi n is high, will be masked. sleep mode the zz input lead is a synchronous input. asserting the zz pin high places the ssram into a power conservative "sleep" mode. to assure the completion of previous commands and through the pipeline prior to entering sleep mode, a minimum of two full clock cycles (t zzs ) are required between the last operation command and asserting the zz input. while in sleep mode, data integrity is guaranteed. changing the input clock frequency or halting the input clock may be executed during sleep mode. the device must be deselected prior to entering sleep mode and remain deselected for the duration of t zzrec after the zz input returns low. shutdown mode the shutdown input pin is an asynchronous input. ass erting shutdown places the device in a power saving shutdown mode. the system clock can be stopped. memory contents are not maintained in shutdown mode. the ssram requires a reset cycle upon exiting shutdown mode. power up/ down requirements the ssram requires that v dd < v ddq at all times. the ssram does require the user to provide an external reset after initial power application, exiting shutdown mode, or any power interruption to the device input voltage outside the specified limit. performing a rese t requires the assertion of the reset device input lead (low) for a minimum of 1us (t rlrh ). after the reset input is returned high, the device requires 50us (t shtdwnrec ) to complete the reset operation. once the reset operation is comp lete, the device requires an additional 20us (t cr ) to synchronize the clock input, providing a stable input clock is presen t. the device ready output lead asserts high once t cr is satisfied at the next rising clock. the ready out lead high indicates the device is available for normal operations. for power down it is required that v dd and v ddq be powered down to < 0.5v for a minimum of 100ms. clock conditioning requirements the clk signal input requirem ents are given in the clock section of the ac characteri zations. ac characterization performances listed herein are based on providing a clock input signal meeting these requirements. table 2. byte write enab le to data input pins byte write enable input data input pins bwe0 dq[7:0] bwe1 dq[15:8] bwe2 dq[23:16] bwe3 dq[31:24] bwe4 dq[39:32] table 3. linear bu rst address table (mode=v ss ) starting address second address third address fourth address a1, a0 a1, a0 a1, a0 a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 table 4. interleaved burst address table (mode=v ddq ) starting address second address third address fourth address a1, a0 a1, a0 a1, a0 a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
7 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel changing clock frequencies the clk inp ut frequency should be established at a power on, and may only be changed while in sleep mode (reference table 6). external connections a precision 25kohm < + 0.2% low tcr < 25ppm/ o c resistor is required to be connected between device pin extres (r15) and v ss . in order to ensure proper operation in conjunction with jtag boundary scan (reference app lications note mem-an-005), aeroflex requires that specific package pins be biased through soft connections to either v ddq or v ssq . table 5 is a list of these required external biases. notes: 1. nuil = not used input low 2. nuih = not used input high 3. aeroflex recommends connecting all dq[47:0] to either v ddq or v ssq through > 10k ? resistors. notes: * all chip selects active when l, at least one chip select inactive when h 1. x = ?don't care?, h = logic high, l = logic low. 2. write is defined by we and bwex 3. when a write cycle is detected, all i/os are tri-stated. 4. the dq pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device will power-up deselected and the i/os in a t ri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs = tri-state when oe is inactive or when the device is deselected and dqs = data when oe is active. table 5. external bias conditions signal name package pin bias condition nuil 1 h1, h20, n1, n2, n19, n20, p13, r7, r8, r10, r12, r13, r14, r16 > 10k ? to v ssq nuih 2 p16, r8 > 10k ? to v ddq tdo r5 > 10k ? to v ddq tck r9 > 10k ? to v ssq dq[47:0] 3 ref table 7 > 10k ? to v ddq or v ssq table 6: truth table for ut8sf2m40 [1,2,3,4,5,6,7] operation address used csx * zz shut down adv_ ld we bwex oe cen clk dqs standby mode none h l l l x x x l l-h 3-state continue deselect none x l l h x x x l l-h 3-state read cycle (start burst) external l l l l h x l l l-h data out read cycle (cont. burst) next x l l h x x l l l-h data out nop/dummy read (start) external l l l l h x h l l-h 3-state nop/dummy read (cont.) next x l l h x x h l l-h 3-state write cycle (start burst) external l l l l l l x l l-h data in write cycle (cont. burst) next x l l h x l x l l-h data in dummy write (start) none l l l l l h x l l-h 3-state dummy write (cont. burst) next x l l h x h x l l-h 3-state clock inhibit (stall) n/a x l l x x x x h l-h n/a sleep mode n/a h h l x x x x x x 3-state shutdown mode none x x h x x x x x x 3-state
8 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel table 7. 288-lead pipelined signal locations notes: 1. pin requires pull-up to v ddq of > 10k ? 10% . 2. pin requires pull-down to v ss of > 10k ? 10% . 3. nuil = not used input low. nuil pins requires > 10k ? 10% pull-down to v ssq . 4. nuih = not used input high. nuih pins requires > 10k ? + 10% pull-up to v ddq . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a vddq cs2 we vss a10 a8 a4 a18 a19 a14 a15 a2 a0 cs0 vss bwe1 b vss vss oe bwe2 a11 a9 a6 a17 vss a20 a16 a13 a12 a1 zz bwe3 shut down vss c vddq vssq vss ready bwe0 bwe4 a7 a5 vss vdd vss vssq vdd vdd a3 adv_ ld cs1 vss vssq vdd d dq33 dq35 vdd vss vss vddq vssq vdd vdd vss vdd vdd vssq vddq vdd vss vss vdd vddq dq32 e dq37 dq1 dq39 vdd vssq vss vssq vddq vss vss vss vssq vddq vss vss vssq vdd dq38 dq36 dq34 f dq3 dq5 dq7 vddq vddq vssq vss vss vdd vss vdd vss vss vddq vssq vddq vddq dq4 dq0 dq2 g dq9 dq11 dq13 vdd vssq vdd vddq vdd vss vdd vss vdd vddq vssq vdd vssq vdd dq10 dq6 dq8 h nuil 3 dq15 cen vss vss vdd vdd vdd vss vss vss vdd vdd vss vss vss vss clk dq12 nuil j dq19 dq17 dq21 vdd vssq vdd vss vdd vss vdd vss vdd vss vssq vdd vssq vdd dq14 dq16 dq18 k dq27 dq25 dq23 vddq vddq vssq vss vddq vdd vss vdd vddq vss vddq vssq vddq vddq dq20 dq24 dq22 l dq31 dq41 dq29 vdd vssq vss vssq vddq vss vss vss vssq vddq vss vss vssq vdd dq26 dq30 dq28 m dq45 dq47 dq43 vdd vss vssq vddq vssq vdd vss vdd vdd vssq vddq vssq vss vdd dq40 dq44 dq42 n nuil 3 nuil 3 vss vss vdd vddq vssq vdd vss vdd vss vss vdd vssq vssq vdd vss dq46 nuil 3 nuil 3 p vss vss vdd vddq vssq vssq vssq vss vss vddq mode nuil 3 vddq tms nuih 4 vssq vss vss r vdd tdi tdo 1 vdd nuil 3 nuih 4 tck 2 nuil 3 reset nuil 3 nuil 3 nuil 3 extres nuil 3 vddq vdd
9 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel absolute maximum ratings 1 (referenced to v ss ) notes: 1. permanent device damage may occur if ab solute ma ximum ratings are ex ceeded. functional operation shou ld be restricted to rec ommended operating conditions. 2. all voltages are referenced to v ss . 3. per mil-std-883, method 1012, section 3.4.1 p d = (t j (max) - t c (max)) operational environments notes: 1. adams 90% worst case environment, geosynchronous orbit, 100mils of aluminum 2. temperature = 105 o c; v dd and v ddq = 3.6v recommended operating conditions symbol parameter va l u e unit v dd /v ddq supply voltage 2 -0.5 to 4.0 v v in voltage on any pin 2 -0.3 to v ddq +0.3 v i io dc i/o current per pin @ t j = 135 o for 15 years + 10 ma p d package power dissipation permitted @ t c = 105c 3 15 w t j maximum junction temperature +150 o c jc thermal resistance junction to case 3 o c/w t stg storage temperature -65 to +150 o c parameter limit units total ionizing dose (tid) 100 krad(si) heavy ion error rate 1 1.7x10 -6 errors/bit-day single event latchup (sel) immune 2 100 mev-cm 2 /mg symbol parameter limits v dd core supply voltage 2.3v to v ddq v ddq i/o power supply voltage 2.3v to 3.6v t c case temperature range -55 c to +105 c v in dc input voltage 0v to v ddq t j junction temperature -55 c to +125 c jc
10 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel dc electrical charac teristics (pre and post-radiation)* (v dd = 2.3v to v ddq , v ddq = 2.3 to 3.6v; unless otherwise noted, tc is per the temperature range ordered ) parameter description condition min max unit v dd core power supply vo l t a g e 2.3 v ddq v v ddq i/o power supply voltage 2.3 3.6 v v oh output high voltage for 3.0v i/o, i oh =-4ma 0.8 * v ddq v for 2.3v i/o, i oh =-1ma 2.0 v v ol output low voltage for 3.0v i/o, i ol =8ma 0.4 v for 2.3v i/o, i ol =1ma 0.4 v v ih input high voltage for 3.0v i/o 2.0 v for 2.3v i/o 1.7 v v il input low voltage for 3.0v i/o 0.8 v for 2.3v i/o 0.7 v i in1 input leakage current v in = v ddq and v ss except device pins tdi and tms -2 2 a i in2 input leakage current v in = v ddq device pins tdi and tms 2 a v in = v ss device pins tdi and tms -100 a i oz three-state output leakage current v dd, v ddq = (max), v o = v ddq and v ss, oe = v ddq (max) -2 2 a i os 1,2 short-circuit output current v dd, v ddq = (max), v o = v ddq and v ss -100 100 ma i dd 3 v dd supply current in active mode v dd, v ddq = (max), i out = 0ma, f = f max 105 o c 900 ma -55 o c and 25 o c 750 ma i ddq 3 v ddq supply current in active mode v dd, v ddq = (max), i out = 0ma, f = f max 105 o c 100 ma -55 o c and 25 o c 100 ma i shtdwn 3 v dd supply current in shutdown mode v dd, v ddq = (max), v in > v ih or v in < v il , shutdown > v ih 105 o c 250 ma -55 o c and 25 o c 200 ma
11 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel capacitance notes: * for devices procured with a total ionizing dose tolerance gu ar ant ee, the post-irradiation pe rformance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maxi mum tid level procured. 1. supplied as a design limit but not guaranteed nor tested. 2. not more than one output may be shorted at a time for maximum duration of one second. 3. post-irradiation limits are the 105 o c limits when specified. 4. measured only for initial qualificatio n and after process or design change s that could affect this parameter. i shtdwnq 3 v ddq supply current in shutdown mode v dd, v ddq = (max), v in > v ih or v in < v il , shutdown > v ih 105 o c 15 ma -55 o c and 25 o c 15 ma i stby 3 v dd supply current in standby mode v dd, v ddq = (max), v in > v ih or v in < v il , f = fmax, device deselected 10 5 o c 650 ma -55 o c and 25 o c 500 ma i stbyq 3 v ddq supply current in standby mode v dd, v ddq = (max), v in > v ih or vin < vil, f = fmax, device deselected 105 o c 100 ma -55 o c and 25 o c 100 ma i zz 3 v dd supply current in sleep mode v dd, v ddq = (max), v in > v ih or v in < v il , zz > v ih , shutdown < v il 105 o c 500 ma -55 o c and 25 o c 350 ma i zzq 3 v ddq supply current in sleep mode v dd, v ddq = (max), v in > v ih or v in < v il , zz > v ih , shutdown < v il 105 o c 85 ma -55 o c and 25 o c 85 ma symbol parameter min max unit c in 4 input capacitance 15 pf c i/o 4 i/o capacitance 15 pf
12 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel ac characteristics (pre and post-radiation)* (v dd = 2.3v to v ddq , v ddq = 2.3 to 3.6v ; unless otherwise noted, tc is per the temperature range ordered.) 1 parameter description min max unit t powerup 2 v dd to first valid command (read or write) 100 ms clock t cyc 6 clock (clk) cycle time 12.5 25.0 ns t ch clk high time 0.4 * t cyc 0.6 * t cyc ns t cl clk low time 0.4 * t cyc 0.6 * t cyc ns t r, t f 2 input clock rise/fall time (10-90%) 2.25 v/ns t clkpj 3,5 input clock period jitter -100 100 ps t clkccj 3,5 input clock cycle to cycle jitter 150 ps setup times t as address setup time prior to clk 2.5 ns t ds data setup time prior to clk 1.5 ns t cens clock enable setup ( cen ) time prior to clk 3 ns t wes write enable ( we ) setup time prior to clk 3 ns t bwes byte write enable ( bwe [4:0]) setup time prior to clk 3 ns t advlds advance load (adv_ ld ) setup time prior to clk 2.5 ns t css chip select (csx) setup time prior to clk 3 ns hold times t ah address hold time after clk 1.2 ns t dh data hold time after clk 1.4 ns t cenh cen hold time after clk 1.2 ns t weh we hold time after clk 1.5 ns t bweh byte write enable ( bwe [4:0]) hold time after clk 1.5 ns t advldh adv_ ld hold time after clk 0.9 ns t csh csx hold time after clk 1.8 ns output times t cqv 4 data valid after rising clk 12 ns t oeqv 4 output enable ( oe ) active to data valid 4.0 ns t cqoh data output hold time after rising clk 2.0 ns t cqz 5 rising clk to output three-state time 5.0 ns t cqx 5 rising clk to output enable time 1.3 ns
13 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel notes: * for devices procured with a total ionizing dose tolerance gu arantee, the post-irradiation pe rformance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured 1. ac characteristics based on comp liance w ith clock in put specifications 2. supplied as a design guidelin e, not teste d or guaranteed. 3. period and cycle to cycle jitter is defined by jedec s tandard 65b 4. maximum data output valid times guaranteed up to 25pf load c apa citance. for loads >25pf, a derating factor of parameter = [s pecification max(ns) + (c load - 25pf)(44.2ps/pf]. 5. guranteed by design. 6. maximum cycle time is tested functionally. shutdown and sleep mode characteris tics (pre and post-radiation)* (v dd = 2.3v to v ddq , v ddq = 2.3 to 3.6v; unless otherwise noted t c is for temperature range ordered.) notes: * for devices procured with a total ionizing dose tolerance gu ar ant ee, the post-irradiation pe rformance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured 1. the clock must start up prior to exiting sleep or s hutdown modes. parameter is guaranteed by design. 2. t cr is necessary anytime the clock is stopped, af ter initial power on, or exiting shutdown mode. 3. tested functionally. 4. guaranteed by design. t oeqz 5 oe inactive to output three-state time 4.5 ns t oeqx 5 oe active to output enable time 0 ns parameter description condition min max unit t zzs 3 device operation to sleep mode ? > v ih 1 t cyc ns t zzh 3 sleep high pulse width ? > v ih 100 s t zzl 3 sleep low pulse width ? < v ih 100 s t shtdwns 3 device operation to shutdown shutdown > v ih 2 t cyc ns t zzrec 3 sleep recovery time standby < v il 100 + (3*t cyc ) ns t shtdwnrec 1,3 shutdown recovery time shutdown < v il 50 us t zzi 4 active to sleep current ? > v ih 100 + (3*t cyc ) ns t shtdwni 4 active to shutdown current shutdown > v ih 250 ns t rzzi 4 time to exit sleep current mode standby < v il 0 ns t rshtdwni 4 time to exit shudown current mode shutdown < v il 0 ns t cr 1,2,3 clock recovery prior to exiting zz ? > v ih 20 s t rlrh reset low to high time shutdown < v il 1 s t pds 3 sleep setup time prior to clk 2.0 ns t pdh 3 sleep hold time after clk 0.5 ns
14 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel clk zz rd / wr rd / wr rd / wr deselect cycle t zzs t zzi t pdh t pds t zzh t cr t zzl t rzzi t zzrec command bus clk rd/ wr rd/ wr deselect cycle t shtdwns t shtdwni t rshtdwni t shtdwnrec t rlrh t cr reset command bus s hutdown clk shutdown rd/ wr rd/ wr deselect cycle power-up t rlrh t shtdwnrec t cr ready reset command bus clk t cl t ch t cyc 64 th non- idle cycle 65 th non - idle cycle non - idle cycle non - idle cycle non - idle cycle non - idle cycle non - idle cycle non - idle cycle idle cycle any cycle any cycle command bus ready t cqv t cqv any cycle 16 cycles max figure 3. switching waveform for internal housekeeping figure 4. switching waveform for sleep mode figure 5. switching wave form for shutdown mode figure 6. switching w aveform for power-up
15 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel figure 7. switching waveforms for pipelined cycle operations &/. &(1 $''5 :( &6&6 $'9b/' 2( 4 287 $ $ 4$ '$ '$ ' ,1 $ $ 1rwhv &6kdvwlplqjwudqvlwlrqvlghqwlfdowr&6dqg&6exwlvlqyhuwhgorjlfdoo\)ruh[dpsohzkhq&6dqg&6duh/2:&6lv+,*+ '$ %:(>@ 4$ 5($' 4$ :5,7( '$ %8567 :5,7( '$ 67$// &<&/( 5($' 4$ 5($' 4$ 67$// &<&/( 67$// &<&/( :5,7( '$ 5($' 4$ w &/ w &+ w &(16 w &(1+ w &66 w &6+ w $6 w $+ w 2(4; w '6 w '+ w &4; w &4= w 2(49 w 2(4= w &49 w :(6 w :(+ w $'9/'6 w $'9/'+ $ $ $ w &<& 67$// &<&/( :5,7( '$ &+,3/(9(/ &200$1' 4$ 4$ '( 6(/(&7 &<&/( 4$ w &42+ w %:(6 w %:(+
16 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel v dd dut zo = 50ohm v dd c l = 40pf r term 100ohm test point r term 100ohm 90% cmos input pulses 10% > 2.25v/ns v ss v dd2 10% 90% > 2.25v/ns figure 8. ac test loads and input waveforms notes: 1. measurement of data output occurs at the low to high or high to low transition mid- point (i.e., cmos input = v dd2 /2
17 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel packaging figure 9. 288-lead ccga
18 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel packaging figure 10. 288-lead clga
19 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel packaging figure 11. advanced 288-lead cbga, ball di mensions (a, a1, a2) are subject to change
20 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel ordering information 2m x 40 ssram package option associated lead finish option (z) 288-clga (c) gold (s) 288-ccga (a) hot solder dipped (c) 288-cbga (a) hot solder dipped lead finish: (note 1) (c) = gold (a) = solder screening: (notes 2, 3) (f) = hirel flow (temperature range: -55 c to +105 c) (in development, contact factory) (p) = prototype flow (temperature range: 25 o c only) package type: (z) = 288-lead ceramic land grid array (clga) (s) = 288-lead ceramic column grid array (ccga) (c) = 288-lead ceramic ball grid array (cbga) access time: (m) = 80mhz maximum frequency device type: (8sf2m40) = 2mbit x 40 ssram device notes: 1. lead finish is per the table below. 2. prototype flow per aeroflex manufacturing flows document. devices are tested at 25 o c only. radiation is neither tested nor guaranteed. 3. hirel flow per aeroflex manufacturing flows docu ment. radiation is neither tested nor guaranteed. ut ******* - * * * *
21 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel 2m x 40 ssram: smd lead finish: (note 1) (c) = gold (f) = solder case outline: (x) = 288-lead ceramic land grid array (clga) (f) = 288-lead ceramic co lumn grid array (ccga) class designator: (q) = qml class q (in development, contact factory) device type: (note 2) (01) = fmax = 80mhz, qml q only (temperature range: -55 c to +105 c) (02) = fmax = 80mhz aeroflex q+ flow (temperature range -55 c to +105 c) drawing number: (tbd) = 2m x 40 ssram total dose: (r) = 100 krad(si) federal stock class designator: no options notes: 1. lead finish is per the table below. 2. aeroflex?s q+ assembly flow, as define d in section 4.2.2.d of the smd, provides qml-q product through the smd that is manufa ctured with aeroflex?s qml-v flow. 5962 * ***** ** *** package option associated lead finish option (x) 288-clga (c) gold (f) 288-ccga (f) hot solder dipped
22 www.aeroflex.com/hirel info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services described herein at any time without notice. consult aeroflex or an authorized sales representa tive to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, ex cept as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service fro m aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. this product is controlled for export u nder the u.s. department of commerce (doc). a license may be required prior to the export of this product from the united states. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel
23 36-00-01-00 5 v er. 1.0.0 aeroflex microelectroni cs solutions - hirel description of change history revision date description of change april 2015 version 1.0.0 release of preliminary data sheet

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