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march 2008 rev 7 1/17 AN1439 application note 30 w ac-dc adapter with the l6565 quasi-resonant pwm controller introduction this application note describes the evaluation board of the quasi-resonant (qr) pwm controller l6565 (order code: steval-isc001v1 - previous code eval6565n) and presents the results of its bench evaluation. the board implements a 30 w, single-output (15 v/2 a), wide-range mains input, qr converter that can be used as a reference design for an ac-dc adapter, where good performance is to be achieved at low cost. www.st.com
contents AN1439 2/17 contents 1 design specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 evaluation board functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AN1439 list of tables 3/17 list of tables table 1. steval-isc001v1 evaluation board: electrical specifications . . . . . . . . . . . . . . . . . . . . . . 5 table 2. steval-isc001v1 evaluation board: bill of material. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. steval-isc001v1: tran sformer specificat ion (part number 55 8179, supplied by albe s.r.l.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. limits set by european code of conduct on efficiency of external power supplies . . . . . . . . 8 table 5. steval-isc001v1: typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. steval-isc001v1: line/load regula tion and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. steval-isc001v1: lig ht-load input power (at p out = 0.5 w) . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. steval-isc001v1: no-load input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. steval-isc001v1: maximum po wer capability (mea sured at 0.95v out ) . . . . . . . . . . . . . 10 table 10. steval-isc001v1: typical wakeup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 11. steval-isc001v1 modified as per optimizati on steps 1 to 3: no-l oad input pow er measure- ments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
list of figures AN1439 4/17 list of figures figure 1. steval-isc001v1 evaluation boar d: electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. steval-isc001v1: pcb layout, s ilk + bottom layer (top view). . . . . . . . . . . . . . . . . . . . . . 7 figure 3. steval-isc0 01v1: full load, v in = 100 vdc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. steval-isc0 01v1: full load, v in = 380 vdc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. steval-isc001v1: half load, v in = 100 vdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. steval-isc001v1: half load, v in = 380 vdc (note uneven skipping) . . . . . . . . . . . . . . . 11 figure 7. steval-isc001v1: no load, v in = 100 vdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. steval-isc001v1: no load, v in = 380 vdc (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. steval-isc001v1: fu ll-load output ripple at v in = 110 v ac : high freq. . . . . . . . . . . . . . . . 12 figure 10. steval-isc001v1: full-load output ripple at v in = 110 v ac : line freq. . . . . . . . . . . . . . . . . 12 figure 11. steval-isc001v1: behavior upon short-circuit on the output. v in =220 v ac . . . . . . . . . . . 13 figure 12. steval-isc001v1: behavi or upon short-circuit on d7. v in =220 v ac . . . . . . . . . . . . . . . . 13 figure 13. steval-isc001v1: load transient (at v in = 220 v ac : i out = 0.5 to 2.5 a). . . . . . . . . . . . . . 13 figure 14. high-voltage active startup circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. low-consumption feedback network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AN1439 design specification 5/17 1 design specification ta bl e 1 summarizes the electrical spec ifications of the application, ta bl e 2 provides the bom and ta bl e 3 lists the transformer's specifications. the electrical schematic is shown in figure 1 and the pcb layout in figure 2 . figure 1. steval-isc001v1 evalua tion board: electrical schematic the electrical specification is typical of an ac-dc adapter for consumer equipment, usually developed as an external unit. as such, it falls within the scope of the european "code of conduct on efficiency of external power supplies" and is required to be "efficient" under no- load conditions as specified in ta b l e 4 . the design target is to fulfill the phase 2 requirements, so as to be up-to-date until the year 2005, when phase 3 sets even more stringent limits. some hints to upgrade the design according to phase 3 is given in the section evaluation board optimization for minimum no-load consumption on page 13 . table 1. steval-isc001v1 evaluation board: electrical specifications input voltage range (v in ) 88 to 264 v ac mains frequency (f l ) 50/60 hz maximum output power (p out ) 30 w output ?v out = 15 v 3%; ?i out = 0 to 2 a; ?v ripple 1% minimum switching frequency (at 100 v dc input voltage) 60 khz target efficiency (at p out = 30 w, v in = 88 264 v ac ) > 80% maximum no-load input power < 0.75 w (1) 1. compliant with european code of conduct on effici ency of external power supplies, phase 2, 01.01.2003. 8 3 r2 1.5m b1 df06g r 3 1.5m r4 1 8 k c5 100 f 400v d1 1n414 8 d2 1n414 8 r16 220k r10 1.5 r 9 1.5 c14 47nf 400v d4 1.5ke220a q1 s tp5nk 8 0zfp d 3 s tth1l06 f1 2a f us e ntc1 10r r1 100 vin 88 v to 264v a c d5 1n414 8 r5 4.7 r 8 47k r6 220 r7 10 r12 33 k ic2 tl4 3 1 d6 1n414 8 t1 1 3 6 ic1 l6565 1 2 7 5 2 2 3 3 4 1 1 c6 2.2nf y1 d7 s tp s8 h100fp l2 10 h r15 5.6k c7 47 f 25v c10,c11 6 8 0f 25v r14 2k r1 3 10k 15v 2a d01in1 3 0 3 b ic 3 pc 8 17x1 r11 1.5k c 8 1nf c 9 2.2nf c15 100pf 1kv c7 b 100nf c1 3 560nf 4 8 5 4 10 c12 33 0f 25v
design specification AN1439 6/17 table 2. steval-isc001v1 evaluation board: bill of material symbol value note r1 100 ? 5% r2, r3 1.5 m ? r4 18 k ? r5 4.7 ? r6 220 ? r7 10 ? r8 47 k ? r9, r10 1.5 ? metallic film r11 1.5 k ? r12 33 k ? r13 10 k ? r14 2 k ? r15 5.6 k ? r16 220 k ? c5 100 f 1 kv, rubycon, mxr series or equivalent c6 2.2 nf y1 class c7 47 f 25 v electrolytic c7b 100 nf plastic film or ceramic c8, c9 2.2 nf plastic film or ceramic c10, c11 680 f 25 v rubycon, zl series or equivalent c12 330 f 25 v sanyo, cg series or equivalent c13 560 nf plastic film or ceramic c14 47 nf 400 v, polyester c15 100 pf 1 kv, y5p, panasonic or equivalent l2 10 h elc08d100e, r=44 m ? , panasonic or equivalent t1 558179 see spec in ta b l e 3 . s u p p l i e d b y a l b e s . r. l . (tel. +39 363 61493) b1 df06g 1a / 600 v bridge, dip4, gi or equivalent d1, d2, d5, d6 1n4148 0.3 a / 75 v, glass case, vishay or equivalent d3 stth1l06 1 a / 600 v turboswitch, f126, st d4 1.5ke220a 220 v transil, cb429, st d7 stps8h100fp 8 a / 100 v schottky, to-220fpac, st ic1 l6565 qr pwm controller, dip8, st (1) ic2 tl431cz shunt regulator, to92, st ic3 pc817x1j000f optocoupler, sharp or equivalent
AN1439 design specification 7/17 figure 2. steval-isc001v1: pcb layout, silk + bottom layer (top view) q1 stp5nk80zfp 1.9 ? / 800 v, to220fp, st ntc1 ssn550 ntc 10 ? , vishay or equivalent f1 t2a250v 2 a, 250 v elu pcb --- fr-4, cu single layer 35 m, 95.8 x 64.7 mm 1. if not otherwise specified, all re sistors are 1%, ? w q1 and d7 are bot h provided with a 40 c/w heatsink sk95/25/sa from fischer elektronik. table 2. steval-isc001v1 evaluation board: bill of material (continued) symbol value note table 3. steval-isc001v1: transformer specification (part number 558179, supplied by albe s.r.l.) core e25/13/7, n67 material or 3c85 or equivalent bobbin vertical mounting, 10 pins air gap 1 mm for an inductance 1-3 of 740 h leakage inductance < 20 h (at 60 khz) pins 1-3 with 4,5,7,8,9,10 shorted windings spec & build pin start/end winding wire turns notes 1/2 pri1 awg26 40 innermost winding 7/9 sec1 2xawg23 8 pins 7-8 will be shorted on the pcb 8/10 sec2 2xawg23 8 pins 9-10 will be shorted on the pcb 2/3 pri2 awg26 40 pin2 will be cut for safety 4/5 aux awg32 8 evenly spaced
design specification AN1439 8/17 1.1 evaluation board functionality the minimum switching frequency (60 khz at v in = 100 v dc ) has been chosen trading off the transformer's size against frequency-related losses. the reflected voltage has been chosen equal to 150 v, then zvs is achieved only when the converter operates from the 110 v mains. this value seems to provide a good compromise between capacitive and switching losses at 220 v mains. to provide room for the leakage inductance spike, an 800 v power mosfet (stp5nk80zfp) is used. to get 150 v reflected voltage, the primary-to-secondary turn ratio is made 1:10, which originates relatively low reverse voltages at the secondary side and allows the use of a schottky rectifier as the secondary diode (d7). an stps8h100fp has been selected. two design choices have been done to meet the no- load consumption target. first, the converter is started up with a charge pump consisting of d1, d2, c14 and r1 instead of the usual dropping resistor. this circuit, usable thanks to the extremely low startup current of the l6565, provides a typical wakeup time going from 2.8 s at 88 v ac to 0.75 s at 264 v ac , while dissipating less than 50 mw at 264 v ac , i.e. saving about 200 mw as compared to a startup circuit made with a dropping resistor that gives the same wakeup time. second, the leakage inductance spikes are handled by a transil clamp (d4, with the addition of d3 to prevent direct conduction during power mosfet's on-time), instead of an rcd clamp, thus saving about 200 mw more. r2+r3 and r4 compensate for the power capability change vs. the input volt age (voltage feedforward). their ratio has been found simply by fixing the high side one (using a high resistance value to keep the losses low) and varying the low side resistance until the converter loses output voltage regulation with the same load at 88 and 264 v ac . a 1nf film capacitor bypasses any noise on pin #3 to ground. to stay within 3% tolerance, the output voltage regulation is done with secondary feedback, using a typical arrangement tl43 1+optocoupler. r12, c13 and c9 (on the primary side) compensate the voltage loop for st ability. typically, the crossover frequency is 5 khz with 70 phase margin. a 100 pf low-loss capacitor (c15) has been added across the primary winding to optimize the power mosfet's losses at maximum load by a small snubbing effect on the drain voltage rate of rise. the delay between transformer' s demagnetization and the power mosfet's turn-on is adjusted by means of r8. the final value of 47 k ? has been experimentally determined so as to achieve the optimum turn-on point (after the addition of c15). the converter is fully protected against short-circ uit. under this condition it operates at the frequency of the internal starte r (2.5 khz) and the reflected voltage on the auxiliary winding drops, hence the supply voltage of the l6565 cannot be maintained. this results in table 4. limits set by european code of conduct on efficiency of external power supplies rated input power no-load power consumption phase 1 01.01.2001 phase 2 01.01.2003 phase 3 01.01.2005 0.3 w and < 15 w 1.0 w 0.75 w 0.30 w 15 w and < 50 w 1.0 w 0.75 w 0.50 w ?50 w and < 75 w 1.0 w 0.75 w 0.75 w
AN1439 design specification 9/17 intermittent operation ("hiccup" mode) with low power throughput (< 1 w at 264 v ac ). r10 prevents improper power mosfet's turn-on, due to signal bouncing on the pin, by pulling up the zcd pin that would be completely floating otherwise. additionally, thanks to the 2 nd overcurrent level on the l6565's current sense pin, also a short - circuit directly across the secondary winding - or d7 failing short - causes an intermittent oper ation with an even lower level of power throughput. board evaluation: getting started the ac voltage, generated by an ac source ranging from 88 v ac to 264 v ac , is applied to connector m1 (at the bottom left-hand corner). should one want to use a high-voltage dc source, remember that the startup charge pump would not work and a dropping resistor would be needed to let the l6565 start. the 15 vdc output (connector m2 ) is located close to the bo ttom right-hand corner and will be connected to the load. if an electronic load is going to be used in cc mode, make sure that the voltage which the load starts sinking current at is > 1 v or use cr mode if this cannot be set, otherwise the board may not start up at maximum load. this happens because v out needs to build up a little in order for the zcd signal to be large enough to trigger qr operation (refer to 2.: "l6565 quasi-resonant controller" (an1326). ) before that, the converter runs at the frequency of the internal starter, with a much lower power capability that may be easily exceeded if the load starts sinking the maximum current as v out is just above zero. in this case v out gets clamped at a low value, the zcd signal cannot reach the minimum amplitude required, qr operation cannot take place and the system cannot start up. caution: like in any offline circuit, extreme caution must be used when working with the application board because it contains dangerous and lethal potentials. the application must be tested with an isolation transformer connected between the ac mains and the input of the board to avoid any risk of electrical shock . board evaluation: bench results and significant waveforms ta bl e 5 , 6 , and 7 summarize the results of some bench evaluations. a number of waveforms under different load and line conditions are shown for the user's reference. table 5. steval-isc001v1: typical performance parameter value unit regulated output voltage (at v in = 220 v ac , i out = 2 a) 14.924 v minimum operating frequency (at v in = 88 v ac , i out = 2 a) 60 khz maximum operating frequency (at v in = 264 v ac , i out = 1.1 a) 214 khz line regulation (v in = 88 to 264 v ac , i out = 2 a) 1 mv load regulation (v in = 88 v ac , i out = 0 to 2 a) 55 mv high-frequency output voltage ripple (at v in = 88 v ac , i out = 2 a) 10 mv line-frequency output voltage ripple (at v in = 88 v ac , f l = 60 hz, i out = 2 a) < 5 mv maximum full-load efficiency (at v in = 176 v ac , i out = 2) 85 % maximum no-load input power (at v in = 264 v ac ) 0.6 w
design specification AN1439 10/17 table 6. steval-isc001v1: line/load regulation and efficiency v ac [v] 88 110 132 176 220 264 i out [a] 2.0 v out = 14.925 v = 82.6 % v out = 14.924 v = 84.0 % v out = 14.924 v = 84.5 % v out = 14.924 v = 85.0 % v out = 14.924 v = 84.5 % v out = 14.924 v = 83.1 % 1.5 v out = 14.938 v = 83.3 % v out = 14.938 v = 84.6 % v out = 14.938 v = 84.9 % v out = 14.938 v = 84.9 % v out = 14.938 v = 83.6 % v out = 14.938 v = 81.8 % 1.0 v out = 14.952 v = 84.0 % v out = 14.952 v = 85.0 % v out = 14.952 v = 85.0 % v out = 14.952 v = 84.0 % v out = 14.952 v = 81.7 % v out = 14.952 v = 78.7 % 0.5 v out = 14.966 v = 83.1 % v out = 14.966 v = 83.1 % v out = 14.966 v = 83.1 % v out = 14.966 v = 81.3 % v out = 14.966 v = 77.1 % v out = 14.966 v = 72.6 % 0.2 v out = 14.974 v = 78.8 % v out = 14.974 v = 78.8 % v out = 14.974 v = 76.8 % v out = 14.974 v = 73.0 % v out = 14.974 v = 66.5 % v out = 14.974 v = 58.7 % table 7. steval-isc001v1: light-load input power ( at p out = 0.5 w) v ac [v] 88 110 132 176 220 264 pin [w] 0.9 1.0 1.1 1.2 1.5 1.6 table 8. steval-isc001v1: no-load input power v ac [v] 88 110 132 176 220 264 pin [w] 0.4 0.4 0.45 0.5 0.55 0.60 table 9. steval-isc001v1: maximum power capability (measured at 0.95v out ) v ac [v] 88 110 132 176 220 264 pinmax [w] 52.5 57.1 59.5 60.2 57.4 52.3 table 10. steval-isc001v1: typical wakeup time v ac [v] 88 110 132 176 220 264 twake [s] 2.8 2.1 1.65 1.17 0.9 0.75
AN1439 design specification 11/17 figure 3. steval-isc001v1: full load, v in = 100 v dc figure 4. steval-isc001v1: full load, v in = 380 v dc ch2: q1 drain voltage ch1: current sense pin ch2: q1 drain voltage ch1: current sense pin figure 5. steval-isc001v1: half load, v in = 100 v dc figure 6. steval-isc001v1: half load, v in = 380 v dc (note uneven skipping) ch2: q1 drain voltage ch1: current sense pin ch2: q1 drain voltage ch1: current sense pin
design specification AN1439 12/17 figure 7. steval-isc001v1: no load, v in = 100 v dc figure 8. steval-isc001v1: no load, v in = 380 v dc (burst mode) ch2: q1 drain voltage ch1: current sense pin ch2: q1 drain voltage ch1: current sense pin figure 9. steval-isc001v1 full-load output ripple at v in = 110 v ac : high freq. figure 10. steval-isc001v1 full-load output ripple at v in = 110 v ac : line freq.
AN1439 design specification 13/17 figure 13. steval-isc001v1: load transient (at v in = 220 v ac : i out = 0.5 to 2.5 a) evaluation board optimization for minimum no-load consumption additional optimization steps ne ed to be taken in order for the steval-isc001v1 to fulfill the limits set by the 3 rd phase of the european code of conduct on efficiency of external power supplies, which has been active from 01.01.2005. according to this standard, the no- load consumption must be less than 0.5 w at rated input voltage (220 v ac for european mains, the 110 v ac of the us mains is not a concern). to have some margin, it is a common design target to fulfill the specification even at maximum input voltage (264 v ac ). figure 11. steval-isc001v1 behavior upon short-circuit on the output. v in =220 v ac figure 12. steval-isc001v1 behavior upon short-circuit on d7. v in =220 v ac ch1: q1 drain voltage ch2: l6565 supply voltage ch1: q1 drain voltage ch2: l6565 supply voltage ch2: output voltage ch2: load current
design specification AN1439 14/17 the optimization steps are basically three: 1. eliminate c15. this slightly hurts efficiency at heavy and moderate load but saves about 100 mw of no-load input consumption at maximum mains. 2. replace the startup charge pump with a more efficient high-voltage active startup circuit, like the one shown in figure 15 . this saves about 40 mw input consumption. 3. the feedback network topology at the primary side should be changed as shown in figure 15 . the feedback topology used in the steval-isc001v1 is such that under no-load conditions the optocoupler draws about 3 ma out of pin comp, which adds up to the quiescent current of the ic. this additional load causes the v cc voltage to drop so that a small dummy load (r15) is required at the secondary side. with the circuit in figure 15 , the operating current of optocoupler is reduced to 1 ma and also the dummy load can be reduced, just the 10 k ? resistor is used to provide adequate bias current to the tl431. the input consumption is reduced by about 100 mw. figure 14. high-voltage active startup circuit figure 15. low-consumption feedback network
AN1439 design specification 15/17 to gain more design margin the following tips could be considered: a) increase r2, r3 and r4: by using 4.7 m ? for r2 and r3 and 56 k ? for r4, the input consumption is reduced by 30 mw. b) reduce the parasitic capacitance of the drain node by using a smaller or lower voltage rating power mosfet. the price to pay might be more dissipation at full load and a larger heatsink. for example the 600v -rated power mosfet with the closest r ds(on) to that of the stp5nk80zfp, the stp4nk80zfp, has a c oss which is only 66%, which allows saving about 15 mw. the full-load losses are essentially the same. c) another way to reduce the drain parasiti c capacitance is to minimize the parasitic capacitance of the primary winding. to achieve a low capacitance, split the primary winding (this goes in favor of a low leakage inductance too) and wind first the half whose end is to be connected to the drain of the power mosfet. in case of multiple layer winding, which exhibits higher capacitance, it is useful to embed one layer of isolation in between. this, however, tends to increase leakage inductance and therefore should be done with care. slotted bobbins are also very effective to this end but they tend to increase leakage inductance too. table 11. steval-isc001v1 modified as per optimization steps 1 to 3: no-load input power measurements v ac [v] 88 110 132 176 220 264 pin [w] 0.3 0.3 0.3 0.35 0.4 0.4
references AN1439 16/17 2 references 1. "l6565 quasi-resonant smps controller" datasheet 2. "l6565 quasi-resonant controller" (an1326). 3 revision history table 12. document revision history date revision changes 28-10-2005 5 first issue in edocs dms 10/02/2006 6 ? obsolete parts replaced with newest ones. ? changed c14 and d4 values. ? updated ta b l e 1 0 . 12-mar-2008 7 ? figure 1 , 2 modified ? eval6565n replaced by steval-isc001v1
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