unisonic technologies co., ltd gm1851 linear integrated circuit www.unisonic.com.tw 1 of 10 copyright ? 2008 unisonic technologies co., ltd qw-r122-007,b ground fault interrupter ? description the utc gm1851 can specially provide ground fault protection for ac power outlets in consumer and industrial environments. as ground fault currents greater than a presentable threshold value, it will trigger an external scr-driven circuit breaker to interrupt the ac line and remove the fault condition. besides of detection of conventional hot wire to ground faults, the neutral fault condition is detected also. in the event that noise pulses introduce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used, circuitry that rapidly resets the timing capacitor. ? features * internal power supply shunt regulator * externally programmable fault current threshold * externally programmable faul t current integration time * direct interface to scr * operates under line reversal; both load vs line and hot vs neutral * detects neutral line faults lead-free: gm1851l halogen-free: gm1851g ? ordering information ordering number normal lead free halogen free package packing gm1851-s08-r gm1851l-s08-r GM1851G-S08-R sop-8 tape reel gm1851-d08-t gm1851l-d08-t gm1851g-d08-t dip-8 tube
gm1851 linear integrated circuit unisonic technologies co., ltd 2 of 10 www.unisonic.com.tw qw-r122-007,b ? pin configuration sense amplifier output inverting input non-inverting input gnd vcc timing capacitor sense itivity set resistor scr trigger 1 2 3 4 8 7 5 6
gm1851 linear integrated circuit unisonic technologies co., ltd 3 of 10 www.unisonic.com.tw qw-r122-007,b ? internal schematic diagram
gm1851 linear integrated circuit unisonic technologies co., ltd 4 of 10 www.unisonic.com.tw qw-r122-007,b ? block diagram
gm1851 linear integrated circuit unisonic technologies co., ltd 5 of 10 www.unisonic.com.tw qw-r122-007,b ? absolute maximum ratings parameter symbol ratings unit supply current i cc 19 ma power dissipation (note 1) p d 1250 mw operating temperature t opr -40 ~ +70 c storage temperature t stg -55 ~ +150 c note: absolute maximum ratings are those values be yond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? electrical characteristics (t a =25 c, i ss =5ma) parameter test conditions min typ max unit dc characteristics power supply shunt regulator voltag e pin 8, average value 22 26 30 v latch trigger voltage pin 7 15 17.5 20 v sensitivity set voltage pin 8 to pin 6 6 7 8.2 v output saturation voltage pin 1, without fault 100 240 mv output drive current pin 1, with fault 0.5 1 2.4 ma output external current sinking capability pin 1, without fault vpin 1 held to 0.3v (note 4) 2.0 5 ma output saturation resistance pin 1, without fault 100 ? noise integration sink current ratio pin 7, ratio of discharge currents between no fault and fault conditions 2.0 2.8 3.6 a/ a ac characteristics normal fault current sensitivity figure 1 (note 3) 3 5 7 ma normal fault trip time 500 ? fault, figure 2 (note 2) 18 ms normal fault with grounded neutral fault trip time 500 ? normal fault, 2 ? neutral, figure 2 (note 2) 18 ms note: 1. 2. 3. 4. for operation in ambient temperatures above 25 , the device must be debated based on a 125 maximum junction temperature and a thermal resistance of 80 / w junction to ambient for the dip and 162/w for the so package. average of 10 trials. required ul sensitivity tolerance is such that exte rnal trimming of utc gm1851 sensitivity will be necessary. this externally applied current is in addition to the internal ''output drive current '' source. figure 1.normal fault s ensitivity test circuit
gm1851 linear integrated circuit unisonic technologies co., ltd 6 of 10 www.unisonic.com.tw qw-r122-007,b ? circuit description (refer to block and connection diagram) the utc gm1851 operates from 26v as set by an internal shunt re gulator, d3. in the absence of a fault (if=0) the feedback path status signal (vs) is correspondingly zero. under these conditions the capacitor discharge current, i1, sits quiescently at three times its threshold value, ith, so that noise induced charge on the timing capacitor will be rapidly removed. when a fault current, if, is induced in the secondary of the exter nal sense transformer, the operational amplifier, a1, uses feedback to force a virtual ground at the input as it extracts if. the presence of if during either half-cycle will cause vs to go high, which in tu rn changes i1 from 3ith to ith. although ith discharges the timing capacitor during both half-cycles of the line, if only charges the capac itor during the half-cycle in which if exits pin 2. thus during one half-cycle if-ith charges the timing capacitor, while during the other half-cycle ith discharges it. when the capacitor voltage reaches 17.5v, the latch engages and turns off q3 permitting i2 to drive the gate of an scr. ? application circuits a typical ground fault interrupter circuit is shown in figure 2. it is designed to operate on 120 vac line voltage with 5 ma normal fault sensitivity. a full-wave rectifier bridge and a 15k/2w resistor are used to supply the dc power required by the ic. a 1 f capacitor at pin 8 used to filter the ripple of the supply vo ltage and is also connected across the scr to allow firing of the scr on either half-cycle. when a f ault causes the scr to trigger, the circuit breaker is energized and line voltage is removed from the load. at this time no fault current flows and the ic discharge current increases from ith to 3ith ( see circuit description and block diagram ). th is quickly resets both the timing capacitor and the output latch. at this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. a 1000:1 sense transformer is used to detect the normal fault. the fault current, which is basically the difference current between the hot and neutra l lines, is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10 f capacitor. the 0.0033 f capacitor between pin 2 and pin 3 and the 200 pf between pins 3 and 4 are added to obtain better noise immunity. the normal fault sensitivity is determined by the timing capacitor discharging current, ith. ith can be calculated by: i th = 7v r set 2 (1) at the decision point, the average fault current just equals the threshold current, ith. i th = i f (rms) 2 0.91 (2) where if(rms) is the rms input fault curre nt to the operational amp and the fact or of 2 is due to the fact that if charges the timing capacitor only during one half-cycle, wh ile ith discharges the capacitor continuously. the factor 0.91 converts the rms value to an average val ue. combining equations (1) and (2) we have r set = i f (rms) 7v 0.91 (3) for example, to obtain 5ma (rms) sensitivit y for the circuit in figure 2 we have: r set = 5ma 7v 0.91 1000 =1.5m (4) the correct value for rset can also be determined from the characteristic curve that pl ots equation (3). note that this is an approximate calculation; the exact value of rset depends on the specific sense transformer used and utc gm1851 tolerances. inasmuch as ul943 specifies a sensitiv ity '' window '' of 4ma ~ 6ma, provision should be made to adjust rset on a per-product basis. independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, ct. due to the large number of variables involved, proper selection of ct is best done empirically. the following design example, then should only be used as a guideline. assume the goal is to meet ul943 timing requirements. also assume that worst-case timing occurs during gf1 start-up (s1 closure) with both a heavy normal fault and a 2 ? grounded neutral fault present. this situation is shown diagrammatically below.
gm1851 linear integrated circuit unisonic technologies co., ltd 7 of 10 www.unisonic.com.tw qw-r122-007,b ul943 specifies 25 ms average trip time under thes e conditions. calculation of c t based upon charging currents due to normal fault only is as follows: 25 ms specification -3 ms gfi turn-on time (15k and 1 f) -8 ms potential loss of one half-cycle due to fault current sense of half-cycles only -4 ms time required to open a sluggish circuit breaker 10 ms maximum integration time that could be allowed 8 ms value of integration time that accommo dates component tolerances and other variables c t = 1 t v (5) where t=integration time v=threshold voltage i=average fault current into c t i = 120v ac(rms) r b r n r g + r n heavy fault current generated (swamps i th ) portion of fault current shunted around gfi (6) 1 turn 1000 turns 1 2 0.91 current division of input sense transformer ct charging on half- cycles only rms to average conversion therefore: 120 500 0.4 1.6+0.4 1 1000 1 2 0.91 0.0008 17.5 c t = c t = 0.01 f (7) in practice, the actual value of c1 will have to be modi fied to include the effects of the neutral loop upon the net charging current. the effect of neutral loop induced currents is difficult to quartile, but typically they sum with normal fault currents, thus allowing a larger value of c1. for ul943 requirements, 0.015 f has been found to be the best compromise between timing and noise. for those gfi standards not requiring gr ounded neutral detection, a still lar ger value capacitor can be used and better noise immunity obtained. the larger capacitor can be accommodated because rn and rg are not present, allowing the full fault cu rrent, i, to enter the gfi. in figure 2, grounded neutral detection is accomplis hed by feeding the neutral coil with 120 hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault.
gm1851 linear integrated circuit unisonic technologies co., ltd 8 of 10 www.unisonic.com.tw qw-r122-007,b ? typical application timing cap scr trigger op amp output v cc -in +in r set gnd mov hot neutral load gnd/neutral coil sense coil 200:1 1000:1 high g coil 10 f tant 0.0033 200 pf 2 3 6 4 7 1 5 8 r set * 1.0 f tant c t 0.015 0.01/400v circuit breaker 15k/2w 0.01 0.01/400v scr + line * adjust r set for desired sensitivity + figure 2. 120hz neutral transformer approach
gm1851 linear integrated circuit unisonic technologies co., ltd 9 of 10 www.unisonic.com.tw qw-r122-007,b ? definition of terms
gm1851 linear integrated circuit unisonic technologies co., ltd 10 of 10 www.unisonic.com.tw qw-r122-007,b ? typical performance characteristics fault current (ma) fault current on line (ma(rms)) output drive current@pin 1 ( a) pin 1 saturation voltage (v) utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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