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1 publication order number : le25w81qe/d ? semiconductor components industries, llc, 2014 november 2014 - rev. p0 ordering information see detailed ordering and shipping info rmation on page 21 of this data sheet. www.onsemi.com le25w81qe overview the le25w81qe is a serial interface-compatible flash memory device with a 1m ? 8-bit configuration. it uses a single 2.6v power supply for both reading and writing (program and erase functions) and does not require a special power supply. as such, it can support on-board programming. it has three erase functions, each of which co rresponds to the size of the memory area in which the data is to be erased at one time: the small sector (4k bytes) erase function, the sector (64k bytes) erase function, and the chip erase function (for erasing all the data to gether). the memory space can be efficiently utilized by selecting one of these functions depending on the application. a page program method is supported for data writing. the page program method of le25w81qe can program any amount of data from 1 to 256 bytes. this ic incorporates on semi?s unique high-speed programming function which enables fast 0.3ms (typ.) page program time. the program time of 1.5s (typ.) when programming 8-mbit full-memory space makes for fast data writing when the chip erase function is used. while making the most of the features inherent to a serial flash memory device, the le25w81qe is housed in an 8-pin ultra-miniature package. serial flash memory devices tend to be at a disadvantage in terms of their read speed, but the le25w81qe has maximally eliminated this speed-related disadvantage by supporting clocks with frequencies up to 50mhz under spi bus specifications. all these features make this device ideally suited to storing program codes in applications such as portable information devices and small disk systems, which are required to have increasingly more compact dimensions. features ? read/write operations enabled by single 2.6v power supply : 2.45 to 3.6v supply voltage range ? operating frequency : 30mhz ? temperature range : ?20 to +70 ? c (read operation) 0 to +70 ? c (write operation) ? serial interface : spi mode 0, mode 3 supported ? sector size : 4k bytes/sm all sector, 64k bytes/sector ? small sector erase, sector erase, chip erase functions ? page program function (256 bytes / page) ? block protect function ? highly reliable read/write number of rewrite times : 100,000 times small sector erase time : 80ms (typ.), 300ms (max.) sector erase time : 100ms (typ.), 400ms (max.) chip erase time : 250ms (typ.), 3.0s (max.) page program time : 0.3ms/256 bytes (typ.), 1ms/256 bytes (max.) ? status functions : ready/busy information, protect information ? data retention period : 20 years ? package : vdfn8 5 ? 6 cmos lsi 8m-bit (1024k x 8) serial flash memory * this product is licensed from s ilicon storage technology, inc. (usa). vdfn8 5x6, 1.27p / vson8t (6x5) advance information this document contains information on a new product. specifications and information herein are subject to change without notice.
le25w81qe www.onsemi.com 2 package dimensions unit : mm figure 1 pin assignments v dfn8 5x6, 1.27p / vson8t (6x5) case 509ag issue o top view cs so wp v ss v dd hold sck si 1 2 3 4 8 7 6 5
le25w81qe www.onsemi.com 3 figure 2 block diagram table 1 pin description symbol pin name description sck serial clock this pin controls the data input/output timing. the input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. si serial data input the data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. so serial data output the data stored insi de the device is output from this pin sy nchronized to the falling edge of the serial clock. cs chip select the device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. wp write protect the status register wr ite protect (srwp) takes effect when the logic level of this pin is low. hold hold serial communication is suspended when the logic level of this pin is low. v dd power supply this pin supplies the 2.45 to 2.75v supply voltage. v ss ground this pin supplies the 0v supply voltage. 8m bit flash eeprom cell array y-decoder i/o buffers & data latches cs sck si hold wp so x- decoder address buffers & latches serial interface control logic
le25w81qe www.onsemi.com 4 table 2 command settings command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle nth bus cycle read 03h a23-a16 a15-a8 a7-a0 0bh a23-a16 a15-a8 a7-a0 x small sector erase d7h or 20h a23-a16 a15-a8 a7-a0 sector erase d8h a23-a16 a15-a8 a7-a0 chip erase c7h page program 02h a23-a16 a15-a8 a7-a0 pd *1 pd *1 pd *1 write enable 06h write disable 04h power down b9h status register read 05h status register write 01h data read silicon id 1 *2 9fh read silicon id 2 *3 abh x x a7-a0 exit power down mode abh explanatory notes for table 2 "x" signifies "don't care" (that is to say, any value may be input). the "h" following each code indicates that the number given is in hexadecimal notation. addresses a23 to a20 for a ll commands are "don't care". in order for commands other than the read command to be recognized, cs must rise after all the bus cycle input. *1: "pd" stands for page program data. any amount of data from 1 to 256 bytes in 1-byte unit is input. *2: of the two silicon id commands, it is for the command with the 9fh setting that the manufacturer code 62h is first output. for as long as the clock input is continue d, 26h of the device code is output continuously, followed by the repeated output of 62h and 26h. *3: of the two silicon id commands, it is for the command w ith the abh setting that manufacturer code 62h is first output when address a0 is "0", and the device code 27h is first output when address a0 is "1". addresses a7 to a1 are "don't care". for as long as the clock inpu t is continued, 62h and 26h are repeatedly output.
le25w81qe www.onsemi.com 5 device operation the le25w81qe features electrical on-chip erase functions using a single 2.6v power supply, that have been added to the eprom functions of the industry standard that support se rial interfaces. interfacing and control are facilitated by incorporating the command registers inside the chip. the read, erase, program and other required functions of the device are executed through the command registers. the command addresses and data input in accordance with "table 2 command settings" are latched inside the device in order to execute the required operations. "figure 3 serial input timing" shows the timing waveforms of the serial data input. first, at the falling cs edge the device is selected, and serial input is enabled for the commands, addresses, etc. thes e inputs are introduced internally in sequence starting with bit 7 in synchronization with the rising sck edge. at this time, output pin so is in the high-impedance state. the output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon id. refer to "figure 4 serial output timing" for the serial output timing. the le25w81qe supports bo th serial interface spi mode 0 and spi mode 3. at the falling cs edge, spi mode 0 is automatically selected if the logic level of sck is low, and spi mode 3 is automatically selected if the logic level of sck is high. figure 3 serial input timing figure 4 serial output timing high impedance t dh t cph t ds t csh t css cs data valid so si sck high impedance t clh t cls t clhi t cllo t ho t chz t clz si t v cs so sck data valid
le25w81qe www.onsemi.com 6 description of commands and their operations "table 2 command settings" provides a list and overview of the commands. a detailed description of the functions and operations corresponding to each command is presented below. 1. read there are two read commands, the 4 bus cycle read command and 5 bus cycle read command. consisting of the first through fourth bus cycles, the 4 bus cycle read command input s the 24-bit addresses following (03h), and the data in the designated addresses is output synchronized to sck. the data is output from so on the falling clock edge of fourth bus cycle bit 0 as a reference. "figure 5-a 4 bus read" shows the timing waveforms. consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0bh). the data is output from so using the falling clock edge of fifth bus cycle bit 0 as a reference. "figure 5-b 5 bus read" shows the timing waveforms. the only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. when sck is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while sck is being input, and the corresponding data is output in sequence. if the sck input is continued after the internal address arrives at the highest address (fffffh), the internal address returns to the lowest address (00000h), and data output is continued. by setting the logic level of cs to high, the device is deselected, an d the read cycle ends. while the devi ce is deselected, the output pin so is in a high-impedance state. figure 5-a 4 bus read figure 5-b 5 bus read n+2 n+1 n cs high impedance data data data sck so si 03h a dd. a dd. a dd. 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 47 8clk mode0 mode3 32 40 n+2 n+1 n cs high impedance data data data sck so si 0bh a dd. a dd. a dd. x 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 48 55 mode3 mode0 8clk
le25w81qe www.onsemi.com 7 2. status registers the status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (statu s register write). there are 8 bits in total, and "table 3 status registers" gives the significance of each bit. table 3 status registers bit name logic function power-on time information bit0 rdy 0 ready 0 1 erase/program bit1 wen 0 write disabled 0 1 write enabled bit2 bp0 0 block protect information see status register descriptions on bp0, bp1, and bp2. nonvolatile information 1 bit3 bp1 0 nonvolatile information 1 bit4 bp2 0 nonvolatile information 1 bit5 reserved bits 0 bit6 0 bit7 srwp 0 status register write enabled nonvolatile information 1 status register write disabled 2-1. status register read the contents of the status registers can be read using the status register read command. this command can be executed even during the following operations. ? small sector erase, sector erase, chip erase ? page program ? status register write "figure 6 status register read" shows the timing waveforms of status register read. consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (sck) with which the eighth bit of (05h) has been input. in terms of the output sequence, srwp (bit 7) is the first to be output, and each time one clock is input, all the other bits up to rdy (bit 0) are output in sequence, synchronized to the falling clock edge. if the clock input is continued after rdy (bit 0) has been output, the data is output by returning to the bit (srwp) that was first output, after which the output is repeated for as long as the clock input is continued. the data can be read by the status register read command at any time (even during a program or erase cycle). figure 6 status register read cs sck si so msb msb msb 05h data data high impedance 8 3 2 1 0 7 6 5 4 15 23 mode 3 mode 0 8clk 16 data
le25w81qe www.onsemi.com 8 2-2. status register write the information in status registers bp0, bp1, bp2 and srwp can be rewritten usi ng the status register write command. rdy , wen, bit 5, and bit 6 are read-only bits and cannot be rewritten. the information in bits bp0, bp1, bp2, and srwp is stored in the non-volatile memory, and when it is wr itten in these bits, the contents are retained even at power- down. "figure 7 status register write" shows the timing waveforms of status register write, and figure 20 shows a status register write flowchart. consis ting of the first and second bus cycles, th e status register write command initiates the internal write operation at the rising cs edge after the data has been input following (01h). erase and program are performed automatically inside the device by status register write so that erasing or ot her processing is unnecessary before executing the command. by the operation of this co mmand, the information in bits bp0, bp1, bp2, and srwp can be rewritten. since bits rdy (bit 0), wen (bit 1), 4, 5, and 6 of the status register cannot be written, no problem will arise if an attempt is made to set th em to any value when rewriting the status register. status register write ends can be detected by rdy of status register read. information in the stat us registers can be rewritten 1,000 times (min.). to initiate status register write, the logic level of the wp pin must be set high and status register wen must be set to "1". figure 7 status register write 2-3. contents of each status register rdy (bit 0) the rdy register is for detecting the write (p rogram, erase and status register write ) end. when it is "1", the device is in a busy state, and when it is "0", it means that write is completed. t srw self-timed write cycle sck si high impedance so cs data 01h 15 0 1 2 3 4 5 6 7 8 mode3 mode0 8clk wp t wph t wps
le25w81qe www.onsemi.com 9 wen (bit 1) the wen register is for detecting whether the device can perfor m write operations. if it is set to "0", the device will not perform the write operation even if th e write command is input. if it is set to "1", the device can perform write operations in any area that is not block-protected. wen can be controlled using the write enable and write disable commands. by inputting the write enable command (06h), wen can be set to "1"; by inputtin g the write disable command (04h), it can be set to "0." in the following states, wen is automatically set to "0" in order to protect against unintentional writing. ? at power-on ? upon completion of small sector er ase, sector erase or chip erase ? upon completion of page program ? upon completion of status register write * if a write operation has not been performed inside the le25w81qe because, for instance, the command input for any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protected address, wen will retain the status established prior to the issue of the command concerned. furthermore, its st ate will not be changed by a read operation. bp0, bp1, bp2 (bits 2, 3, 4) block protect bp0, bp1, and bp2 are stat us register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. for the setting conditions, refer to "table 4 protect level setting conditions". table 4 protect level setting conditions protect level status register bits protected area bp2 bp1 bp0 0 (whole area unprotected) 0 0 0 none 1 (1/16 protected) 0 0 1 f0000h to fffffh 2 (1/8 protected) 0 1 0 e0000h to fffffh 3 (1/4 protected) 0 1 1 c0000h to fffffh 4 (1/2 protected) 1 0 0 80000h to fffffh 5 (whole area protected) 1 0 1 00000h to fffffh 5 (whole area protected) 1 1 0 00000h to fffffh 5 (whole area protected) 1 1 1 00000h to fffffh * chip erase is enabled only when the protect level is 0. srwp (bit 7) status register write protect srwp is the bit for protecting the status registers, and its information can be rewritten. when srwp is "1" and the logic level of the wp pin is low, the status register write command is ignored, and status registers bp0, bp1, bp2, and srwp are protected. when the logic level of the wp pin is high, the status registers are not protected regardless of the srwp state. the srwp setting conditions are shown in "table 5 srwp setting conditions". table 5 srwp setting conditions wp pin srwp status register protect state 0 0 unprotected 1 protected 1 0 unprotected 1 unprotected bits 5 and 6 are reserved bits, and have no significance.
le25w81qe www.onsemi.com 10 3. write enable before performing any of the operations lis ted below, the device must be placed in the write enable state. operation is the same as for setting status register wen to "1", and the state is enabled by inputting the write enable command. "figure 8 write enable" shows the timing waveforms when the write enable operation is performed. the write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). ? small sector erase, sector erase, chip erase ? page program ? status register write 4. write disable the write disable command sets status register wen to "0" to prohibit unintentional writing. "figure 9 write disable" shows the timing waveforms. the write disable command co nsists only of the first bus cycle, and it is initiated by inputting (04h). the write disable state (wen "0") is exited by setting wen to "1" using the write enable command (06h). figure 8 write enable figure 9 write disable 5. power-down the power-down command sets all the commands, with th e exception of the silicon id read command and the command to exit from power-do wn, to the acceptance prohibited state (pow er-down). "figure 10 power-down" shows the timing waveforms. the power-down command consists only of the first bus cycle, and it is initiated by inputting (b9h). however, a power-down command issued during an internal write operation will be ignored. the power-down state is exited using the power-down exit command (power-dow n is exited also when one bus cycle or more of the silicon id read command (abh) has been input). "figure 11 exiting from power-down" shows the timing waveforms of the power-down exit command. figure 10 power-down figure 11 exiting from power-down sck si high impedance so cs 06h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs 04h 012 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs b9h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs a bh 012 3 4 5 6 7 mode3 mode0 8clk t prb t dp power down mode power down mode
le25w81qe www.onsemi.com 11 6. small sector erase small sector erase is an operation that sets the memory cell da ta in any small sector to "1". a small sector consists of 4kbytes. "figure 12 small sector er ase" shows the timing waveforms, and figure 21 shows a small sector erase flowchart. the small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (d7h or 20h). addresses a19 to a12 are valid, and addresses a23 to a20 are "don't care". after the command has been input, the in ternal erase operation starts from the rising cs edge, and it ends automatically by the control exercised by the internal timer. erase end can also be detected using status register rdy . figure 12 small sector erase 7. sector erase sector erase is an operation that sets the memory cell data in any sector to "1". a sector consists of 64kbytes. "figure 13 sector erase" shows the timing waveforms, and figure 21 shows a sector erase flowchart. the sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (d8h). addresses a19 to a16 are valid, and addresses a23 to a20 are "don't care". after the command has been input, the internal erase operation st arts from the rising cs edge, and it ends automatically by the control exercised by the internal timer. erase end can also be detected using status register rdy . figure 13 sector erase so self-timed erase cycle sck si high impedance cs t sse add. d7h or 20h add. add. 15 0 1 2 3 4 5 6 7 8 23 16 24 31 mode3 mode0 8clk sck si high impedance so cs t se self-timed erase cycle add. d8h add. add. 15 0 1 2 3 4 5 6 7 8 23 16 24 31 mode3 mode0 8clk
le25w81qe www.onsemi.com 12 8. chip erase chip erase is an operation that sets the memory cell data in all the sectors to "1". "fig ure 14 chip erase" shows the timing waveforms, and figure 21 shows a chip erase flowchart. the chip erase command consists only of the first bus cycle, and it is initiated by inputting (c7h). after the comma nd has been input, the internal erase operation starts from the rising cs edge, and it ends automatically by the control exercised by the inte rnal timer. erase end can also be detected using status register rdy . figure 14 chip erase 9. page program page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: a19 to a8). before initiating page program, the data on the page concerned must be erased using small sector erase, sector erase, or chip erase. "figure 15 page program" shows the page program timing waveforms, and figure 22 shows a page program flowchart. after the falling cs , edge, the command (02h) is input followed by the 24- bit addresses. addresses a19 to a0 are valid. the program data is then loaded at each rising clock edge until the rising cs edge, and data loading is continued until the rising cs edge. if the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. the program data must be loaded in 1-byte increments, and the program operation is not performed at the rising cs edge occurring at any other timing. the page programming time of 0.3ms (typ.) when programming 256 bytes (1 page) at one time makes for fast data writing. figure 15 page program sck si high impedance so cs t che self-timed erase cycle c7h 0 1 2 3 4 5 6 7 mode3 mode0 8clk t pp self-timed program cycle sck si high impedance so cs pd a dd. a dd. 02h a dd. pd 15 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 mode3 mode0 8clk pd 2079
le25w81qe www.onsemi.com 13 10. silicon id read silicon id read is an operation that reads the manufacturer c ode and device code information. "table 6 silicon id codes table" lists the silicon id codes. the silicon id read command is not accepted during writing. two methods are used for silicon id reading. the first method involves inputting the 9fh command: the setting is completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h and device code 26h are repeatedly output in succession so long as the clock input is continued. refer to "figure 16-a silicon id read 1" for the waveforms. the second method involves inputting the abh command. this co mmand consists of the first through fourth bus cycles, and the silicon id can be read when 16 dummy bits and an 8- bit address are input after (abh ). when address a0 is "0", the manufacturer code 62h is read in the fifth bus cycle, and the device code 26h is read in the sixth bus cycle. "figure 16-b silicon id read 2" shows the timing waveforms. if, afte r the manufacturer code or device code has been read, the sck input is continued, the manufacturer code and device code are output alternately with each bus cycle. when address a0 is "1", reading starts with device code 26h in the fifth bus cycle. table 6 silicon id codes address a0 output code manufacturer code 0 62h device code 1 27h the data is output starting with the falling clock edge of th e fourth bus cycle bit 0, and silicon id reading ends at the rising cs edge. figure 16-a silicon id read 1 figure 16-b silicon id read 2 n n+1 n cs high impedance siid siid siid sck so si 9fh 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 8clk mode0 mode3 n n+1 n cs high impedance siid siid siid sck so si a bh a dd. x x 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 47 8clk mode0 mode3 32 40
le25w81qe www.onsemi.com 14 11. hold function using the hold pin, the hold function suspends serial communication (it places it in the hold status). "figure 17 hold " shows the timing waveforms. the device is pl aced in the hold stat us at the falling hold edge while the logic level of sck is low, and it exits from the hold status at the rising hold edge. when the logic level of sck is high, hold must not rise or fall. the hold function takes effect when the logic level of cs is low, the hold status is exited and serial communication is reset at the rising cs edge. in the hold status, the so output is in the high-impedance state, and si and sck are "don't care". figure 17 hold 12. power-on in order to protect against unintentional writing, cs must be kept at v dd at power-on. after power-on, the supply voltage has stabilized at 2.70v or higher, wait for 100 ? s (t pu _read) before inputting the command to start a read operation. similarly, wait for 10ms (t pu _write) after the voltage has stabilized before inputting the command to start a write operation. figure 18 power-on timing cs hold sck so a ctive hold a ctive t hh t hs t hlz t hhz high impedance t hh t hs v dd (max) v dd (min) v dd chip selection not allowed 0v t pu _write t pu _read program, erase and write command not allowed read access allowed full access allowed
le25w81qe www.onsemi.com 15 13. hardware data protection in order to protect against unintentional writing at power-on, the le25w81qe incorporates a power-on reset function. the following conditions must be met in order to ensure that the power reset circuit will operate stably. no guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. figure 19 power-down timing 14. software data protection the le25w81qe eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. ? when a write command is input and the rising cs edge timing is not in a bus cycle (8 clk units of sck) ? when the page program data is not in 1-byte increments ? when the status register write command is input for 2 bus cycles or more 15. decoupling capacitor a 0.1 ? f ceramic capacitor must be provided to each device and connected between v dd and v ss in order to ensure that the device will operate stably. v dd (max) v dd (min) v dd no device access allowed 0v vbot t pu _write t pu _read t pd program, erase and write command not allowed
le25w81qe www.onsemi.com 16 specifications absolute maximum ratings parameter symbol conditions ratings unit maximum supply voltage v dd max with respect to v ss ? 0.5 to +4.6 v dc voltage (all pins) vin/vout with respect to v ss ? 0.5 to v dd +0.5 v storage temperature tstg ? 55 to +150 ? c operating conditions parameter symbol conditions ratings unit operating supply voltage v dd 2.45 to 3.6 v operating ambient temperature topr read operation ? 20 to 70 ? c write operation 0 to 70 ? c allowable dc operating conditions parameter symbol conditions ratings unit min typ max read mode operating current i ccr cs =0.1v dd , hold = wp =0.9v dd si=0.1v dd /0.9v dd , so=open v dd =v dd max operating frequency=30mhz 6ma write mode operating current (erase+page program) i ccw v dd =v dd max, t sse =80ms, t se =100ms, t che =250ms, t pp =0.5ms 15 ma cmos standby current i sb cs = hold = wp =v dd ? 0.3v, si=v ih /v il, so=open, v dd= v dd max 0 ? c to 70 ? c 10 ? a input leakage current i li v in =v ss to v dd , v dd =v dd max 2 ? a output leakage current i lo v in =v ss to v dd , v dd =v dd max 2 ? a input low voltage v il v dd =v dd max ? 0.3 0.3v dd v input high voltage v ih v dd =v dd min 0.7v dd v dd +0.3 v output low voltage v ol i ol =100 ? a, v dd =v dd min 0.2 v i ol =1.6ma, v dd =v dd min 0.4 output high voltage v oh i oh = ? 100 ? a, v dd =v dd min v dd ? 0.2 v power-on timing parameter symbol ratings unit min max time from power-on to read operation t pu _read 100 ? s time from power-on to write operation t pu _write 10 ms power-down time t pd 10 ms power-down voltage v bot 0.2 v pin capacitance at ta=25 ? c, f=1mhz parameter symbol conditions ratings unit max output pin capacitance c dq v dq =0v 12 pf input pin capacitance c in v in =0v 6pf note: these parameter values do not represent the results of measurements undertaken for a ll devices but rather values for some of the sampled devices. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
le25w81qe www.onsemi.com 17 ac characteristics parameter symbol ratings unit min typ max clock frequency f clk 30 mhz sck logic high level pulse width t clhi 16 ns sck logic low level pulse width t cllo 16 ns input signal rising/falling time t rf 20 ns cs setup time t css 10 ns sck setup time t cls 10 ns data setup time t ds 5 ns data hold time t dh 5 ns cs hold time t csh 10 ns sck hold time t clh 10 ns cs wait pulse width t cph 25 ns output high impedance time from cs t chz 15 ns output data time from sck t v 12 15 ns output data hold time t ho 1 ns hold setup time t hs 7 ns hold hold time t hh 3 ns output low impedance time from hold t hlz 9 ns output high impedance time from hold t hhz 9 ns wp setup time t wps 20 ns wp hold time t wph 20 ns write status register time t srw 5 15 ms page programming cycle time t pp 0.3 1.0 ms small sector erase cycle time t sse 0.08 0.3 s sector erase cycle time t se 0.1 0.4 s chip erase cycle time t che 0.25 3 s power-down time t dp 3 ? s power-down recovery time t prb 3 ? s output low impedance time from sck t clz 0 ns ac test conditions input pulse level 0v, 2.6v input rising/falling time 5ns input timing level 0.3v dd , 0.7v dd output timing level 1/2 ? v dd output load 30pf note: as the test conditions for "typ", the measurements are conducted using 2.6v for v dd at room temperature. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
le25w81qe www.onsemi.com 18 figure 20 status register write flowchart status register write start 05h set status register read command set status register write command program start on rising edge of cs end of status register write yes bit 0= ?0? ? 06h write enable 01h no * automatically placed in write disabled state at the end of the status register write data
le25w81qe www.onsemi.com 19 figure 21 erase flowcharts start 05h set status register read command set small sector erase command address 1 address 2 start erase on rising edge of cs end of erase bit 0 = ?0? ? yes small sector erase address 3 06h write enable d7h or 20h no * automatically placed in write disabled state at the end of the erase start 05h set status register read command set sector erase command address 1 address 2 start erase on rising edge of cs end of erase bit 0 = ?0? ? yes sector erase address 3 06h write enable d8h no * automatically placed in write disabled state at the end of the erase
le25w81qe www.onsemi.com 20 figure 22 page program flowchart start 05h set status register read command set chip erase command start erase on rising edge of cs end of erase bit 0 = ?0? ? yes chip erase 06h write enable c7h no * automatically placed in write disabled state at the end of the erase page program start 05h set status register read command set page program command address 1 address 2 start program on rising edge of cs end of programming yes bit 0= ?0? ? address 3 06h write enable 02h no * automatically placed in write disabled state at the end of the programming operation. data 0 data n
le25w81qe www.onsemi.com 21 figure 23 making diagrams ordering information device package shipping (qty / packing) LE25W81QES00-AH-1 vdfn8 5x6, 1.27p (pb-free / halogen free) 2000 / tape & real on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. 25w81 ymxxx 25w81 =specific device code y =production year, last number of a.d. m = production month xxx =serial no. 00

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