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mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) description the mh16v7245batj is 16777216-word x 72-bit dynamic ram module. this consist of eighteen industry standard 16m x 4 dynamic rams in tsop and three industry standard input buffer in tssop. the mounting of tsop on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. this is a socket-type memory module ,suitable for easy interchange or addition of module. features MH16V7245BATJ-5 mh16v7245batj-6 type name /ras access time (max.ns) /cas address /oe cycle power access time (max.ns) access time (max.ns) access time (max.ns) time (min.ns) dissipation (typ.w) 50 60 18 20 30 35 18 20 84 104 utilizes industry standard 16m x 4 rams tsop and industry standard input buffer in tssop 168-pin (84-pin dual in-line pacege) single 3.3v(+/-0.3v) supply operation low stand-by power dissipation . . . . . . . . 121mw(max) low operation power dissipation mh16v7245batj -5 . . . . . . . . . . . . . . . . . 8.53w(max) mh16v7245batj -6 . . . . . . . . . . . . . . . . . 7.88w(max) all input,output lvttl compatible includes(0.22uf x 20) decoupling capacitors 4096 refresh cycle every 64ms (a0~a11) jedec standard pin configration & buffered pd pin buffered input except /ras and dq gold plating contact pads application main memory unit for computers , microcomputer memory pd&id table pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 id0 id1 - 6 1 = nc , 0 = drive to vol pd pin . . . buffered. when /pde is low, pd information can be read id pin . . . non-buffered 1 1 1 1 1 1 1 0 0 0 7.12 5.95 1 pin configuration 1pin 10pin 11pin 40pin 41pin 84pin 85pin 94pin 95pin 124pin 125pin 168pin front side back side - 5 1 1 1 1 1 0 0 0 0 0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) pin configuration reserved: reserved use rfu: reserved for future use pin no. pin name pin no. pin name pin no. pin name pin no. pin name 9 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 51 85 86 87 88 89 90 91 92 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 93 127 128 129 130 131 132 133 134 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 135 reserved vss dq36 dq37 dq38 dq39 vcc dq40 dq41 dq42 dq43 dq44 vss dq45 dq46 dq47 dq48 dq49 vcc dq50 dq51 dq52 dq53 vss reserved reserved vcc rfu rfu vss a1 a3 a5 a7 a9 vcc rfu b0 reserved reserved reserved reserved vss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 vss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 dq16 dq17 vss reserved reserved vcc /we0 /cas0 /ras0 /oe0 vss a0 a2 a4 a6 a8 vcc rfu rfu dq26 vss /oe2 /ras2 /cas4 reserved /we2 vcc reserved reserved dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 rfu rfu rfu rfu dq25 dq27 dq30 vss dq28 dq29 dq31 vcc dq32 vss pd1 pd3 pd5 pd7 id0 vcc dq34 dq33 dq35 dq62 vss rfu reserved /pde vcc reserved reserved dq54 dq55 vss dq56 dq57 dq58 dq59 vcc dq60 rfu rfu rfu rfu dq61 dq63 dq66 vss dq64 dq65 dq67 vcc dq68 vss pd2 pd4 pd6 pd8 id1 vcc reserved reserved dq70 dq69 dq71 a10 a11 2 nc
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) block diagram /ras /cas /w /oe dq1 ~dq4 d1 /ras /cas /w /oe dq1 ~dq4 d2 /ras /cas /w /oe dq1 ~dq4 d3 /ras /cas /w /oe dq1 ~dq4 d4 /ras /cas /w /oe dq1 ~dq4 d5 /ras /cas /w /oe dq1 ~dq4 d6 /ras /cas /w /oe dq1 ~dq4 d7 /ras /cas /w /oe dq1 ~dq4 d8 /ras /cas /w /oe dq1 ~dq4 d9 dq32 dq33 dq34 dq35 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 /ras0 /cas0 /we0 /oe0 /ras /cas /w /oe dq1 ~dq4 m5m465405b m5m465405b d10 /ras /cas /w /oe dq1 ~dq4 d11 /ras /cas /w /oe dq1 ~dq4 d12 /ras /cas /w /oe dq1 ~dq4 d13 /ras /cas /w /oe dq1 ~dq4 d14 /ras /cas /w /oe dq1 ~dq4 d15 /ras /cas /w /oe dq1 ~dq4 d16 /ras /cas /w /oe dq1 ~dq4 d17 /ras /cas /w /oe dq1 ~dq4 d18 dq68 dq69 dq70 dq71 dq64 dq65 dq66 dq67 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dq36 dq37 dq38 dq39 /ras2 /cas4 /we2 /oe2 a0 b0 a1~a11 d1~d9 d10~d18 d1~d18 . . . vcc vss c 1 ~c 20 d1~d18 & input buffer row address strobe input column address strobe input write control input output enable input data i/o address input power supply ground /ras0, /ras2 /cas0, /cas2 /we0, /we2 /oe0, /oe2 a0~a11, b0 dq0~dq71 vcc vss pin name function m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b m5m465405b 3
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) function the mh16v7245batj provide, in addition to normal read, write, and read-modify-write operations, table 1 input conditions for each mode operation /ras /cas a number of other functions, e.g., hyper page mode, /cas before /ras refresh, and delayed-write. the input conditions for each are shown in table 1. inputs input/output refresh remark /w row address address column output read write (early write) write (delayed write) read-modify-write /cas before /ras refresh standby hidden refresh act act act act act act nac act act act act act act dnc nac act act act dnc nac dnc apd apd apd apd dnc dnc dnc opn vld ivd vld vld opn opn no no no no yes yes no hyper page mode identical note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open /oe act dnc dnc act act dnc dnc apd apd apd apd dnc dnc dnc input vld vld vld dnc dnc opn opn 4
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) (ta = 0~70?, vcc = 3.3v+/-0.3v, vss = 0v, unless otherwise noted) (ta=0~70?, vcc=3.3v+/-0.3v, vss=0v, unless otherwise noted) (note 2) absolute maximum ratings symbol vcc io pd topr tstg parameter conditions ratings -0.5~4.6 50 21.6 0~70 -40~100 with respect to vss ta=25? supply voltage output current power dissipation operating temperature storage temperature recommended operating conditions unit limits min nom max v v v v 3.6 0 vcc+0.3 3.3 0 3.0 0 2.0 parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage vcc symbol vss vih vil (ta=0~70?, unless otherwise noted) (note 1) note 1 : all voltage values are with respect to vss electrical characteristics capacitance symbol voh vol ioz i i icc1 (av) icc2 icc4(av) icc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current (except /ras) average supply current from vcc operating (note 3,4,5) (note 3,4,5) (note 3) supply current from vcc , stand-by average supply current from vcc hyper-page-mode average supply current from vcc /cas before /ras refresh mode ioh=-2ma iol=2ma q floating 0v vout vcc 0v vin vcc+0.3, other input pins=0v /ras, /cas cycling trc=twc=min. output open /ras=/cas =vih, output open /ras=/cas=/we 3 vcc -0.2, output open /ras=vil,/cas cycling tpc=min. output open /cas before /ras refresh cycling trc=min. output open note 2: current flowing into an ic is positive, out is negative. 3: icc1 (av), icc3 (av), icc4 (av) and icc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: icc1 (av) and icc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: under condition of colmun address being changed once or less while /ras=vil and /cas=vih i i (ras) input current (/ras) 0v vin vcc+0.3, other input pins=0v 2.4 0 -10 -10 -90 vcc 0.4 10 10 90 v v ua ua ma ma ma ma ua limits min max unit typ pf pf pf ci ci (/ras) c(dq) symbol parameter test conditions input capacitance, /ras input input/output capacitance,data vi=vss f=1mhz vi=25mvrms input capacitance, except /ras input 15 80 18 unit v ma w ? ? -6 2360 38 29 1820 1640 2360 0.8 -0.3 vi vo -0.5~ 4.6 -0.5~ 4.6 5 -5 -5 input voltage output voltage -5 -6 -6 2180 2180
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 6 (ta=0~70?, vcc=3.3v+/-0.3v, vss=0v, unless otherwise noted , see notes 6,14,15) switching characteristics note 6: an initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /ras-only refresh or /cas before /ras refresh). note the /ras may be cycled during the initial pause . and any 8 /ras or /ras /cas cycles are required after prolonged periods (greater than 64 ms) of /ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to 1ttl loads and 50pf,voh=2.4v(ioh=-2ma) and vol=0.4v(iol=-2ma). the reference levels for measuring of output signals are 2.0v (voh) and 0.8v (vol). 8: assumes that trcd 3 trcd(max), tasc 3 tasc(max) and tcp 3 tcp(max). 9: assumes that trcd trcd(max) and trad trad(max). if trcd or trad is greater than the maximum recommended value shown in this table,trac will increase by amount that trcd exceeds the value shown. 10: assumes that trad 3 trad(max) and tasc tasc(max). 11: assumes that tcp tcp(max) and tasc 3 tasc(max). 12: toez (max), twez(max), toff(max) and trez(max) defines the time at which the output achieves the high impedance state (iout i+/-10uai) and is not reference to voh(min) or vol(max). 13: output is disable after both /ras and /cas go to high limits parameter symbol unit -6 min max tcac trac taa tcpa toea tclz toff toez tohc tohr twez trez access time from /cas access time from /ras columu address access time access time from /cas precharge output low impedance time from /cas low output disable time after /cas high output disable time after /oe high access time from /oe output hold time /cas high output hold time /ras high output disable time after /ras high output disable time after /we high (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) (note 12,13) (note 12) (note 7) (note 13) (note 12) (note 12,13) ns ns ns ns ns ns ns ns ns ns ns ns (ta=0~70?, vcc=3.3v+/-0.3v, vss=0v, unless otherwise noted ,see notes 14,15) limits parameter symbol unit (note21) (note16) (note17) (note18) timing requirements (for read, write, read-modify-write ,refresh, and hyper-page mode cycles) note 14: the timing requirements are assumed tt =2ns. 15: vih(min) and vil(max) are reference levels for measuring timing of input signals. 16: trcd(max) is specified as a reference point only. if trcd is less than trcd(max), access time is trac. if trcd is greater than trcd(max), access time is controlled exclusively by tcac or taa. . 17: trad(max) is specified as a reference point only. if trad 3 trad(max) and tasc tasc(max), access time is controlled exclusively by taa. 18: tasc(max) is specified as a reference point only. if trcd 3 trcd(max) and tasc 3 tasc(max), access time is controlled exclusively by tcac. 19: either tdzc or tdzo must be satisfied. 20: either trdd or tcdd or todd must be satisfied. 21: tt is measured between vih(min) and vil(max). (note19) (note20) (note19) (note20) min max 64 40 25 50 -6 tref trp trcd tcrp trpc tcpn trad tasr tasc trah tcah tt tdzc tdzo tcdd todd trdd refresh cycle time /ras high pulse width delay time, /ras low to /cas low delay time, /cas high to /ras low delay time, /ras high to /cas low /cas high pulse width column address delay time from /ras low row address setup time before /ras low column address setup time before /cas low row address hold time after /ras low column address hold time after /cas low transition time delay time, data to /cas low delay time, data to /oe low delay time, /cas high to data delay time, /oe high to data delay time, /ras high to data 0 40 9 10 10 7 5 10 5 0 1 0 0 20 20 15 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (note20) 5 20 35 38 20 60 20 20 20 15 10 10 -5 min max 18 30 33 50 18 18 18 18 13 5 10 10 min max 64 32 20 50 0 30 9 10 8 5 3 8 5 0 1 0 0 18 18 13 10 13 -5
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 7 read and refresh cycles limits parameter symbol unit (note 22) write cycle (early write and delayed write) (note 22) limits parameter symbol unit (note 24) ns ns ns ns ns ns ns ns ns ns ns ns twc tras tcas tcsh trsh twcs twch tcwl trwl twp tds tdh write cycle time /ras iow pulse width /cas iow pulse width /cas hold time after /ras iow write setup time before /cas low write hold time after /cas iow /ras hold time after /cas iow /cas hold time after /w iow /ras hold time after w iow data setup time before /cas iow or w iow data hold time after /cas iow or w iow write pulse width note 22: either trch or trrh must be satisfied for a read cycle. -6 10000 10000 min max 10000 10000 10 0 104 60 10 35 20 10 10 -5 15 -6 min max trc tras tcas tcsh trsh trcs trch trrh tral toch torh tcal read cycle time /ras iow pulse width /cas iow pulse width /cas hold time after /ras iow read setup time after /cas high read hold time after /cas iow /ras hold time after /cas iow read hold time after /ras iow column address to /ras hold time /cas hold time after /oe iow /ras hold time after /oe iow column address to /cas hold time ns ns ns ns ns ns ns ns ns ns ns ns 0 0 104 60 10 43 20 0 35 15 20 read-write and read-modify-write cycles limits parameter symbol unit (note23) (note24) read write/read modify write cycle time ras iow pulse width cas iow pulse width cas hold time after ras low ras hold time after cas low read setup time before cas low delay time, cas iow to w iow delay time, ras iow to w iow delay time, address to w iow oe hold time after w iow trwc tras tcas tcsh trsh trcs tcwd trwd tawd toeh ns ns ns ns ns ns ns ns ns ns (note24) (note24) note 23: trwc is specified as trwc(min)=trac(max)+todd(min)+trwl(min)+trp(min)+4tt. 24: twcs, tcwd,trwd ,tawd and,tcpwd are specified as reference points only. if twcs 3 twcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if tcwd 3 tcwd(min), trwd 3 trwd (min), tawd 3 tawd(min) and tcpwd 3 tcpwd(min) (for hyper page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until /cas or /oe goes back to vih) is indeteminate. min max -6 10000 10000 49 133 44 77 0 32 72 47 15 89 18 15 -5 min 0 0 84 50 8 30 18 0 30 13 18 13 10000 10000 max 10000 10000 8 0 84 50 8 30 18 8 8 -5 13 min max 13 -5 min max -5 10000 10000 43 109 38 65 0 28 60 40 13 75
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 8 hyper page mode cycle (read, early write, read -write, read-modify-write cycle, read write mix cycle,hi-z control by /oe or /we) (note 25) note 25: all previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 26: tras(min) is specified as two cycles of cas input are performed. 27: tcp(max) is specified as a reference point only. limits parameter symbol (note26) (note27) /cas before /ras refresh cycle (note 28) limits parameter symbol unit note 28: eight or more /cas before /ras cycles instead of eight /ras cycles are necessary for proper operation of /cas before /ras refresh mode. min max 18 100000 -6 min max -6 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns thpc thprwc tras tcp tcprh tcpwd tchol toepe twpe thcwd thawd thpwd thcod thaod thpod hyper page mode read/write cycle time /ras iow pulse width for read write cycle /cas high pulse width /ras hold time after /cas precharge delay time, /cas precharge to w low hyper page mode read write/read modify write cycle time hold time to maintain the data hi-z until /cas access /oe pulse width (hi-z control) /w pulse width (hi-z control) delay time, /cas low to /w low after read delay time, address to /w low after read delay time, /cas precharge to /w low after read delay time, /cas low to /oe high after read delay time, address to /oe high after read delay time, /cas prechargeto /oe high after read 38 25 77 10 50 66 7 7 7 32 47 50 15 30 33 (note24) ns ns ns ns tcsr tchr trsr trhr /cas setup time before /ras low /cas hold time after /ras low read setup time before /ras low read hold time after /ras low 10 15 5 5 min max 15 100000 -5 33 20 65 8 43 55 7 7 7 28 40 43 13 25 28 min max -5 5 5 10 15
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 9 timing diagrams (note 29) read cycle dq (inputs) /ras /w dq (outputs) /oe /cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t rch t rrh t asr t crp t rp hi-z hi-z row row address note 29 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. v ih v il address column address t dzc hi-z t oez t odd t oea t och t dzo t orh t rez t off t cal t ohr t ohc t cdd t wez data valid t rdd a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 10 early write cycle dq (inputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp hi-z row column row address data valid /ras /w dq (outputs) v ih v il /oe address address t ds t dh /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 11 delayed write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 12 read-write, read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b10
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 13 hyper page mode read cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr t wez dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 14 hyper page mode early write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr address column-1 row address t rp t cas row t asc t wcs v ih v il t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t cah t asc t asc hi-z t wch t wcs t wch t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh t cal t cal t crp dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 15 t dzo hyper page mode read-write,read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl address column-1 row address row t cah t asc t rcs t rwd t dzc t ds column-2 t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t oez t oeh v ih v il t rad t cwd t awd t awd t cwd t aa t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd data valid-1 t crp dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 16 t dzo t wch t dh hyper page mode mix cycle (1) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac hi-z address column-1 row address t rp t cas row t asc t rcs t dzc v ih v il t dzo t oea t och data valid-1 t csh data valid-2 t hpc t cas t cp t cas column-2 column-3 t cah t asc t cah t asc t hprwc t cpwd t wp t wcs t ds t clz t cpa data valid-3 t aa t cal t cal t cwd t oez t odd t wez t oeh t oez t clz t oea t asr t crp t cac t odd t dh t ds data valid-3 t rwl t cwl t dz c t awd dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 17 t cpa data valid-1 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t cah t asc v ih v il t hpc data valid-3 t aa t cac t oez t ds t odd data valid-2 hi-z t dh t dzc hi-z column-1 t cah t asc t cah t asc column-2 column-3 t aa t wch t cac t oea t clz hi-z t cpa t cal t cp t cas t rch t wcs t wez t cal hyper page mode mix cycle (2) t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 18 hyper page mode read cycle ( hi-z control by oe ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t oez t cac data valid-3 t aa t clz hi-z t oepe t chol t oepe t oez t oea t och data valid-1 t ohr t ohc t crp t wez dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 19 hyper page mode read cycle ( hi-z control by w ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t wez t aa t cac data valid-3 t wpe t rch t rcs t clz hi-z t ohr t ohc t rrh t crp dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 20 /cas before /ras refresh cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t asr t crp t rpc t rp row column address address t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs hi-z v ih v il t oez t rp t chr t rez t rpc t rrh t off t ohr t ohc dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 21 hidden refresh cycle (read) (note 31) note 31: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t rrh t asr t rp hi-z address column row address data valid t ras t rc t rp t rsh row t asc address t ral hi-z t dzc v ih v il hi-z t dzo t oea t orh t odd t oez t rez t cdd t rch t rdd t ohr t ohc t off dq (inputs) /ras /w dq (outputs) /oe /cas a0~a11,b0
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) 22 package outline 133.35 unit:mm 127.35 3.0 31.75 4.0 3.0 3.0 8.89 23.50 43.18 9x1.27=11.43 29x1.27=36.83 2.0 2.0 6.35 6.35 43x1.27=54.61 1.27 2- +/-3.0 2- +/-2.0 17.78 17.78 3.0 4.0 3.52max
mitsubishi lsis mh16v7245batj -5, -6 preliminary spec. mitsubishi electric 5/nov./1998 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0277-0.0 ( / 23 ) keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1.these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to mitsubishi electric corporation or a third party. 2.mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.all information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. 6.if these products or technologies are subject the japanese export control restrictions,they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 7.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. 23

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