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1 www.pericom.com 10/22/14 description pericoms PI3V724 is a 7-channel video mux/demux used to switch between multiple vga sources or end points. in a note - book application where analog video signals are found in both the notebook and the dock, a switch solution is required to switch between the two video port locations. with the high bandwidth of ~1.7ghz, the signal integrity will remain strong even through the long fr4 trace between the notebook and the docking sta - tion. in addition to high signal performance, the video signals are also protected against high esd with integrated diodes to vdd and gnd that will support up to +/-4kv contact esd protection. in addition to switching, the product also integrates a monitor detection feature. te monitor detection feature works indepen - dently on each of the two outputs and allows automatic switching as well as a self generated hpd signal that lets the system know when a monitor is connected or disconnected. features ?? full vga 1:2 demux with vsis compliance r , g, b, hsync, vsync, ddc data, and ddc clk channels are switched ?? integrated monitor detection circuit allows automatic or manual control ?? generates hot plug output signal to inform system when monitor is present or not ?? dual power supply, 3.3v and 5v ?? integrated ddc level shifer from 5v to 3.3v(bi-directional) ?? integrated 5v h/v output bufer with +/-24ma drive ?? esd tolerance on video i/o pins up to +/-4kv contact per iec61000-4-2 specifcation ?? -3db bw of 1.7ghz (typ) ?? low xtalk, (-38db typ) ?? low and flat on-state resistance (ron = 4-ohm, ron(flat) = 0.5ohm, typ) ?? low input/output capacitance (con = 5.6pf, typ) ?? packaging (pb-free and green): 3 2-contact tqfn (zl) pin diagram gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 32 31 30 29 28 test gnd priority/sel out ce r g gnd v dd b h_source v_source ms sda_source scl_source rref sda1 sda2 scl1 scl2 v dd 5_in r1 r2 g1 g2 v dd b1 b2 h1_out h2_out v1_out v2_out PI3V724 1 to 2 vga demux 14-0168
2 www.pericom.com 10/22/14 block diagram g g1 v1 v2 r1 r g2 r2 h1_out h_source v_source h2_out sda_source scl_source 5v to 3.3v level shifter sda1 scl1 sda2 scl2 control logic +5v buffer buffer v v v v v v v detect detect logic control detection start logic priority/sel to timer timer pulse ms ce result en result en b v v v v v v v v buffer b1 b2 +5v buffer out rref PI3V724 1 to 2 vga demux 14-0168
3 www.pericom.com 10/22/14 pinout table pin # name ty pe description 1 r i/o red signal from source 2 g i/o green signal from source 3 gnd ground ground 4 vdd power 3.3v power supply 5 b i/o blue signal from source 6 h_source i horizontal synchronous signal from source. internal 300kohm pull-down 7 v_ sou rce i vertical synchronous signal from source. internal 300kohm pull-down 8 ms i mode select (switch between auto switch vs. manual switch). outx pins work regardless of ms pin status. internal pull down. 9 sda_source i/o ddc data signal from source 10 scl_source i/o ddc clock signal from source 11 rref i connect external resistor to ground to determine which application scheme best matches your design. for actual r values, please see page 6 12 sda1 i/o ddc data signal from vga connector 1 13 sda2 i/o ddc data signal from vga connector 2 14 scl1 i/o ddc clock signal from vga connector 1 15 scl2 i/o ddc clock signal from vga connector 2 16 vdd5_ i n i (power) 5v input power supply 17 v2_out o bufered, vertical synch signal output for vga connector #2 18 v1_out o bufered vertical synchronous signal driving vga connector #1 19 h2_out o bufered, horizontal synch signal output for vga connector #2 20 h1_out o bufered horizontal synchronous signal driving vga connector #1 21 b2 i/o un-bufered, blue signal driving vga connector 2 22 b1 i/o un-bufered, blue signal driving vga connector 1 23 vdd power 3.3v power supply 24 g2 i/o un-bufered, green signal driving vga connector 2 25 g1 i/o un-bufered, green signal driving vga connector 1 26 r2 i/o un-bufered, red signal driving vga connector 2 27 r1 i/o un-bufered, red signal driving vga connector 1 28 ce i chip enable input. if signal is low, then chip is fully functional. if signal is high, then ic is powered down and all i/os are hi-z 29 out o open drain output describing external monitor status. if connected, out is low, if not connected, out is hi-z. out will only provide the status of the chosen port. chosen port can be determined based on manual switching or automatic switching (please see truth table for more information on how to confgure into auto mode or manual mode) 30 priority/sel i output port selection or output port priority depending on ms pin status 31 gnd ground ground 32 test i please tie high or leave foating for normal operation. internal pull-up PI3V724 1 to 2 vga demux 14-0168
4 www.pericom.com 10/22/14 automatic switching scheme as external monitors are properly detected, the PI3V724 can support automatic switching. if only one monitor is connected, then the port is easily chosen regardless of what pin 30 (priority) pin status is. port selection (only one monitor is present) at power on, ms pin (pin 31) is checked to determine if auto switching is enabled or not (to enable, ms needs to be low). next the part will look to see if external monitors are connected or not. if only one monitor is connected, the PI3V724 will automatically en- able the signal path to drive the connected the monitor. out pin will then be pulled low. port selection (both monitors are present) at power on, ms pin (pin 31) is checked to determine if auto switching is enabled or not (to enable, ms needs to be low). next the part will look to see if external monitors are connected or not. if only both monitors are connected, the PI3V724 will then check the priority pin (pin 30). if pin 30 is low, then port 1 will have priority and therefore will be activated. however, if pin 30 is high, then port 2 will have priority and therefore port 2 will be enabled. state machine reset procedure ? if the monitor from chosen port is disconnected, the state machine is reset (to determine chosen port, see above). ? if ms pin status changes, state machine is reset ? if ce/ pin goes high then low again, state machine is reset ? if vdd goes low and then high again, state machine resets truth table ce/ ms (internal pull-down) switching mode pin 30 role sel priority result 0 0 automatic switching priority pin n/a 0 port1 has priority 0 0 automatic switching priority pin n/a 1 port 2 has priority 0 1 manual switch - ing selpin 0 n/a port 1 is active 0 1 manual switch - ing selpin 1 n/a port 2 is active 1 x n/a n/a x x all i/o's hi-z PI3V724 1 to 2 vga demux 14-0168
5 www.pericom.com 10/22/14 application note introduction PI3V724 is a full vga de-mux switch with integrated monitor detection circuit. port switching can be selected manually or auto- matically to ofer more fexibility to users. v v v v v v v detect detect logic control detection start logic priority/sel timer pulse ms ce result en result en b v v v v v v b1 b2 rref PI3V724 detection block diagram automatic monitor detection if ms pin (pin 8) is set to low or foat, PI3V724 enters auto switch mode. when external monitor(s) is/are properly detected, PI3V724 can support automatic switching. detection pulse when auto switch mode is selected via ms pin, PI3V724 sends a detection pulse through blue signal to check if any termination is present. once a monitor is attached, its termination is determined. PI3V724 will switch to the port with such termination accord- ingly. a detection pulse is sent by PI3V724 every 1.6 seconds when source or sink is not attached. furthermore, the detection pulse is sent immediately afer sensing vsync pulse. te detection pulse is of the width within 30us and the voltage level around 0.7v. PI3V724 detection pulse on blue b2 without source or sink device PI3V724 1 to 2 vga demux 14-0168
6 www.pericom.com 10/22/14 PI3V724 detection pulse on blue b2 immediately afer vsync pulse te detection pulse is generated by PI3V724 within the back porch period, which is before active blue video is delivered. back porch detection pulse active blue active blue PI3V724 vsync pulse (with negative polarity) vs. blue b2 at 1024x768@60hz PI3V724 1 to 2 vga demux 14-0168
7 www.pericom.com 10/22/14 port selection when PI3V724 is powered up, ms pin (pin 8) is checked to determine if auto switching is enabled or not. if ms pin is set to low, PI3V724 will determine if any monitor is attached. if only one monitor is connected, PI3V724 will automatically en?able the signal path to the attached monitor. /out pin (pin 29) will then be pulled low to indicate the presence of a monitor at the chosen port. if two monitors are attached to both output ports, PI3V724 will check the priority pin (pin 30). if priority pin is set to low, output port 1 will be prioritized and thus active. on the other hand, if priority pin is high, output port 2 will be prioritized and thus enabled. / out pin will then be pulled low. rref external value truth table rref application case supported (see page 8 for drawings) 330kohm case_150//75 250kohm case_75//75 500k case_75 application scheme with proper reference resistor assembled to rref pin (pin 11), monitors with various application schemes can be determined auto- matically. active blue detection pulse active blue back porch PI3V724 vsync pulse (with positive polarity) vs. blue b2 at 1280x1024@60hz PI3V724 1 to 2 vga demux 14-0168
8 www.pericom.com 10/22/14 if monitor on port is removed or if priority pin changes if monitor on port 1 is removed or if priority pin changes if monitor is unplugged state machine PI3V724 1 to 2 vga demux 14-0168
9 www.pericom.com 10/22/14 output pin behavior (pin 29) with auto switch enabled output pin behavior (pin 29) with manual switching mode enabled ms priority (0 = port 1) (1 = port 2) port 1 monitor status 0 = unplug, 1 = plug port 2 monitor status 0 = unplug, 1 = plug port 1 path port 2 path out status 0 0 0 0 on off hi z 0 0 0 1 off on low 0 0 1 0 on off low 0 0 1 1 on off low 0 1 0 0 off on hi z 0 1 0 1 off on low 0 1 1 0 on off low 0 1 1 1 off on low ms priority (0 = port 1) (1 = port 2) port 1 monitor status 0 = unplug, 1 = plug port 2 monitor status 0 = unplug, 1 = plug port 1 path port 2 path out status 1 0 0 x on off hi z 1 0 1 x on off low 1 1 x 0 off on hi z 1 1 x 1 off on low rref (pin 11) external value truth table rref application case supported (see page 8 for drawings) 330kohm case_150//75 250kohm case_75//75 500k case_75 PI3V724 1 to 2 vga demux 14-0168
10 www.pericom.com 10/22/14 PI3V724 application drawing for case 75//75 monitors notebook case_75//75 dock 150 r2 150 r1 75 75 r5 75 r3 r4 gpu 724 PI3V724 application drawing for case 150//75 PI3V724 application drawing for case 75 monitors notebook case_150//75 dock 150 rb 150 75 re 75 rc rd gpu 724 150 ra monitors notebook case_75 dock 75 re 75 rc gpu 724 75 ra PI3V724 1 to 2 vga demux 14-0168
11 www.pericom.com 10/22/14 application diagram for ddc path PI3V724 1 to 2 vga demux 14-0168
12 www.pericom.com 10/22/14 note: stresses greater than those listed under maximum rat- ings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) v dd (power supply)..3.0v to 3.6v v dd 5_in(power supply).4.5v to 5.5v operating ambient temperature.40 o c to +85 o c storage temperature-55 o c to +150 o c dc electricalcharacteristics for video switching over operating range (t a = C40c to +85c,v dd = 3.3v10% ,v dd 5_in = 5v) parameters description test conditions(1) min. ty p.(2) max. units v ih input high voltage (sel/priority and ms pins) guaranteed high level 2 - - v v il input lowvoltage (sel/priority, and ms pins) guaranteed low level C0.5 - 0.8 v v ik clamp diode voltage v dd = max., iselx = C18ma - C0.8 C1.2 v i ih input high current (sel/priority) v dd = max., vselx = v dd - - 5 a i il input low current (sel/priority) v dd = max., vselx = gnd - - 5 a i off_h/v power down leakage current for h/v channels only vdd = 0v, vb = 0v, va 3.6 - - 22 ma i off_ddc power down leakage current for ddc channels only vdd = 0v, vb = 0v, va 3.6 - - 5 ma ioz (ddc and rgb path) switch leakage when switch is of v dd = 3.6v, ce/ = high, vinput = 0v to vdd 5 a r on_rgb switch on-resistance for rgb path (3) v dd = min., 0v vinput 1.2v, iinput = C40ma - 4.8 5.6 ? r flat(on) on-resistance flatness for rgb path (4) v dd = min., vinput @ 0v and 1.2v, iinput = C40ma - 0.5 +1 ? ? ron on-resistance match from center ports to any other port (rgb path only)(4) v dd = min., 0v vinput 1.2v, iinput = C40ma - 0.1 1 ? v oh (h/v) output high for h1_out/v1_out signals v dd 5 = 5v, i oh = -24ma 3.0 vdd5 v v ol(h/v) output low for h1_out/v1_out signals v dd 5 = 5v, i ol = 24ma 0 0.8 v vout _ ddc ddc switch path ouput voltage vdd = min, vinput = >2v (either side, since ddc path is bi-directional). 2 v PI3V724 1 to 2 vga demux 14-0168
13 www.pericom.com 10/22/14 capacitance (ta = -40o to+85oc, f = 1mhz) parameters (4) description test conditions(1) ty p.(2) units c in input capacitance 2.0 pf c off _com rgb capacitance, switch off 3.4 pf c off _p1p2 r1, g1, b1 or r2, g2, b2 switch of capaci- tance 2.4 pf c on_rgb rgb switch capacitance, switch on b path 5.8 pf c on_ddc ddc switch capacitance, switch on 5.8 pf power supply characteristics parameters description test conditions(1) min. ty p.(2) max. units i cc _ 3.3v rail quiescent power supply current for 3.3v power rail v dd = 3.6v, 5v_v dd = 5.5v v sel = gnd or vdd - 250 500 a i cc _vdd5_ i n quiescent power supply current for 5vv dd 5v_v dd = 5.5v, v dd = 3.6v, v sel = gnd or v dd 100 500 na iccq_3.3v chip disabled ce/ = high 10 a iccq _vdd5_ i n chip disabled ce/ = high 100 500 na dynamic electrical characteristics over the operating range (t a =-40o to+85oc,v dd =3.3v10%, gnd=0v) parameters description test conditions min. ty p.(2) max. units xtalk crosstalk f = 250mhz, see fig. 2 - -38 - db oirr off isolation f = 250mhz, see fig. 3 - -46 - db bw bandwidth C3db see fig. 1 - 1.7 - ghz freq = 10mhz (vga) -1.77 db iloss insertion loss for rgb path with 75-ohm load freq = 100mhz (xga) -1.88 db freq = 300mhz (uxga) -2.09 db parameters description min. ty p. (2) max. units t pd propagation delay(2,3) - 0.25 ns t pzh , t pzl line enable time -selto input, output 0.5 - 15 ns t phz , t plz line disable time -selto input, output 0.5 - 10 ns t sk(p) skew between opposite transitions of the same output (tphl-tplh) (2) - 0.1 0.2 ns t rise (h/v) horizontal/vertical synchronous output rise time (h1_out, v1_out) 1.5 ns t fall (h/v) horizontal/vertical synchronous output fall time (h1_out, v1_out) 1.6 ns PI3V724 1 to 2 vga demux 14-0168
14 www.pericom.com 10/22/14 1 description: 32-contact, thin fine pitch quad flat no-lead (tqfn) package code: zl (zl32) document control #: pd-2044 revision: a date: 10/09/09 09-0125 pericom semiconductor corporation ? 1-800-435-2336 ordering code package code package description PI3V724zle zl 32-contact, tin fine pitch quad flat no-lead (tqfn) notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free and green ? x sufx = tape/reel PI3V724 1 to 2 vga demux 14-0168

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