? semiconductor components industries, llc, 2013 october, 2013 ? rev. 13 1 publication order number: mc74hc03a/d mc74hc03a quad 2-input nand gate with open-drain outputs high ? performance silicon ? gate cmos the mc74hc03a is identical in pinout to the ls03. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. the hc03a nand gate has, as its outputs, a high ? performance mos n ? channel transistor. this nand gate can, therefore, with a suitable pullup resistor, be used in wired ? and applications. having the output characteristic curves given in this data sheet, this device can be used as an led driver or in any other application that only requires a sinking current. features ? output drive capability: 10 lsttl loads with suitable pullup resistor ? outputs directly interface to cmos, nmos and ttl ? high noise immunity characteristic of cmos devices ? operating voltage range: 2.0 to 6.0 v ? low input current: 1 a ? in compliance with the jedec standard no. 7 a requirements ? chip complexity: 28 fets or 7 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant pin 14 = v cc pin 7 = gnd * denotes open-drain outputs logic diagram 3,6,8,11 y* 1,4,9,12 a 2,5,10,13 b output protection diode v cc pinout: 14 ? lead packages (top view) 13 14 12 11 10 9 8 2 1 34567 v cc b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 gnd http://onsemi.com l l h h l h l h function table inputs output ab z z z l y z = high impedance see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information marking diagrams a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package tssop ? 14 dt suffix case 948g 14 1 soic ? 14 d suffix case 751a 14 1 hc03ag awlyww 1 14 hc 03a alyw 1 14 (note: microdot may be in either location)
mc74hc03a http://onsemi.com 2 ??????????????????????? ??????????????????????? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? v cc ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ?????????????? ?????? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 20 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 25 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 50 ?? ?? ???? ???? ???? ?????????????? ?????????????? ?????????????? ?????? ?????? ?????? ?? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? c ???? ???? ???? ?????????????? ?????????????? ?????????????? ?????? ?????? ?????? ?? ?? ?? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recomme nded operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ?derating ? soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c recommended operating conditions ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ???? ???? v cc ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? c ???? ???? ???? ?????????????? ?????????????? ?????????????? ??? ??? ??? ???? ???? ???? ?? ?? ?? design guide criteria value unit internal gate count* 7.0 ea internal gate propagation delay 1.5 ns internal gate power dissipation 5.0 w speed power product 0.0075 pj *equivalent to a two ? input nand gate this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc03a http://onsemi.com 3 dc characteristics (voltages referenced to gnd) v cc v guaranteed limit symbol parameter condition ? 55 to 25 c 85 c 125 c unit v ih minimum high ? level input voltage v out = 0.1v or v cc ? 0.1v |i out | 20 a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum low ? level input voltage v out = 0.1v or v cc ? 0.1v |i out | 20 a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v ol maximum low ? level output voltage v out = 0.1v or v cc ? 0.1v |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 1.0 10 40 a i oz maximum three ? state leakage current output in high ? impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10 a ac characteristics (c l = 50 pf, input t r = t f = 6 ns) v cc v guaranteed limit symbol parameter ? 55 to 25 c 85 c 125 c unit t plz , t pzl maximum propagation delay, input a or b to output y (figures 1 and 2) 2.0 3.0 4.5 6.0 120 45 24 20 150 60 30 26 180 75 36 31 ns t tlh , t thl maximum output transition time, any output (figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance 10 10 10 pf c out maximum three ? state output capacitance (output in high ? impedance state) 10 10 10 pf c pd power dissipation capacitance (per buffer)* typical @ 25 c, v cc = 5.0 v, v ee = 0 v pf 8.0 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc03a http://onsemi.com 4 figure 1. switching waveforms c l * *includes all probe and jig capacitance test point device under test output figure 2. test circuit 1k r pd v cc input a 90% 50% 10% t f t r gnd v cc output y t pzl t thl high impedance v ol 10% t plz 90% 50% 10% v o , output voltage (volts) 012345 0 5 10 15 20 25 i d , sink current (ma) figure 3. open ? drain output characteristics a1 b1 a2 b2 an bn 1/4 hc03 1/4 hc03 1/4 hc03 y1 y2 yn typical t=25 c t=25 c t=85 c t=125 c expected minimum* v cc =5v *the expected minimum curves are not guarantees, but are design aids. v cc pullup resistor output output = y1 ? y2 ? . . . ? yn = a1b1 ? a2b2 ? . . . ? anbn figure 4. wired and led1 1/4 hc03 led2 led enable v cc + v r - + v f - 1/4 hc03 v cc design example conditions: i d 10ma typical curve, at i d =10ma, v ds 0.4v r v cc v f v o i d 5v 1.7v 0.4v 10ma use r = 270 290 figure 5. led driver with blanking
mc74hc03a http://onsemi.com 5 ordering information device package shipping ? mc74hc03adg soic ? 14 (pb ? free) 55 units / rail mc74hc03adr2g soic ? 14 (pb ? free) 2500 / tape & reel mc74hc03adtr2g tssop ? 14 (pb ? free) 2500 / tape & reel nlv74hc03adg* soic ? 14 (pb ? free) 55 units / rail nlv74hc03adr2g* soic ? 14 (pb ? free) 2500 / tape & reel NLV74HC03ADTR2G* tssop ? 14 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable
mc74hc03a http://onsemi.com 6 package dimensions soic ? 14 nb case 751a ? 03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc03a http://onsemi.com 7 package dimensions tssop ? 14 dt suffix case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc03a http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 mc74hc03a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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