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1/11 august 2001 n high speed : t pd = 5.5ns (typ.) at v cc =3.3v n 5v tolerant inputs n input voltage level : v il =0.8v, v ih =2v at v cc =3v n low power dissipation: i cc =4 m a (max.) at t a =25 c n low noise: v olp = 0.3v (typ.) at v cc = 3.3v n symmetrical output impedance: |i oh |=i ol = 4ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) n pin and function compatible with 74 series 594 n improved latch-up immunity n power down protection on inputs description the 74lvx594 is a low voltage cmos 8 bit shift register with output register fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power, battery operated and low noise 3.3v applications. this device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit d-type storage register. separate clocks and direct overriding clear (sclr, rclr) are provided for both the shift register and the storage register. a serial (qh') output is provided for cascading purposes. both the shift register and storage register use positive-edge triggered clocks. if the clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v system. it combines high speed performance with the true cmos low power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvx594 low voltage cmos 8 bit shift register with output register (5v tolerant inputs) pin connection and iec logic symbols order codes package tube t & r sop 74LVX594M 74LVX594Mtr tssop 74lvx594ttr tssop sop
74lvx594 2/11 input equivalent circuit pin description truth table x : don't care pin no symbol name and function 1, 2, 3, 4, 5, 6, 7, 15 qa to qh data outputs 9 qh' serial data output 10 sclr shift register clear input 11 sck shift register clock input 13 rclr storage register clear input 14 si serial data input 12 rck storage register clock input 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs si sck sclr rck rclr x x l x x shift register is clear lhxx first stage of shift register goes low other stages store the data of previ- ous stage, respectively hhxx first stage of shift register goes high other stages store the data of previ- ous stage, respectively l h x x shift register state is not changed xxxxl storage register is cleared xxx h shift register data is stored in the storage register x x x h storage register state is not changed
74lvx594 3/11 logic diagram this logic diagram has not be used to estimate propagation delays
74lvx594 4/11 timing chart absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current -20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c
74lvx594 5/11 recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2.0v dc specifications dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) (v cc = 3.3v) 0 to 100 ns/v symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 2.0 2.0 2.0 3.6 2.4 2.4 2.4 v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 0.8 0.8 0.8 3.6 0.8 0.8 0.8 v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 3.0 i o =-4 ma 2.58 2.48 2.4 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 i i input leakage current 3.6 v i =5vorgnd 0.1 1 1 m a i cc quiescent supply current 3.6 v i =v cc or gnd 44040 m a symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l =50pf 0.3 0.5 v v olv -0.5 -0.3 v ihd dynamic high voltage input (note 1, 3) 3.3 2 v ild dynamic low voltage input (note 1, 3) 3.3 0.8
74lvx594 6/11 ac electrical characteristics (input t r =t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t plh t phl propagation delay time (rck - qn) 2.7 15 5.5 9.5 1.0 10.0 1.0 10.0 ns 2.7 50 9.0 13.0 1.0 14.5 1.0 14.5 3.3 (*) 15 4.9 8.2 1.0 8.8 1.0 8.8 3.3 (*) 50 8.1 11.9 1.0 13.1 1.0 13.1 t plh t phl propagation delay time (sck - qh') 2.7 15 6.5 11.0 1.0 12.5 1.0 12.5 ns 2.7 50 9.2 14.0 1.0 16.0 1.0 16.0 3.3 (*) 15 5.5 9.2 1.0 9.9 1.0 9.9 3.3 (*) 50 8.4 12.5 1.0 13.9 1.0 13.9 t phl propagation delay time (rclr - qn) 2.7 15 7.3 11.0 1.0 13.0 1.0 13.0 ns 2.7 50 10.5 14.5 1.0 16.0 1.0 16.0 3.3 (*) 15 6.0 9.8 1.0 10.6 1.0 10.6 3.3 (*) 50 9.0 13.1 1.0 14.4 1.0 14.4 t plh t phl propagation delay time (sclr - qh') 2.7 15 6.3 10.5 1.0 12.0 1.0 12.0 ns 2.7 50 9.0 13.5 1.0 15.5 1.0 15.5 3.3 (*) 15 5.6 9.2 1.0 10.0 1.0 10.0 3.3 (*) 50 8.5 12.4 1.0 14.0 1.0 14.0 f max maximum clock frequency 2.7 15 70 110 60 60 mhz 2.7 50 40 90 35 35 3.3 (*) 15 80 120 70 70 3.3 (*) 50 55 105 50 50 t w(h) minimum pulse width (sck, rck) 2.7 50 6.5 6.5 6.5 ns 3.3 (*) 50 5.5 5.5 5.5 t w(l) minimum pulse width (sclr,rclr) 2.7 50 5.0 5.0 5.0 ns 3.3 (*) 50 5.0 5.0 5.0 t s minimum set-up time (si - cck) 2.7 50 3.5 3.5 3.5 ns 3.3 (*) 50 3.0 3.0 3.0 t s minimum set - up time (sck, rck) 2.7 50 9.0 9.0 9.0 ns 3.3 (*) 50 85. 8.5 8.5 t s minimum set - up time (scrl - rck) 2.7 50 8.0 8.0 8.0 ns 3.3 (*) 50 7.5 7.5 7.5 t h minimum hold time 2.7 50 1.5 1.5 1.5 ns 3.3 (*) 50 1.5 1.5 1.5 t rem minimum clear- removal time 2.7 50 3.0 3.0 3.0 ns 3.3 (*) 50 3.0 3.0 3.0 t oslh t oshl output to output skew time (note1, 2) 2.7 50 0.5 1.0 1.5 1.5 ns 3.3 (*) 50 0.5 1.0 1.5 1.5
74lvx594 7/11 capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r t =z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 3.3 7101010pf c out output capacitance 3.3 9 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 55 pf
74lvx594 8/11 waveform 1 : propagation delays, setup and hold times (f=1mhz; 50% duty cycle) waveform 2: minimum pulse width (f=1mhz; 50% duty cycle)
74lvx594 9/11 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
74lvx594 10/11 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
74lvx594 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - swit zerland - united kingdom ? http://w ww.st.com 11/11

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