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r08 ds01 21 ej0100 re v.1.00 pag e 1 of 18 mar 20, 2014 the mark shows major revised points. the revise d po in ts ca n be easily s ear ched by copying an "" in the pdf fil e an d sp ec ifying it in the "find what:" fiel d. preliminary data sheet ps9551al4 optically isolated delta-sigma modulator description the ps 95 51a l4 is an op ticall y iso lat ed d elt a ? sigma modu la tor that in cl udes high -accur acy a/d convertor and converts an analog voltage input into one-bit data stream. ps9551al4 provides effec ti ve number of bit (enob) is 12 bits (typ) with a sinc 3 digital filter. the ps9551al4 is de signed spe cifica ll y for high common mode transient immunity (cmr) and high lin ea rity (n onlinearity). the ps9551al4 is suitable for curr ent sensing and voltage sensing in motor drives. features ? internal reference voltage tolerance (g e = 1% max.) ? effective number of bit (enob = 12 bits typ.) ? operating ambient temperature (t a = ? 40 to 105 c) ? non-linearity (i nl = 0.14 max.) ? input offset voltage (v os = 3 mv max.) ? in put offs et voltage dr ift vs. temperature ( ? dvos/dt a ? = 2 c t yp .) ? output clock frequency (f clk = 10 mhz typ.) ? high common mode transient immun it y (cmr = 15 kv/ ? pac kage: 8-pin dip lead bending type (gull-wing) for long creepage distance for surface mount (l4) ? e mboss ed tape product: ps9551al4-e3: 1 000 pcs/reel ? pb-free product ? safety s ta ndards ? ul approved: no. e72422 ? csa approved: no. ca 101391 (ca5a, can /c sa-c22.2 60065, 60950) ? semko approved (en 60065, en60950) ? din en 60 74 7-5-5 (vde 0884-5) ap proved (op ti on) applications ? ac servo, inverter ? solar inverter ? measurement equipment r08ds0121ej0100 rev.1.00 mar 20, 2014 1. v dd1 2. v in+ 3. v in ? 4. gnd1 5. gnd2 6. mdat 7. mclk 8. v dd2 1 2 43 6 5 8 7 shield a/d converter decorder pin connection (top view) a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08d s01 21ej 01 00 rev.1.0 0 page 2 of 18 mar 20, 2014 package dimensions (unit: mm) lead bending type (gull-wing) for long creepage distance for surface mount (l4) 9.25 +0.5 ?0.25 6.5 +0.5 ?0.1 10.05 0.4 0.620.25 0.20.15 3.70.35 3.50.2 1.01 +0.4 ?0.2 2.54 0.50.15 photocoupler construction .nim retemarap air di st ance 8 mm outer creepage distance 8 mm isolation distance 0.4 mm a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08d s01 21ej 01 00 rev.1.0 0 page 3 of 18 mar 20, 2014 marking example r 9551a nt431 no. 1 pin mark 4 31 year assembled (last 1 digit) t n rank code in-house code (t: pb-free) week assembled assembly lot type number company initial ordering information part number order number solder plating specificatio n packing st yle safety standard approval application part number * 1 ps9551al4 ps9551al4-ax pb-fr ee maga zin e case 5 0 p cs standard products ps9551al4 ps9551al4-e3 ps9551al4-e3-ax (ni/pd/au) embossed tape 1 000 pcs/reel (ul, csa, semko approved) PS9551AL4-V PS9551AL4-V-ax maga zin e case 5 0 p cs ul,csa,semko, PS9551AL4-V-e3 PS9551AL4-V-e3-ax embossed tape 1 000 pcs/reel din en 60747-5-5 (vde 0884 -5) *1 for t he appl ic at ion of the safety stand ard , followi ng part numbe r shou ld be used. a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 4 of 18 mar 20, 2014 absolute maximum ratings (t a = 25 c, unless otherwise specified) parameter s ymbol ratings unit operating ambient temperature t a ?40 to +105 c storage temperature t stg ?55 to +125 c supply voltage v dd1 , v dd2 0 to 5.5 v input voltage v in + , v in ? ?2 to v dd1 +0.5 v 2 seconds transient input voltage v in + , v in ? ?6 to v dd1 +0.5 v output voltage v out + , v out ? ?0.5 to v dd2 +0. 5 v isolation voltage *1 bv 5 000 vr.m.s. *1 ac voltage for 1 minute at t a = 25 c, rh = 60% between input and output. pins 1-4 shorted together, 5-8 shorted together. recommended operating conditions parameter s ymbol min. ty p. max. unit operating ambient temperature t a ? 40 105 c supply voltage v dd1 , v dd2 4.5 5 5.5 v input voltage (accurate and linear) *1 v in + , v in ? ?200 200 mv *1 using v in ? = 0 v (to be connected to gnd1) is recommended. avoid using v in ? of 2.5 v or more, because the internal test mode is activated when the voltage v in ? reaches more than 2.5 v. a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 5 of 18 mar 20, 2014 electrical characteristics (typ.: t a = 25 c, v in + = v in ? = 0 v, v dd1 = v dd2 = 5 v, min., max.: refer to recommended o perating conditions, unless otherwise specified) parameter symbol conditions min. typ. max. unit input supply current i dd1 v in + = 350 mv 12 15 ma output supply current i dd2 v in + = ?350 mv 6 15 ma input bias current i in ? 5 ? 0.6 5 a low level saturated output voltage v ol i out = 1.6 ma 0.1 0.6 v high level saturated output voltage v oh i out = ?100 a 3.9 4.9 v output short-circuit current |i osc | v out = v dd2 or v out = gnd2 17 40 ma equivalent input resistance r in 450 k output clock frequency f clk 8.2 10 13.2 mhz isolation resistance r i-o v i-o = 1 kv dc , t a = 25 c 1 0 11 isolation capacitance c i-o f = 1 mhz 0.7 pf data hold time *1 t hddat 4 10 16 ns common mode transient immunity *2 cmr v cm = 1 kv, t a = 25 c 15 kv/ s *1 the data hold time (t hddat ) is that the data (mdat) will stay stable following the rising edge of the clock (mclk). t hddat is shown in the below timing chart. fig. timing chart *2 common mode transient immunity (cmr) is specified by t he rate of rise / fall of a pulse applied between gnd1 on the input side and gnd2 on the output side (p ins 4 and 5) by using the circuit shown in fig. 6 cmr test circuit . cmr is defined at the point t hat clock signals are corrupted. mclk m dat t hddat a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 6 of 18 mar 20, 2014 electrical characteristics (tested with sinc 3 filter, 256 decimation ratio.) (typ.: t a = 25 c, v in + = v in ? = 0 v, v dd1 = v dd2 = 5 v, min., max.: refer to recommended o perating conditions, unless otherwise specified) parameter s ymbol conditions min. t yp. max. unit integral non-linearity *3 inl ?200 mv v in + 200 mv 3 30 lsb 0.01 0.14 % differential non-linearity *4 dnl ? 200 mv v in + 200 mv 1 lsb input offset voltage *5 v os ? 3 0 3 mv input offset voltage drift vs. temperature ? dv os /dt a ? 2 10 v/ c input offset voltage drift vs. supply voltage ? dv os /dv dd1 ? 0.1 mv/v internal reference voltage *6 v ref 320 mv absolute internal reference voltage tolerance g e t a = 25 c ? 1 1 % t a = ?40 to 105 c ? 4 4 % internal reference voltage drift vs. temperature ? dv ref /dt a ? 60 ppm/ c internal reference voltage drift vs. supply voltage ? dv ref /dv dd1 ? 0.2 mv/v input dc common-mode rejection ratio *7 cmrr in 70 db *3 integral non-linearity (inl) is the maximum deviation between the ideal conversion line (best-fit line) and measured points. the best-fit line is obtained by using the leas t-squares method from the differential input voltage (v in+ ? v in ? : v in+ = ? 200 mv to 200 mv, v in ? = 0 v) and the output data that is measured under the circuit shown in fig. 7 inl test circuit . inl is defined as the ratio (%) obtained by dividing [half of the peak to peak value of the deviation] by [full-scale differential input voltage 400 mv]. for example, if the differential input voltage is v in+ = ? 200 mv to 200 mv, and the peak to peak value of the deviation is 1.12 mv, integral non-li nearity is obtained as follows: inl = 1.12 mv/(2 400 mv) = 0.14% and input full-scale 640 mv ( ? 320 to 320 mv) of ps9551a is assigned 15 bits (2 15 = 32768). therefore, least significant bit (lsb) is 19.5 v. by lsb indication, above-mentioned inl is 1.12 mv/(2 0.0195 mv) = 29 lsbs. *4 differential non-linearity (dnl) is the difference bet ween a measured code width and ideal 1 lsb in the adc transfer curve. *5 input offset voltage (v os ) is a measured value after sinc 3 digital filter when the input voltage is 0 v (v in+ = v in- = 0 v). *6 absolute internal reference voltage tolerance (g e ) is the gap rate between the ideal conversion line slope (slope = 1) and a best-fit line slope that provided by the least-sq uares method from a real conversion level output for the differential input voltage (v in+ ? v in- : v in+ = ? 200 mv to 200 mv, v in- = 0 v). *7 input dc common-mode rejection ratio (cmrr in ) is the ratio of the differential signal (v in+ = ? 200 mv to 200 mv, v in ? = 0 v) to the common-mode signal (v in+ = v in ? = ? 200 mv to 200 mv: both input pins are connected). cmrr in is defined as follows, cmrr in (db) = 20log (vdo/vco) vdo : output voltage when the differential signal voltage input vco : output voltage when the common-mode signal voltage input a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 7 of 18 mar 20, 2014 electrical characteristics (tested with sinc 3 filter, 256 decimation ratio.) (typ.: t a = 25 c, v in + = v in ? = 0 v, v dd1 = v dd2 = 5 v, min., max.: refer to recommended o perating conditions, unless otherwise specified) parameter s ymbol conditions min. typ. max. unit signal to noise ratio *8 snr v in + = 35 hz, 400 mvpk-pk (141 mvr.m.s.) sine wave 62 74 db total harmonic distortion *9 thd ? 80 db signal to noise and distortion ratio *10 sndr 72 db effective number of bit *11 enob 10 12 bits *8 signal to noise ratio (snr) is the ratio of the ac si gnal power to the noise power that excludes harmonic signals and dc. snr is defined as follows, snr (db) = 10log(p s /p n ) p s : signal power (fundamental) p n : noise power (excluding harmonic signals and dc) *9 total harmonic distortion (thd) is the ratio of the ac signal power (fundamental) to the sum of harmonic signals that are occurred by the non-linearity. thd is defined as follows, thd (db) = 10log((p h2 + p h3 + ... + p h5 )/p s ) p s : signal power (fundamental) p h2 , p h3 ... p h5 : second through fifth harmonics power *10 signal to noise and distortion ratio (sndr) is the rati o of the ac signal power (fundamental) to the noise power plus distortion power. sndr is defined as follows, sndr (db) = 10log(p s /(p n + p h2 + p h3 + ... + p h5 )) p s : signal power (fundamental) p n : noise power (excluding harmonic signals and dc) p h2 , p h3 ... p h5 : second through fifth harmonics power *11 effective number of bit (enob) is the effectiv e resolution of adc that is considered the noise. enob is defined as follows, enob (bits) = (snr ? 1.76)/6.02 a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 8 of 18 mar 20, 2014 test circuit i dd1 0.01uf i dd2 0.1uf 0.1uf v oh 0.01uf 0.1uf 0.1uf v ol 0.01uf 0.1uf 0.1uf 0.01uf 0.1uf 0.1uf 0.01uf 0.1uf 0.1uf i in v dd1 v in+ v dd2 v dd2 v in+ v dd1 v dd1 v in+ v dd2 v dd2 v dd2 v dd1 v dd1 fig.1 i dd1 test circuit fig.2 i dd2 test circuit fig.3 i in test circuit fig.4 vout test circuit v ol v oh v in+ y= 400mv v in+ = 400mv a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 9 of 18 mar 20, 2014 0.01uf 0.1uf 0.01uf 0.1uf 0.1uf i osc 0.1uf i osc 0.1uf 0.1uf 0.1uf v dd 2 clk ? vcm 0.1uf 0.1uf v in 39? 0.01uf v dd 2 v dd 1 sinc filter 3 data v dd1 v in+ v dd2 v dd1 v dd2 78l05 9v v in+ fig.5 i osc test circuit fig.6 cmr test circuit fig.7 vos, inl, dnl, g e , snr, thd, sndr, enob test circuit a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 10 of 18 mar 20, 2014 typical chara cteristics (t a = 25 c, v in + = v in ? = 0 v, v dd1 = v dd2 = 5 v, tested with sinc 3 filter, 256 decimation ratio, unless otherwise specified) input supply current vs. input voltage input supply current i dd1 (ma) input voltage v in (mv) input supply current vs. ambient temperature ambient temperature t a (c) output supply current vs. input voltage y input current i in (a) input voltage v in (mv) output supply current i dd2 (ma) output supply current i dd2 (ma) input voltage v in (mv) ambient temperature t a (c) - 25 0 25 50 10075 - 50 12 5 15 9 10 11 12 13 14 -400 -200 0 200 400 - 50 - 25 0 25 50 75 100 12 5 - 300 - 200 -100 0 200100 - 400 300 400 1 -5 -4 -3 -2 -1 0 4.5v 5.0v input current vs. input voltage input voltage v in (v) input current i in (mae -400 -200 0 200 400 15 9 10 11 12 13 14 9 8 7 6 5 4 9 8 7 6 5 4 2 0 -2 -4 -6 -8 -10 -1 - 0.5 0 0.5 1 1.5 2 v in = -350mv v in = 350mv -40c 25c t a = 105c t a = 105c 25c -40c v dd1 = v dd2 = 5.5v v dd1 = v dd2 = 5.5v 5.0v 4.5v input current vs. input voltage input supply current i dd1 (ma) output supply current vs. ambient temperature rema rk the graphs indicate nominal characteristics. a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 11 of 18 mar 20, 2014 input offset voltage vs. ambient temperature input offset voltage v os (mv) absolute internal reference voltage toletance vs. ambient temperature integral non-linearity(lsb) vs. ambient temperature absolute internal reference voltage tolerance g e (%e input offset voltage change ?) - 25 0 25 50 10075 - 50 125 1 -2 -1.5 -1 -0.5 0 0.5 - 25 0 25 50 10075 - 50 12 5 750 -750 -500 -250 0 250 500 - 25 0 25 50 10075 - 50 125 3 -3 -2 -1 0 1 2 integral non-linearity inl (lsb) - 25 0 25 50 10075 - 50 125 7 1 2 3 4 5 6 integral non-linearity(%) vs. ambient temperature integral non-linearity inl (%) - 25 0 25 50 10075 - 50 12 5 0.06 0.00 0.01 0.02 0.03 0.04 0.05 output clock frequency vs. ambient temperature output clock frequency f clk (mhz) - 25 0 25 50 100 12 5 75 - 50 11.3 10.3 10.7 10.6 10.5 10.4 10.8 10.9 11.0 11.1 11.2 input offset voltage change vs. ambient temperature v dd1 = v dd2 = 4.5v 5.0v 5.5v v dd1 = v dd2 = 5.5v 5.0v 4.5v v dd1 = v dd2 = 5.0v 5.5v 4.5v v dd1 = v dd2 = 4.5v 5.5v 5.0v v dd1 = v dd2 = 4.5v 5.0v 5.5v v dd1 = v dd2 = 5.0v 5.5v 4.5v normalized to 0 v at t a =25? ?200mv ? v in ? 20 0mv ?200mv ? v in ? 20 0mv ambient temperature t a (c) ambient temperature t a (c) ambient temperature t a (c) ambient temperature t a (c) ambient temperature t a (c) ambient temperature t a (c) ? rema rk the graphs indicate nominal characteristics. a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 12 of 18 mar 20, 2014 signal to noise and distortion ratio vs. ambient temperature signal to noise and distortion ratio sndr (db) - 25 0 25 50 10075 - 50 12 5 78 66 68 70 72 74 76 4.5v 5.0v signal to noise ratio snr (dbe - 25 0 25 50 10075 - 50 125 78 66 68 70 72 74 76 5.5v 4.5v - 25 0 25 50 10075 - 50 125 13.0 10.0 10.5 11.0 11.5 12.0 12.5 effective number of bit vs. ambient temperature effective number of bit enob (bits) v dd1 = v dd2 = 5.5v v dd1 = v dd2 = 5.0v v dd1 = v dd2 = 5.0v 5.5v 4.5v signal to noise ratio vs. ambient temperature ambient temperature t a (c) ambient temperature t a (c) ambient temperature t a (c) v in = 3 5 h z,4 0 0mv pk-pk (141mvr.m.s.) sin e w a ve v in = 3 5 h z,4 0 0mv pk-pk (141mvr.m.s.) sin e w a ve v in = 3 5 h z,4 0 0mv pk-pk (141mvr.m.s.) sin e w a ve remark the graphs indicate nominal characteristics. a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 13 of 18 mar 20, 2014 taping specifications (unit: mm) 3302.0 1001.0 2.00.5 13.00.2 r 1.0 21.00.8 2.00.5 21.51.0 17.51.0 ps9551al4-e3 1.550.1 2.00.1 4.00.1 1.750.1 4.65 max. 9.950.1 12.00.1 1.5 +0.1 ?0 7.50.1 10.550.1 16.00.3 4.20.1 0.30.05 outline and dimensions (tape) outline and dimensions (reel) tape direction packing: 1 000 pcs/reel a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 14 of 18 mar 20, 2014 recommended mount pad dimensions (unit: mm) d c b a part number ps9551al4 lead bending a lead bending type (gull-wing) for surface mount 9.0 b 2.54 c 1.7 d 2.0 a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 15 of 18 mar 20, 2014 notes on handling 1 . reco mmended soldering conditions (1 ) infrared reflow soldering ? peak reflow temp erature 260 c or below (package surface temperature) ? time of peak reflow temperature 10 seconds or less ? time of temperature higher than 220 c 60 seconds or less ? time to preheat temperature from 120 to 180 c 120 30 s ? num ber of reflows three ? flux rosin flux containing small amount of chlorine (the flux with a maximum chlorine content of 0.2 wt% is recommended.) 12030 s (preheating) 220c 180c package surface temperature t (c) time (s) recommended temperature profile of infrared reflow (heating) to 10 s to 60 s 260c max. 120c (2 ) wave soldering ? tem perature 260 c or below (molten solder temperature) ? time 10 seconds or less ? preh eating conditions 120 c or below (package surface temp erature) ? number of time s one (allowed to be dipped in solder including plastic mold portion.) ? flux rosin flux containing small amount of chlorine (the flux with a maximum chlorine content of 0.2 wt% is recommended.) (3) so ldering by soldering iron ? peak temperature (lead part temperature) 350 c or below ? time (each pins) 3 seconds or less ? flux rosin flux containing small amount of chlorine (the flux with a maximum chlorine content of 0.2 wt% is recommended.) (a) soldering of leads should be made at the point 1.5 to 2.0 mm from the root of the lead a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 16 of 18 mar 20, 2014 (4 ) ca utions ? fl uxes avoid removing the residual flux with freon-based and chlorine-based cleaning solvent. 2. cau tions regarding no ise b e aware that when voltage is applied suddenly between the photocoupler?s input and output at startup, the output transistor may enter the on state, even if the voltage is within the absolute maximum ratings. usage cautions 1. this product is weak for static electricity by designed w ith high-speed integrated circuit so protect against static electricity when handling. 2. b oard designing (1) below fi gure shows a typical application circu it where the ps9551a is used . a digital filter (sinc 3 filter) red uces high frequency quantization noise from the ps9551a and convers from one-bit data stream to 3-wi re serial data. f ig. ps9551a typical application circuit (2 ) by -pass capacitor of more than 0.1 f is used between v dd and gnd near device. also, ensure that the distance between the leads of the photocoupler and capacitor is no more than 10 mm. (3) keep the pattern connected the input (v in+ , v in ) and the output (mclk, mdat), respectively, as short as possible. mclk and mdat are digital signal, but when the lines between the photocoupler and a dig ital filter are long , the digital filter might not read the da ta. when using long lines, use a line driver between the photocoupler and the digital filter, and keep the pa ttern bet ween the output (mclk, mdat) and the line driver as short as possibl e. (4) do not connect any routing to the portion of the frame exposed between the pins on the package of the photocoupler. if connected, it will affect the photocoupler's internal voltage and the photocoupler will not operate normally . (5) because the maximum frequency of the signal input to the photocoupler must be lower than the allowable freq uency band, be sure to connect an anti-aliasing filter (an rc filter with r = 39 and c = 0.01 f, fo r exam ple). (6) when vdd is lower than 4.5 v that is the outside of recommended operating condition, the output (mclk, m dat) of this product is unstable, and this might pr oduce undesirable operation. be sure to check the operation of an ic that is connected to this product during power-up and power-down process. and we recommend to use a disable function (shutdown function) of the connected ic or a reset ic to avoid this undesirable operation. 3. avoid storage at a high temperature and high humidity . v in+ v in ? mclk mdat +5v 0.1uf 39? 0.01uf clk dat v dd gnd sclk sdat cs v dd2 gnd2 v dd1 gnd1 ps9551a +5v 0.1uf r shunt 3-wire seria l interface sinc 3 filter a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 17 of 18 mar 20, 2014 specification of vde marks license document parameter symbol spec. unit climatic test class (iec 60068-1/ din en 60068-1) 40/105/21 dielectric strength maximum operating isolation voltage test voltage (partial discharge test, procedure a for type test and random test) u pr = 1.6 u iorm , p d < 5 pc u iorm u pr 1 130 1 808 v peak v peak test voltage (partial discharge test, procedure b for all devices) u pr = 1.875 u iorm , p d < 5 pc u pr 2 119 v peak highest permissible overvoltage u tr 8 000 v peak degree of pollution (din en 60664-1 vde 0110 part 1) 2 comparative tracking index (iec 60112/di n en 60112 (vde 0303 part 11)) cti 175 material group (din en 60664 -1 vde 0110 part 1) iii a storage temperature range t stg ?55 to +125 c operating temperature range t a ?40 to +105 c isolation resistance, minimum value v io = 500 v dc at t a = 25c v io = 500 v dc at t a max. at least 100c ris min. ris min. 10 12 10 11 safety maximum ratings (ma ximum permissible in case of fault, see thermal derating curve) package temperature current (input current i f , psi = 0) power (output or total power dissipation) isolation resistance v io = 500 v dc at t a = tsi tsi isi psi ris min. 175 400 700 10 9 c ma mw a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
ps9551al4 chapter title r08ds0121ej0100 rev.1.00 page 18 of 18 mar 20, 2014 caution gaas products this product uses gallium arsenide (gaas). gaas vapor and powder are hazardous to human health if inhaled or ingested, so please observe the following points. ? follow related laws and ordinances when disposi ng of the product. if there are no applicable laws and/or ordinances, dispose of the product as recommended below. 1. commission a disposal compa ny able to (with a license to) collect, transport and di spose of materials that contain arsenic and other such industrial w aste materials. 2. exclude the pr oduct from general industrial waste and household garbage, and en sure that the product is controlled (as industrial w aste subjec t to special control) up until final disposal. ? do not burn, destroy, cut, crush, or chemically dissolve the product. ? do not lick the product or in an y way allow it to enter the mouth. a b usine ss par tn er o f ren esas ele ctro nics c or pora ti on.
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history ps9551al4 data sheet re v. date description page summary 1.00 mar 20, 2014 throughout preliminary data sheet -> data sheet throughout safety standards approved p.3 modification of marking example addition of ordering information p.4 modification of absolute maximum ratings modification of recommended operating condi tions p.5 to 7 modification of electrical characteristics p.8 to 9 addition of test circuit p.10 to 12 addition of typical characteristics p.14 addition of recommended mount pad dimensions p.16 modification of usage cautions p.17 addition of specification of vde marks license document
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including without limitation, the eu rohs directive. california eastern laboratories and renesas electronics assume no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of california eastern laboratories, who distributes, disposes of, or otherwise places the renesas electronics product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, california eastern laboratories and renesas electronics assume no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 1 1. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of california eastern laboratories. 12. please contact a california eastern laboratories sales offce if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. note 1: renesas electronics as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. note 2: renesas electronics product(s) means any product developed or manufactured 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