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42681fc ltc4268-1 1 high power pd with synchronous no-opto flyback controller the lt c ? 4268-1 is an integrated powered device ( pd) controller and switching regulator intended for ieee 802.3 af and high power poe applications up to 35 w. by including a precision dual current limit, the ltc4268-1 keeps inrush below ieee 802.3 af current limit levels to ensure interop- erability success while enabling high power applications with a 750ma operational current limit.the ltc4268-1 synchronous, current - mode, flyback controller generates multiple supply rails in a single conversion providing for the highest system efficiency while maintaining tight regulation across all outputs. the ltc4268-1 includes linear technology s patented no - opto feedback topology to provide full ieee 802.3 af isolation without the need of opto-isolator circuitry. the oversized power path and high performance flyback controller of the ltc4268-1 combine to make the ultimate solution for power hungry poe applications such as waps , ptz security cameras, rfid readers and ultra-efficient 802.3af applications running near the 12.95w limit. the ltc4268-1 is available in a space saving 32- pin dfn package. n robust 35w pd front end n ieee 802.3af compliant n rugged 750 ma power mosfet with precision dual level current limit n high performance synchronous flyback controller n ieee isolation obtained without an opto-isolator n adjustable frequency from 50khz to 250khz n tight multi-output regulation with load compensation n onboard 25k signature resistor n programmable classification current to 75ma n complete thermal and over-current protection n available in compact 32-pin 7mm 4mm dfn package n voip phones with advanced display options n dual-radio wireless access points n ptz security cameras n rfid readers n industrial controls n magnetic card readers n high power poe systems 35w high efficiency pd solution 169k r class 3.01k1% 28.7k1% 20 47 47k 100k bas21 56 ? ? ? ? 100pf 5f 470f4 3.3v C54v from data pair C54v from spare pair t1 0.02 47f smaj58a t1: pa1477nl t2: pa0184 df1501sdf1501s 0.1f 100k 20k 10k 15 330 47pf 0.033f 10nf 2.2nf t2 0.1f 42681 ta01a 1f bat54 t on 12k pgdly v neg sync r class v portn shdn sense C v cmp sense + r cmp endly osc ltc4268-1 gnd sfst sg si7336adp b0540w si4490dy fmmt618fmmt718 v cc i lim_en uvlo pwrgd pwrgd v portp t1 ? pgfb c cmp +C ~~ +C ~~ + + typical application description features applications l , lt , lt c , lt m and switchercad are registered trademarks and ltpoe ++ and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5841643. downloaded from: http:///
ltc4268-1 2 42681fc pin configuration absolute maximum ratings v portn voltage .......................................... 0.3 v to C90 v v neg voltage .................. v portn + 90v to v portn C0.3 v v cc to gnd voltage ( note 3) low impedance source ......................... C0.3 v to 18 v current fed .......................................... 30 ma into v cc r class , i lim _ en voltage .. v portn + 7v to v portn C 0.3 v shdn voltage ............... v portn + 90v to v portn C 0.3 v pwrgd voltage ( note 3) low impedance source .... v neg + 11 v to v neg C 0.3 v current fed .......................................................... 5 ma pwrgd voltage ............ v portn + 80v to v portn C 0.3 v pwrgd current ..................................................... 10 ma r class current .................................................... 100 ma sense C , sense + voltage ........................ C0.5 v to +0.5 v uvlo , sync voltage ................................... C0.3 v to v cc fb current .............................................................. 2 ma v cmp current ......................................................... 1 ma operating ambient temperature range ( notes 4, 5) ltc 4268 -1 c ............................................. 0 c to 70 c ltc 4268 -1 i .......................................... C40 c to 85 c junction temperature ( note 5) ............................. 150 c storage temperature range .................. C65 c to 150 c (notes 1, 2) 3231 30 29 28 27 26 25 24 23 22 21 20 19 18 17 33 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 v portp nc pwrgd pwrgd v neg v neg v neg ncpg pgdly r cmp c cmp sense+senseC uvlo v cmp shdn nc r class i lim_en v portn v portn v portn ncsg v cc t on endly sync sfst osc fb top view dkd32 package 32-lead (7mm 4mm) plastic dfn t jmax = 150c, ja = 49c/w, jc = 4.7c/w exposed pad (pin 33) must be soldered to heat sinking plane that is electrically connected to gnd lead free finish tape and reel part marking* package description temperature range ltc4268cdkd-1#pbfltc4268idkd-1#pbf ltc4268cdkd-1#trpbfltc4268idkd-1#trpbf 4268142681 32-lead (7mm 4mm) plastic dfn32-lead (7mm 4mm) plastic dfn 0c to 70cC40c to 85c lead based finish tape and reel part marking* package description temperature range ltc4268cdkd-1ltc4268idkd-1 ltc4268cdkd-1#trltc4268idkd-1#tr 4268142681 32-lead (7mm 4mm) plastic dfn32-lead (7mm 4mm) plastic dfn 0c to 70cC40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ order information downloaded from: http:///
42681fc ltc4268-1 3 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 14v, sg open, v cmp = 1.5v, v sense = 0v, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise specified. symbol parameter conditions min typ max units v port supply voltage ieee 802.3af system signature range classification range uvlo turn-on voltage uvlo turn-off voltage voltage with respect to v portp pin (notes 6, 7, 8, 9, 10) l l l l l C1.5 C12.5 C37.7 C29.8 C38.9 C30.6 C57 C10.1 C21 C40.2 C31.5 v v v v v v turnon v cc turn-on voltage voltage with respect to gnd l 14 15.3 16.6 v v turnoff v cc turn-off voltage voltage with respect to gnd l 8 9.7 11 v v hyst v cc hysteresis v turnon C v turnoff l 4 5.6 7.2 v v clamp v cc shunt regulator voltage i vcc = 15ma, v uvlo = 0v, voltage with respect to gnd l 19.5 20.2 v i vcc v cc supply current v cmp = open (note 11) l 4 6.4 10 ma i vcc_start v cc start-up current v cc = 10v l 180 400 a v fb feedback regulation voltage l 1.22 1.237 1.251 v i fb_bias feedback pin input bias current r cmp open 200 na g m feedback amplifier transconductance l 700 1000 1400 a/v i fb feedback amplifier source or sink current l 25 55 90 a v fbclamp feedback amplifier clamp voltage v fb = 0.9v v fb = 1.4v 2.56 0.84 v v %v ref reference voltage line regulation 12v v cc 18v l 0.005 0.02 %/v a v feedback amplifier voltage gain v cmp = 1.2v to 1.7v 1500 v/v i sfst soft-start charging current v sfst = 1.5v 16 20 25 a i sfst soft-start discharge current v sfst = 1.5v, v uvlo = 0v 0.8 1.3 ma v cmp_thld control pin threshold (vcmp) duty cycle = min 1 v v pg_high , v sg_high pg, sg, output high level l 6.6 7.4 8 v v pg_low , v sg_low pg, sg, output low level l 0.01 0.05 v v pg_shdn , v sg_shdn pg, sg, output shutdown strength v uvlo = 0v; i pg , i sg = 20ma l 1.4 2.3 v t pg_rise , t sg_rise pg, sg rise time c pg , c sg = 1nf 15 ns t pg_fall , t sg_fall pg, sg fall time c pg , c sg = 1nf 15 ns v sense_lim switch current threshold at maximum v cmp measured at v sense+ l 88 100 110 mv d v sense / d v cmp sense threshold vs v cmp 0.07 v/v v sense_oc sense pin overcurrent fault voltage v sense+ , v sfst < 1v l 205 230 mv v ih_shdn shutdown high level input voltage with respect to v portn high level = shutdown (note 12) l 3 57 v v il_shdn shutdown low level input voltage with respect to v portn l 0.45 v downloaded from: http:///
ltc4268-1 4 42681fc symbol parameter conditions min typ max units r input_shdn shutdown input resistance with respect to v portn l 100 k w v ih_ilim i lim_en high level input voltage with respect to v portn (note 13) high level enables current limit l 4 v v il_ilim i lim_en low level input voltage with respect to v portn (note 13) l 1 v i vportn v portn supply current v portn = C54v l 3 ma i in_class ic supply current during classification v portn = C17.5v, v neg tied to v portp (note 14) l 0.55 0.62 0.70 ma d i class current accuracy during classification 10ma < i class < 75ma C12.5v v portn C21v (notes 15, 16) l 3.5 % r signature signature resistance C1.5v v portn C10.1v, shdn tied to v portn , ieee 802.3af tw o -point measurement (notes 8, 9) l 23.25 26 k w r invalid invalid signature resistance C1.5v v portn C10.1v, shdn tied to v portp , ieee 802.3af tw o -point measurement (notes 8, 9) 10 11.8 k w v pwrgd _out active low power good output voltage i = 1ma, v portn = C54v, pwrgd referenced to v portn l 0.5 v i pwrgd _leak active low power good output leakage v port = 0v, v pwrgd = 57v l 1 a v pwrgd_out active high power good output voltage i = 0.5ma, v portn = C52v, v neg = C4v pwrgd referenced to v neg (note 17) l 0.35 v v pwrgd_vclamp active high power good voltage limiting clamp i = 2ma, v neg = 0v, pwrgd referenced to v neg (note 3) l 12 14 16.5 v i pwrgd_leak active high power good output leakage v pwrgd = 11v with respect to v neg , v neg = v portn = C54v l 1 a r on on-resistance i = 700ma, v portn = C48v, measured from v portn to v neg (note 16) l 0.5 0.6 0.8 w w i out_leak v out leakage v portn = C57v, v portp = shdn = v neg = 0v (note 15) l 1 a i lim_hi input current limit, high level v portn = C54v, v neg = C53v i lim_en floating (notes 18, 19) l 700 750 800 ma i lim_lo input current limit, low level v portn = C54v, v neg = C53v (notes 18, 19) l 250 300 350 ma i lim_disa safeguard current limit when i lim is disabled v portn = C54v, v neg = C52.5v i lim_en tied to v portn (notes 18, 19, 20) 1.2 1.45 1.65 a f osc oscillator frequency c osc = 100pf l 84 100 110 khz c osc oscillator capacitor value (note 21) 33 200 pf t on(min) minimum switch on time 200 ns t endly flyback enable delay time 265 ns t pgdly pg turn-on delay time 200 ns dc on(max) maximum switch duty cycle l 85 88 % v sync sync pin threshold l 1.53 2.1 v r sync sync pin input resistance 40 k w electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 14v, sg open, v cmp = 1.5v, v sense = 0v, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise specified. downloaded from: http:///
42681fc ltc4268-1 5 symbol parameter conditions min typ max units i lcomp feedback pin load compensation current v rcmp with v sense + = 0v 20 a v lcomp load comp to v sense offset voltage v sense+ = 20mv, v fb = 1.23v 1 mv v uvlo uvlo pin threshold l 1.215 1.237 1.265 v i uvlol i uvloh uvlo pin bias current v uvlo = 1.2v v uvlo = 1.3v C0.25 C4.50 0 C3.4 0.25 C2.5 a a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to v portp pin unless otherwise noted. note 3: active high pwrgd internal clamp circuit self-regulates to 14v with respect to v neg . v cc has internal 20v clamp with respect to gnd. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 5: t j is calculated from the ambient temperature t a and power dissipation p dis according to the formula: t j = t a + (p dis ? 49 c/w) note 6: the ltc4268-1 operates with a negative supply voltage in the range of C1.5v to C57v. to avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. terms such as maximum negative voltage refer to the largest negative voltage and a rising negative voltage refers to a voltage that is becoming more negative. note 7: in ieee 802.3af systems, the maximum voltage at the pd jack is defined to be C57v.note 8: the ltc4268-1 is designed to work with two polarity protection diodes in series with the input. parameter ranges specified in the electrical characteristics are with respect to ltc4268-1 pins and are designed to meet ieee 802.3af specifications when the drop from the two diodes is included. see applications information. note 9: signature resistance is measured via the two-point d v/ d i method as defined by ieee 802.3af. the ltc4268-1 signature resistance is offset from 25k to account for diode resistance. with two series diodes, the total pd resistance will be between 23.75k and 26.25k and meet ieee 802.3af specifications. the minimum probe voltages measured at the ltc4268-1 pins are C1.5v and C2.5v. the maximum probe voltages are C9.1v and C10.1v. note 10: the ltc4268-1 includes hysteresis in the uvlo voltages to preclude any start-up oscillation. per ieee 802.3af requirements, the ltc4268-1 will power up from a voltage source with 20 series resistance on the first trial. note 11: supply current does not include gate charge current to the mosfets. see application information. note 12: to disable the 25k signature, tie shdn to v portp (0.1v) or hold shdn high with respect to v in . see applications information. note13: i lim_en pin is pulled high internally and for normal operation should be left floating. to disable current limit, tie i lim_en to v in . see applications information.note 14: i in_class does not include classification current programmed at pin 3. total supply current in classification mode will be i in_class + i class (see note 15).note 15: i class is the measured current flowing through r class . ?i class accuracy is with respect to the ideal current defined as i class = 1.237/ r class . t classrdy is the time for i class to settle to within 3.5% of ideal. the current accuracy specification does not include variations in r class resistance. the total classification current for a pd also includes the ic quiescent current (i in_class ). see applications information. note 16: this parameter is assured by design and wafer level testing. note 17: active high power good is referenced to v neg and is valid for v portp C v neg 4v. note 18: the ltc4268-1 includes a dual current limit. at turn on, before c1 is charged, the ltc4268-1 current level is set to i limit_low . after c1 is charged and with i lim_en floating, the ltc4268-1 switches to i limit_high . with i lim_en pin tied low, the ltc4268-1 switches to i limit_disa . the ltc4268-1 stays in i limit_high or i limit_disa until the input voltage drops below the uvlo turn-off threshold or a thermal overload occurs.note 19: the ltc4268-1 features thermal overload protection. in the event of an over temperature condition, the ltc4268-1 will turn off the power mosfet, disable the classification load current, and present an invalid power good signal. once the ltc4268-1 cools below the over temperature limit, the ltc4268-1 current limit switches to i limit_low and normal operation resumes.note 20: i limit_disa is a safeguard current limit that is activated when the normal input current limit (i limit_high ) is defeated using the i lim_en pin. currents at or near i limit_disa will cause significant package heating and may require a reduced maximum ambient operating temperature in order to avoid tripping the thermal overload protection. note 21: component value range guaranteed by design. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 14v, sg open, v cmp = 1.5v, v sense = 0v, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise specified. downloaded from: http:///
ltc4268-1 6 42681fc input voltage (v) 0 0 input current (ma) 0.1 0.2 0.3 0.4 0.5 C2 C4 C6 C8 42681 g01 C10 t a = 25c input voltage (v) 0 0 input current (ma) 20 40 60 80 100 C10 C20 C30 *optional class 5 current C40 42681 g02 C50 C60 t a = 25c class 5* class 4 class 3 class 2 class 1 class 0 input voltage (v) C12 9.0 input current (ma) 9.5 10.5 11.0 11.5 C14 C16 42681 g03 10.0 C18 C20 C22 12.0 85c C40c class 1 operation input voltage (v) C1 22 v1:v2: signature resistance (k) 23 25 26 27 C3 C5 42681 g04 24 C7 C9 C6 C10 C2 C4 C8 28 resistance = diodes: df1501s t a = 25c = ? v ? i v2 C v1 i 2 C i 1 ieee upper limit ieee lower limit ltc4268-1 + 2 diodes ltc4268-1 only input voltage 10v/div class current 20ma/div time (10s/div) 42681 g05 t a = 25c junction temperature (c) C50 0 resistance () 0.2 0.4 0.6 0.8 1.0 C25 0 25 50 42681 g06 75 100 input current (ma) 0 v pwrgd_out C v portn (v) 2 3 8 42681 g07 10 2 4 6 10 4 t a = 25c input current (ma) 0 0 pwrgd C v neg (v) 0.4 1.0 0.5 1 42681 g08 0.2 0.8 0.6 1.5 2 t a = 25c gnd C v neg = 4v input voltage (v) C40 200 current limit (ma) 400 600 800 C40cC40c 85c85c C45 C50 42681 g09 C55 C60 high current mode low current mode typical performance characteristics input current vs input voltage 25k detection range input current vs input voltage input current vs input voltage signature resistance vs input voltage class operation vs time on resistance vs temperature active low pwrgd : output low voltage vs current active high pwrgd: output low voltage vs current current limit vs input voltage downloaded from: http:///
42681fc ltc4268-1 7 temperature (c) C50 v cc (v) 15 25 42681 g10 1210 C25 0 50 98 1614 13 11 75 100 125 v cc(on) v cc(off) temperature (c) C50 i vcc (a) 200 250 300 25 75 42681 g11 150 100 C25 0 50 100 125 50 0 temperature (c) C50 8 9 25 75 42681 g12 76 C25 0 50 100 125 5 43 10 i vcc (ma) dynamic current c pg = 1nf, c sg = 1nf, f osc = 100khz static part current v cc = 14v temperature (c) C50 90 sense voltage (mv) 92 96 98 100 110104 0 50 75 42681 g13 94 106 108102 C25 25 100 125 fb = 1.1vsense = v sense + with v sense C = 0v temperature (c) C50 sense voltage (mv) 215 25 42681 g14 200190 C25 0 50 185180 220210 205 195 75 100 125 sense = v sense + with v sense C = 0v temperature (c) C50 90 f osc (khz) 92 96 98 100 110104 0 50 75 42681 g15 94 106 108102 C25 25 100 125 c osc = 100pf temperature (c) C50 1.230 v fb (v) 1.231 1.233 1.234 1.235 1.2401.237 0 50 75 42681 g16 1.232 1.238 1.2391.236 C25 25 100 125 temperature (c) C50 feedback pin input bias (na) 200 250 300 25 75 42681 g17 150 100 C25 0 50 100 125 50 0 r cmp open temperature (c) C50 v fb reset (v) 1.03 25 42681 g18 1.000.98 C25 0 50 0.970.96 1.041.02 1.01 0.99 75 100 125 typical performance characteristics v cc(on) and v cc(off) vs temperature v cc start-up current vs temperature v cc current vs temperature sense voltage vs temperature sense fault voltage vs temperature oscillator frequency vs temperature v fb vs temperature feedback pin input bias vs temperature v fb reset vs temperature downloaded from: http:///
ltc4268-1 8 42681fc v fb (v) 0.9 C70 i vcmp (a) C50 C30 C10 7030 1 1.1 1.4 50 10 1.2 1.3 1.5 42681 g19 125c 25c C40c temperature (c) C50 i vcmp (a) 60 65 70 25 75 42681 g20 55 50 C25 0 50 100 125 45 40 source current v fb = 1.1v sink current v fb = 1.4v temperature (c) C50 900 g m (mho) 950 1000 1050 1100 C25 0 25 50 42681 g21 75 100 125 temperature (c) C50 a v (v/v) 1550 25 42681 g22 14001300 C25 0 50 12501200 1150 1100 1600 1650 17001500 1450 1350 75 100 125 temperature (c) C50 uvlo (v) 1.240 1.245 1.250 25 75 42681 g23 1.235 1.230 C25 0 50 100 125 1.225 1.220 temperature (c) C50 3.4 3.5 3.7 25 75 42681 g24 3.33.2 C25 0 50 100 125 3.1 3.0 3.6 i uvlo (a) temperature (c) C50 sfst charge current (a) 23 25 42681 g25 2018 C25 0 50 1716 15 2221 19 75 100 125 capacitance (nf) 0 time (ns) 8070 60 50 40 30 20 10 0 8 42681 g26 2 4 6 10 7 1 3 5 9 t a = 25c fall time rise time typical performance characteristics feedback amplifier output current vs v fb feedback amplifier source and sink current vs temperature feedback amplifier g m vs temperature feedback amplifier voltage gain vs temperature uvlo vs temperature i uvlo hysteresis vs temperature soft-start charge current vs temperature pg, sg rise and fall times vs load capacitance downloaded from: http:///
42681fc ltc4268-1 9 temperature (c) C50 C25 19.0 v cc (v) 20.0 21.5 0 50 75 42681 g27 19.5 21.0 20.5 25 100 125 i cc = 10ma temperature (c) C50 t on(min) (ns) 330 25 42681 g28 300280 C25 0 50 270260 340320 310 290 75 100 125 r ton(min) = 158k temperature (c) C50 0 t pgdly (ns) 50 150 200 250 0 50 75 42681 g29 100 C25 25 100 125 300 r pgdly = 16.9k r pgdly = 27.4k temperature (c) C50 t endly (ns) 285 305 325 25 75 42681 g30 265 245 C25 0 50 100 125 225 205 r endly = 90k v cc clamp voltage vs temperature typical performance characteristics minimum pg on time vs temperature pg delay time vs temperature enable delay time vs temperature downloaded from: http:///
ltc4268-1 10 42681fc pin functions shdn ( pin 1): shutdown input. used to command the ltc4268-1 to present an invalid signature and remain inactive. connecting shdn to v portp lowers the signature resistance to an invalid value and disables the ltc4268-1 pd interface operations. if unused, tie shdn to v portn . nc (pin 2): no internal connection. r class ( pin 3): class select input. used to set the current the ltc4268-1 maintains during classification. connect a resistor between r class and v portn . (see table 2.) i lim_en ( pin 4): input current limit enable. used for controlling the ltc4268-1 current limit behavior during powered operation. for normal operation, float i lim_en to enable i limit_high current. tie i lim_en to v portn to disable input current limit. note that the inrush current limit will always be active. see applications information.v portn ( pins 5, 6, 7): power input. tie to the pd input through the diode bridge. pins 5, 6 and 7 must be electri- cally tied together.nc (pin 8): no internal connection. sg ( pin 9): secondary gate driver output. this pin pro- vides an output signal for a secondary-side synchronous switch. large dynamic currents may flow during voltage transitions. see the applications information for details. v cc ( pin 10): converter voltage supply. bypass this pin to gnd with 4.7 f or greater. this pin has a 20 v clamp to ground. v cc has an undervoltage lockout function that turns on when v cc is approximately 15.3 v and off at 9.7 v. in a conventional trickle - charge bootstrapped configura - tion, the v cc supply current increases significantly during turn-on causing a benign relaxation oscillation action on the v cc pin if the part does not start normally. t on ( pin 11): primary switch minimum on time control. a programming resistor ( r ton ) to gnd sets the minimum time for each cycle. see applications information for details . endly ( pin 12): enable delay time control. the enable delay time is set by a programming resistor ( r endly ) to gnd and disables the feedback amplifier for a fixed time after the turn-off of the primary-side mosfet. this allows the leakage inductance voltage spike to be ignored for flyback voltage sensing. see applications information for details. sync ( pin 13): external sync input. this pin is used to synchronize the internal oscillator with an external clock. the positive edge of the clock causes the oscillator to dis- charge causing pg to go low ( off) and sg high ( on). the sync threshold is typically 1.5 v. tie to ground if unused. see applications information for details.sfst ( pin 14): soft-start. this pin, in conjunction with a capacitor ( c sfst ) to gnd, controls the ramp-up of peak primary current through the sense resistor. it is also used to control converter inrush at start-up. the sfst clamps the v cmp voltage and thus limits peak current until soft- start is complete. the ramp time is approximately 70 ms per f of capacitance. leave sfst open if not using the soft-start function.osc ( pin 15): oscillator. this pin in conjunction with an external capacitor ( c osc ) to gnd defines the controller oscillator frequency. the frequency is approximately 100khz ? 100/ c osc (pf). fb ( pin 16): feedback amplifier input. feedback is usually sensed via a third winding and enabled during the flyback period. this pin also sinks additional current to compensate for load current variation as set by the r cmp pin. keep the thevenin equivalent resistance of the feedback divider at roughly 3k.v cmp ( pin 17): frequency compensation control. v cmp is used for frequency compensation of the switcher control loop. it is the output of the feedback amplifier and the input to the current comparator. switcher frequency compensa- tion components are normally placed on this pin to gnd. the voltage on this pin is proportional to the peak primary switch current. the feedback amplifier output is enabled during the synchronous switch on time.uvlo ( pin 18): undervoltage lockout. a resistive divider from v in to this pin sets an undervoltage lockout based upon v in level ( not v cc ). when the uvlo pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from v cc . the v cc undervolt- age lockout supersedes this function so v cc must be great enough to start the part. the bias current on this pin has hysteresis such that the bias current is sourced when uvlo threshold is exceeded. this introduces a hysteresis at the pin equivalent to the bias current change times the imped- downloaded from: http:///
42681fc ltc4268-1 11 pin functions ance of the upper divider resistor. the user can control the amount of hysteresis by adjusting the impedance of the divider. tie the uvlo pin to v cc if you are not using this function. see the applications information for details. this pin is used for the uvlo function of the switching regulator. the pd interface section has an uvlo defined by the ieee 802.3af specification. sense?, sense + ( pins 19, 20): current sense inputs. these pins are used to measure primary side switch cur- rent through an external sense resistor. peak primary side current is used in the converter control loop. make kelvin connections to the sense resistor r sense to reduce noise problems. senseC connects to the gnd side. at maximum current ( v cmp at its maximum voltage) sense pins have 100mv threshold. the signal is blanked ( ignored) during the minimum turn-on time.c cmp ( pin 21): load compensation capacitive control. connect a capacitor from c cmp to gnd in order to reduce the effects of parasitic resistances in the feedback sensing path. a 0.1 f ceramic capacitor suffices for most applica- tions. short this pin to gnd in less demanding applications . r cmp ( pin 22): load compensation resistive control. connect a resistor from r cmp to gnd in order to com- pensate for parasitic resistances in the feedback sensing path. in less demanding applications, this resistor is not needed and this pin can be left open. see applications information for details. pgdly ( pin 23): primary gate delay control. connect an external programming resistor ( r pgdly ) to set delay from synchronous gate turn-off to primary gate turn-on. see applications information for details.pg ( pin 24): primary gate drive. pg is the gate drive pin for the primary side mosfet switch. large dynamic cur- rents flow during voltage transitions. see the applications information for details. nc (pin 25): no internal connection. v neg ( pins 26, 27, 28): system negative rail. tie to the gnd pin to supply power to the flyback controller through the internal power mosfet. v neg is high impedance until the input voltage rises above the uvlo turn-on threshold. the output is then connected to v portn through a current- limited internal mosfet switch. pins 26, 27 and 28 must be electrically tied together. pwrgd ( pin 29): active high power good output , open-collector. signals to the flyback controller that the ltc4268-1 mosfet is on and that the flyback controller can start operation. high impedance indicates power is good. pwrgd is referenced to v neg and is low imped- ance during inrush and in the event of a thermal overload. pwrgd is clamped to 14v above v neg . pwrgd (pin 30): active low power good output, open- drain. signals to the dc/dc converter that the ltc4268-1 mosfet is on and that the converter can start operation. low impedance indicates power is good. pwrgd is ref- erenced to v portn and is high impedance during detec- tion, classification and in the event of a thermal overload. pwrgd has no internal clamps. nc (pin 31): no internal connection. v portp ( pin 32): positive power input. tie to the input port power return through the input diode bridge.gnd ( pin 33): ground. this is the negative rail connec- tion for both signal ground and gate driver grounds. this pin should be connected to v neg . careful attention must be paid to layout. see the applications information for details. downloaded from: http:///
ltc4268-1 12 42681fc block diagram 19 sense C 20 sense + c cmp v cc 3v to fb pgate sgate currentsense amp r cmpf 50k load compensation C + C + C + C + C + C + C + v cc 15.3v v cc uvlo 10 uvlo i uvlo 18 osc 15 t on 11 pgdly 23 endly 12 sync 13 1.237v reference (v fb ) internal regulator uvlo 3v collapse detect error amp clamps 0.71.3 20v + C sr qq 1v 16 fb 17 v cmp 14 sfst tsd current trip slope compensation current comparator overcurrent fault logic block C + C + 21 r cmp gate drive 22 pg 24 sg 9 gnd 33 oscillator set enable v cc gate drive bold line indicates high current path 14v C + 32 nc 2 r class 3 i lim_en 4 shdn pwrgd v portp 31 nc 1 30 pwrgd 29 v neg 28 v neg v neg 26 control circuits input current limit classification current load 1.237v 1400ma 300ma 750ma C + 16k 25k 7 v portn v portn 6 27 42681 bd v portn 5 downloaded from: http:///
42681fc ltc4268-1 13 overview power over ethernet ( poe) continues to gain popularity as an increasing number of products are taking advantage of having dc power and high speed data available from a single rj45 connector. as poe is becoming established in the marketplace, powered device ( pd) equipment vendors are running into the 12.95 w power limit established by the ieee 802.3 af standard. to solve this problem and expand the application of poe, the ltc4268-1 breaks the power barrier by allowing custom poe applications to deliver up to 35w for power hungry poe applications such as dual band access points, rfid readers and ptz security cameras. the ltc4268-1 is designed to be a complete solution for pd applications with power requirements up to 35 w. the ltc4268-1 interfaces with custom power sourcing equip - ment ( pse) using a high efficiency flyback topology for maximum power delivery without the need for opto - isolator feedback. off - the - shelf high power pses are available today from a variety of vendors for use with the ltc4268-1 to allow quick implementation of a custom system. applications information operation note: please refer to the simplified application circuit (figure 1) for voltage naming conventions used in this data sheet. the ltc4268-1 high power pd interface controller and switching regulator has several modes of operation depend - ing on the applied v port voltage as shown in figure 2 and summarized in table 1. these various modes satisfy the requirements defined in the ieee 802.3 af specification. the input voltage is applied to the v portn pin with reference to the v portp pin and is always negative. series diodes the ieee 802.3 af-defined operating modes for a pd refer- ence the input voltage at the rj45 connector on the pd. in this data sheet port voltage is normally referenced to the pins of the ltc4268-1. note that the voltage ranges specified in the ltc4268-1 electrical specifications are referenced with respect to the ic pins. ? ? 1614 15 13 2 rx C 6 rx + 3 tx C 2 tx + rj45 pd front end switching regulator isolated output t1 42681 f01 17 8 5 4 11 9 10 68 7 to phy v portp ltc4268-1 v portn v neg gnd v cc pg spare C spare + v port v in v out +C ~~ +C ~~ + + figure 1. simplified application circuit with voltage naming conventions downloaded from: http:///
ltc4268-1 14 42681fc applications information the pd must be able to handle power received in either polarity. for this reason, it is common to install diode bridges between the rj45 connector and the ltc4268-1 (figure 3). the diode bridges introduce an offset that affects the threshold points for each range of operation. the ltc4268-1 meets the ieee 802.3 af-defined operating modes by compensating for the diode drops in the threshold points. for the signature, classification, and the uvlo thresholds, the ltc4268-1 extends two diode drops below the ieee 802.3 af specifications. the ltc4268-1 threshold points support the use of either traditional or schottky diode bridges. figure 2. v in voltage, pwrgd , pwrgd and pd current as a function of port voltage detection v1 classification uvloturn-on uvlo off power bad uvlo off uvlo on uvloturn-off = r load c1 pwrgd tracks v in detection v2 C10 time C20C30 v portn (v) C40C50 C10 time C20C30 v in (v) C40C50 C10 time C20C30 pwrgd (v) pwrgd C v in (v) C40C50 2010 i class pd current i limit_high i limit_low dv dt i limit_low c1 = power bad power bad power bad timetime power good power good detection i 1 classification detection i 2 load, i load (up to i limit_high ) 42681 f02 i class dependent on r class selection i limit_low = 300ma, i limit_high = 750ma i 1 = v1 C 2 diode drops 25k i load = v in r load i 2 = v2 C 2 diode drops 25k v portp pse i in r load r class v in c1 r class pwrgd pwrgd ltc4268-1 v neg v portn v port + rx C 6 rx + 3 tx C 2 tx + rj45 t1 powered device (pd) interface as defined by ieee 802. 3af 42681 f03 1 78 5 4 spare C spare + to phy br2 0.1f100v br1 v portp d3 ltc4268-1 v portn figure 3. pd front end using diode bridges on main and spare inputs detection during detection, the pse will apply a voltage in the range of C2.8 v to C10 v on the cable and look for a 25 k signature resistor. this identifies the device at the end of the cable as a pd. with the pse voltage in the detection range, the ltc4268-1 presents an internal 25 k resistor between the v portp and v portn pins. this precision, temperature- compensated resistor provides the proper characteristics to alert the pse that a pd is present and requests power to be applied. downloaded from: http:///
42681fc ltc4268-1 15 applications information table 1. ltc4268-1 operational mode as a function of v port voltage v port mode of operation 0v to C1.4v inactive C1.5v to C10.1v 25k signature resistor detection C10.3v to C12.4v classification load current ramps up from 0% to 100% C12.5v to uvlo* classification load current active uvlo* to C57v power applied to pd load *uvlo includes hysteresis. rising input threshold @ C38.9v falling input threshold @ C30.6v the ieee 802.3 af specification requires the pse to use a d v/ d i measurement technique to keep the dc offset voltage of the diode bridge from affecting the signature resistance measurement. however, the diode resistance appears in series with the signature resistor and must be included in the overall signature resistance of the pd. the ltc4268-1 compensates for the two series diodes in the signature path by offsetting the internal resistance so that a pd built with the ltc4268-1 meets the ieee 802.3af specification. in some designs that include an auxiliary power option, such as an external wall adapter, it is necessary to con- trol whether or not the pd is detected by a pse. with the ltc4268-1, the 25 k signature resistor can be enabled or disabled with the shdn pin ( figure 4). taking the shdn pin high will reduce the signature resistor to 10 k which is an invalid signature per the ieee 802.3 af specifications. this will prevent a pse from detecting and powering the pd. this invalid signature is present in the pse probing range of C2.8 v to C10 v. when the input rises above C10 v, the signature resistor reverts to 25 k to minimize power dissipation in the ltc4268-1. to disable the signature, tie shdn to v portp . alternately, the shdn pin can be driven high with respect to v portn . when shdn is high, all functions are disabled. for normal operation tie shdn to v portn . classification once the pse has detected a pd, the pse may optionally classify the pd. classification provides a method for more efficient allocation of power by allowing the pse to identify lower-power pds and assign the appropriate power level to these devices. for each class, there is an associated load current that the pd asserts onto the line during clas- sification probing. the pse measures the pd load current in order to assign the proper pd classification. class 0 is included in the ieee 802.3 af specification to cover pds that do not support classification. class 1-3 partition pds into three distinct power ranges as shown in table 2. table 2. summary of ieee 802.3af power classifications and ltc4268-1 r class resistor selection class usage maximum power levels at input of pd (w) nominal classification load current (ma) ltc4268-1 rclass resistor ( w , 1%) 0 default 0.44 to 13.0 <5 open 1 optional 0.44 to 3.84 10.5 124 2 optional 3.84 to 6.49 18.5 69.8 3 optional 6.49 to 13.0 28 45.3 4 reserved by ieee. see apps 40 30.9 5 undefined by ieee. see apps 56 22.1 class 4 was reserved by the ieee 802.3 af committee for future use and has been reassigned as a high power indicator by ieee 802.3 at. the new class 5 defined here is available for system vendors to implement a unique v portp v portn shdn ltc4268-1 signature disable 42681 f04 25k signatureresistor 16k to pse figure 4. 25k signature resistor with disable downloaded from: http:///
ltc4268-1 16 42681fc applications information classification for use in closed systems and is not defined or supported by the ieee 802.3 af. with the extended clas- sification range available in the ltc4268-1, it is possible for system designers to define multiple classes using load currents between 40ma and 75ma. during classification, the pse presents a fixed voltage between C15.5 v and C20.5 v to the pd ( figure 5). with the input voltage in this range, the ltc4268-1 asserts a load current from the v portp pin through the r class resistor. the magnitude of the load current is set with the selection of the r class resistor. the resistor value associated with each class is shown in table 2. a substantial amount of power is dissipated in the ltc4268-1 during classification. the ieee 802.3 af specifi- cation limits the classification time to 75 ms in order avoid excessive heating. the ltc4268-1 is designed to handle the power dissipation during the probe period. if the pse probing exceeds 75 ms, the ltc4268-1 may overheat. in this situation, the thermal protection circuit will engage and disable the classification current source, protecting the ltc4268-1 from damage. when the die cools, clas- sification is automatically resumed. classification presents a challenging stability problem for the pse due to the wide range of loads possible. the ltc4268-1 has been designed to avoid pse interoperability problems by maintaining a positive i-v slope throughout the signature and classification ranges up to uvlo turn on as shown in figure 6. the positive i-v slope avoids areas of negative resistance and helps prevent the pse from power cycling or getting stuck during signature or classification probing. in the event a pse overshoots beyond the classification voltage range, the available load current aids in returning the pd back into the classification voltage range . ( the pd input may otherwise be trapped by a reverse-biased diode bridge and the voltage held by the 0.1 f capacitor.) by gently ramping the classification current on and maintaining a positive i-v slope until uvlo turn-on, the ltc4268-1 provides a well behaved load, assuring interoperability with any pse. v portp r class v portn ltc4268-1 constantload current internal to ltc4268-1 42681 f05 r class current path v pd pse pse current monitor pse probingvoltage source C15.5v to C20.5v v port (v) 0 input current (ma) C40 42681 f06 C10 C20 C30 figure 5. pse probing pd during classification figure 6. ltc4268-1 positive i-v slope downloaded from: http:///
42681fc ltc4268-1 17 applications information undervoltage lockout the ieee 802.3 af specification dictates a maximum turn - on voltage of 42 v and a minimum turn-off voltage of 30 v for the pd. in addition, the pd must maintain large on-off hysteresis to prevent current-resistance ( i-r) drops in the wiring between the pse and the pd from causing start-up oscillation. the ltc4268-1 incorporates an undervoltage lockout ( uvlo) circuit that monitors line voltage at v portn to determine when to apply power to the pd load ( figure 7). before power is applied to the load, the v neg pin is high impedance and there is no charge on capacitor c1. when the input voltage rises above the uvlo turn-on threshold, the ltc4268-1 removes the classification load current and turns on the internal power mosfet. c1 charges up under ltc4268-1 inrush current limit control and the v neg pin transitions from 0 v to v portn as shown in figure 2. the ltc4268-1 includes a hysteretic uvlo circuit on v portn that keeps power applied to the load until the magnitude of the input voltage falls below the uvlo turn-off threshold. once v portn falls below uvlo turn-off, the internal power mosfet disconnects v neg from v portn and the classification current is re-enabled. c1 will discharge through the pd circuitry and the v neg pin will go to a high impedance state. input current limitieee 802.3 af specifies a maximum inrush current and also specifies a minimum load capacitor between the v portp and v neg pins. to control turn-on surge currents in the system the ltc4268-1 integrates a dual current limit circuit using an onboard power mosfet and sense resistor to provide a complete inrush control circuit without additional external components. at turn-on, the ltc4268-1 will limit the inrush current to i limit_low , allowing the load capaci- tor to ramp up to the line voltage in a controlled manner without interference from the pse current limit. by keeping the pd current limit below the pse current limit, pd power up characteristics are well controlled and independent of pse behavior. this ensures interoperability regardless of pse output characteristics. after load capacitor c1 is charged up, the ltc4268-1 switches to the high input current limit, i limit_high . this allows the ltc4268-1 to deliver up to 35 w to the pd load for high power applications. to maintain compatibility with ieee 802.3 af power levels, it is necessary for the pd designer to ensure the pd steady - state power consumption remains below the limits shown in table 2. the ltc4268-1 maintains the high input current limit until the port voltage drops below the uvlo turn-off threshold. v portp c1 5f min v portn v neg v in ltc4268-1 42681 f07 to pse undervoltage lockout circuit current-limitedturn on + v port ltc4268-1 voltage power mosfet 0v to uvlo* off >uvlo* on *uvlo includes hysteresis rising input threshold ? C38.9v falling input threshold ? C30.6v figure 7. ltc4268-1 undervoltage lockout downloaded from: http:///
ltc4268-1 18 42681fc during the inrush event as c1 is being charged, a large amount of power is dissipated in the mosfet. the ltc4268-1 is designed to accept this load and is thermally protected to avoid damage to the onboard power mosfet. if a thermal overload does occur, the power mosfet turns off, allowing the die to cool. once the die has returned to a safe temperature, the ltc4268-1 automatically switches to i limit_low , and load capacitor c1 charging resumes. the ltc4268-1 has the option of disabling the normal operating input current limit, i limit _ high , for custom high power poe applications. to disable the current limit, connect i lim_en to v portn . to protect the ltc4268-1 from damage when the normal current limit is disabled, a safeguard current limit, i limit _ disa keeps the current below destructive levels, typically 1.4 a. note that continuous operation at or near the safeguard current limit will rapidly overheat the ltc4268-1, engaging the thermal protection circuit. for normal operations, float the i lim_en pin. the ltc4268-1 maintains the i limit_low inrush current limit for charging the load capacitor regardless of the state of i lim_en . the operation of the i lim_en pin is summarized in table 3. table 3. summary of ieee 802.3af power classifications and ltc4268-1 r class resistor selection state of i lim_en inrush current limit operating input current limit floating i limit_low i limt_high tied to v portn i limit_low i limit_disa power good the ltc4268-1 includes complementary power good outputs ( figure 8) to simplify connection to any dc/dc converter. power good is asserted at the end of the inrush event when load capacitor c1 is fully charged and the dc/dc converter can safely begin operation. the power good signal stays active during normal operation and is de-asserted at power off when the port drops below the uvlo threshold or in the case of a thermal overload event. for pd designs that use a large load capacitor and also applications information 42681 f08 bold line indicates high current path pwrgd power not good inrush complete and not in thermal shutdown v port < uvlo off or thermal shutdown power good 29 pwrgd ltc4268-1 30 v neg 28 v neg 26 v portn 7 v neg 27 v portn 6 v portn ref uvlo thermal sd 5 control circuit figure 8. ltc4268-1 power good functional and state diagram downloaded from: http:///
42681fc ltc4268-1 19 consume a lot of power, it is important to delay activation of the dc/dc converter with the power good signal. if the converter is not disabled during the current-limited turn-on sequence, the dc/dc converter will rob current intended for charging up the load capacitor and create a slow rising input, possibly causing the ltc4268-1 to go into thermal shutdown.the active high pwrgd pin features an internal , open-collector output referenced to v neg . during inrush, the active high pwrgd pin becomes valid when c 1 reaches C4v and pulls low until the load capacitor is fully charged. at that point, pwrgd becomes high impedance, indicating the switching regulator may begin running. the active high pwrgd pin interfaces directly to the uvlo pin of the ltc4268-1 with the aid of an external pull-up resistor to vcc. the pwrgd pin includes an internal 14 v clamp to v neg . during a power supply ramp down event, pwrgd becomes low impedance when v port drops below the 30 v pd uvlo turn-off threshold, then goes high impedance when the v port voltages fall to within the detection voltage range. figure 11 shows a typical connection scheme for the active high pwrgd pin. the ltc4268-1 also includes an active low pwrgd pin for system level use. pwrgd is referenced to the v portn pin and when active will be near the v portn potential. the negative rail ( gnd) of the internal switching regulator will typically be referenced to v neg and care must be taken to ensure that the difference in potential of the pwrgd pin does not cause a problem for the switcher. thermal protection the ltc4268-1 includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. at turn-on, before load capacitor c1 has charged up, the instantaneous power dissipated by the ltc4268-1 can be as high as 20 w. as the load capacitor charges, the power dissipation in the ltc4268-1 will decrease until it reaches a steady-state value dependent on the dc load current. the ltc4268-1 can also experience device heating after turn-on if the pd experiences a fast input voltage rise. for example, if the pd input voltage steps from C37 v to C57 v, the instantaneous power dissipated by the ltc4268-1 can be as high as 16 w. the ltc4268-1 protects itself from damage by monitoring die temperature. if the die exceeds the overtemperature trip point, the power mosfet and classification transistors are disabled until the part cools down. once the die cools below the overtemperature trip point, all functions are enabled automatically. during classification, excessive heating of the ltc4268-1 can occur if the pse violates the 75 ms probing time limit. in addition, the ieee 802.3 af specification requires a pd to withstand application of any voltage from 0 v to 57 v indefinitely. to protect the ltc4268-1 in these situations, the thermal protection circuitry disables the classification circuit and the input current if the die temperature exceeds the overtemperature trip point. when the die cools down, classification and input current are enabled.once the ltc4268-1 has charged up the load capacitor and the pd is powered and running, there will be some residual heating due to the dc load current of the pd flowing through the internal mosfet. in some high current applications, the ltc4268-1 power dissipation may be significant. the ltc4268-1 uses a thermally enhanced dfn package that includes an exposed pad which should be soldered to the gnd plane for heat sinking on the printed circuit board. maximum ambient temperature the ltc4268-1 i lim_en pin allows the pd designer to disable the normal operating current limit. with the normal current limit disabled, it is possible to pass currents as high as 1.4 a through the ltc4268-1. in this mode, significant package heating may occur. depending on the current, voltage, ambient temperature, and waveform characteristics, the ltc4268-1 may shut down. to avoid nuisance trips of the thermal shutdown, it may be necessary to limit the maximum ambient temperature. limiting the die temperature to 125 c will keep the ltc4268-1 from hitting thermal shutdown. for dc loads the maximum ambient temperature can be calculated as: t max = 125 C ja ? pwr (c) where t max is the maximum ambient operating tempera- ture, ja is the junction-to-ambient thermal resistance (49c/w), and pwr is the power dissipation for the ltc4268-1 in watts (i pd 2 ? r on ). applications information downloaded from: http:///
ltc4268-1 20 42681fc external interface and component selection transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer ( figure 9). for powered devices, the isolation transformer must include a center tap on the media ( cable) side. proper termination is required around the transformer to pro - vide correct impedance matching and to avoid radiated and conducted emissions. for high power applications beyond ieee 802.3 af limits, the increased current levels increase the current imbalance in the magnetics. this imbalance reduces the perceived inductance and can interfere with data transmission. transformers specifi - cally designed for high current applications are required . transformer vendors such as bel fuse, coilcraft, halo , pulse, and tyco ( table 4) can provide assistance with selection of an appropriate isolation transformer and proper termination methods. these vendors have trans - formers specifically designed for use in high power pd applications . table 4. power over ethernet transformer vendors v port mode of operation bel fuse inc. 206 van vorst street jersey city, nj 07302 tel : 201-432-0463 www.belfuse.com coilcraft inc. 1102 silver lake road gary, il 60013 tel : 847-639-6400 www.coilcraft.com halo electronics 1861 landings drive mountain view, ca 94043 tel : 650-903-3800 www.haloelectronics.com pulse engineering 12220 world trade drive san diego, ca 92128 tel : 858-674-8100 www.pulseeng.com tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel : 800-227-7040 www.circuitprotection.com ieee 802.3 af allows power wiring in either of two configu- rations on the tx/rx wires, and power can be applied to the pd via the spare wire pair in the rj45 connector. the applications information 1614 15 13 2 rx C 6 rx + 3 tx C 2 tx + rj45 t1 pulse h2019 42681 f09 17 8 5 4 11 9 10 6 8 4 5 8 7 d3 smaj58a tvs br1hd01 10 br2hd01 to phy v portp v out ltc4268-1 c1 v portn v neg spare C spare + c140.1f 100v figure 9. pd front-end isolation transformer, diode bridges, capacitors and tvs downloaded from: http:///
42681fc ltc4268-1 21 pd is required to accept power in either polarity on both the data and spare inputs; therefore it is common to install diode bridges on both inputs in order to accommodate the different wiring configurations. figure 9 demonstrates an implementation of the diode bridges to minimize heating. the ieee 802.3 af specification also mandates that the leakage back through the unused bridge be less than 28 a when the pd is powered with 57v. the ltc4268-1 has several different modes of operation based on the voltage present between the v portn and v portp pins. the forward voltage drop of the input diodes in a pd design subtracts from the input voltage and will affect the transition point between modes. the input diode bridge of a pd can consume over 4% of the available power in some applications. schottky diodes can be used in order to reduce power loss. the ltc4268-1 is designed to work with both standard and schottky diode bridges while maintaining proper threshold points for ieee 802.3af compliance.input capacitor the ieee 802.3 af/at standard includes an impedance requirement in order to implement the ac disconnect function. a 0.1 f capacitor ( c14 in figure 9) is used to meet the ac impedance requirement.input series resistance li near technology has seen the customer community cable discharge requirements increase by nearly 500,000 times the original test levels. the pd must survive and operate reliably not only when an initially charged cable connects and dissipates the energy through the pd front end, but also when the electrical power system grounds are subject to very high energy events (e.g., lightning strikes). in these high energy events, adding 10 series resistance into the v portp pin greatly improves the robustness of the ltc4268-1 based pd ( see figure 9). the tvs limits the voltage across the port while the 10 and 0.1 f ca- pacitance reduces the edge rate the lt4268-1 encounters across its pin. the added 10 series resistance does not operationally affect the ltc4268-1 pd interface, nor does it affect its compliance with the ieee 802.3 standard. transient voltage suppressor the ltc4268-1 specifies and absolute maximum volt- age of 100 v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world can routinely see excessive peak voltages. to pro- tect the ltc4268-1, install a transient voltage suppressor (d3) between the input diode bridge and the ltc4268-1, as shown in figure 9. an smaj58a is recommended for typical pd applications. however, an smbj58a may be preferred in applications where the pd front end must absorb higher energy discharge events. auxiliary power source in some applications, it may be necessary to power the pd from an auxiliary power source such as a wall adapter. the auxiliary power can be injected into the pd at several locations and various trade-offs exist. figure 10 demon- strates four methods of connecting external power to a pd . option 1 in figure 10 inserts power before the ltc4268-1 interface controller. in this configuration, it is necessary for the wall adapter to exceed the ltc4268-1 uvlo turn- on requirement. this option provides input current limit for the adapter, provides a valid power good signal and simplifies power priority issues. as long as the adapter applies power to the pd before the pse, it will take priority and the pse will not power up the pd because the external power source will corrupt the 25 k signature. if the pse is already powering the pd, the adapter power will be in parallel with the pse. in this case, priority will be given to the higher supply voltage. if the adapter voltage is higher, the pse may remove the port voltage since no current will be drawn from the pse. on the other hand, if the adapter voltage is lower, the pse will continue to supply power to the pd and the adapter will not be used. proper operation will occur in either scenario.option 2 applies power directly to the dc/dc converter. in this configuration the adapter voltage does not need to exceed the ltc4268-1 turn-on uvlo requirement and can be selected based solely on the pd load requirements. it is necessary to include diode d9 to prevent the adapter from applying power to the ltc4268-1. power priority issues require more intervention. if the adapter voltage is below the pse voltage, then the priority will be given applications information downloaded from: http:///
ltc4268-1 22 42681fc applications information rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 78 5 4 spare C +C spare + isolated wall transformer to phy v portp option 1: auxiliary power inserted before ltc4268-1 option 2: auxiliary power inserted after ltc4268-1 with signature disabled v portn v neg v ww v ww v ww d8 s1b d3smaj58a tvs c1 ? 42v v ww 57v ? no power priority issues? ltc4268-1 current limits for both poe and v ww ? 42v v ww 57v ? no power priority issues? no ltc4268-1 current limits for v ww ? v ww any voltage based on pd load ? requires extra diode? see apps regarding power priority c140.1f 100v rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 78 5 4 spare C +C spare + isolated wall transformer to phy v portp ltc4268-1 ltc4268-1 br2 ~~ +C br1 ~~ +C br1 ~~ +C v portn shdn bss63 4.7k100k v neg d10 s1b d3smaj58a tvs c1 d9 s1b option 3: auxiliary power applied to ltc4268-1 and pd load rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 78 5 4 spare C +C spare + isolated wall transformer to phy v portp ltc4268-1 v portn v neg d10 s1b d3smaj58a tvs c1 c140.1f 100v c140.1f 100v br2 ~~ +C br1 ~~ +C option 4: auxiliary power applied to isolated load br2 ~~ +C v ww ? v ww any voltage based on pd load ? see apps regarding power priority? best isolation rx C 6 rx + 3 tx C 2 tx + rj45 t1 1 78 5 4 spare C +C spare + isolated wall transformer to phy v portp pg gnd ltc4268-1 br1 ~~ +C v portn shdn v neg d3smaj58a tvs c1 drive load c14 0.1f 100v br2 ~~ +C isolated dc/dc converter v in v in v in + + + + figure 10. interfacing auxiliary power source to the pd downloaded from: http:///
42681fc ltc4268-1 23 to the pse power. the pd will draw power from the pse while the adapter will remain unused. this configuration is acceptable in a typical poe system. however, if the adapter voltage is higher than the pse voltage, the pd will draw power from the adapter. in this situation, it is necessary to address the issue of power cycling that may occur if a pse is present. the pse will detect the pd and apply power. if the pd is being powered by the adapter, then the pd will not meet the minimum load requirement and the pse may subsequently remove power. the pse will again detect the pd and power cycling will start. with an adapter voltage above the pse voltage, it is necessary to either disable the signature as shown in option 2, or install a minimum load on the output of the ltc4268-1 to prevent power cycling. a 3 k , 1 w resistor connected between v portp and v neg will present the required minimum load.option 3 applies power directly to the dc/dc converter bypassing the ltc4268-1 and omitting diode d9. with the diode omitted, the adapter voltage is applied to the ltc4268-1 in addition to the dc/dc converter. for this reason, it is necessary to ensure that the adapter maintain the voltage between 42 v and 57 v to keep the ltc4268-1 in its normal operating range. the third option has the advantage of corrupting the 25 k signature resistance when the external voltage exceeds the pse voltage and thereby solving the power priority issue. option 4 bypasses the entire pd interface and injects power at the output of the low voltage power supply. if the adapter output is below the low voltage output there are no power priority issues. however, if the adapter is above the internal supply, then option 4 suffers from the same power priority issues as option 2 and the signature should be disabled or a minimum load should be installed. shown in option 4 is one method to disable to the signature while maintaining isolation. if employing options 1 through 3, it is necessary to ensure that the end-user cannot access the terminals of the aux- iliary power jack on the pd since this would compromise ieee 802.3 af isolation requirements and may violate local applications information safety codes. using option 4 along with an isolated power supply addresses the isolation issue and it is no longer necessary to protect the end -user from the power jack. the above power cycling scenarios have assumed the pse is using dc disconnect methods. for a pse using ac disconnect, a pd with less than minimum load will continue to be powered. wall adapters have been known to generate voltage spikes outside their expected operating range. care should be taken to ensure no damage occurs to the ltc4268-1 or any support circuitry from extraneous spikes at the auxiliary power interface. classification resistor selection (r class ) the ieee 802.3 af specification allows classifying pds into four distinct classes with class 4 being reserved for future use ( table 2). the ltc4268-1 supports all ieee classes and implements an additional class 5 for use in custom poe applications. an external resistor connected from r class to v portn ( figure 6) sets the value of the load current. the designer should determine which class the pd is to advertise and then select the appropriate value of r class from table 2. if a unique load current is required, the value of r class can be calculated as: r class = 1.237v/(i load C i in_class ) i in_class is the ltc4268-1 ic supply current during classification given in the electrical specifications. the r class resistor must be 1% or better to avoid degrading the overall accuracy of the classification circuit. resis- tor power dissipation will be 100 mw maximum and is transient so heating is typically not a concern. in order to maintain loop stability, the layout should minimize capacitance at the r class node. the classification circuit can be disabled by floating the r class pin. the r class pin should not be shorted to v portn as this would force the ltc4268-1 classification circuit to attempt to source very large currents. in this case, the ltc4268-1 will quickly go into thermal shutdown. downloaded from: http:///
ltc4268-1 24 42681fc power good interfacethe ltc4268-1 provides complimentary power good signals to simplify the dc/dc converter interface. using the power good signal to delay converter operation until the load capacitor is fully charged is recommended as this will help ensure trouble free start-up. the active high pwrgd pin is controlled by an open col- lector transistor referenced to v neg while the active low pwrgd pin is controlled by a high voltage, open-drain mosfet referenced to v portn . the pwrgd pin is de- signed to interface directly to the uvlo pin with the aid of a pull-up resistor to vcc. an example interface circuit is shown in figure 11. the pin voltage and thus creating hysteresis. as the pin voltage drops below this threshold, the current is disabled, further dropping the uvlo pin voltage. if not used, the uvlo pin can be disabled by tying to v cc . shutdown interfaceto disable the 25 k signature resistor, connect shdn to the v portp pin. alternately, the shdn pin can be driven high with respect to v portn . examples of interface circuits that disable the signature and all ltc4268-1 functions are shown in figure 10, options 2 and 4. note that the shdn input resistance is relatively large and the threshold volt- age is fairly low. because of high voltages present on the printed circuit board, leakage currents from the v portp pin could inadvertently pull shdn high. to ensure trouble-free operation, use high voltage layout techniques in the vicinity of shdn. if unused, connect shdn directly to v portn . load capacitorthe ieee 802.3 af specification requires that the pd maintain a minimum load capacitance of 5 f. it is permissible to have a much larger load capacitor and the ltc4268-1 can charge very large load capacitors before thermal issues become a problem. however, the load capacitor must not be too large or the pd design may violate ieee 802.3 af requirements. if the load capacitor is too large, there can be a problem with inadvertent power shutdown by the pse . for example, if the pse is running at C57 v ( ieee 802.3 af maximum allowed) and the pd is detected and powered up, the load capacitor will be charged to nearly C57 v. if for some reason the pse voltage is suddenly reduced to C44v ( ieee 802.3 af minimum allowed), the input bridge will reverse bias and the pd power will be supplied by the load capacitor. depending on the size of the load capacitor and the dc load of the pd, the pd will not draw any power from the pse for a period of time. if this period of time exceeds the ieee 802.3 af 300 ms disconnect delay, the pse will remove power from the pd. for this reason, it is necessary to evaluate the load current and capacitance to ensure that inadvertent shutdown cannot occur. refer also to thermal protection in this data sheet for further discussion on load capacitor selection. applications information v portp v cc 4k pwrgd ?54v 42681 f11 to pse ltc4268-1 active-high enable v portn uvlo 100k figure 11. power good interface example port voltage lockout poe applications require the pd interface to turn on below 42v and turn off above 30v. the ltc4268-1 includes an internal port voltage lockout circuit to implement this basic chip on/off control. additionally, the ltc4268-1 includes an enable/lockout function for the dc/dc converter that is controlled by the uvlo pin and is intended to be driven by pwrgd to ensure proper start-up . ( refer to power good interface.) users have the ability to implement higher turn-on voltages if necessary by connecting the uvlo pin to an external resistive divider between v portp and v portn . the uvlo pin also includes a bias current allowing implementation of hysteresis. when uvlo is below 1.24 v, gate drivers are disabled and the converter sits idle. when the pin rises above the lockout threshold a small current is sourced out of the uvlo pin, increasing downloaded from: http:///
42681fc ltc4268-1 25 maintain power signature in an ieee 802.3 af system, the pse uses the maintain power signature ( mps) to determine if a pd continues to require power. the mps requires the pd to periodically draw at least 10ma and also have an ac impedance less than 26.25 k in parallel with 0.05 f. if either the dc current is less than 10 ma or the ac impedance is above 26.25 k, the pse may disconnect power. the dc current must be less than 5 ma and the ac impedance must be above 2 m to guarantee power will be removed. the pd application circuits shown in this data sheet present the required ac impedance necessary to maintain power. ieee 802.3at interoperability in anticipation of the ieee 802.3 at standard release, the ltc4268-1 can be combined with a simple external circuit to be fully interoperable with an ieee 802.3 at-compliant pse. for more information, please contact linear technol- ogys application engineering. switching regulator overview the ltc4268-1 includes a current mode converter designed specifically for use in an isolated flyback topology employing synchronous rectification. the ltc4268-1 operation is similar to traditional current mode switchers. the major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. this precludes the need of an opto-isolator in isolated designs greatly improving dynamic response and reliability. the ltc4268-1 has a unique feedback amplifier that samples a transformer winding voltage during the flyback period and uses that voltage to control output voltage. the internal blocks are similar to many current mode controllers. the differences lie in the feedback amplifier and load compensation circuitry. the logic block also contains circuitry to control the special dynamic requirements of flyback control. for more information on the basics of current mode switcher/controllers and isolated flyback converters see application note 19. feedback amplifier?pseudo dc theory for the following discussion refer to the simplified flyback amplifier diagram(figure 12). when the primary side mosfet switch mp turns off, its drain voltage rises above the v portp rail. flyback occurs when the primary mosfet is off and the synchronous secondary mosfet is on. during flyback the voltage on nondriven transformer pins is determined by the secondary voltage. the amplitude of this flyback pulse as seen on the third winding is given as: v flbk = v out + i sec ? esr + r ds(on) ( ) n sf r ds(on) = on resistance of the synchronous mosfet ms i sec = transformer secondary current esr = impedance of secondary circuit capacitor, winding and tracesn sf = transformer effective secondary-to-flyback winding turns ratio (i.e., n s /n flbk ) applications information + C v fb 1.237v enable collapsedetect 1v ltc4268-1 feedback amp fb r1r2 16 17 v cmp v in primary flyback secondary ? ? ? mp t1 v flbk ms c vc 42681 f12 c out isolatedoutput + s r q C + figure 12. ltc4268-1 switching regulator feedback amplifier downloaded from: http:///
ltc4268-1 26 42681fc the flyback voltage is scaled by an external resistive divider r1/r2 and presented at the fb pin. the feedback amplifier compares the voltage to the internal bandgap reference. the feedback amp is actually a transconductance amplifier whose output is connected to v cmp only during a period in the flyback time. an external capacitor on the v cmp pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. the regulation voltage at the fb pin is nearly equal to the bandgap reference v fb because of the high gain in the overall loop. the relationship between v flbk and v fb is expressed as: v flbk = r1 + r2 r2 ? v fb combining this with the previous v flbk expression yields an expression for v out in terms of the internal reference, programming resistors and secondary resistances: v out = r1 + r2 r2 ? v fb ? n sf ?? ? ?? ? ? i sec ? esr + r ds(on) ( ) the effect of nonzero secondary output impedance is discussed in further detail; see load compensation theory . the practical aspects of applying this equation for v out are found in the applications information. feedback amplifier dynamic theory so far, this has been a pseudo-dc treatment of flyback feedback amplifier operation. but the flyback signal is a pulse, not a dc level. provision is made to turn on the flyback amplifier only when the flyback pulse is present using the enable signal as shown in the timing diagram (figure 13). minimum output switch on time (t on(min) ) the ltc4268-1 affects output voltage regulation via flyback pulse action. if the output switch is not turned on, there is no flyback pulse and output voltage information is not available. this causes irregular loop response and start-up/latch-up problems. the solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. to accomplish this the current limit feedback is blanked each cycle for t on(min) . if the output load is less than that developed under these conditions , forced continuous operation normally occurs. see applications information for further details.enable delay t ime (endly) the flyback pulse appears when the primary side switch shuts off. however, it takes a finite time until the transformer primary side voltage waveform represents the output voltage. this is partly due to rise time on the primary applications information primary side mosfet drain voltage pg voltagesg voltage v in t on(min) enable delay min enable feedback amplifier enabled pg delay 42681 f13 v flbk 0.8 ? v flbk figure 13. ltc4268-1 switching regulator timing diagram downloaded from: http:///
42681fc ltc4268-1 27 side mosfet drain node but, more importantly, is due to transformer leakage inductance. the latter causes a voltage spike on the primary side, not directly related to output voltage. some time is also required for internal settling of the feedback amplifier circuitry. in order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. this is termed enable delay. in certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. see applications information for further details.collapse detect once the feedback amplifier is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, which compares the flyback voltage ( fb) to a fixed reference, nominally 80% of v fb . when the flyback waveform drops below this level, the feedback amplifier is disabled. minimum enable time the feedback amplifier, once enabled, stays on for a fixed minimum time period termed minimum enable time. this prevents lockup, especially when the output voltage is abnormally low; e.g., during start-up. the minimum enable time period ensures that the v cmp node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. this time is set internally. effects of variable enable period the feedback amplifier is enabled during only a portion of the cycle time. this can vary from the fixed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of feedback amp behavior are directly affected by the variable enable period. these include effective transconductance and v cmp node slew rate. load compensation theorythe ltc4268-1 uses the flyback pulse to obtain information about the isolated output voltage. an error source is caused by transformer secondary current flow applications information through the synchronous mosfet r ds(on) and real life nonzero impedances of the transformer secondary and output capacitor. this was represented previously by the expression i sec ? ( esr + r ds(on) ). however, it is generally more useful to convert this expression to effective output impedance. because the secondary current only flows during the off portion of the duty cycle ( dc), the effective output impedance equals the lumped secondary impedance divided by off time dc. since the off time duty cycle is equal to 1 C dc then: r s(out) = esr + r ds(on) 1 ? dc where: r s(out) = effective supply output impedance dc = duty cycle r ds(on) and esr are as defined previously this impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. in these cases the external fb resistive divider is adjusted to compensate for nominal expected error. in more demanding applications, output impedance error is minimized by the use of the load compensation function. figure 14 shows the block diagram of the load compensation function. switch current is converted to a voltage by the external sense resistor, averaged and t1 ?? ? mp r cmpf 50k v portp v flbk r2 load comp i r1 fb v fb q1 q2 r cmp c cmp r sense sense + 42681 f13 q3 C + a1 16 22 21 20 figure 14. load compensation diagram downloaded from: http:///
ltc4268-1 28 42681fc applications information lowpass filtered by the internal 50 k resistor r cmpf and the external capacitor on c cmp . this voltage is impressed across the external r cmp resistor by op amp a1 and transistor q3 producing a current at the collector of q3 that is subtracted from the fb node. this effectively increases the voltage required at the top of the r1/r2 feedback divider to achieve equilibrium. the average primary side switch current increases to maintain output voltage regulation as output loading increases. the increase in average current increases r cmp resistor current which affects a corresponding increase in sensed output voltage, compensating for the ir drops. assuming relatively fixed power supply efficiency, eff, power balance gives: p out = eff ? p in v out ? i out = eff ? v in ? i in average primary side current is expressed in terms of output current as follow: i in = k1 ? i out where: k1= v out v in ? eff so the effective change in v out target is: d v out = k1 ? r sense r cmp ? r1 ? n sf thus: d v out d i out = k1 ? r sense r cmp ? r1 ? n sf where: k1 = dimensionless variable related to v in , v out and efficiency as explained above r sense = external sense resistor nominal output impedance cancellation is obtained by equating this expression with r s(out) : k1 ? r sense r cmp ? r1 ? n sf = esr + r ds(on) 1 ? dc solving for r cmp gives: r cmp = k1 ? r sense ? 1 ? dc ( ) esr + r ds(on) ? r1 ? n sf the practical aspects of applying this equation to determine an appropriate value for the r cmp resistor are found in the applications information. transformer design transformer design / specification is the most critical part of a successful application of the ltc4268-1. the following sections provide basic information about designing the transformer and potential trade-offs. if you need help, the lt c applications group is available to assist in the choice and/or design of the transformer. turns ratios the design of the transformer starts with determining duty cycle ( dc). dc impacts the current and voltage stress on the power switches, input and output capacitor rms currents and transformer utilization (size vs power). the ideal turns ratio is: n deal = v out v in ? 1 ? dc dc avoid extreme duty cycles as they, in general, increase current stresses. a reasonable target for duty cycle is 50% at nominal input voltage.for instance, if we wanted a 48v to 5v converter at 50% dc then: n deal = 5 48 ? 1 ? 0.5 0.5 = 1 9.6 downloaded from: http:///
42681fc ltc4268-1 29 applications information in general, better performance is obtained with a lower turns ratio. a dc of 45.5% yields a 1:8 ratio. note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. turns ratios that are the simple ratios of small integers; e.g ., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. when building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous rectifier on longer, and thus, keep secondary windings coupled longer. for a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. the ratio between two output voltages is set with the formula v out2 = v out1 ? n21 where n21 is the turns ratio between the two windings. also keep the secondary mosfet r ds(on) small to improve cross regulation. the feedback winding usually provides both the feedback voltage and power for the ltc4268-1. set the turns ratio between the output and feedback winding to provide a rectified voltage that under worst-case conditions is greater than the 11 v maximum v cc turn-off voltage. n sf > v out 11 + v f where: v f = diode forward voltage for our example: n sf > 5 11 + 0.7 = 1 2.34 we will choose 1 3 leakage inductance transformer leakage inductance ( on either the primary or secondary) causes a spike after the primary side switch turn-off. this is increasingly prominent at higher load currents, where more stored energy is dissipated. higher flyback voltage may break down the mosfet switch if it has too low a bv dss rating. one solution to reducing this spike is to use a snubber circuit to suppress the voltage excursion. however, suppressing the voltage extends the flyback pulse width. if the flyback pulse extends beyond the enable delay time, output voltage regulation is affected . the feedback system has a deliberately limited input range , roughly 50 mv referred to the fb node. this rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude; a further increase in amplitude has little effect on the feedback system. therefore, it is advisable to arrange the snubber circuit to clamp at as high a voltage as possible, observing mosfet breakdown , such that leakage spike duration is as short as possible. application note 19 provides a good reference on snubber design. as a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to perhaps ten percent cause increasing regulation error. avoid double digit percentage leakage inductances. there is a potential for abrupt loss of control at high load current. this curious condition potentially occurs when the leakage spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. once load current is reduced sufficiently, the system snaps back to normal operation. when using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short-circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at an abnormally low value, the system has a problem. this is usually evident by simultaneously viewing the primary side mosfet drain voltage to observe firsthand the leakage spike behavior. a final notethe susceptibility of the system to bistable behavior is somewhat a function of the load current/ voltage characteristics. a load with resistivei.e., i = v/r downloaded from: http:///
ltc4268-1 30 42681fc applications information behavioris the most apt to be bistable. capacitive loads that exhibit i = v 2 /r behavior are less susceptible. secondary leakage inductance leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the flyback pulse. this increases the output voltage target by a similar percentage. note that unlike leakage spike behavior; this phenomenon is independent of load. since the secondary leakage inductance is a constant percentage of mutual inductance ( within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate.winding resistance effects primary or secondary winding resistance acts to reduce overall efficiency ( p out /p in ). secondary winding resistance increases effective output impedance, degrading load regulation. load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. bifilar winding a bifilar or similar winding is a good way to minimize troublesome leakage inductances. bifilar windings also improve coupling coefficients and thus improve cross regulation in multiple winding transformers. however, tight coupling usually increases primary-to-secondary capacitance and limits the primary - to - secondary breakdown voltage, so it isnt always practical.primary inductance the transformer primary inductance, l p , is selected based on the peak-to-peak ripple current ratio ( x) in the transformer relative to its maximum value. as a general rule, keep x in the range of 20% to 40% (i.e., x = 0.2 to 0.4). higher values of ripple will increase conduction losses, while lower values will require larger cores.ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. l p is calculated from: l p = v in(max) ? dc min ( ) 2 f osc ? x max ? p in = v in(max) ? dc min ( ) 2 ? eff f osc ? x max ? p out where: f osc is the oscillator frequency dc min is the dc at maximum input voltage x max is ripple current ratio at maximum input voltage using common high power poe values a 48 v (41 v < v in < 57 v) to 5 v/5.3a converter with 90% efficiency, p out = 26.5w and p in = 29.5 w using x = 0.4 n = 1/8 and f osc = 200khz: dc min = 1 1 + n ? v in(max) v out = 1 1 + 1 8 ? 57 5 = 41.2% l p = 57v ? 0.412 ( ) 2 200khz ? 0.4 ? 26.5w = 260 h optimization might show that a more efficient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. a simple spreadsheet program is useful for looking at trade-offs. downloaded from: http:///
42681fc ltc4268-1 31 applications information transformer core selection once l p is known, the type of transformer is selected. high efficiency converters use ferrite cores to minimize core loss. actual core loss is independent of core size for a fixed inductance, but decreases as inductance increases. since increased inductance is accomplished through more turns of wire, copper losses increase. thus transformer design balances core and copper losses. remember that increased winding resistance will degrade cross regulation and increase the amount of load compensation required. the main design goals for core selection are reducing copper losses and preventing saturation. ferrite core material saturates hard, rapidly reducing inductance when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. do not allow the core to saturate! the maximum peak primary current occurs at minimum v in : i pk = p in v in(min) ? dc max ? 1 + x min 2 ?? ? ?? ? now : dc max = 1 1 + n ? v in min ( ) v out = 1 1 + 1 8 ? 41 5 = 49.4% x min = v in(min) ? dc max ( ) 2 f osc ? l p ? p in = 41 ? 49.4% ( ) 2 200khz ? 260 h ? 29.5w = 0.267 using the example numbers leads to: i pk = 29.5w 41 ? 0.494 ? 1 + 0.267 2 ?? ? ?? ? = 1.65a multiple outputs one advantage that the flyback topology offers is that additional output voltages can be obtained simply by adding windings. designing a transformer for such a situation is beyond the scope of this document. for multiple windings, realize that the flyback winding signal is a combination of activity on all the secondary windings. thus load regulation is affected by each windings load. take care to minimize cross regulation effects.setting feedback resistive divider the expression for v out developed in the operation section is rearranged to yield the following expression for the feedback resistors: r1 = r2 v out + i sec ? esr + r ds(on) ( ) ?? ?? v fb ? n sf ? 1 ?? ?? ?? ?? continuing the example, if esr + r ds(on) = 8 m w , r 2 = 3.32k, then: r1 = 3.32k 5 + 5.3 ? 0.008 1.237 ? 1/ 3 ? 1 ?? ? ?? ? = 37.28k choose 37.4k. it is recommended that the thevenin impedance of the resistive divider ( r1||r2) is roughly 3 k for bias current cancellation and other reasons.current sense resistor considerations the external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. use a noninductive current sense resistor ( no wire-wound resistors). mounting the resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance and inductance low. the dual sense pins allow for a full kelvin connection. make sure that sense+ and senseC are isolated and connect close to the sense resistor. peak current occurs at 100 mv of sense voltage v sense . so the nominal sense resistor is v sense /i pk . for example, a peak switch current of 10 a requires a nominal sense resistor of 0.010 w note that the instantaneous peak power in the sense resistor is 1 w, and that it is rated accordingly. the use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. downloaded from: http:///
ltc4268-1 32 42681fc size r sense using worst-case conditions, minimum l p , v sense and maximum v in . continuing the example, let us assume that our worst-case conditions yield an i pk of 40% above nominal so i pk = 2.3 a. if there is a 10% tolerance on r sense and minimum v sense = 88 mv, then r sense ? 110% = 88 mv/2.3a and nominal r sense = 35 m w . round to the nearest available lower value, 33m w . selecting the load compensation resistor the expression for r cmp was derived in the operation section as: r cmp = k1 ? r sense ? 1 ? dc ( ) esr + r ds(on) ? r1 ? n sf continuing the example: k1= v out v in ? eff ?? ? ?? ? = 5 48 ? 90% = 0.116 dc= 1 1+ n ? v in(nom) v out = 1 1 + 1 8 ? 48 5 = 45.5% if esr + r ds(on) = 8m w r cmp = 0.116 ? 33m w ? 1 ? 0.455 ( ) 8m w ? 37.4k w ? 1 3 = 3.25k this value for r cmp is a good starting point, but empirical methods are required for producing the best results. this is because several of the required input variables are difficult to estimate precisely. for instance, the esr term above includes that of the transformer secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resistance. similarly, k1 appears as a simple ratio of v in to v out times efficiency, but theoretically estimating efficiency is not a simple calculation. the suggested empirical method is as follows: 1. build a prototype of the desired supply including the actual secondary components. 2. temporarily ground the c cmp pin to disable the load compensation function. measure output voltage while sweeping output current over the expected range . approximate the voltage variation as a straight line. d v out / d i out = r s(out) . 3. calculate a value for the k1 constant based on v in , v out and the measured efficiency. 4. compute: r cmp = k1 ? r sense r s(out) ? r1 ? n sf 5. verify this result by connecting a resistor of this value from the r cmp pin to ground. 6. disconnect the ground short to c cmp and connect a 0.1 f filter capacitor to ground. measure the output imped- ance r s( out ) = d v out / d i out with the new compensation in place. r s(out) should have decreased significantly. fine tuning is accomplished experimentally by slightly altering r cmp . a revised estimate for r cmp is: r cmp = r cmp ? 1 + r s(out)cmp r s(out) ?? ? ?? ? where r cmp is the new value for the load compensation resistor. r s( out ) cmp is the output impedance with r cmp in place and r s(out) is the output impedance with no load compensation (from step 2). applications information downloaded from: http:///
42681fc ltc4268-1 33 applications information setting frequency the switching frequency of the ltc4268-1 is set by an external capacitor connected between the osc pin and ground. recommended values are between 200 pf and 33pf, yielding switching frequencies between 50 khz and 250khz. figure 15 shows the nominal relationship between external capacitance and switching frequency. place the capacitor as close as possible to the ic and minimize osc trace length and area to minimize stray capacitance and potential noise pickup. you can synchronize the oscillator frequency to an external frequency. this is done with a signal on the sync pin. set the ltc4268-1 frequency 10% slower than the desired external frequency using the osc pin capacitor, then use a pulse on the sync pin of amplitude greater than 2 v and with the desired frequency. the rising edge of the sync signal initiates an osc capacitor discharge forcing primary mosfet off ( pg voltage goes low). if the oscillator frequency is much different from the sync frequency, problems may occur with slope compensation and system stability. keep the sync pulse width greater than 500ns. selecting timing resistors there are three internal one - shot times that are programmed by external application resistors: minimum on time, enable delay time and primary mosfet turn - on delay . these are all part of the isolated flyback control technique, and their functions are previously outlined in the theory of operation section. the following information should help in selecting and/or optimizing these timing values. minimum output switch on time (t on(min) ) minimum on time is the programmable period during which current limit is blanked ( ignored) after the turn on of the primary side switch. this improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. this spike is due to both the gate / source charging current and the discharge of drain capacitance. the isolated flyback sensing requires a pulse to sense the output. minimum on time ensures that the output switch is always on a minimum time and that there is always a signal to close the loop. the ltc4268-1 does not employ cycle skipping at light loads. therefore, c osc (pf) 30 50 f osc (khz) 100 200 300 100 200 42681 f15 figure 15. f osc vs osc capacitor values downloaded from: http:///
ltc4268-1 34 42681fc minimum on time along with synchronous rectification sets the switch over to forced continuous mode operation. the t on(min) resistor is set with the following equation r ton(min) k w ( ) = t on(min) ns ( ) ? 104 1.063 keep r ton(min) greater than 70 k. a good starting value is 160k. enable delay time (endly) enable delay time provides a programmable delay between turn - off of the primary gate drive node and the subsequent enabling of the feedback amplifier. as discussed earlier, this delay allows the feedback amplifier to ignore the leakage inductance voltage spike on the primary side. the worst - case leakage spike pulse width is at maximum load conditions . so set the enable delay time at these conditions . while the typical applications for this part use forced continuous operation, it is conceivable that a secondary side controller might cause discontinuous operation at light loads. under such conditions the amount of energy stored in the transformer is small. the flyback waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage. the enable delay time should be made long enough to ignore the irrelevant portion of the flyback waveform at light loads. even though the ltc4268-1 has a robust gate drive, the gate transition time slows with very large mosfets. in- crease delay time as required when using such mosfets. the enable delay resistor is set with the following equation : r endly k w ( ) = t endly ns ( ) ? 30 2.616 keep r endly greater than 40 k. a good starting point is 56 k. primary gate delay time (pgdly) primary gate delay is the programmable time from the turn-off of the synchronous mosfet to the turn-on of the primary side mosfet. correct setting eliminates overlap between the primary side switch and secondary side synchronous switch(es) and the subsequent current spike in the transformer. this spike will cause additional component stress and a loss in regulator efficiency. the primary gate delay resistor is set with the following equation: r pgdly k w ( ) = t pgdly ns ( ) + 47 9.01 a good starting point is 27k.soft-start function the ltc4268-1 contains an optional soft - start function that is enabled by connecting an external capacitor between the sfst pin and ground. internal circuitry prevents the control voltage at the v cmp pin from exceeding that on the sfst pin. there is an initial pull-up circuit to quickly bring the sfst voltage to approximately 0.8 v . from there it charges to approximately 2.8 v with a 20 a current source . the sfst node is discharged to 0.8 v when a fault occurs. a fault occurs when v cc is too low ( undervoltage lockout), current sense voltage is greater than 200 mv or the ics thermal ( over temperature) shutdown is tripped. when sfst discharges, the v cmp node voltage is also pulled low to below the minimum current voltage. once discharged and the fault removed, the sfst charges up again. in this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. the time it takes to fully charge soft-start is: t ss = c sfst ? 1.4v 20 a = 70k w ? c sfst f ( ) applications information downloaded from: http:///
42681fc ltc4268-1 35 converter start-up the standard topology for the ltc4268-1 utilizes a third transformer winding on the primary side that provides both feedback information and local v cc power for the ltc4268 -1 ( see figure 16). this power bootstrapping improves converter efficiency but is not inherently self- starting. start - up is affected with an external trickle charge resistor and the ltc4268-1s internal v cc undervoltage lockout circuit. the v cc undervoltage lockout has wide hysteresis to facilitate start-up. in operation, the trickle charge resistor r tr is connected to v in and supplies a small current, typically on the order of 1 ma to charge c tr . initially the ltc4268-1 is off and draws only its start-up current. when c tr reaches the v cc turn-on threshold voltage the ltc4268-1 turns on abruptly and draws its normal supply current. switching action commences and the converter begins to deliver power to the output. initially the output voltage is low and the flyback voltage is also low, so c tr supplies most of the ltc4268-1 current ( only a fraction comes from r tr .) v cc voltage continues to drop until after some time, typically tens of milliseconds, the output voltage approaches its desired value. the flyback winding then provides the ltc4268-1 supply current and the v cc voltage stabilizes. applications information if c tr is undersized, v cc reaches the v cc turn - off threshold before stabilization and the ltc4268-1 turns off. the v cc node then begins to charge back up via r tr to the turn-on threshold, where the part again turns on. depending upon the circuit, this may result in either several on-off cycles before proper operation is reached, or permanent relaxation oscillation at the v cc node. r tr is selected to yield a worst-case minimum charging current greater than the maximum rated ltc4268-1 start- up current, and a worst-case maximum charging current less than the minimum rated ltc4268-1 supply current. r tr(max) < v in(min) ? v cc(on _ max) i cc(st _ max) and r tr(min) > v in(max) ? v cc(on _ min) i cc(min) make c tr large enough to avoid the relaxation oscillatory behavior described above. this is complicated to deter- mine theoretically as it depends on the particulars of the secondary circuit and load behavior. empirical testing is recommended. note that the use of the optional soft-start function lengthens the power-up timing and requires a correspondingly larger value for c tr . + i vcc 42681 f16 r tr c tr v in v in i vcc v vcc v on threshold 0 v pg v cc ltc4268-1 pg gnd ?? ? figure 16. typical power bootstrapping downloaded from: http:///
ltc4268-1 36 42681fc applications information the ltc4268-1 has an internal clamp on v cc of approxi- mately 20 v. this provides some protection for the part in the event that the switcher is off ( uvlo low) and the v cc node is pulled high. if r tr is sized correctly the part should never attain this clamp voltage.control loop compensation loop frequency compensation is performed by connect- ing a capacitor network from the output of the feedback amplifier ( v cmp pin) to ground as shown in figure 17. because of the sampling behavior of the feedback amplifier , compensation is different from traditional current mode controllers. normally only c vcmp is required. r vcmp can be used to add a zero but the phase margin improve- ment traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. c vcmp2 can be used to add an additional high frequency pole and is usually sized at 0.1 times c vcmp . in further contrast to traditional current mode switchers, v cmp pin ripple is generally not an issue with the ltc4268-1. the dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the v cmp voltage changes during the flyback pulse, but is then held during the subsequent switch on portion of the next cycle. this action naturally holds the v cmp voltage stable during the current comparator sense action ( current mode switching). application note 19 provides a method for empirically tweaking frequency compensation. basically it involves introducing a load current step and monitoring the response. slope compensationthe ltc4268-1 incorporates current slope compensation . slope compensation is required to ensure current loop stability when the dc is greater than 50%. in some switching regulators, slope compensation reduces the maximum peak current at higher duty cycles. the ltc4268-1 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. minimum load considerations at light loads, the ltc4268-1 derived regulator goes into forced continuous conduction mode. the primary side switch always turns on for a short time as set by the t on(min) resistor. if this produces more power than the load requires, power will flow back into the primary during the off period when the synchronization switch is on. this does not produce any inherently adverse problems, although light load efficiency is reduced. maximum load considerations the current mode control uses the v cmp node voltage and amplified sense resistor voltage as inputs to the current comparator. when the amplified sense voltage exceeds the v cmp node voltage, the primary side switch is turned off. in normal use, the peak switch current increases while fb is below the internal reference. this continues until v cmp reaches its 2.56 v clamp. at clamp, the primary side mosfet will turn off at the rated 100 mv v sense level. this repeats on the next cycle. it is possible for the peak primary switch currents as referred across r sense to exceed the 17 r vcmp v cmp c vcmp 42681 f17 c vcmp2 figure 17. v cmp compensation network downloaded from: http:///
42681fc ltc4268-1 37 applications information max 100 mv rating because of the minimum switch on time blanking. if the voltage on v sense exceeds 205 mv after the minimum turn-on time, the sfst capacitor is discharged, causing the discharge of the v cmp capacitor. this then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. short-circuit conditions loss of current limit is possible under certain conditions such as an output short circuit. if the duty cycle exhibited by the minimum on time is greater than the ratio of secondary winding voltage ( referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. it ratchets up cycle-by-cycle to some higher level. expressed mathematically, the requirement to maintain short-circuit control is dc min = t on(min) ? f osc < i sc ? r sec + r ds(on) ( ) v in ? n sp where: t on(min) is the primary side switch minimum on-time i sc is the short-circuit output current n sp is the secondary - to - primary turns ratio ( n sec /n pri ) ( other variables as previously defined) trouble is typically encountered only in applications with a relatively high product of input voltage times secondary to primary turns ratio and / or a relatively long minimum switch on time. additionally, several real world effects such as transformer leakage inductance, ac winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction for these losses. output voltage error sources the ltc4268-1s feedback sensing introduces additional minor sources of errors. the following is a summary list. ? the internal bandgap voltage reference sets the reference voltage for the feedback amplifier. the specifications detail its variation. ? the external feedback resistive divider ratio directly affects regulated voltage. use 1% components. ? leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio ( ns/nf) from its ideal value. this increases the output voltage target by a similar percentage. since secondary leakage inductance is constant from part to part ( within a tolerance) adjust the feedback resistor ratio to compensate. ? the transformer secondary current flows through the impedances of the winding resistance, synchronous mosfet r ds(on) and output capacitor esr. the dc equivalent current for these errors is higher than the load current because conduction occurs only during the converters off time. so divide the load current by (1 C dc). if the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. otherwise, use the ltc4268-1 load compensation circuitry . (see load compensation.) if multiple output windings are used, the flyback winding will have a signal that represents an amalgamation of all these windings impedances. take care that you examine worst - case loading conditions when tweaking the voltages. downloaded from: http:///
ltc4268-1 38 42681fc power mosfet selectionthe power mosfets are selected primarily on the criteria of on resistance r ds ( on ) , input capacitance, drain - to - source breakdown voltage ( bv dss ), maximum gate voltage ( v gs ) and maximum drain current (id (max) ). for the primary-side power mosfet, the peak current is: i pk(pri) = p in v in(min) ? dc max ? 1 + x min 2 ?? ? ?? ? where x min is peak - to - peak current ratio as defined earlier. for each secondary-side power mosfet, the peak current is: i pk(sec) = i out 1 ? dc max ? 1 + x min 2 ?? ? ?? ? select a primary-side power mosfet with a bv dss greater than: bv dss i pk l lkg c p + v in(max) + v out(max) n sp where n sp reflects the turns ratio of that secondary-to primary winding. l lkg is the primary-side leakage induc- tance and c p is the primary-side capacitance ( mostly from the drain capacitance ( c oss ) of the primary-side power mosfet). a snubber may be added to reduce the leakage inductance as discussed. for each secondary - side power mosfet, the bv dss should be greater than: bv dss v out + v in(max) ? n sp applications information choose the primary side mosfet r ds(on) at the nominal gate drive voltage (7.5 v). the secondary side mosfet gate drive voltage depends on the gate drive method. primary side power mosfet rms current is given by: i rms(pri) = p in v in(min) dc max for each secondary-side power mosfet rms current is given by: i rms(sec) = i out 1 ? dc max calculate mosfet power dissipation next. because the primary-side power mosfet operates at high v ds , a transition power loss term is included for accuracy. c miller is the most critical parameter in determining the transition loss, but is not directly specified on the data sheets. c miller is calculated from the gate charge curve included on most mosfet data sheets (figure 17). the flat portion of the curve is the result of the miller (gate-to-drain) capacitance as the drain voltage drops. the miller capacitance is computed as: c miller = q b ? q a v ds the curve is done for a given v ds . the miller capacitance for different v ds voltages are estimated by multiplying the computed c miller by the ratio of the application v ds to the curve specified v ds . q a v gs a b 42681 f18 q b miller effect gate charge (q g ) figure 18. gate charge curve downloaded from: http:///
42681fc ltc4268-1 39 with c miller determined, calculate the primary - side power mosfet power dissipation: p d(pri) = i rms(pri) 2 ? r ds(on) 1 + d ( ) + v in(max) ? p in(max) dc min ? r dr ? c miller v gate(max) ? v th ? f osc where: r dr is the gate driver resistance ( 10 w ) v th is the mosfet gate threshold voltage f osc is the operating frequency v gate(max) = 7.5v for this part (1 + d ) is generally given for a mosfet in the form of a normalized r ds ( on ) vs temperature curve. if you don t have a curve, use d = 0.005/ c ? d t for low voltage mosfets. the secondary-side power mosfets typically operate at substantially lower v ds , so you can neglect transition losses. the dissipation is calculated using: p dis(sec) = i rms(sec) 2 ? r ds(on) (1 + d ) with power dissipation known, the mosfets junction temperatures are obtained from the equation: t j = t a + p dis ? ja where t a is the ambient temperature and ja is the mosfet junction to ambient thermal resistance. once you have t j iterate your calculations recomputing d and power dissipations until convergence. gate drive node consideration the pg and sg gate drivers are strong drives to minimize gate drive rise and fall times. this improves efficiency but the high frequency components of these signals can cause problems. keep the traces short and wide to reduce parasitic inductance. the parasitic inductance creates an lc tank with the mosfet gate capacitance. in less than ideal layouts, a series resistance of 5 w or more may help to dampen the ringing at the expense of slightly slower rise and fall times and poorer efficiency. the ltc4268-1 gate drives will clamp the max gate voltage to roughly 7.5 v, so you can safely use mosfets with maximum v gs of 10v and larger. synchronous gate drive there are several different ways to drive the synchronous gate mosfet. full converter isolation requires the synchro - nous gate drive to be isolated. this is usually accomplished by way of a pulse transformer. usually the pulse driver is used to drive a buffer on the secondary as shown in the application on the front page of this data sheet. however, other schemes are possible. there are gate drivers and secondary side synchronous controllers available that provide the buffer function as well as additional features. capacitor selection in a flyback converter, the input and output current flows in pulses, placing severe demands on the input and output filter capacitors. the input and output filter capacitors are selected based on rms current ratings and ripple voltage. select an input capacitor with a ripple current rating greater than: i rms(pri) = p in v in(min) 1 ? dc max dc max continuing the example: i rms(pri) = 29.5w 41v 1 ? 49.4% 49.4% = 0.728a keep input capacitor series resistance ( esr) and inductance ( esl) small, as they affect electromagnetic interference suppression. in some instances, high esr can also produce stability problems because flyback converters exhibit a negative input resistance characteristic. refer to application note 19 for more information. the output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. applications information downloaded from: http:///
ltc4268-1 40 42681fc the output capacitor should have an rms current rating greater than: i rms(sec) = i out dc max 1 ? dc max continuing the example: i rms(sec) = 5.3a 49.4% 1 ? 49.4% = 5.24a this is calculated for each output in a multiple winding application. esr and esl along with bulk capacitance directly affect the output voltage ripple. the waveforms for a typical flyback converter are illustrated in figure 19. the maximum acceptable ripple voltage ( expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. for the purpose of simplicity we will choose 2% for the maximum output ripple, divided equally between the esr step and the charging/discharging d v. this percentage ripple changes, depending on the requirements of the application. you can modify the equations below. for a 1% contribution applications information to the total ripple voltage, the esr of the output capacitor is determined by: esr cout 1% ? v out ? 1 ? dc max ( ) i out the other 1% is due to the bulk c component, so use: c out i out 1% ? v out ? f osc in many applications the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reliability and cost goals. for example, a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor satisfies the required bulk c.continuing our example, the output capacitor needs: esr cout 1% ? 5v ? 1 ? 49.4% ( ) 5.3a = 4m w c out 5.3a 1% ? 5 ? 200khz = 600 f these electrical characteristics require paralleling several low esr capacitors possibly of mixed type. output voltage ripple waveform secondary current primary current i pri ?v cout 42681 f19 ringing due to esl i pri n ?v esr figure 19. typical flyback converter waveforms downloaded from: http:///
42681fc ltc4268-1 41 most capacitor ripple current ratings are based on 2000 hour life. this makes it advisable to derate the capacitor or to choose a capacitor rated at a higher temperature than required. one way to reduce cost and improve output ripple is to use a simple lc filter. figure 20 shows an example of the filter. the design of the filter is beyond the scope of this data sheet. however, as a starting point, use these general guidelines. start with a c out 1/4 the size of the nonfilter solution. make c 1 1/4 of c out to make the second filter pole independent of c out . c1 may be best implemented with multiple ceramic capacitors. make l1 smaller than the output inductance of the transformer. in general, a 0.1h filter inductor is sufficient. add a small ceramic capacitor ( c out2 ) for high frequency noise on v out . for those interested in more details refer to second-stage lc filter design, ridley, switching power magazine, july 2000 p8-10. circuit simulation is a way to optimize output capacitance and filters, just make sure to include the component parasitic. lt c switchercad ? is a terrific free circuit simulation tool that is available at www.linear.com. final optimization of output ripple must be done on a dedicated pc board. parasitic inductance due to poor layout can significantly impact ripple. refer to the pc board layout section for more details. isolation the 802.3 standard requires ethernet ports to be electrically isolated from all other conductors that are user accessible. this includes the metal chassis, other connectors and any auxiliary power connection. for pds, there are two common methods to meet the isolation requirement. if there will be any user accessible connection to the pd, then an isolated dc/dc converter is necessary to meet the isolation requirements. if user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the pd in an insulated housing. in all pd applications, there should be no user accessible electrical connections to the ltc4268-1 or support circuitry other than the rj-45 port. layout considerations for the ltc4268-1 the ltc4268-1s pd front end is relatively immune to layout problems. place c 14 ( figure 9) as close as physically possible to the ltc4268-1. place the series 10 resistor close to c 14. excessive parasitic capacitance on the r class pin should be avoided. include a pcb heat sink to which the exposed pad on the bottom of the package can be soldered. this heat sink should be electrically connected to gnd. for optimum thermal performance, make the heat sink as large as possible. voltages in a pd can be as large as C57 v for poe applications, so high voltage layout techniques should be employed. the shdn pin should be separated from other high voltage pins, like v portp , v out , to avoid the possibility of leakage shutting down the ltc4268-1. if not used, tie shdn to v portn . the load capacitor connected between v portp and v out of the ltc4268-1 can store significant energy when fully charged. the design of a pd must ensure that this energy is not inadvertently dissipated in the ltc4268-1. the polarity-protection diodes prevent an accidental short on the cable from causing damage. however if, v portn is shorted to v portp inside the pd while capacitor c1 is charged, current will flow through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4268-1. r load c out2 1f v out c out 470f c147f 3 from secondary winding l1 0.1h 42681 f20 + + figure 20. lc filter applications information downloaded from: http:///
ltc4268-1 42 42681fc in order to minimize switching noise and improve output load regulation, connect the gnd pin of the ltc4268-1 directly to the ground terminal of the v cc decoupling capacitor, the bottom terminal of the current sense resistor and the ground terminal of the input capacitor, using a ground plane with multiple vias. place the v cc capacitor immediately adjacent to the v cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. use a low esr ceramic capacitor. take care in pcb layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. these are typically the traces associated with the switches. this reduces the parasitic inductance and also minimizes magnetic field radiation. figure 21 outlines the critical paths . keep electric field radiation low by minimizing the length and area of traces ( keep stray capacitances low). the drain of the primary side mosfet is the worst offender in this category. always use a ground plane under the switcher circuitry to prevent coupling between pcb planes. check that the maximum bv dss ratings of the mosfets are not exceeded due to inductive ringing. this is done by viewing the mosfet node voltages with an oscilloscope. if it is breaking down either choose a higher voltage device, add a snubber or specify an avalanche-rated mosfet.place the small - signal components away from high frequency switching nodes. this allows the use of a pseudo - kelvin connection for the signal ground, where high di/ dt gate driver currents flow out of the ic ground pin in one direction ( to the bottom plate of the v cc decoupling capacitor) and small-signal currents flow in the other direction. keep the trace from the feedback divider tap to the fb pin short to preclude inadvertent pickup. for applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the ltc4268-1 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple and this could interfere with the ltc4268-1 operation. a few inches of pc trace or wire ( l @ 100nh) between the c in of the ltc4268-1 and the actual source v in is sufficient to prevent current sharing problems. t2 t1 c r c vin ms mp gate turn-on gate turn-on r sense ? ? c vcc sg v cc pg v cc v cc v cc v in gate turn-off gate turn-off q4q3 c out 42681 f21 out ? ? ? + + + figure 21. layout critical high current paths applications information downloaded from: http:///
42681fc ltc4268-1 43 typical application r ton 100k r class ? ? ? ? ? r sense 0.0151/8w 1% q3si4488dy q4 si4362dy r1091 r203.01k 1% r1329.4k 1% c18 22f 16v r920k 1/4w c19 0.1f d11bas21 r cmp 2.1k r endly 150k r27 10k c26 680pf r2810k r2215 r1547 r810 1/4w r210 r13b0540w t2 pa0184 d14 bat54 r17330 c osc 33pf c1a12f 100v c8 0.1f 100v d1 smaj58a c1b2.2f 100v c cmp 0.1f c333300pf c28 2200pf c23 4700pf 250vac q7 fmmt718 q6 fmmt618 c11 220pf c27 0.1f c24 1f c2147f 2 c22100f 3.3v4a l3 0.33h t1 pa1558nl 42681 ta02 t on r pgdly 15k pgdly v neg v neg v neg s2b c sfst 0. 033 f sync r class shdn sense C v cmp sense + r cmp endly osc sfst ltc4268-1 gnd sg v portp pwrgd uvlo pg v cc i lim_en fb c cmp pwrgd l2 4.7h l1 0.33h c7 1000pf 100v + + c6100f ? q2 si4488dy 11.8v0.27a c1022f 2 r310 1/4w c4 1500pf ? q1 si4470ey c547f 5v2.4a + + + + + 100k v portn v portn v portn 1614 15 1 r675 r144.7k r18 100k r2120k r5 75 c14 0.01f 200v r4 75 24v 30w aux power in j3 c13 0.01f 200v c15 0.01f 200v c16 0.01f 200v c44 0.001f 2kv r775 3 2 rx C 6 rx + 3 tx C 2 tx + j1 C54v in fromhigh power pse rj45 t3 eth1C230ld xfmr 17 8 5 4 11 9 10 68 7 tophy spare C spare + 0.1f 100v v portp d2 d3 d4 d5 d6 d7 d8 b2100x8 q5 fmmt723 10 d9 30w high efficiency triple output pd supply (order demo circuit dc1080a) downloaded from: http:///
ltc4268-1 44 42681fc note:1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) bottom viewexposed pad r = 0.115typ 0.20 0.05 1 16 17 32 6.00 ref 6.43 0.10 2.65 0.10 4.00 0.10 0.75 0.05 0.00 C 0.05 0.200 ref 7.00 0.10 (dkd32) qfn 0707 rev a 0.40 bsc recommended solder pad layout apply solder mask to areas that are not soldered 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer 6.43 0.05 2.65 0.05 0.70 0.05 0.40 bsc 6.00 ref 3.10 0.05 4.50 0.05 0.40 0.10 0.20 0.05 packageoutline r = 0.05 typ dkd package 32-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1734 rev a) package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
42681fc ltc4268-1 45 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 08/12 simplified overview section, including removal of figure 1a and 1b which caused renumbering of all figures in data sheet 13, 14 changed maximum power levels for class 0 and class 3 to 13.0w 15 added 10 resistor to v portp pin on schematic to make solution more robust to current surges 20, 43 added input capacitor, input series resistance and transient voltage supressor sections 21 added c14 and 10 resistor layout recommendation 41 (revision history begins at rev c) downloaded from: http:///
ltc4268-1 46 42681fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2007 lt 0812 rev c ? printed in usa part number description comments ltc4257-1 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classification dual current limit ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classification, autonomous operation or i 2 c control ltc4259a-1 quad ieee 802.3af power over ethernet controller ac or dc disconnect ieee-compliant pd detection and classification, autonomous operation or i 2 c control ltc4263 single ieee 802.3af power over ethernet controller ac or dc disconnect ieee-compliant pd detection and classification, autonomous operation or i 2 c control ltc4263-1 high power single pse controller internal switch, autonomous operation, 30w ltc4264 high power pd interface controller with 750ma current limit 750ma internal switch, programmable classification current to 75ma. precision dual current limit with disable. ltc4266 quad ieee 802.3at poe pse controller with programmable i cut / i lim , 2-event classification, and port current and voltage monitoring ltc4266a quad ltpoe++ pse controller provides up to 90w. backwards compatible with ieee 802.3af and ieee 802.3at pds. with programmable i cut / i lim , 2-event classification, and port current and voltage monitoring ltc4266c quad ieee 802.3af pse controller with programmable i cut / i lim , 1-event classification, and port current and voltage monitoring ltc4267 ieee 802.3af pd interface with an integrated switching regulator 100v 400ma internal switch, programmable classification, 200khz constant- frequency pwm , interface and switcher optimized for ieee-compliant pd system ltc4267-1 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, programmable class, 200khz constant-frequency pwm ltc4267-3 ieee 802.3af pd interface with an integrated switching regulator 100v 400ma internal switch, programmable classification, 300khz constant-frequency pwm , interface and switcher optimized for ieee-compliant pd system ltc4269-1 ieee 802.3af pd interface with integrated flyback switching regulator 2-event classification, programmable classification, synchronous no-opto flyback controller, 50khz to 250khz, aux support ltc4269-2 ieee 802.3af pd interface with integrated forward switching regulator 2-event classification, programmable classification, synchronous forward controller, 100khz to 500khz, aux support ltc4270/ltc4271 12-port poe/poe+/ltpoe++? pse controller transformer isolation, supports type 1,type 2 and ltpoe++ pds ltc4274 single ieee 802.3at poe pse controller with programmable i cut / i lim , 2-event classification, and port current and voltage monitoring ltc4274a single ltpoe++ pse controller provides up to 90w. backwards compatible with ieee 802.3af and ieee 802.3at pds. with programmable i cut / i lim , 2-event classification, and port current and voltage monitoring ltc4274c single ieee 802.3af pse controller with programmable i cut / i lim , 1-event classification, and port current and voltage monitoring ltc4278 ieee 802.3af pd interface with integrated flyback switching regulator 2-event classification, programmable classification, synchronous no-opto flyback controller, 50khz to 250khz, 12v auxiliary support related parts downloaded from: http:///

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