View 8P391208NLGIW_8835096.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ?2016 integrated device technology september 1, 2016 general description 8p391208 is intended to take 1 or 2 reference clocks, select between them, using a pin selection and generate up to 8 outputs that are the same as the reference frequency. 8p391208 supports two output banks, each with its own power supply. all outputs in one bank would generate the same output frequency, and each bank can be individually controlled for output type or output enable. the device can operate over the -40c to +85c temperature range. features ? two differential inputs support lvpecl, lvds, hcsl or lvcmos reference clocks ? accepts input frequencies ranging from 1pps (1hz) to 700mhz (up to 1ghz when configured into hcsl output mode at 3.3v) ? select which of the two input clocks is to be used as the reference clock for which bank via pin selection ? generates 8 differential outputs ? differential outputs selectable as lvpecl, lvds, cml or hcsl ? cml mode supports two different voltage swings ? differential outputs support frequencies from 1pps to 700mhz (up to 1ghz when configured into hcsl output mode at 3.3v) ? outputs arranged in 2 banks of 4 outputs each ? each bank supports a separate power supply of 3.3v, 2.5v or 1.8v ? controlled by 3-level input pins ? input mux selection control pin ? control inputs are 3.3v-tolerant for all core voltages ? output noise floor of -153dbc/hz @ 156.25mhz ? core voltage supply of 3.3v, 2.5v or 1.8v ? -40c to +85c ambient operating temperature ? lead-free (rohs 6) packaging 8p391208 datasheet low additive jitter 2:8 buffer with universal differential outputs
2 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 8p391208 block diagram qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 clk_sel clk1 nclk1 ioa logic clk0 nclk0 iob 2 2 pin assignment figure 1: 8p391208 pin assignment for 5mm x 5mm 32-pin vfqfn package nqb2 qb2 v ccob nqb1 qb1 nqb0 qb0 iob1 clk0 nclk0 nclk1 clk1 iob0 v cc v cc ioa0 nqa2 qa2 v ccoa nqa1 qa1 nqa0 qa0 ioa1 qa3 nqa3 nc v cc clk_sel nc nqb3 qb3 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8
3 ?2016 integrated device technology september 1, 2016 8p391208 datasheet pin description and characteristic tables table 1: pin description number name type [1] description 1 ioa1 input pullup / pulldown controls output functions for bank a. 3-level input. 2qa0 output positive differential clock output. included in bank a. ? refer to output drivers section for more details. 3nqa0 output negative differential clock output. included in bank a. ? refer to output drivers section for more details. 4qa1 output positive differential clock output. included in bank a. ? refer to output drivers section for more details. 5nqa1 output negative differential clock output. included in bank a. ? refer to output drivers section for more details. 6v ccoa power output voltage supply for output bank a. 7qa2 output positive differential clock output. included in bank a. ? refer to output drivers section for more details. 8nqa2 output negative differential clock output. included in bank a. ? refer to output drivers section for more details. 9qa3 output positive differential clock output. included in bank a. ? refer to output drivers section for more details. 10 nqa3 output negative differential clock output. included in bank a. ? refer to output drivers section for more details. 11 nc unused unused. do not connect. 12 v cc power core logic voltage supply. 13 clk_sel input pullup / pulldown input clock selection control pin. 3-level input. this pin?s function is described in the input selection section. 14 nc unused unused. do not connect. 15 nqb3 output negative differential clock output. included in bank b. refer to ? output drivers section for more details. 16 qb3 output positive differential clock output. included in bank b. refer to ? output drivers section for more details. 17 nqb2 output negative differential clock output. included in bank b. refer to ? output drivers section for more details. 18 qb2 output positive differential clock output. included in bank b. refer to ? output drivers section for more details. 19 v ccob power output voltage supply for output bank b. 20 nqb1 output negative differential clock output. included in bank b. refer to ? output drivers section for more details. 21 qb1 output positive differential clock output. included in bank b. refer to ? output drivers section for more details.
4 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 22 nqb0 output negative differential clock output. included in bank b. ? refer to output drivers section for more details. 23 qb0 output positive differential clock output. included in bank b. ? refer to output drivers section for more details. 24 iob1 input pullup / pulldown controls output functions for bank b. 3-level input. 25 clk1 input pulldown non-inverting differential clock input. 26 nclk1 input pullup / pulldown inverting differential clock input. v cc /2 when left floating (set by the internal pullup and pulldown resistors). 27 v cc power core logic voltage supply. 28 iob0 input pullup / pulldown controls output functions for bank b. 3-level input. 29 ioa0 input pullup / pulldown controls output functions for bank a. 3-level input. 30 v cc power core logic voltage supply. 31 nclk0 input pullup / pulldown inverting differential clock input. v cc /2 when left floating (set by the internal pullup and pulldown resistors). 32 clk0 input pulldown non-inverting differential clock input. ep v ee ground exposed pad must be connected to gnd. 1. pullup and pulldown refer to internal input resistors. see table 2 , pin characteristics, for typical values. table 1: pin description (continued) table 2: pin characteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf c pd power dissipation capacitance ? (per output pair) qa[0:3], nqa[0:3]; qb[0:3], nqb[0:3] lvpecl v ccox [1] = 3.465v or 2.625v 2.0 pf lvds pf cml, 400mv pf cml, 800mv pf lvpecl v ccox [1] = 1.89v 2.5 pf lvds pf cml, 400mv pf cml, 800mv pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? 1. v ccox refers to v ccoa for qa[3:0], nqa[3:0] or v ccob for qb[3:0], nqb[3:0].
5 ?2016 integrated device technology september 1, 2016 8p391208 datasheet principles of operation input selection the 8p391208 supports two input references: clk0 and clk1 that may be driven with differential or single-ended clock signals. e ither may be used as the source frequency for either or both output banks under control of the clk_sel input pin. output drivers the qa[0:3] and qb[0:3] clock outputs are provided with pin-controlled output drivers. the following table shows how each bank can be controlled. each bank is separately controlled and all outputs within a single bank will behave the same way. cml operation supports both a 400mv (pk-pk) swing and an 800mv (pk-pk) swing selection. the operating voltage ranges of each output is determined by its independent output power pin (v ccoa or v ccob ) and thus each can have different output voltage levels. output voltage levels of 1.8v, 2.5v or 3.3v are supported for differential operation . table 3: input selection control clk_sel description high banks a & b both driven from clk1 middle [1] 1. a ?middle? voltage level is defined in table 10 . leaving the input pin open will also generate this level via a weak internal resistor network. bank a driven from clk0 & bank b driven from clk1 low banks a & b both driven from clk0 table 4: output mode and enable control iox[1] iox[0] output bank function high high all outputs in the bank are high-impedance high middle all outputs in the bank are lvpecl high low all outputs in the bank are lvds middle high all outputs in the bank are cml (400mv) middle middle all outputs in the bank are high-impedance middle low all outputs in the bank are hcsl low high all outputs in the bank are cml (800mv) low middle all outputs in the bank are lvpecl low low all outputs in the bank are high-impedance
6 ?2016 integrated device technology september 1, 2016 8p391208 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage characteristics symbol parameter test conditions minimum typical maximum units table 5: absolute maximum ratings item rating supply voltage, v ccx [1] to gnd 1. v ccx denotes v cc , v ccoa , or v ccob . 3.6v inputs ioa[1:0], iob[1:0], clk_sel, clk0, nclk0, clk1, nclk1 -0.5v to 3.6v outputs, i o qa[0:3], nqa[0:3]; qb[0:3], nqb[0:3] continuous current surge current 40ma 60ma outputs, v o qa[0:3], nqa[0:3]; qb[0:3], nqb[0:3] -0.5v to 3.6v operating junction temperature 125c storage temperature, t stg -65c to 150c lead temperature (soldering, 10s) +260c table 6: power supply characteristics, v cc = v ccox [1] = 3.3v 5%, v ee = 0v, t a = -40c to +85c 1. note 1. v ccox denotes v ccoa , v ccob . v cc core supply voltage 3.135 3.3 3.465 v v ccox output supply voltage 3.135 3.3 3.465 v i cc core supply current all outputs configured for lvds logic levels; outputs unloaded 22 25 ma i ccox output supply current [2] 2. internal dynamic switching current at maximum f out is included. all outputs configured for lvds logic levels; outputs unloaded 139 157 ma table 7: power supply characteristics, v cc = v ccox [1] = 2.5v 5%, v ee = 0v, t a = -40c to +85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v ccox output supply voltage 2.375 2.5 2.625 v i cc core supply current all outputs configured for lvds logic levels; outputs unloaded 19 22 ma i ccox output supply current [2] all outputs configured for lvds logic levels; outputs unloaded 137 154 ma 1. note 1. v ccox denotes v ccoa , v ccob . 2. internal dynamic switching current at maximum f out is included.
7 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 8: power supply characteristics, v cc = v ccox [1] = 1.8v 5%, v ee = 0v, t a = -40c to +85c 1. note 1. v ccox denotes v ccoa , v ccob . symbol parameter test conditions minimum typical maximum units v cc core supply voltage 1.71 1.8 1.89 v v ccox output supply voltage 1.71 1.8 1.89 v i cc core supply current all outputs configured for lvds logic levels; outputs unloaded 15 17 ma i ccox output supply current [2] 2. internal dynamic switching current at maximum f out is included. all outputs configured for lvds logic levels; outputs unloaded 125 141 ma table 9: typical output supply current, v cc = 3.3v, 2.5v or 1.8v, v ee = 0v, t a = 25c symbol parameter [1] 1. internal dynamic switching current at maximum f out is included. test conditions v ccox [2] = 3.3v 2. v ccox denotes v ccoa , or v ccob . v ccox [2] = 2.5v v ccox [2] = 1.8v units lvpecl lvds hcsl cml (400mv) cml (800mv) lvpecl lvds hcsl cml (400mv) cml (800mv) lvpecl lvds hcsl cml (400mv) cml (800mv) i ccoa bank a output supply current outputs unloaded 50 66 41 33 33 49 65 37 31 31 43 28 31 27 27 ma i ccob bank b output supply current outputs unloaded 50 66 41 33 33 49 65 37 31 31 43 28 31 27 27 ma
8 ?2016 integrated device technology september 1, 2016 8p391208 datasheet dc electrical characteristics symbol parameter signals test conditions minimum typical maximum units , table 10: lvcmos/lvttl control / status signals dc characteristics for 3-level pins, v ee = 0v, t a = -40c to +85c v ih input high voltage clk_sel, ioa[1:0], iob[1:0] v cc = 3.3v 0.85*v cc 3.465 v v cc = 2.5v 0.85*v cc 2.625 v v cc = 1.8v 0.85*v cc 1.89 v v im input middle voltage [1] 1. for 3-level input pins, a mid-level voltage is used to select the 3 rd state. this voltage will be maintained by a weak internal pull-up / pull-down network for each pin to select this state if the pin is left open. it is recommended that any external resistor netwo rks used to select a middle-level input voltage be terminated to the device?s core v cc voltage level. clk_sel, ioa[1:0], iob[1:0] v cc = 3.3v 0.45*v cc 0.55*v cc v v cc = 2.5v 0.45*v cc 0.55*v cc v v cc = 1.8v 0.45*v cc 0.55*v cc v v il input low voltage clk_sel, ioa[1:0], iob[1:0], v cc = 3.3v -0.3 0.15*v cc v v cc = 2.5v -0.3 0.15*v cc v v cc = 1.8v -0.3 0.15*v cc v i ih input high current clk_sel, ioa[1:0], iob[1:0] v cc = v in = 3.465v or 2.625v or 1.89v 150 p a i im input middle current clk_sel, ioa[1:0], iob[1:0] v cc = 3.465v or 2.625v or 1.89v, v in = v cc /2 -10 10 p a i il input low current clk_sel, ioa[1:0], iob[1:0], v cc = 3.465v or 2.625v or 1.89v, v in = 0v -150 p a table 11: differential input dc characteristics, v cc = 3.3v5%, 2.5v5% or 1.8v5%, v ee = 0v, t a = -40c to +85c symbol parameter test conditions minimum typical maximum units i ih input high current clkx, nclkx [1] v cc = v in = 3.465v or 2.625v 150 p a i il input low current clkx [1] v cc = 3.465v or 2.625v, v in = 0v -5 p a nclkx [1] v cc = 3.465v or 2.625v, v in = 0v -150 p a v pp peak-to-peak voltage [2] 0.2 1.3 v v cmr common mode input voltage [2] , [3] v ee v cc -1.2 v 1. clkx denotes clk0, clk1. nclkx denotes nclk0, nclk1. 2. v il should not be less than -0.3v. v ih should not be higher than v cc. 3. common mode voltage is defined as the cross-point.
9 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 12: lvpecl dc characteristics, v cc = 3.3v5%, 2.5v5% or 1.8v5%, v ee = 0v, ? t a = -40c to +85c symbol parameter v ccox [1] = 3.3v5% 1. v ccox denotes v ccoa, v ccob. v ccox [1] = 2.5v5% v ccox [1] = 1.8v5% units min typ max min typ max min typ max v oh output ? high voltage [2] 2. outputs terminated with 50 ? to v ccox ? 2v when v ccox = 3.3v5% or 2.5v5%. outputs terminated with 50 ? to ground when v ccox = 1.8v5%. qx, nqx [3] 3. qx denotes qa0, qa1, qa2, qa3, qb0, qb1, qb2, qb3. nqx denotes nqa0, nqa1, nqa2, nqa3, nqb0, nqb1, nqb2, nqb3. v ccox - 1.3 v ccox - 0.8 v ccox - 1.35 v ccox - 0.9 v ccox - 1.50 v ccox - 0.9 v v ol output ? low voltage [2] qx, nqx [2] v ccox - 2 v ccox - 1.75 v ccox - 2 v ccox - 1.75 v ee 0.25 v table 13: lvds dc characteristics, v ccox [1] = 3.3v 5%, v ee = 0v, t a = -40c to +85c [1] 1. v ccox denotes v ccoa , v ccob . symbol parameter test conditions minimum typical maximum units v od differential output voltage qx, nqx [2] 2. qx denotes qa0, qa1, qa2, qa3, qb0, qb 1, qb2, qb3. ? nqx denotes nqa0, nqa1, nqa2, nqa3, nqb0, nqb1, nqb2, nqb3. terminated 100 ? across qx and nqx 195 480 mv ? v od v od magnitude change qx, nqx [2] 50 mv v os offset voltage qx, nqx [2] 1.1 1.375 v ? v os v os magnitude change qx, nqx [2] 50 mv table 14: lvds dc characteristics, v ccox [1] = 2.5v 5%, v ee = 0v, t a = -40c to +85c 1. v ccox denotes v ccoa , v ccob . symbol parameter test conditions minimum typical maximum units v od differential output voltage qx, nqx [2] 2. qx denotes qa0, qa1, qa2, qa3, qb0, qb 1, qb2, qb3. ? nqx denotes nqa0, nqa1, nqa2, nqa3, nqb0, nqb1, nqb2, nqb3. terminated 100 ? across qx and nqx 195 470 mv ? v od v od magnitude change qx, nqx [2] 50 mv v os offset voltage qx, nqx [2] 1.1 1.375 v ? v os v os magnitude change qx, nqx [2] 50 mv
10 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 15: lvds dc characteristics, v ccox [1] = 1.8v 5%, v ee = 0v, t a = -40c to +85c symbol parameter test conditions minimum typical maximum units v od differential output voltage qx, nqx [2] terminated 100 ? across qx and nqx 195 454 mv ? v od v od magnitude change qx, nqx [2] 50 mv v os offset voltage qx, nqx [2] 1.1 1.375 v ? v os v os magnitude change qx, nqx [2] 50 mv 1. v ccox denotes v ccoa, v ccob. 2. qx denotes qa0, qa1, qa2, qa3, qb0, qb 1, qb2, qb3. ? nqx denotes nqa0, nqa1, nqa2, nqa3, nqb0, nqb1, nqb2, nqb3. table 16: cml (400mv swing) dc characteristics, v cc = 3.3v 5%, 2.5v 5% or 1.8v 5%, ? v ccox [1] = 3.3v 5%, 2.5v 5% or 1.8v 5%, v ee = 0v, t a = -40c to +85c 1. v ccox denotes v ccoa, v ccob. symbol parameter test conditions minimum typical maximum units v oh output high voltage qx, nqx [2] 2. qx denotes qa0, qa1, qa2, qa3, qb0, qb 1, qb2, qb3. ? nqx denotes nqa0, nqa1, nqa2, nqa3, nqb0, nqb1, nqb2, nqb3. terminated with 50 ? to v ccox v ccox - 0.1 v ccox v v ol output low voltage qx, nqx [2] v ccox - 0.5 v ccox - 0.3 v v out output voltage swing qx, nqx [2] 300 500 mv table 17: cml (800mv swing) dc characteristics, v cc = 3.3v 5%, 2.5v 5% or 1.8v 5%, ? v ccox [1] = 3.3v 5%, 2.5v 5% or 1.8v 5%, v ee = 0v, t a = -40c to +85c 1. v ccox denotes v ccoa , v ccob . symbol parameter test conditions minimum typical maximum units v oh output high voltage qx, nqx [2] 2. qx denotes qa0, qa1, qa2, qa3, qb0, qb 1, qb2, qb3. ? nqx denotes nqa0, nqa1, nqa2, nqa3, nqb0, nqb1, nqb2, nqb3. terminated with 50 ? to v ccox v ccox - 0.1 v ccox v v ol output low voltage qx, nqx [2] v ccox - 0.95 v ccox - 0.7 v v out output voltage swing qx, nqx [2] 575 1000 mv table 18: hcsl dc characteristics, v cc = v ccoa = v ccob = 3.3v 5%, v ee = 0v, t a = 25c [1] , [2] 1. guaranteed by design and characterization, not 100% tested in production. 2. c l = 2pf, r s = 33.2 ? , r p = 49.9 ? symbol parameter test conditions minimum typical maximum units v oh output high voltage qx, nqx 475 900 mv v ol output low voltage qx, nqx -100 mv v out output voltage swing qx, nqx 475 900 mv
11 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 19: input frequency characteristics, v cc = 3.3v5%, 2.5v5% or 1.8v5%, v ee = 0v, ? t a = -40c to +85c symbol parameter test conditions minimum typical maximum units f in input frequency clkx, nclkx [1], [2] 1. clkx denotes clk0, clk1. nclkx denotes nclk0, nclk1. 2. input frequency is up to 1ghz when v cc /v ccox = 3.3v5% for hcsl output mode. 1hz 700mhz idc input duty cycle [3] 3. any deviation from a 50% duty cycle on the input may be reflected in the output duty cycle. 50 %
12 ?2016 integrated device technology september 1, 2016 8p391208 datasheet ac electrical characteristics symbol parameter [2] table 20: lvds, lvpecl, cml ac characteristics, v cc = 3.3v 5%, 2.5v 5% or 1.8v 5%, v ccox [1] = 3.3v 5%, 2.5v 5% or 1.8v 5%, v ee = 0v, t a = -40c to +85c 1. v ccox denotes v ccoa , v ccob . 2. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. test conditions [3] 3. tested for the following out frequencies: 100mhz, 156.25mhz, 312.5mhz, 700mhz. minimum typical maximum units f out output frequency lvds, lvpecl, cml 1pps 700 mhz t r / t f output rise and fall times lvpecl 20% to 80% 100 705 ps lvds 20% to 80%, v ccox = 3.3v 150 530 ps 20% to 80%, v ccox = 2.5v 165 530 ps 20% to 80%, v ccox = 1.8v 200 565 ps cml 400mv 20% to 80% 100 625 ps cml 800mv 20% to 80% 150 580 ps t sk (b) bank skew [4], [5], [6] 4. this parameter is guaranteed by characterization. not tested in production. 5. this parameter is defined in accordance with jedec standard 65. 6. defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. lvpecl [7] 7. measured at the output differential crosspoint. 55 ps lvds [7] 55 ps cml 400mv [7] 55 ps cml 800mv [7] 55 ps odc output duty cycle [8] 8. measured using 50% duty cycle on input reference. 45 50 55 % mux isol mux isolation 70 db t startup startup time 25 ms
13 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 21: hcsl ac characteristics, f out = 100mhz, v cc = 3.3v 5%, 2.5v 5% or 1.8v 5%, ? v ccox [1] = 3.3v 5%, 2.5v 5% or 1.8v 5%, v ee = 0v, t a = -40c to +85c 1. v ccox denotes v ccoa , v ccob . symbol parameter [2] 2. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. test conditions minimum typical maximum units v rb ring-back voltage margin [3], [4] 3. measurement taken from differential waveform. 4. t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100mv differential range. -100 100 mv t stable time before v rb is allowed [3] , [4] 500 ps v max absolute max. output voltage [5], [6] 5. measurement taken from single ended waveform. 6. defined as the maximum instantaneous voltage including overshoot. 1150 mv v min absolute min. output voltage [5] , [7] 7. defined as the minimum instantaneous voltage including undershoot. -300 mv v cross absolute crossing voltage [8], [9], [5] 8. measured at crossing point where the instantaneous voltage value of the rising edge of qx equals the falling edge of nqx. 9. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 200 550 mv ? v cross total variation of v cross over all edge [8] , [10], [5] 10.defined as the total variation of all crossing voltages of rising qx and falling nqx, this is the maximum allowed variance i n v cross for any particular system. 140 mv
14 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 22: hcsl electrical characteristics, current mode differential pair, v cc = v ccoa = v ccob = 3.3v5%, 2.5v 5% or 1.8v 5%, v ee = 0v, t a = -40c to +85c [1], [2] symbol parameter test conditions [3] , [4] minimum typical maximum units v oh output voltage high statistical measurement on single-ended signal using oscilliscope math function 300 950 mv v ol output voltage low -100 mv v max absolute max. output voltage [5], [6] 1150 mv v min absolute min. output voltage [5] , [7] -300 mv v cross absolute crossing voltage [5] , [8], [9] 150 550 mv ? v cross total variation of v cross over all edges [5] , [8] , [10] 140 mv edge rate rise rising edge rate [11], [12] 0.3 4.5 v/ns edge rate fall falling edge rate [11] , [12] 0.3 4.5 v/ns 1. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. 2. guaranteed by design and characterization, not 100% tested in production. 3. test configuration: c l = 2pf, r s = 33.2 ? , r p = 49.9 ?? 4. tested for the following out frequencies: 156.25mhz, 245.76mhz, 312.5mhz, and 625mhz. for other frequencies, contact idt marketing. 5. measurement taken from a single-ended waveform. 6. defined as the maximum instantaneous voltage including overshoot. 7. defined as the minimum instantaneous voltage including undershoot. 8. measured at crossing point where the instantaneous voltage value of the rising edge of clk+ equals the falling edge of clk-. 9. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 10.defined as the total variation of all crossing voltages of rising clk+ and falling clk-. this is the maximum allowed varianc e in vcross for any particular system. 11.measurement taken from a differential waveform. 12.measured from -150mv on the differential waveform (derived from q minus nq). the signal must be monotonic through the measur ement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossing. table 23: typical additive jitter, v cc = 3.3v 5%, 2.5v 5% or 1.8v 5%, v ccox [1] = 3.3v 5%, 2.5v 5%, 1.8v 5%, v ee = 0v, t a = -40c to +85c 1. v ccox denotes v ccoa , v ccob . symbol parameter test conditions [2] 2. all outputs configured for the specific output type, as shown in the table. minimum typical maximum units t jit (f) rms ? additive jitter (random) lvpecl f out = 156.25mhz, integration range: 12khz - 20mhz 62 fs lvds 82 fs hcsl 74 fs cml, 400mv 68 fs cml, 400mv 65 fs
15 ?2016 integrated device technology september 1, 2016 8p391208 datasheet applications information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos lvttl level control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional prot ection. a 1k ? resistor can be used. lvcmos 3-level i/o control pins these pins are 3-level pins and if left unconnected this is interpreted as a valid input selection option (middle). outputs: differential outputs all unused differential outputs can be left floating. it is recommended that there is no trace attached. lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential ou tput pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached.
16 ?2016 integrated device technology september 1, 2016 8p391208 datasheet wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 : applications, r3 and r4 can be 100 : . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than 1v/ns. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applica tions, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datashe et specifications are characterized and guaranteed by using a differential signal. figure 2: recommended schematic for wiring a differential input to accept single-ended levels
17 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 3.3v differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 3 to figure 7 show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termi nation requirements. for example, in figure 3 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3: clk/nclk input driven by an ? idt open emitter lvhstl driver figure 4: clk/nclk input driven by a ? 3.3v lvpecl driver figure 5: clk/nclk input driven by a ? 3.3v lvds driver figure 6: clk/nclk input driven by a ? 3.3v lvpecl driver figure 7: clk/nclk input driven by a ? 3.3v hcsl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input
18 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 2.5v differential clock input interface clkx/nclkx accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 8 to figure 12 show interface examples for the clkx/nclkx input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termi nation requirements. for example, in figure 8 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 8: clkx/nclkx input driven by an ? idt open emitter lvhstl driver figure 9: clkx/nclkx input driven by a ? 2.5v lvpecl driver figure 10: clkx/nclkx input driven by a ? 2.5v hcsl driver figure 11: clkx/nclkx input driven by a ? 2.5v lvpecl driver figure 12: clkx/nclkx input driven by a ? 2.5v lvds driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 2.5v lvhstl idt open emitter lvhstl driver differential input hcsl *r3 33 *r4 33 clk nclk 2.5v 2.5v zo = 50 zo = 50 differential input r1 50 r2 50 *optional C r3 and r4 can be 0
19 ?2016 integrated device technology september 1, 2016 8p391208 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 : and 132 : . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 : parallel resistor at the receiver and a 100 : differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds co mpliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 13 can be used with either type of output structure. figure 14 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termina tion, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since the se outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the outpu t. figure 13: standard lvds termination figure 14: lvds driver z o | z t lvds receiver c z t 2 z t 2 optional lvds termination lvds driver z o | z t z t lvds receiver
20 ?2016 integrated device technology september 1, 2016 8p391208 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are reco mmended only as guidelines. the differential output is a low impedance follower output that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 15 and figure 16 show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be rec ommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 15: 3.3v lvpecl output termination figure 16: 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? inp ut 3.3v 3 .3v + _
21 ?2016 integrated device technology september 1, 2016 8p391208 datasheet termination for 2.5v lvpecl outputs figure 17 and figure 18 show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to ? v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 18 can be eliminated and the termination is shown in figure 19 . figure 17: 2.5v lvpecl driver termination example figure 18: 2.5v lvpecl driver termination example figure 19: 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
22 ?2016 integrated device technology september 1, 2016 8p391208 datasheet recommended termination for hcsl outputs figure 20 is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this terminat ion is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 21 is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflec tions will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the o ptional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 20: recommended source termination (where the driver and receiver will be on separate pcbs) figure 21: recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
23 ?2016 integrated device technology september 1, 2016 8p391208 datasheet cml termination figure 22 shows an example of the termination for a cml driver. in this example, the transmission line characteristic impedance is 50 ? . the r1 and r2 50 ? matched load terminations are pulled up to v ddo. the matched loads are located close to the receiver. figure 22: cml termination example cml driv er zo = 50 zo = 50 r1 50 r2 50 vddo vddo
24 ?2016 integrated device technology september 1, 2016 8p391208 datasheet power dissipation and thermal considerations the 8p391208 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions is enabled. the 8p391208 device was designed and characterized to operate within the ambient industrial temperature range of ? t a = -40c to +85c. the ambient temperature represents the temperature around the device, not the junction temperature. when using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable junction temperature. extreme care must be taken to avoid exceeding 125c junction temperature. the power calculation examples below were generated using a maximum ambient temperature and supply voltage. for many applicatio ns, the power consumption will be much lower. please contact idt technical support for any concerns on calculating the power dissipatio n for your own specific configuration. power domains the 8p391208 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). figure 23 below indicates the individual domains and the associated power pins. figure 23: 8p391208 power domains
25 ?2016 integrated device technology september 1, 2016 8p391208 datasheet power consumption calculation determining total power consumption involves several steps: 1. determine the power consumption using maximum current values for core voltage from table 6 , table 7 , table 8 and table 9, page 7 for the appropriate case of how many banks or outputs are enabled. 2. determine the nominal power consumption of each enabled output path. a. this consists of a base amount of power that is independent of operating frequency, as shown in table 25 through table 36 (depending on the chosen output protocol). b. then there is a variable amount of power that is related to the output frequency. this can be determined by multiplying the o utput frequency by the fq_factor shown in table 25 through table 36 . 3. all of the above totals are then summed. thermal considerations once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature f or the device under the environmental conditions it will operate in. thermal conduction paths, air flow rate and ambient air temperatu re are factors that can affect this. the thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow o r via conduction into the pcb through the device pads (including the epad). thermal conduction data is provided for typical scenarios in table 42, page 36 . please contact idt for assistance in calculating results under other scenarios. table 24: ? ja vs. air flow table for a 32-lead 5mm x 5mm vfqfn ? ja vs. air flow meters per second 0 1 2 multi-layer pcb, jedec standard test boards 35.23c/w 31.6c/w 30.0c/w
26 ?2016 integrated device technology september 1, 2016 8p391208 datasheet current consumption data and equations table 25: 3.3v lvds output calculation table lvds fq_factor (ma/mhz) base_current (ma) bank a 0.07 30.0 bank b 0.07 30.0 table 26: 2.5v lvds output calculation table lvds fq_factor (ma/mhz) base_current (ma) bank a 0.07 26.0 bank b 0.07 26.0 table 27: 1.8v lvds output calculation table lvds fq_factor (ma/mhz) base_current (ma) bank a 0.06 38.0 bank b 0.06 38.0 table 28: 3.3v lvpecl output calculation table lvpecl fq_factor (ma/mhz) base_current (ma) bank a 0.04 22.0 bank b 0.04 22.0 table 29: 2.5v lvpecl output calculation table lvpecl fq_factor (ma/mhz) base_current (ma) bank a 0.04 21.0 bank b 0.04 21.0 table 30: 1.8v lvpecl output calculation table lvpecl fq_factor (ma/mhz) base_current (ma) bank a 0.04 20.0 bank b 0.04 20.0
27 ?2016 integrated device technology september 1, 2016 8p391208 datasheet table 31: 3.3v cml output (400mv) calculation table cml (400mv) fq_factor (ma/mhz) base_current (ma) bank a 0.02 19.0 bank b 0.02 19.0 table 32: 2.5v cml output (400mv) calculation table cml (400mv) fq_factor (ma/mhz) base_current (ma) bank a 0.02 16.0 bank b 0.02 16.0 table 33: 1.8v cml output (400mv) calculation table cml (400mv) fq_factor (ma/mhz) base_current (ma) bank a 0.02 15.0 bank b 0.02 15.0 table 34: 3.3v cml output (800mv) calculation table cml (800mv) fq_factor (ma/mhz) base_current (ma) bank a 0.02 19.0 bank b 0.02 19.0 table 35: 2.5v cml output (800mv) calculation table cml (800mv) fq_factor (ma/mhz) base_current (ma) bank a 0.02 16.0 bank b 0.02 16.0 table 36: 1.8v cml output (800mv) calculation table cml (800mv) fq_factor (ma/mhz) base_current (ma) bank a 0.02 15.0 bank b 0.02 15.0
28 ?2016 integrated device technology september 1, 2016 8p391208 datasheet applying the values to the following equation will yield output current by frequency: qx current (ma) = fq_factor * frequency (mhz) + base_current where: qx current is the specific output current according to output type and frequency fq_factor is used for calculating current increase due to output frequency base_current is the base current for each output path independent of output frequency the second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: t j = t a + (t ja * pd total ) where: t j is the junction temperature (c) t a is the ambient temperature (c) t ja is the thermal resistance value from table 42, page 36 , dependent on ambient airflow (c/w) pd total is the total power dissipation of the 8p391208 under usage conditions, including power dissipated due to loading (w) note that for lvpecl outputs the power dissipation through the load is assumed to be 27.95mw). example calculations circuit configuration frequency (mhz) v cco ? core supply current, i cc = 25ma (maximum) output supply current, bank a current = 0.07ma x 125mhz + 30ma = 38.75ma output supply current, bank b current = 0.07ma x 125mhz + 30ma = 38.75ma ? total device current = 25ma + 38.75ma + 38.75ma = 102.5ma ? total device power = 3.465v * 102.5ma = 355.2mw or 0.3552w with an ambient temperature of 85c and no airflow, the junction temperature is: t j = 85c + 35.23c/w * 0.3552w = 97.5c table 37: example 1 ? common customer configuration (3.3v core voltage) bank a lvds 125 3.3v bank b lvds 3.3v
29 ?2016 integrated device technology september 1, 2016 8p391208 datasheet lvds power considerations this section provides information on power dissipation and junction temperature for the 8p391208. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8p391208 is the sum of the core power plus the power dissipated in the load(s). ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v cc_max * i cc_max = 3.465v * 25ma = 86.625mw ? power (outputs) max = v cco_max * i cco_max = 3.465v * 157ma = 544.005mw ? total power_ max = 86.625mw + 544.005mw = 630.63mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 35.23c/w per table 38 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.631w *35.23c/w = 107.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 38: thermal resistance ? ja for 32-lead 5mm x 5mm vfqfn, forced convection ? ja by velocity meters per second 0 1 2 multi-layer pcb, jedec standard test boards 35.23c/w 31.6c/w 30.0c/w
30 ?2016 integrated device technology september 1, 2016 8p391208 datasheet lvpecl power considerations this section provides information on power dissipation and junction temperature for the 8p391208. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8p391208 is the sum of the core power plus the power dissipated in the load(s). ? the following is the power dissipation for v cc + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i cc_max = 3.465v * 128.1ma = 443.9mw ? power (outputs) max = 27.95mw/loaded output pair ? if all outputs are loaded, the total power is 8 * 27.95mw = 223.6mw ? total power_ max (3.465v, with all outputs switching) = 443.9w + 223.6mw = 667.5mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 35.23c/w per table 39 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.6675 w * 35.23c/w = 108.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 39: thermal resistance ? ja for 32-lead 5mm x 5mm vfqfn, forced convection ? ja by velocity meters per second 0 1 2 multi-layer pcb, jedec standard test boards 35.23c/w 31.6c/w 30.0c/w
31 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 24 . figure 24: v out v cco v cco - 2v q1 rl 50 lvpecl driver circuit and termination to calculate power dissipation per output pair due to loading, use the following equations which assume a 50 : load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.8v (v cco_max ? v oh_max ) = 0.8v ? for logic low, v out = v ol_max = v cco_max ? 1.75v (v cco_max ? v ol_max ) = 1.75v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_ma ? (v cco_ma ? 2v))/r l ] * (v cco_ma ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.8v)/50 : ] * 0.8v = 19.2mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_ma ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.75v)/50 : ] * 1.75v = 8.75mw total power dissipation per output pair = pd_h + pd_l = 2 7.95mw
32 ?2016 integrated device technology september 1, 2016 8p391208 datasheet hcsl power considerations this section provides information on power dissipation and junction temperature for the 8p391208. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8p391208 is the sum of the core power plus the power dissipated in the load(s). ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i cc_max = 3.465v * 23.60ma = 81.774mw ? power (outputs) max = 44.5mw/loaded output pair ? if all outputs are loaded, the total power is 8 * 44.5mw = 356.0mw ? total power_ max = 81.774mw + 356.0mw = 437.77mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 35.23c/w per table 40 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.4378w * 35.23c/w = 100.42c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 40: thermal resistance ? ja for 32-lead 5mm x 5mm vfqfn, forced convection ? ja by velocity meters per second 0 1 2 multi-layer pcb, jedec standard test boards 35.23c/w 31.6c/w 30.0c/w
33 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 25 . figure 25: v cco v out r l 50: ic x i out = 17ma r ref = 475 : 1% hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 : load to ground. the highest power dissipation occurs when v cco _ max . power= (v cco_max ? v out ) * i out , since v out ? i out * r l = (v cco_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 : ) * 17ma total power dissipation per output pair = 44 .5mw
34 ?2016 integrated device technology september 1, 2016 8p391208 datasheet cml power considerat ions (400mv - 800mv) this section provides information on power dissipation and junction temperature for the 8p391208. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8p391208 is the sum of the core power plus the power dissipation in the load(s). ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation in the load. ? power (core) max = v cc_max * i cc_max = 3.465v * 26.35ma = 91.30mw ? power (outputs) max = v cco_max * i cco_max = 3.465v * 68.66ma = 237.91mw ? if all outputs are loaded, the total power is 8 * 56.03mw = 448.24mw ? total power_ max (3.465v, with all outputs switching) = 91.30mw + 237.91mw + 448.24mw = 777.45mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 35.23c/w per table 41 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.777w * 35.23c/w = 112.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 41: thermal resistance ? ja for 32-lead 5mm x 5mm vfqfn, forced convection ? ja by velocity meters per second 0 1 2 multi-layer pcb, jedec standard test boards 35.23c/w 31.6c/w 30.0c/w
35 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 3. calculations and equations. the purpose of this section is to calculate the power dissipati on for the cml driver output pair. the cml output circuit and te rmination are shown in figure 26 . figure 26: cml driver (without built-in 50 : pullup) circuit and termination rl1 50 rl2 50 vcco q ic nq external loads i_load q1 v_output q2 to calculate worst case power dissipation due to the load, use the following equations. power dissipation when the output driver is logic low: pd_l = _load * v_output = (v out_max /r l) * (v cco_max ? v out_max ) = (1000mv/50 : ) * (3 .465v ? 1000mv) = 49.3mw power dissipation when the output driver is logic high: pd_h = i_load * v_output = (0.1v/50 : ) * (3 .465v ? 0.1v) = 6.73mw total power dissipation per output pair = pd_h + pd_l = 56 .03mw
36 ?2016 integrated device technology september 1, 2016 8p391208 datasheet reliability information table 42: ? ja vs. air flow table for a 32-lead 5mm x 5mm vfqfn transistor count the 8p391208 transistor count is: 6930 ? ja vs. air flow meters per second 0 1 2 multi-layer pcb, jedec standard test boards 35.23c/w 31.6c/w 30.0c/w
37 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 32-lead vfqfn package outline and package dimensions
38 ?2016 integrated device technology september 1, 2016 8p391208 datasheet 32-lead vfqfn package outline and package dimensions (continued)
39 ?2016 integrated device technology september 1, 2016 8p391208 datasheet ordering information part/order number marking package shipping packaging temperature 8p391208nlgi idt8p391208nlgi 32-lead vfqfn, lead free tray -40c to +85c 8p391208nlgi8 idt8p391208nlgi 32-lead vfqfn, lead free tape & reel, pin 1 orientation: eia-481-c -40c to +85c 8p391208nlgi/w idt8p391208nlgi 32-lead vfqfn, lead free tape & reel, pin 1 orientation: eia-481-d -40c to +85c table 43: pin 1 orientation in tape and reel packaging part number suffix pin 1 orientation illustration nlgi8 quadrant 1 (eia-481-c) nlgi/w quadrant 2 (eia-481-d) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes) user direction of feed correct pin 1 orientation carrier tape topside (round sprocket holes)
40 ?2016 integrated device technology september 1, 2016 8p391208 datasheet revision history revision date description of change september 1, 2016 initial final datasheet release.
disclaimer integrated device technology, inc. (idt) and its subsidiaries rese rve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of t he described products are determi ned in the independent state and are not guaranteed to perform the same way when installed in custom er products. the information c ontained herein is provided withou t representation or warranty of any kind, whether express or impli ed, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infringement of th e intellectual property rights of others. this docum ent is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone us ing an idt product in such a manner does so at their own risk, abs ent an express, written agreement by idt. integrated device technology, idt and the idt logo are register ed trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8p391208 datasheet

▲Up To Search▲

Price & Availability of 8P391208NLGIW

	To Download 8P391208NLGIW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .