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w25q256fv publication release date: february 11, 2015 preliminary - revision h 3v 256 m - bit serial flash memory with dual / quad spi & qpi
w25q256fv - 1 - table of contents 1. general descriptions ................................ ................................ ................................ ............. 5 2. feat ures ................................ ................................ ................................ ................................ ....... 5 3. package types and pi n configurations ................................ ................................ .......... 6 3.1 pad configuration wson 8x6 - mm ................................ ................................ ...................... 6 3.2 pad description wson 8x6 - mm ................................ ................................ .......................... 6 3.3 pin configuration soic 300 - mil ................................ ................................ ........................... 7 3.4 pin description soic 300 - mil ................................ ................................ ............................... 7 3.5 ball configuration tfbga 8x6 - mm (5x5 or 6x4 ball array) ................................ ................. 8 3.6 ball description tfbga 8x6 - mm ................................ ................................ ......................... 8 4. pin descriptions ................................ ................................ ................................ ........................ 9 4.1 chip select (/cs) ................................ ................................ ................................ .................. 9 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) ................................ .... 9 4.3 write protect (/wp) ................................ ................................ ................................ ............... 9 4.4 hold (/hold) ................................ ................................ ................................ ..................... 9 4.5 serial clock (clk) ................................ ................................ ................................ ................ 9 4.6 reset (/reset) ................................ ................................ ................................ .................... 9 5. block diagram ................................ ................................ ................................ .......................... 10 6. functional descripti ons ................................ ................................ ................................ ..... 11 6.1 spi / qpi operations ................................ ................................ ................................ .......... 11 6.1.1 standard spi instructions ................................ ................................ ................................ ..... 11 6.1.2 dual spi instructions ................................ ................................ ................................ ............ 11 6.1.3 quad spi instructions ................................ ................................ ................................ .......... 12 6.1.4 qpi instructions ................................ ................................ ................................ .................... 12 6.1.5 3 - byte / 4 - byte address modes ................................ ................................ ............................ 12 6.1.6 hold function ................................ ................................ ................................ ....................... 13 6.1.7 s oftware reset & hardware /reset pin ................................ ................................ ............. 13 6.2 write protection ................................ ................................ ................................ .................. 14 7. status and configura tion registers ................................ ................................ ............ 15 7.1 status registers ................................ ................................ ................................ ................. 15 7.1.1 erase/write in progress (busy) C status only ................................ ................................ .... 15 7.1.2 writ e enable latch (wel) C status only ................................ ................................ .............. 15 7.1.3 block protect bits (bp3, bp2, bp1, bp0) C volatile/non - volatile writable ........................... 16 7.1.4 to p/bottom block protect (tb) C volatile/non - volatile writable ................................ ........... 16 7.1.5 complement protect (cmp) C volatile/non - volatile writable ................................ ............... 16 7.1.6 status register protect (srp 1, srp0 ) C volatile/non - volatile writable .............................. 16 7.1.7 erase/program suspend status (sus) C status only ................................ .......................... 17 7.1.8 security register lock bits (lb3, lb2, lb1) C volatile/non - volatile otp writable .............. 17
w25q256fv publication release date: february 11, 2015 - 2 - preliminary C revision h 7.1.9 quad enable ( qe ) C volatile/non - volatile writable ................................ .............................. 17 7.1.10 current address mode (ads) C status only ................................ ................................ ...... 18 7.1.11 power - up address mode (adp) C non - volatile writable ................................ ................... 18 7.1.12 write protect selection (wps) C volatile/non - volatile writable ................................ ......... 18 7.1.13 output driver strength (drv1, drv0) C volatile/non - volatile writable ............................. 19 7.1.14 hold or /reset pin function (hold/rst) C volatile/non - volatile writable ................... 19 7.1.15 reserved bits C non functional ................................ ................................ ......................... 19 7.1.16 w25q256fv status register memory protection (wps = 0, cmp = 0) ............................. 20 7.1.17 w25q256fv status register memory protection (wps = 0, cmp = 1) ............................. 21 7.1.18 w25q256fv individual block memory protection (wps=1) ................................ .............. 22 7.2 extended address register C volatile writable only ................................ ......................... 23 8. instructions ................................ ................................ ................................ ............................. 24 8.1 device id and instruction set tables ................................ ................................ ................. 24 8.1.1 manufacture r and device identification ................................ ................................ ................ 24 8.1.2 instruction set table 1 (standard/dual/quad spi, 3 - byte & 4 - byte address mode) (1) ......... 25 8.1.3 instruction set table 2 (standard/dual/quad spi instructions, 3 - byte address mode) (1) .... 26 8.1.4 instruction set table 3 (standard/dual/quad spi instructions, 4 - byte address mode) (1) .... 27 8.1.5 instruction set table 4 (qpi instructions, 3 - byte & 4 - byte address mode) (14) ...................... 28 8.1.6 instruction set table 5 (qpi instructions, 3 - byte address mode) (14) ................................ .... 29 8.1.7 instruction set table 6 (qpi instructions, 4 - byte address mode) (14) ................................ .... 29 8.2 instruction descript ions ................................ ................................ ................................ ...... 31 8.2.1 write enable (06h) ................................ ................................ ................................ ............... 31 8.2.2 write enable for volatile status register (50h) ................................ ................................ .... 31 8.2.3 write disable (04h) ................................ ................................ ................................ ............... 32 8.2.4 read status register - 1 (05h), status register - 2 ( 3 5h) & status register - 3 (15h) ............... 32 8.2.5 write status register - 1 (01h), status register - 2 ( 3 1h) & status register - 3 (11h) ............... 33 8.2.6 read extended address register (c8h) ................................ ................................ .............. 36 8.2.7 write extended address register (c5h) ................................ ................................ ............... 37 8.2.8 enter 4 - byte address mode (b7h) ................................ ................................ ........................ 38 8.2.9 exit 4 - byte address mode (e9h) ................................ ................................ .......................... 38 8.2.10 read data (03h) ................................ ................................ ................................ ................. 39 8.2.11 read data with 4 - byte address (13h) ................................ ................................ ................ 40 8.2.12 fast read (0bh) ................................ ................................ ................................ ................. 41 8.2.13 fast read with 4 - byte address (0ch) ................................ ................................ ................ 43 8.2.14 fast read dual output (3bh) ................................ ................................ ............................. 44 8.2.15 fast read dual output with 4 - byte address (3ch) ................................ ............................ 45 8.2.16 fast read quad output (6bh) ................................ ................................ ............................ 46 8.2.17 fast read quad output with 4 - byte address (6ch) ................................ ........................... 47 8.2.18 f ast read dual i/o (bbh) ................................ ................................ ................................ ... 48 8.2.19 f ast read dual i/o with 4 - byte address (bch) ................................ ................................ .. 50 8.2.20 fast read quad i/o (ebh) ................................ ................................ ................................ . 52 8.2.21 fast read quad i/ o with 4 - byte address (ech) ................................ ................................ 55
w25q256fv - 3 - 8.2.22 word read quad i/o (e7h) ................................ ................................ ................................ 57 8.2.23 octal word read quad i/o (e3h) ................................ ................................ ....................... 59 8.2.24 set burst with wrap (77h) ................................ ................................ ................................ .. 61 8.2.25 page program (02h) ................................ ................................ ................................ ........... 62 8.2.26 quad input pa ge program ( 3 2h) ................................ ................................ ........................ 64 8.2.27 sector erase (20h) ................................ ................................ ................................ ............. 65 8.2.28 32kb block erase (52h) ................................ ................................ ................................ ..... 66 8.2.29 64kb block erase (d8h) ................................ ................................ ................................ ..... 67 8.2.30 chip erase (c7h / 60h ) ................................ ................................ ................................ ....... 68 8.2.31 erase / program suspend (75h) ................................ ................................ ......................... 69 8.2.32 erase / program resume (7ah) ................................ ................................ ......................... 71 8.2.33 power - down (b9h) ................................ ................................ ................................ .............. 72 8. 2.34 release power - down / device id (abh) ................................ ................................ ............. 73 8.2.35 read manufacturer / device id (90h) ................................ ................................ ................. 75 8.2.36 read manufacturer / device id dual i/o (92h) ................................ ................................ ... 76 8.2.37 read manufacturer / device id quad i/o (94h) ................................ ................................ . 77 8.2.38 read unique id number (4bh) ................................ ................................ .......................... 78 8.2.39 read jedec id (9fh) ................................ ................................ ................................ ........ 79 8.2.40 read sfdp register (5ah) ................................ ................................ ................................ 80 8.2.41 erase sec urity registers (44h) ................................ ................................ ........................... 81 8.2.42 program security registers (42h) ................................ ................................ ...................... 82 8.2.43 read security registers (48h) ................................ ................................ ........................... 83 8.2.44 set read parameters (c0h) ................................ ................................ ............................... 84 8.2.45 burst read with wrap (0ch) ................................ ................................ ............................... 85 8.2.46 ente r qpi mode (38h) ................................ ................................ ................................ ........ 86 8.2.47 exit qpi mode (ffh) ................................ ................................ ................................ .......... 87 8.2.48 individual block/sector lock (36h) ................................ ................................ ..................... 88 8.2.49 individual block/sector unlock (39h) ................................ ................................ .................. 89 8.2.50 read block/sector lock (3dh) ................................ ................................ ........................... 90 8.2.51 glob al block/sector lock (7eh) ................................ ................................ .......................... 91 8.2.52 global block/sector unlock (98h) ................................ ................................ ....................... 91 8.2.53 enable reset (66h) and reset device (99h) ................................ ................................ ...... 92 9. electrical character istics ................................ ................................ .............................. 93 9.1 absolute maximum ratings (1) (2) ................................ ................................ ...................... 93 9.2 operating ranges ................................ ................................ ................................ .............. 93 9.3 power - up timing and write inhibit threshold ( 1 ) ................................ ............................... 94 9.4 dc electrical characteristics ................................ ................................ .............................. 95 9.5 ac measurement conditions ( 1 ) ................................ ................................ ......................... 96 9.6 ac electrical characteristics (6) ................................ ................................ ........................... 97 9.7 serial output timing ................................ ................................ ................................ ........... 99 9.8 serial input timing ................................ ................................ ................................ .............. 99
w25q256fv publication release date: february 11, 2015 - 4 - preliminary C revision h 9.9 hold timing ................................ ................................ ................................ ...................... 99 9.10 wp timing ................................ ................................ ................................ .......................... 99 10. package specificatio ns ................................ ................................ ................................ ..... 100 10.1 8 - pad wson 8x6 - mm (package code e) ................................ ................................ ....... 100 10.2 16 - pin soic 300 - mil (package code f) ................................ ................................ .......... 102 10.3 24 - ball tfbga 8x6 - mm (package code b, 5x5 - 1 ball array) ................................ ......... 103 10.4 24 - ball tfbga 8x6 - mm (package code c, 6x4 ball array) ................................ ............ 104 11. ordering information ................................ ................................ ................................ ........ 105 11.1 valid part numbers and top side marking ................................ ................................ ...... 106 12. revision history ................................ ................................ ................................ .................... 107
w25q256fv - 5 - 1. general description s the w25q256fv ( 256 m - bit) serial flash memory provide s a storage solution for systems with limited space, pins and power. the 25 q series offers flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly from d ua l/quad spi (xip ) and storing voice, text and data. the device operate s on a single 2.7 v to 3.6 v power supply with current consumption as low as 4 ma active and 1a for power - down. all devices are of fered in space - saving packages. the w25q256fv array is organized into 131 , 072 programmable pages of 256 - bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 ( 4kb sector erase), groups of 128 (32kb block erase), groups of 256 ( 64kb block erase) or the entire chip (chip erase). the w25q256fv has 8 , 192 erasable sector s and 512 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w25q256fv support the standard serial peripheral interface (spi), dual/quad i/o spi as well as 2 - clocks instruction cycle quad peripheral interface (qpi) : serial clock, chip select, serial data i/o 0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold) . spi clock frequencies of up to 104 mhz are supported allowing equivalent clock rates of 208 mhz ( 1 04 mhz x 2) for dual i/o and 416 mhz ( 104 mhz x 4) for quad i/o when us ing the fast read dual/quad i/o instructions. these transfer rates can outperform standard asynchronous 8 and 16 - bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8 - clocks of instruction - overhead to read a 24 - bit address, allowing true xip ( execute in place) operation. a hold pin, write protect pin and programmable write protect ion, with top or bottom array control , provide further cont rol flexibility. additionally, the device supports jedec standard manufacturer and device id and sfdp register , a 64 - bit unique serial number and three 256 - bytes security registers . 2. features ? new family of spiflash memories C w25q256fv: 256m - bit / 32m - byte C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 C 3 or 4 - byte addressing mode C software & hardware reset ? highest performance serial flash C 104 mhz standard/dual/quad spi clo cks C 208 / 416 mhz equivalent dual/quad spi C 50 mb/s continuous data transfer rate C more than 100,000 erase/program cycles C more than 20 - year data retention ? efficien t continuous read C continuous read with 8/16/32/64 - byte wrap C as few as 8 clocks to add ress memory C quad peripheral interface (qpi) reduces instruction overhead C allows true xip (execute in place) operation C outperforms x16 parallel flash ? low power, wide temperature range C single 2.7 to 3.6v supply C 4ma active current, <1a power - down ( typ.) C - 40c to +85c operating range ? flexible architecture with 4kb sectors C uniform sector/block erase (4k/32k/64k - byte ) C program 1 to 256 byte per programmable page C erase/program suspend & resume ? advanced security features C software and hardware w rite - protect C power supply lock - down and otp protection C top/bottom, c omplement array protection C individual block/sector array protection C 64 - bit unique id for each device C discoverable parameters (sfdp) register C 3 x256 - bytes security registers with otp locks C volatile & non - volatile status register bits ? space efficient packaging C 8 - pad wson 8x6 - mm C 16 - pin soic 300 - mil (additional /reset pin) C 24 - ball tfbga 8x6 - mm C contact winbond for kgd and other options
w25q256fv publication release date: february 11, 2015 - 6 - preliminary C revision h 3. package types and pi n configurations w 25q256fv is offered in an 8 - pad wson 8x6 - mm (package code e), a 16 - pin soic 300 - mil (package code f) and two 24 - ball 8x6 - mm tfbga (package code b & c) packages as shown in figure 1a - c respectively. package diagrams and dimensions are illustrated at the end of this datasheet. 3.1 pad configuration wson 8x6 - mm figure 1 a. w25q256fv pad assignments, 8 - pad wson 8x6 - mm (package code e) 3.2 pad description wson 8x6 - mm pad no. pad name i/o function 1 /cs i chip select input 2 do (io1) i/ o data output ( data input outp ut 1) (1) 3 /wp (io2) i /o write protect input ( data input output 2) (2) 4 gnd ground 5 di (io0) i/o data input ( data input output 0) (1) 6 clk i serial clock input 7 /hold or /reset (io3) i /o hold or reset input (data input output 3) (2) 8 vcc power s upply notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, /wp & /hold (or /reset) functions are only available for standard/dual spi. 1 2 3 4 / cs do ( io 1 ) / wp ( io 2 ) gnd vcc / hold or / reset ( io 3 ) di ( io 0 ) clk top view 8 7 6 5
w25q256fv - 7 - 3.3 pin configuration soic 300 - mil figure 1b. w25q2 56fv pin assignments, 16 - pin soic 300 - mil (package code f) 3.4 pin description soic 300 - mil pin no. pin name i/o function 1 /hold (io3) i /o hold input (data input output 3) (2) 2 vcc power supply 3 /reset i reset input (3) 4 n/c no connect 5 n/c no conne ct 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/ o data output (data input output 1) (1) 9 /wp (io2) i /o write protect input (data input output 2) (2) 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no conn ect 15 di (io0) i /o data input (data input output 0) (1) 16 clk i serial clock input notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, /wp & /hold (or /reset) functions are only avail able for standard/dual spi. 3. t he /reset pin on soic - 16 package is independent of the hold/rst bit and qe bit settings in the status register. this pin can be treated as no connect in the system if reset function is not needed 1 2 3 4 / cs do ( io 1 ) / wp ( io 2 ) gnd vcc / hold ( io 3 ) di ( io 0 ) clk top view nc / reset nc nc nc nc nc nc 5 6 7 8 10 9 11 12 13 14 15 16
w25q256fv publication release date: february 11, 2015 - 8 - preliminary C revision h 3.5 ball configuration tfbga 8x6 - mm (5x5 or 6x4 ball array) figure 1c. w25q256fv ball assignments, 24 - ball tfbga 8x6 - mm (package code b & c) 3.6 ball description tfbga 8x6 - mm ball no. pin name i/o function b2 clk i serial clock input b3 gnd ground b4 vcc power supply c2 /cs i ch ip select input c4 /wp (io2) i /o write protect input (data input output 2) (2) d2 do (io1) i/ o data output (data input output 1) (1) d3 di (io0) i /o data input (data input output 0) (1) d4 /hold or /reset (io3) i /o hold or reset input (data input output 3 ) (2) multiple nc no connect notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, /wp & /hold (or /reset) functions are only available for standard/dual spi. d 1 / h o l d ( i o 3 ) / r e s e t d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c f 1 n c n c n c f 2 f 3 f 4 n c a 1 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e c d 1 / h o l d ( i o 3 ) / r e s e t d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c b 5 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e b c 5 n c d 5 n c e 5 n c a 5 n c
w25q256fv - 9 - 4. pin descriptions 4.1 chip selec t (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do, or io0, io1, io2, io3) pins are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power - up, /cs must transition from high to low before a new instruction will be accepted. the /cs input must track the vcc supply level at power - up (see write protection and figure 5 8). if needed a pull - up resister on the /cs pin can be used to accomplish this. 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) the w25q256fv supports standard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write instruction s, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual and quad spi instructions use the bidi rectional io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. quad spi instructions require the non - volatile quad enable bit (qe) in status re gister - 2 to be set. when qe=1, the /wp pin becomes io2 and /hold pin becomes io3. 4.3 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protect (cmp, tb, bp3, bp2, bp1 and bp0) bits and status register protect (srp) bits, a portion as small as a 4kb sector or the entire memory array can be hardware protected. the /wp pin is active low. when the qe bit of status register - 2 is set for quad i/o, the /wp pin function is not available since this pin is used for io2. see figure 1a - c for the pin configuration of quad i/o operation. 4.4 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (dont care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. the /hold pin is active low. when the qe bit of status register - 2 is set for quad i/o, the /hold pin function is not available since this pin is used for io3. see figure 1a - c for the pin configuration of quad i/o operation. 4.5 serial clock (clk) the spi seri al clock input (clk) pin provides the timing for serial input and output operations. ("see spi operations") 4.6 reset (/reset) the /reset pin allows the device to be reset by the controller. for 8 - pin packages, when qe=0, the io3 pin can be configured either a s a /hold pin or as a /reset pin depending on status register setting. when qe=1, the /hold or /reset function is not available for 8 - pin configuration.
w25q256fv publication release date: february 11, 2015 - 10 - preliminary C revision h 5. block diagram figure 2. w25q256fv serial flash m emory block diagram 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256 - byte page buffer beginning page address ending page address w25q256fv spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) or reset /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 0000ff00h 0000ffffh ? block 0 (64kb) ? 00000000h 000000ffh ? ? ? 007fff00h 007fffffh ? block 127 (64kb) ? 007f0000h 007f00ffh 0080ff00h 0080ffffh ? block 128 (64kb) ? 00800000h 008000ffh ? ? ? 00ffff00h 00ffffffh ? block 255 (64kb) ? 00ff0000h 00ff00ffh 0100ff00h 0100ffffh ? block 256 (64kb) ? 01000000h 010000ffh ? ? ? 01ffff00h 01ffffffh ? block 511 (64kb) ? 01ff0000h 01ff00ffh
w25q256fv - 11 - 6. functional descripti on s 6.1 spi / qpi operations figure 3. w25q256fv serial flash memory operation diagram 6.1.1 standard spi instructions the w25q256fv is accessed through an spi compatible bus consisting of four s ignals: serial clock (clk), chip select ( /cs ), serial data input ( di ) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device on the rising edge of clk . the do output pin i s used to read data or status from the device on the falling edge of clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 , the clk signal is normally low on the falling and rising edges of /cs. for mode 3 , the clk signal is normally high on the falling and rising edges of /cs . 6.1.2 dual spi instructions th e w25q256fv support s dual spi operation when using instructions such as fast read dual output (3bh) and fast read dual i/o (bbh) . th ese instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial fl ash devices. the dual spi read i nstruction s are ideal for quickly downloading code to ram upon power - up (code - shadowing) or for execut ing non - speed - power up adp bit value 3 - byte address standard spi dual spi quad spi enable 4 - byte ( b 7 h ) 4 - byte address qpi 4 - byte address standard spi dual spi quad spi 3 - byte address qpi disable 4 - byte ( e 9 h ) enable 4 - byte ( b 7 h ) disable 4 - byte ( e 9 h ) enable qpi ( 38 h ) enable qpi ( 38 h ) disable qpi ( ffh ) disable qpi ( ffh ) spi reset ( 66 h + 99 h ) qpi reset ( 66 h + 99 h ) adp = 0 adp = 1 device initialization & status register refresh ( non - volatile cells ) hardware reset hardware reset
w25q256fv publication release date: february 11, 2015 - 12 - preliminary C revision h critical code directly from the spi bus (xip) . when using dual spi instructions , the di and do pins become b idirectional i/ o pins: io0 and io1. 6.1.3 quad spi instructions the w25q256fv supports quad spi operation whe n using instructions such as fast read quad output (6bh) , fast read quad i/o (ebh) , word read quad i/o (e7h) and octal word read quad i/o (e3h) . these instructions allow data to be transferred to or from the device four to six times the rate of ordinary serial flash. the quad read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code - shadowin g to ram or execution directly from the spi bus (xip) . when using quad spi instructions the di and do pins become bidirectional io0 and io1 , and the /wp and /hold pins become io2 and io3 respectively. quad spi instructions require the non - volatile quad ena ble bit (qe) in status register - 2 to be set . 6.1.4 qpi instructions the w25q256fv supports quad peripheral interface (qpi) operations only when the device is switched from standard/dual/quad spi mode to qpi mode using the enter qpi (38h) instruction. the typic al spi protocol requires that the byte - long instruction code being shifted into the device only via di pin in eight serial clocks. the qpi mode utilizes all four io pins to input the instruction code, thus only two serial clocks are required. this can sign ificantly reduce the spi instruction overhead and improve system performance in an xip environment. standard/dual/quad spi mode and qpi mode are exclusive. only one mode can be active at any given time. enter qpi (38h) and exit qpi (ffh) instructions a re used to switch between these two modes. upon power - up or after a software reset using reset (99h) instruction, the default state of the device is standard/dual/quad spi mode. to enable qpi mode, the non - volatile quad enable bit (qe) in status register - 2 is required to be set. when using qpi instructions, the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3 respectively. see figure 3 for the device operation modes. 6.1.5 3 - byte / 4 - byte address modes the w25q256fv provides two address modes that can be used to specify any byte of data in the memory array. the 3 - byte address mode is backward compatible to older generations of serial flash memory that only support up to 128m - bit data. to address the 256m - bit or more data in 3 - byte address mode , extended address register must be used in addition to the 3 - byte addresses . 4 - byte address mode is designed to support serial flash memory devices from 256m - bit to 32g - bit. the extended address register is not necessary when th e 4 - byte address mode is enabled. upon power up, the w25q256fv can operate in either 3 - byte address mode or 4 - byte address mode, depending on the non - volatile status register bit ad p (s17) setting. if ad p =0, the device will operate in 3 - byte address mode; if ad p =1, the device will operate in 4 - byte address mode. the factory default value for ad p is 0. to switch between the 3 - byte or 4 - byte address modes, enter 4 - byte mode (b7h) or exit 4 - byte mode (e9h) instructions must be used. the current address mod e is indicated by the status register bit ad s (s16).
w25q256fv - 13 - 6.1.6 hold function for standard spi and dual spi operations, t he /hold signal allows the w25q256fv operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the i nstruction and the data in the buffer so programming can resume where it left off once the bus is available again. the /hold function is only available for standard spi and dual spi operation, not during quad spi. the quad enable bit qe in status register - 2 is used to determine if the pin is used as /hold pin or data i/o pin. when qe=0 (factory default), the pin is /hold, when qe=1, the pin will become an i/o pin, /hold function is no longer available. to initiate a /hold condition, the device must be selec ted with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will termina te on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, a nd se rial data input (di ) and serial clock (clk) are ignored. the chip select ( /cs ) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the internal logic state of the device. 6.1.7 software reset & hardware / reset pin t he w25q 256 fv can be reset to the initial power - on state by a software reset sequence, either in spi mode or qpi mode. this sequence must include two consecutive commands: enable reset (66h) & reset (99h). if the command sequence is successfully accepted, t he device will take approximately 30us ( t rst ) to reset. no command will be accepted during the reset period. for the wson - 8 and tfbga package types, w25q 256 fv can also be configured to utilize a hardware /reset pin. the hold/rst bit in the status register - 3 is the configuration bit for /hold pin function or reset pin function. when hold/rst=0 (factory default), the pin acts as a /hold pin as described above; when hold/rst=1, the pin acts as a /reset pin. drive the /reset pin low for a minimum period of ~1us (treset*) will reset the device to its initial power - on state. any on - going program/erase operation will be interrupted and data corruption may happen. while /reset is low, the device will not accept any command input. if qe bit is set to 1, the /hold or /reset function will be disabled, the pin will become one of the four data i/o pins. hardware /reset pin has the highest priority among all the input signals. drive /reset low for a minimum period of ~1us (treset*) will interrupt any on - going external/int ernal operations, regardless the status of other spi signals (/cs, clk, ios, /wp and/or /hold). note: while a faster /reset pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operatio n.
w25q256fv publication release date: february 11, 2015 - 14 - preliminary C revision h 6.2 w rite p rotection applications that use non - volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern , the w25q256fv provides several means to protect the data from inadvertent writes. ? device resets when vcc is below threshold ? time delay write disable after power - up ? write enable/disable instructions and a ut omatic write disable after e rase or program ? software and hardware (/wp pin) write p r otecti on using status registers ? additional individual block/sector locks for array protection ? write protection using power - down instruction ? lock down write protection for status register until the next power - up ? one time program (otp) write protection for array and security register s using status register * * note : this feature is available upon special order. please contact winbond for details. upon power - up or at power - down , the w25q256fv will maintain a reset condition while vcc is below the threshold value of v wi , (see power - up timing and voltage levels and figure 43 ). while reset, all operations are disabled and no instructions are recognized. during power - up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disable d for a time delay of t puw . this includes the write enable, page program, sector erase, block erase, chip erase and the write status register instructions. note that the chip select pin ( /cs ) must track the vcc supply level at power - up until the vcc - min le vel and t vsl time delay is reached. after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, bl ock erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write - disabled state of 0. software controlled write protection i s facilitated using the write status register instruction and setting the status register protect (srp 0, srp1 ) and block protect ( cmp , tb, bp [ 3 :0] ) bits. these settings allow a portion or the entire memory array to be configured as read only. used in conju nction with the write protect ( /wp ) pin, changes to the status register can be enabled or disabled under hardware control. see status register section for further information. additionally, the power - down instruction offers an extra level of write protecti on as all instructions are ignored except for the release power - down instruction. the w25q256fv also provides another write protect method using the individual block locks. each 64kb block (except the top and bot tom blocks , total of 510 blocks ) and each 4k b sector within the top/bottom blocks (total of 32 sectors) are equipped with an individual block lock bit. when the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, erase or program commands issu ed to the corresponding sector or block will be ignored. when the device is powered on, all individual block lock bits will be 1, so the entire memory array is protected from erase/program. an individual block unl ock (39h) instruction must be issued to u nlock any specific sector or block. the wps bit in status register - 3 is used to decide which write protect scheme should be used. when wps=0 (factory default), the device will only utilize cmp, tb, bp[3:0] bits to protect specific areas of the arra y; when wps=1, the device will utilize the individual block locks for write protection.
w25q256fv - 15 - 7. status and configuration registers three status and configuration registers are provided for w25q256fv. the read status register - 1/ 2 /3 instruction s can be used to provide sta t us on the availability of the flash memory array, whether the device is write enabled or disabled, t he state of write protection , quad spi s e tting , se curity register lock status, erase/program suspend status , output driver strength, power - up and current a ddress mode . the write status register instruction can be used to configure the device write protection features , quad spi sett i ng , security register otp lock s, hold/reset functions, output driver strength and power - up address mode . write access to the st atus register is controlled by the state of the non - volatile s tatus register protect bits (srp 0, srp1 ) , the write enable instruction, and during standard/dual spi operations, the /wp pin . 7.1 status registers figure 4 a . status register - 1 7.1.1 erase/write in progress ( busy ) C status only busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, quad page program, sector erase, block erase, chip erase, write status register or erase/program securi ty register instruction. during this time the device will ignore further instructions except for the read status register and erase /program suspend instruction (see t w , t pp , t se , t b e , and t c e in ac characteristics). when the program, erase or write status / security register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 write enable latch (wel) C status only write enable latch (wel) is a read only bit in the statu s register (s1) that is set to 1 after executing a write enable instruction. th e wel status bit is cleared to 0 when the device is write disabled. a write disable state occurs upon power - up or after any of the following instructions: write disable, page program, quad page program, sector erase, block erase, chip erase, write status register , erase security register and program security register . s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 srp 0 tb bp 3 bp 2 bp 1 bp 0 wel busy status register protect 0 ( volatile / non - volatile writable ) top / bottom protect bit ( volatile / non - volatile writable ) block protect bits ( volatile / non - volatile writable ) write enable latch ( status - only ) erase / write in progress ( status - only )
w25q256fv publication release date: february 11, 2015 - 16 - preliminary C revision h 7.1.3 block protect bits ( bp3, bp2, bp1, bp0) C volatile/non - volatile writable the block protect bits ( bp3, bp2, bp1, bp0 ) are non - vola tile read/write bits in the status register ( s5, s4, s3, and s2 ) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memor y array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. 7.1.4 top/bottom block protect (tb) C volatile/non - volatile writable the non - volatile top/bottom bit (tb) controls if the block protect bits ( bp3, bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the f actory default setting is tb=0 . the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 7.1.5 complement protect (cmp) C volatile/non - volatile writable the c omplement p rotect bit (cmp) is a non - volatile read/write bit in the st atus register (s14). it is used in conjunction with tb, bp3, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previo us array protection set by tb, bp3, bp2, bp1 and bp0 will be reversed. for instance, when c mp=0, a top 6 4kb block can be protected while the rest of the array is not; when cmp=1, the top 6 4kb block will become unprotected while the rest of the array become read - only. please refer to the status register memory protection table for details. the de fault setting is cmp =0. 7.1.6 status register protect (srp 1 , srp 0 ) C volatile/non - volatile writable the status register protect bits (srp 1 and srp0 ) are non - volatile read/write bits in the status register (s8 and s7). the srp bits control the method of write pro tection: s oftware p rotection, h ardware p rotection, p ower s upply l ock - d own or o ne t ime p rogrammable (otp) p rotection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction , wel=1 . [factory default] 0 1 0 hardware protect ed when /wp pin is low the status register locked and can not be written to . 0 1 1 hardware unprotected when /wp pin is high the status register is unlocked and can be written to a fter a write enable instruction , wel=1. 1 0 x power supply lock - down status register is protected and can not be written to again until the next power - down , power - up cycle . ( 1 ) 1 1 x one time program ( 2 ) status register is permanently protected and can not be written to. note s : 1. when srp1, srp0 = (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. 2 . this feature is available upon special order. please contact winbond for details.
w25q256fv - 17 - figure 4 b . status register - 2 7.1.7 erase/pro gram suspend status (sus) C status only the suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase/program suspend (75h) instruction. the sus status bit is cleared to 0 by erase/program resume (7ah) inst r uction as well as a power - down, power - up cycle. 7.1.8 security register lock bits (lb3, lb2, lb1 ) C volatile/non - volatile otp writable the security regist er lock bits (lb3, lb2, lb1 ) are non - volatile one time program (otp) bits in sta tus register (s13, s12, s11 ) that provide the write protect control and status to the security registers . t he default state of lb3 - 1 is 0, securi ty registers are unlocked. lb3 - 1 can be set to 1 individually using the write status register instruction. lb3 - 1 are one time programmable (otp), once its set to 1, the corresponding 256 - byte security register will become read - only permanently. 7.1.9 quad enable ( qe ) C volatile/non - volatile writable the quad enable (qe ) bit is a non - volatile read/write bit in the status register (s 9 ) that enable s quad spi operation . when the qe bit is set to a 0 state (factory default for part number with ordering options ig and if ) , the /wp pin and /hold are enabled , the device operates in standard/dual spi modes . when the qe bit is set to a 1 (factory default for quad enabled part numbers with ordering option iq ) , the quad io2 and i o3 pins are enabled , and /wp and /hold functions are disabled , the device operates in standard/dual/quad spi modes . qe bit is required to be set to a 1 before issuing an enter qp i (38h) to switch the device from standard/dual/quad spi to qpi, otherwise the command will be ignored. when the device is in qpi mode, qe bit will remain to be 1. a write status register command in qpi mode cannot change qe bit from a 1 to a 0. war ning: if the /wp or /hold pins are tied directly to the power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1. s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 sus cmp lb 3 lb 2 lb 1 ( r ) qe srp 1 status register protect 1 ( volatile / non - volatile writable ) complement protect ( volatile / non - volatile writable ) security register lock bits ( volatile / non - volatile otp writable ) reserved quad enable ( volatile / non - volatile writable ) suspend status ( status - only )
w25q256fv publication release date: february 11, 2015 - 18 - preliminary C revision h figure 4 c . status register - 3 7.1.10 current address mode (ad s ) C status only the current address mode bit is a read only bit in the status register - 3 that indicates which address mode the device is currently operating in . when ad s =0, the device is in the 3 - byte address mode, when ad s =1, the device is in the 4 - byte address mode. 7.1.11 power - up address mode (ad p ) C non - volatile writable the ad p bit is a non - volatile bit that determines the initial address mo de when the device is powered on or reset . this bit is only used during the power on or device reset initialization period, and it is only writable by the non - volatile write status sequence (06h + 11h). when adp=0 (factory default), the device will power up into 3 - byte address mode, the extended address register must be used to access memory regions beyond 128mb. when adp=1, the device will power up into 4 - byte address mode directly. 7.1.12 write protect selection (wp s) C volatile/non - volatile writable the wps bit is used to select which write protect scheme should be used . when wps=0, the device will use the combination of cmp, tb, bp[3:0] bits to protect a specif ic area of the memory array. when wps=1, the device will utilize the individual block locks to protect any individual sector or blocks. the default value for all individual block lock bits is 1 upon device power on or after reset. s 23 s 22 s 21 s 20 s 19 s 18 s 17 s 16 hold / rst drv 1 drv 0 ( r ) ( r ) wps adp ads power up address mode ( non - volatile writable ) output driver strength ( volatile / non - volatile writable ) reserved write protect selection ( volatile / non - volatile writable ) current address mode ( status - only ) / hold or / reset function ( volatile / non - volatile writable )
w25q256fv - 19 - 7.1.13 output driver strength ( drv1, drv0) C volatile/non - volatile writable the drv1 & drv0 bits are used to determine the output driver strength for the read operations . drv1, drv0 driver strength 0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default) 7.1.14 /hold or / reset pin function (hold/rs t) C volatile/non - volatile writable the hold/rst bit is used to determine whether /hold or /reset function should be implemented on the hardware pin. when hold/rst=0 (factory default), the pin acts as /hold; when hold/rst=1, the pin acts as /reset. however , /hold or /reset functions are only available when qe=0. if qe is set to 1, the /hold and /reset functions are disabled, the pin acts as a dedicated data i/o pin. 7.1.15 reserved bits C non functional there are a few reserved status register bits that may be rea d out as a 0 or 1. it is recommended to ignore the values of those bits. during a write status register instruction, the reserved bits can be written as 0, but there will not be any effects.
w25q256fv publication release date: february 11, 2015 - 20 - preliminary C revision h 7.1.16 w25q256fv s tatus register memory protection ( wps = 0 , cm p = 0 ) status register (1) w25q256fv ( 256 m - bit / 32m - byte ) memory protection (2 ) tb bp3 bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x 0 0 0 0 none none none none 0 0 0 0 1 511 01ff0000h - 01ffffffh 64 kb upper 1/ 512 0 0 0 1 0 510 thru 511 01fe0000h - 01ffffffh 128kb upper 1/256 0 0 0 1 1 508 thru 511 01fc0000h - 01ffffffh 256kb upper 1/128 0 0 1 0 0 504 thru 511 01f80000h - 01ffffffh 512kb upper 1/64 0 0 1 0 1 496 thru 511 01f00000h - 01ffffffh 1mb upper 1/32 0 0 1 1 0 480 thru 511 01e00000h - 01ffffffh 2mb upper 1/16 0 0 1 1 1 448 thru 511 01c00000h - 01ffffffh 4mb upper 1/8 0 1 0 0 0 384 thru 511 01800000h - 01ffffffh 8mb upper 1/4 0 1 0 0 1 256 thru 511 01000000h - 01ffffffh 16mb upper 1/2 1 0 0 0 1 0 0 0000000h - 0000ffffh 64kb lower 1/512 1 0 0 1 0 0 thru 1 00000000h - 0001ffffh 128kb lower 1/256 1 0 0 1 1 0 thru 3 00000000h - 0003ffffh 256kb lower 1/128 1 0 1 0 0 0 thru 7 00000000h - 0007ffffh 512kb lower 1/64 1 0 1 0 1 0 thru 15 00000000h - 000fff ffh 1mb lower 1/32 1 0 1 1 0 0 thru 31 00000000h - 001fffffh 2mb lower 1/16 1 0 1 1 1 0 thru 63 00000000h - 003fffffh 4mb lower 1/8 1 1 0 0 0 0 thru 127 00000000h - 007fffffh 8mb lower 1/4 1 1 0 0 1 0 thru 255 00000000h - 00ffffffh 16mb lower 1/2 x 1 1 0 x 0 thru 511 00000000h - 01ffffffh 32mb all x 1 x 1 x 0 thru 511 00000000h - 01ffffffh 32mb all notes: 1. x = dont care 2. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
w25q256fv - 21 - 7.1.17 w25q 256fv status register memory protection ( wps = 0, cmp = 1) status register (1) w25q256fv (256m - bit / 32m - byte ) memory protection (2) tb bp3 bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x 0 0 0 0 all 00000000h - 01 ffffffh all all 0 0 0 0 1 0 thru 510 00000000 h - 01feffffh 32,704kb lower 511/512 0 0 0 1 0 0 thru 509 00000000 h - 01fdffffh 32,640kb lower 255/256 0 0 0 1 1 0 thru 507 00000000 h - 01fbffffh 32,512kb lower 127/128 0 0 1 0 0 0 thru 503 00000000 h - 01f7f fffh 32,256kb lower 63/64 0 0 1 0 1 0 thru 495 00000000 h - 01 e fffffh 31mb lower 31/32 0 0 1 1 0 0 thru 479 00000000 h - 01 d fffffh 30mb lower 15/16 0 0 1 1 1 0 thru 447 00000000 h - 01 b fffffh 28mb lower 7/8 0 1 0 0 0 0 thru 383 00000000 h - 01 7 fffffh 24mb lower 3/4 0 1 0 0 1 0 thru 255 0 0 000000h - 0 0 ffffffh 16mb lower 1/2 1 0 0 0 1 1 thru 511 000 1 0000h - 0 1ff ffffh 32,704kb upper 511/512 1 0 0 1 0 2 thru 51 1 000 2 0000h - 01ffffff h 32,640kb upper 255/256 1 0 0 1 1 4 thru 511 000 4 0000h - 01ffffff h 32,512kb upper 127/128 1 0 1 0 0 8 thru 511 000 8 0000h - 01ffffff h 32,256kb upper 63/64 1 0 1 0 1 16 thru 511 00 1 00000h - 01ffffff h 31mb upper 31/32 1 0 1 1 0 32 thru 511 00 2 00000h - 01ffffff h 30mb upper 15/16 1 0 1 1 1 64 thru 511 00 4 00000h - 01ffffff h 28mb upp er 7/8 1 1 0 0 0 128 thru 511 00 8 00000h - 01ffffff h 24mb upper 3/4 1 1 0 0 1 256 thru 511 0 1 000000h - 0 1 ffffffh 16mb upper 1/2 x 1 1 0 x none none none none x 1 x 1 x none none none none note s : 1. x = dont care 2. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
w25q256fv publication release date: february 11, 2015 - 22 - preliminary C revision h 7.1.18 w25q256fv individual block memory protection (wps=1) figure 4 d . individual block/sector locks note s : 1. individual block/sector protection is only valid when wps=1. 2. a ll individual block/sector lock bits are set to 1 by default after power up, all memory array is protected. s e c t o r 0 ( 4 k b ) s e c t o r 1 ( 4 k b ) s e c t o r 1 4 ( 4 k b ) s e c t o r 1 5 ( 4 k b ) b l o c k 1 ( 6 4 k b ) b l o c k 5 1 0 ( 6 4 k b ) s e c t o r 0 ( 4 k b ) s e c t o r 1 ( 4 k b ) s e c t o r 1 4 ( 4 k b ) s e c t o r 1 5 ( 4 k b ) b l o c k 0 ( 6 4 k b ) b l o c k 5 1 1 ( 6 4 k b ) i n d i v i d u a l b l o c k l o c k s : 3 2 s e c t o r s ( t o p / b o t t o m ) 5 1 0 b l o c k s i n d i v i d u a l b l o c k l o c k : 3 6 h + a d d r e s s i n d i v i d u a l b l o c k u n l o c k : 3 9 h + a d d r e s s r e a d b l o c k l o c k : 3 d h + a d d r e s s g l o b a l b l o c k l o c k : 7 e h g l o b a l b l o c k u n l o c k : 9 8 h
w25q256fv - 23 - 7.2 extended address register C volatile writable only in addition to the status registers, w25q256fv provides a volatile extended address register wh ich consists of the 4 th byte of memory address . the extended address register is used only when the device is operating in the 3 - byte address mode (ads=0) . the lower 128mb memory array (00000 000h C 00ffffffh) is selected when a24=0, all instructions with 3 - byte addresses will be executed within that region. when a24=1, the upper 128mb memory array (01000000h C 01ffffffh) will be selected. if the device powers up with adp bit set to 1, or an enter 4 - byte address mode (b7h) instruction is issued, the device will require 4 - byte address input for all address related instructions, and the extended address register setting will be ignored. however, any command with 4 - byte address input will replace the extended address register bits (a31 - a24) with new settings. upon power up or after the execution of a software/hardware reset, the extended address register values will be cleared to 0 . figure 4 e . extended address register e a 7 e a 6 e a 5 e a 4 e a 3 e a 2 e a 1 e a 0 a 3 1 a 3 0 a 2 9 a 2 8 a 2 7 a 2 6 a 2 5 a 2 4 r e s e r v e d f o r h i g h e r d e n s i t i e s 5 1 2 m b ~ 3 2 g b ( v o l a t i l e w r i t a b l e o n l y ) a d d r e s s b i t # 2 4 a 2 4 = 0 : s e l e c t l o w e r 1 2 8 m b a 2 4 = 1 : s e l e c t u p p e r 1 2 8 m b ( v o l a t i l e w r i t a b l e o n l y )
w25q256fv publication release date: february 11, 2015 - 24 - preliminary C revision h 8. instructions the standard/dual/quad spi instruction set of the w25q256fv consists of 48 basic instructions that are fully controlled through the spi bus (see instruction set table1 - 3). instructions are initiated with the falling edge of chip select (/cs). the first byte of data clocked into the di input provides the instruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. the qpi instruction set of the w25q256fv consists of 35 basic instructions that are fully controlled through the spi bus (see instruction set table 4 - 6). instruc tions are initiated with the falling edge of chip select (/cs). the first byte of data clocked through io[3:0] pins provides the instruction code. data on all four io pins are sampled on the rising edge of clock with most significant bit (msb) first. all q pi instructions, addresses, data and dummy bytes are using all four io pins to transfer every byte of data with every two serial clocks (clk). spi/qpi protocol 3 - byte address mode (ads=0) 4 - byte address mode (ads=1) standard/dual/quad spi instruction set table 1 & 2 instruction set table 1 & 3 qpi instruction set table 4 & 5 instruction set table 4 & 6 instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some c ases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diagrams for each instruction are included in figures 5 through 57. all read instructions can be completed after any clocked bit. however, all instructi ons that write, program or erase must complete on a byte boundary (/cs driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignored. this feature further protects the device from inadvertent writes. additionally, while the m emory is being programmed or erased, or when the status register is being written, all instructions except for read status register will be ignored until the program or erase cycle has completed. 8.1 device id and instruction set tables 8.1.1 manufacturer and device identification manufacturer id (mf7 - mf0) winbond serial flash ef h device id (id7 - id0) (id15 - id0) instruction abh, 90h, 92h, 94h 9fh w25q256fv (spi mode) 18h 4019h w25q256fv (qpi mode) 18h 6019h
w25q256fv - 25 - 8.1.2 instruction set table 1 (standard/dual/qu ad spi, 3 - byte & 4 - byte address mode) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 clock number (0 C 7) (8 C 15) (16 C 23) (24 C 31) (32 C 39) (40 C 47) (48 C 55) write enable 06h volatile sr write enable 50h write disable 04h read status register - 1 05h (s7 - s0) (2) write status register - 1 (4) 01h (s7 - s0) (4) read status register - 2 35h (s15 - s8) (2) write status register - 2 31h (s15 - s8) read status register - 3 15h (s23 - s16) (2) write status register - 3 11h (s23 - s16) rea d extended addr. register c8h (ea7 - ea0) (2) write extended addr. register c5h (ea7 - ea0) chip erase c7h /60h erase / program suspend 75h erase / program resume 7ah power - down b9h release power - down / id abh dummy dummy dummy (id7 - id0) (2) man ufacturer/device id 90h dummy dummy 00h (mf7 - mf0) (id7 - id0) jedec id 9fh (mf7 - mf0) (id15 - id8) (id7 - id0) global block lock 7eh global block unlock 98h enter qpi mode 38h enter 4 - byte address mode b7h exit 4 - byte address mode e9h enable re set 66h reset device 99h read data with 4 - byte address 13h a31 - a24 a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read with 4 - byte address 0ch a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) fast read dual output with 4 - byte address 3ch a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (7) fast read quad output with 4 - byte address 6ch a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (9) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 clock number (0 C 7) (8 C 11) (12 C 15) (16 C 19) (20 C 23) (24 C 27) (28 C 31) fast read dual i/o with 4 - byte address bch a31 - a24 a23 - a16 a15 - a8 a7 - a0 m7 - m0 (d7 - d0) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 clock number (0 C 7) (8, 9) (10, 11) (12, 13) (14, 15 ) (16, 17) (18, 19) (20 , 21) (22, 23) fast read quad i/o with 4 - byte address ech a31 - a24 a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy dummy (d7 - d0)
w25q256fv publication release date: february 11, 2015 - 26 - preliminary C revision h 8.1.3 instruction set table 2 (standard/dual/quad spi instructions, 3 - byte address mode) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0 C 7) (8 C 15) (16 C 23) (24 C 31) (32 C 39) (40 C 47) read unique id 4bh dummy dummy dummy dummy (uid63 - uid0) page program 02h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) quad page program 3 2h a23 - a16 a15 - a8 a7 - a0 d7 - d0 , (9) d7 - d0 , (3 ) sector erase (4kb) 20h a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a23 - a16 a15 - a8 a7 - a0 block erase (64kb) d8h a23 - a16 a15 - a8 a7 - a0 read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) fast read dual outpu t 3bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (7) fast read quad output 6bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (9) read sfdp register 5ah a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) erase security register (5) 44h a23 - a16 a15 - a8 a7 - a0 program security register (5 ) 42h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) read security register (5) 48h a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) individual block lock 36h a23 - a16 a15 - a8 a7 - a0 individual block unlock 39h a23 - a16 a15 - a8 a7 - a0 read block lock 3dh a23 - a16 a15 - a8 a7 - a0 d7 - d0 data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 clock number (0 C 7) (8 C 11) (12 C 15) (16 C 19) (20 C 23) (24 C 27) (28 C 31) fast read dual i/o bbh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) mftr./device id dual i/o 92h a23 - a16 a15 - a8 a 7 - a0 dummy (mf7 - mf0) (id7 - id0) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 clock number (0 C 7) (8, 9) (10, 11) (12, 13) (14, 15 ) (16, 17) (18, 19) (20, 21) (22, 23) set burst with wrap 77h dummy dummy dummy w8 - w0 fast read quad i/o ebh a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy dummy (d7 - d0) (d7 - d0) word read quad i/o (12) e7h a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy (d7 - d0) (d7 - d0) (d7 - d0) octal word read quad i/o (13) e3h a23 - a16 a15 - a8 a7 - a0 m7 - m0 (d7 - d0) (d7 - d0) (d7 - d0) (d7 - d0) mftr./device id quad i/o 94h a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy dummy (mf7 - mf0) (id7 - id0)
w25q256fv - 27 - 8.1.4 instruction set table 3 (standard/dual/quad spi instructions, 4 - byte address mode) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 clock numb er (0 C 7) (8 C 15) (16 C 23) (24 C 31) (32 C 39) (40 C 47) (48 C 55) read unique id 4bh dummy dummy dummy dummy dummy (uid63 - uid0) page program 02h a31 - a24 a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) quad page program 3 2h a31 - a24 a23 - a16 a15 - a8 a7 - a0 d7 - d0 , (9) d7 - d0 , (3) sector erase (4kb) 20h a31 - a24 a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a31 - a24 a23 - a16 a15 - a8 a7 - a0 block erase (64kb) d8h a31 - a24 a23 - a16 a15 - a8 a7 - a0 read data 03h a31 - a24 a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a31 - a24 a2 3 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) fast read dual output 3bh a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (7) fast read quad output 6bh a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (9) read sfdp register 5ah a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) era se security register (5) 44h a31 - a24 a23 - a16 a15 - a8 a7 - a0 program security register (5) 42h a31 - a24 a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) read security register (5) 48h a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) individual block lock 36h a31 - a24 a23 - a16 a15 - a8 a7 - a0 individual block unlock 39h a31 - a24 a23 - a16 a15 - a8 a7 - a0 read block lock 3dh a31 - a24 a23 - a16 a15 - a8 a7 - a0 d7 - d0 data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 clock number (0 C 7) (8 C 11) (12 C 15) (16 C 19) (20 C 23) (24 C 27) (28 C 31) (32 C 35) fast read dual i/o bbh a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) (d7 - d0) mftr./device id dual i/o 92h a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (mf7 - mf0) (id7 - id0) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 byte 10 clock number (0 C 7) (8, 9) (10, 11) (12, 13) (14, 15 ) (16, 17) (18, 19) (20, 21) (22, 23) (24, 25) set burst with wrap 77h dummy dummy dummy dummy w8 - w0 fast read quad i/o ebh a31 - a24 a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy dum my (d7 - d0) (d7 - d0) word read quad i/o (12) e7h a31 - a24 a23 - a16 a15 - a8 a7 - a0 m7 - m0 dummy (d7 - d0) (d7 - d0) (d7 - d0) octal word read quad i/o (13) e3h a31 - a24 a23 - a16 a15 - a8 a7 - a0 m7 - m0 (d7 - d0) (d7 - d0) (d7 - d0) (d7 - d0) mftr./device id quad i/o 94h a31 - a24 a23 - a 16 a15 - a8 a7 - a0 m7 - m0 dummy dummy (mf7 - mf0) (id7 - id0)
w25q256fv publication release date: february 11, 2015 - 28 - preliminary C revision h 8.1.5 instruction set table 4 (qpi instructions, 3 - byte & 4 - byte address mode) (14) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0, 1) (2 , 3) (4, 5) (6 , 7) (8, 9) (10, 11) wr ite enable 06h volatile sr write enable 50h write disable 04h read status register - 1 05h (s7 - s0) (2) write status register - 1 (4) 01h (s7 - s0) (4) read status register - 2 35h (s15 - s8) (2) write status register - 2 31h (s15 - s8) read status register - 3 1 5h (s23 - s16) (2) write status register - 3 11h (s23 - s16) read extended addr. register c8h (ea7 - ea0) (2) write extended addr. register c5h (ea7 - ea0) chip erase c7h /60h erase / program suspend 75h erase / program resume 7ah power - down b9h set rea d parameters c0h p7 - p0 release powerdown / id abh dummy dummy dummy (id7 - id0) (2) manufacturer/device id 90h dummy dummy 00h (mf7 - mf0) (id7 - id0) jedec id 9fh (mf7 - mf0) (id15 - id8) (id7 - id0) global block lock 7eh global block unlock 98h exit qpi mo de ffh enter 4 - byte address mode b7h exit 4 - byte address mode e9h enable reset 66h reset device 99h
w25q256fv - 29 - 8.1.6 instruction set table 5 (qpi instructions, 3 - byte address mode) (14) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0, 1) (2 , 3) (4, 5) (6 , 7) (8, 9) (10, 11) page program 02h a23 - a16 a15 - a8 a7 - a0 d7 - d0 (9) d7 - d0 (3) sector erase (4kb) 20h a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a23 - a16 a15 - a8 a7 - a0 block erase (64kb) d8h a23 - a16 a15 - a8 a7 - a0 fast read 0bh a2 3 - a16 a15 - a8 a7 - a0 dummy (15) (d7 - d0) burst read with wrap (16) 0ch a23 - a16 a15 - a8 a7 - a0 dummy (15) (d7 - d0) fast read quad i/o ebh a23 - a16 a15 - a8 a7 - a0 m7 - m0 (15) (d7 - d0) individual block lock 36h a23 - a16 a15 - a8 a7 - a0 individual block unlock 39h a23 - a16 a 15 - a8 a7 - a0 read block lock 3dh a23 - a16 a15 - a8 a7 - a0 (l7 - l0) 8.1.7 instruction set table 6 (qpi instructions, 4 - byte address mode) (14) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 clock number (0, 1) (2 , 3) (4, 5) (6 , 7) (8, 9) (10, 11 ) (12, 13) page program 02h a31 - a24 a23 - a16 a15 - a8 a7 - a0 d7 - d0 (9) d7 - d0 (3) sector erase (4kb) 20h a31 - a24 a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a31 - a24 a23 - a16 a15 - a8 a7 - a0 block erase (64kb) d8h a31 - a24 a23 - a16 a15 - a8 a7 - a0 fast read 0bh a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (15) (d7 - d0) burst read with wrap (16) 0ch a31 - a24 a23 - a16 a15 - a8 a7 - a0 dummy (15) (d7 - d0) fast read quad i/o ebh a31 - a24 a23 - a16 a15 - a8 a7 - a0 m7 - m0 (15) (d7 - d0) individual block lock 36h a31 - a24 a23 - a16 a15 - a8 a7 - a0 indivi dual block unlock 39h a31 - a24 a23 - a16 a15 - a8 a7 - a0 read block lock 3dh a31 - a24 a23 - a16 a15 - a8 a7 - a0 (l7 - l0)
w25q256fv publication release date: february 11, 2015 - 30 - preliminary C revision h notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ( ) indicate data output from the de vice on either 1, 2 or 4 io pins. 2. the status register contents and device id will repeat continuously until /cs terminates the instruction. 3. at least one byte of data input is required for page program, quad page program and program security registers, up t o 256 bytes of data input. if more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. write status register - 1 (01h) can also be used to program status register - 1&2, see s ection 8.2.5. 5. security register address: security register 1: a23 - 16 = 00h; a15 - 8 = 10h; a7 - 0 = byte address security register 2: a23 - 16 = 00h; a15 - 8 = 20h; a7 - 0 = byte address security register 3: a23 - 16 = 00h; a15 - 8 = 30h; a7 - 0 = byte address 6. dual spi address input format: io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 7. dual spi data output form at: io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 8. quad spi address input format: set burst with wrap input format: io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 9. quad spi data input/output format: io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 10. fast read quad i/o data output format: io0 = (x, x, x, x, d4, d0, d4, d0) io1 = (x, x, x, x, d5, d1, d5, d1) io2 = (x, x, x, x, d6, d2, d6, d2) io3 = (x, x, x, x, d7, d3, d7, d3) 11. word read quad i/o data output format: io0 = (x, x, d4, d0, d4, d0, d4, d0) io1 = (x, x, d5, d1, d5, d1, d5, d1 ) io2 = (x, x, d6, d2, d6, d2, d6, d2) io3 = (x, x, d7, d3, d7, d3, d7, d3) 12. for word read quad i/o, the lowest address bit must be 0. (a0 = 0) 13. for octal word read quad i/o, the lowest four address bits must be 0. (a3, a2, a1, a0 = 0) 14. qp i command, address, data input/output format: clk # 0 1 2 3 4 5 6 7 8 9 10 11 io0 = c4, c0, a20, a16, a12, a8, a4, a0, d4, d0, d4, d0 io1 = c5, c1, a21, a17, a13, a9, a5, a1, d5, d1, d5, d1 io2 = c6, c2, a22, a18, a14, a10, a6, a2, d6, d2, d6, d2 io3 = c7, c3, a23, a19, a15, a11, a7, a3, d7, d3, d7, d3 15. the number of dummy clocks for qpi fast read, qpi fast read quad i/o & qpi burst read with wrap is contr olled by read parameter p7 C p4. 16. the wrap around length for qpi burst read with wrap is controlled by read parameter p3 C p0.
w25q256fv - 31 - 8.2 instruction descriptions 8.2.1 write enable (06h) the write enable instruction (figure 5) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, quad page program, sector erase, block erase, chip erase, write status register and erase/program security registers instruction. the write enable instruction is entered by drivin g /cs low, shifting the instruction code 06h into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 5. write enable instruction for spi mode (left) or qpi mode (right) 8.2.2 write enable for volatile status register (50 h) the non - volatile status register bits described in section 7.1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a write status register ( 01h) instruction. write enable for volatile status register instruction (figure 6) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit values. figure 6. w rite enable for volatile status register instruction for spi mode (left) or qpi mode (right) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk mode 0 mode 3 0 1 mode 0 mode 3 io 0 io 1 io 2 io 3 06h instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance /cs clk mode 0 mode 3 0 1 mode 0 mode 3 io 0 io 1 io 2 io 3 50h instruction
w25q256fv publication release date: february 11, 2015 - 32 - preliminary C revision h 8.2.3 write disable (04h) the write disable instruction (figure 7) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction i s entered by driving /cs low, shifting the instruction code 04h into the di pin and then driving /cs high. note that the wel bit is automatically reset after power - up and upon completion of the write status register, erase/program security registers, pag e program, quad page program, sector erase, block erase, chip erase and reset instructions. figure 7. write disable instruction for spi mode (left) or qpi mode (right) 8.2.4 read status register - 1 (05h), status register - 2 ( 3 5h) & status register - 3 (15h) the read status register instructions allow the 8 - bit status registers to be read. the instruction is entered by driving /cs low and shifting the instruction code 05h for status register - 1, 35h for status register - 2 or 15h for status register - 3 into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 8. refer to section 7.1 for status register descriptions. the read status re gister instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. t he status register can be read continuously, as shown in figure 8. the instruction is completed by driving /cs high. figure 8a. read status register instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance /cs clk mode 0 mode 3 0 1 mode 0 mode 3 io 0 io 1 io 2 io 3 04h instruction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 5 h / 3 5 h / 1 5 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 s t a t u s r e g i s t e r - 1 / 2 / 3 o u t s t a t u s r e g i s t e r - 1 / 2 / 3 o u t * * = m s b *
w25q256fv - 33 - figure 8b. read status register instruction (qpi mode) 8.2.5 write status registe r - 1 (01h), status register - 2 ( 3 1h) & status register - 3 (11h) the write status register instruction allows the status registers to be written. the writable status register bits include: srp0, tb, bp[3:0] in status register - 1; cmp, lb[3:1], qe, srp1 in statu s register - 2; hold/rst, drv1, drv0, wps & adp in status register - 3. all other status register bit locations are read - only and will not be affected by the write status register instruction. lb[3:1] are non - volatile otp bits, once it is set to 1, it cannot b e cleared to 0. to write non - volatile status register bits, a standard write enable (06h) instruction must previously have been executed for the device to accept the write status register instruction (status register bit wel must equal 1). once write enab led, the instruction is entered by driving /cs low, sending the instruction code 01h/31h/11h, and then writing the status register data byte as illustrated in figure 9a & 9b. to write volatile status register bits, a write enable for volatile status regi ster (50h) instruction must have been executed prior to the write status register instruction (status register bit wel remains 0). however, srp1 and lb[3:1] cannot be changed from 1 to 0 because of the otp protection for these bits. upon power off or t he execution of a software/hardware reset, the volatile status register bit values will be lost, and the non - volatile status register bit values will be restored. during non - volatile status register write operation (06h combined with 01h/31h/11h), after /c s is driven high, the self - timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction may still be accessed to check the sta tus of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write status register cycle has finished, the write enable latch (wel) bit in the sta tus register will be cleared to 0. during volatile status register write operation (50h combined with 01h/31h/11h), after /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shsl2 (see ac characterist ics). busy bit will remain 0 during the status register bit refresh period. / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 0 5 h / 3 5 h / 1 5 h 2 3 4 5 4 0 4 0 5 1 6 2 7 3 5 1 6 2 7 3 4 5 6 7 s r - 1 / 2 / 3 o u t s r - 1 / 2 / 3 o u t i n s t r u c t i o n
w25q256fv publication release date: february 11, 2015 - 34 - preliminary C revision h the write status register instruction can be used in both spi mode and qpi mode. however, the qe bit cannot be written to when the device is in the qpi mode, because qe=1 is requir ed for the device to enter and operate in the qpi mode. refer to section 7.1 for status register descriptions. factory default for all status register bits are 0. figure 9a. write status register - 1/2/3 instruction (spi mode) figure 9b. write status register - 1/2/3 instruction (qpi mode) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 1 h / 3 1 h / 1 1 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 7 6 5 4 3 2 1 0 r e g i s t e r - 1 / 2 / 3 i n m o d e 0 m o d e 3 * = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 0 1 / 3 1 / 1 1 h 2 3 4 0 5 1 6 2 7 3 s r 1 / 2 / 3 i n m o d e 0 m o d e 3 i n s t r u c t i o n
w25q256fv - 35 - the w25q256fv is also backward compatible to winbonds previous generations of serial flash memories, in which the status register - 1&2 can be written using a sing le write status register - 1 (01h) command. to complete the write status register - 1&2 instruction, the /cs pin must be driven high after the sixteenth bit of data that is clocked in as shown in figure 9c & 9d. if /cs is driven high after the eighth clock, the write status register - 1 (01h) instruction will only program the status register - 1, the status register - 2 will not be affected (previous generations will clear cmp and qe bits). figure 9c. write status register - 1/2 instructi on (spi mode) figure 9d. write status register - 1/2 instruction (qpi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 01h 2 3 4 5 4 0 12 8 5 1 6 2 7 3 13 9 14 10 15 11 sr1 in sr2 in mode 0 mode 3 instruction
w25q256fv publication release date: february 11, 2015 - 36 - preliminary C revision h 8.2.6 read extended address register (c8h) when the device is in the 3 - byte address mode, the extended address register is used as the 4 th address byte a[31: 24] to access memory regions beyond 128mb. the read extended address register instruction is entered by driving /cs low and shifting the instruction code c8h into the di pin on the rising edge of clk. the extended address register bits are then shifted o ut on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 10. when the device is in the 4 - byte address mode, the extended address register is not used. figure 10a. read extended address register instruction (sp i mode) figure 10b. read extended address register instruction (qpi mode) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( c 8 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 e x t e n d e d a d d r . r e g . o u t e x t e n d e d a d d r . r e g . o u t * * = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 c 8 h 2 3 4 5 4 0 4 0 5 1 6 2 7 3 5 1 6 2 7 3 4 5 6 7 e x t a d d r e g o u t i n s t r u c t i o n e x t a d d r e g o u t
w25q256fv - 37 - 8.2.7 write extended address register (c5h) the extended address register is a volatile register that stores the 4 th byte address (a31 - a24) when the device is operating in the 3 - b yte address mode (ads=0). to write the extended address register bits, a write enable (06h) instruction must previously have been executed for the device to accept the write extended address register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code c5h, and then writing the extended address register data byte as illustrated in figure 11. upon power up or the execution of a software/hardware reset, the extend ed address register bit values will be cleared to 0. the extended address register is only effective when the device is in the 3 - byte address mode. when the device operates in the 4 - byte address mode (ads=1), any command with address input of a31 - a24 will replace the extended address register values. it is recommended to check and update the extended address register if necessary when the device is switched from 4 - byte to 3 - byte address mode. figure 11a. write extended address r egister instruction (spi mode) figure 11b. write extended address register instruction (qpi mode) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( c 5 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 7 6 5 4 3 2 1 0 e x t . a d d . r e g i n m o d e 0 m o d e 3 * = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 c 5 h 2 3 4 0 5 1 6 2 7 3 e x t a d d r e g . i n m o d e 0 m o d e 3 i n s t r u c t i o n
w25q256fv publication release date: february 11, 2015 - 38 - preliminary C revision h 8.2.8 enter 4 - byte address mode (b7h) the enter 4 - byte address mode instruction (figure 12) will allow 32 - bit address (a31 - a0) to be used to access the memory array beyond 128mb. the enter 4 - byte address mode instruction is entered by driving /cs low, shifting the instruction code b7h into the di pin and then driving /cs high. figure 12. enter 4 - byte address mode instruction for spi mode (left) or qpi mode (right) 8.2.9 exit 4 - byte address mode (e9h) in order to be backward compatible, the exit 4 - byte address mode instruction (figure 13) will only allow 24 - bit address (a23 - a0) to be used to access the memory array up to 128mb. the exte nded address register must be used to access the memory array beyond 128mb. the exit 4 - byte address mode instruction is entered by driving /cs low, shifting the instruction code e9h into the di pin and then driving /cs high. figure 13. exit 4 - byte a ddress mode instruction for spi mode (left) or qpi mode (right) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( b 7 h ) h i g h i m p e d a n c e / c s c l k m o d e 0 m o d e 3 0 1 m o d e 0 m o d e 3 i o 0 i o 1 i o 2 i o 3 b 7 h i n s t r u c t i o n / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( e 9 h ) h i g h i m p e d a n c e / c s c l k m o d e 0 m o d e 3 0 1 m o d e 0 m o d e 3 i o 0 i o 1 i o 2 i o 3 e 9 h i n s t r u c t i o n
w25q256fv - 39 - 8.2.10 read data (03h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h followed by a 24 - bit address (a23 - a0) or a 32 - bit address (a31 - a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory locati on will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figure 14. if a read data instruction is issued while a n erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). the read da ta (03h) instruction is only supported in standard spi mode. figure 14. read data instruction (spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
w25q256fv publication release date: february 11, 2015 - 40 - preliminary C revision h 8.2.11 read data with 4 - byte address (13h) t he read data with 4 - byte address instruction is similar to the read data (03h) instruction. instead of 24 - bit address, 32 - bit address is needed following the instruction code 13h. no matter the device is operating in 3 - byte address mode or 4 - byte address m ode, the read data with 4 - byte address instruction will always require 32 - bit address to access the entire 256mb memory. the read data with 4 - byte address instruction sequence is shown in figure 15. if this instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data with 4 - byte address instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). the read da ta with 4 - byte address (13h) instruction is only supported in standard spi mode. figure 15. read data with 4 - byte address instruction (spi mode only) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 1 3 h ) h i g h i m p e d a n c e 8 9 1 0 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 7 6 5 4 3 2 1 0 7 3 2 - b i t a d d r e s s 3 1 3 0 2 9 3 2 1 0 d a t a o u t 1 * * = m s b *
w25q256fv - 41 - 8.2.12 fast read (0bh) the fast read instruction is similar to the read data instr uction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24/32 - bit address as shown in figure 16. the dummy clocks allow the devices interna l circuits additional time for setting up the initial address. during the dummy clocks the data value on the do pin is a dont care. figure 16a. fast read instruction (spi mode) 32 - bit address is required when the device is operating in 4 - byte addres s mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
w25q256fv publication release date: february 11, 2015 - 42 - preliminary C revision h fast read (0bh) in qpi mode the fast read instruction is also supported in qpi mode. when qpi mode is enabled, the number of dummy clocks is configured by the set read parameters (c0h) instruction to accommodate a wide range of applications wit h different needs for either maximum fast read frequency or minimum data access latency. depending on the read parameter bits p[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. the default number of dummy clocks upon power up or after a reset instruction is 2. figure 16b. fast read instruction (qpi mode) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 0bh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 dummy * byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 4 5 6 7 ios switch from input to output * "set read parameters" instruction (c0h) can set the number of dummy clocks. instruction
w25q256fv - 43 - 8.2.13 fast read with 4 - byte address (0ch) the fast read with 4 - byte address instruction is sim ilar to the fast read instruction except that it requires 32 - bit address instead of 24 - bit address. no matter the device is operating in 3 - byte address mode or 4 - byte address mode, the read data with 4 - byte address instruction will always require 32 - bit ad dress to access the entire 256mb memory. the fast read with 4 - byte address (0ch) instruction is only supported in standard spi mode. in qpi mode, the instruction code 0ch is used for the burst read with wrap instruction. figure 17. fast read with 4 - by te address instruction (spi mode only) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 c h ) h i g h i m p e d a n c e 8 9 1 0 3 6 3 7 3 8 3 9 3 2 - b i t a d d r e s s 3 1 3 0 2 9 3 2 1 0 d a t a o u t 1 * / c s c l k d i ( i o 0 ) d o ( i o 1 ) 5 7 5 8 5 9 6 0 6 1 6 2 6 3 3 9 d u m m y c l o c k s h i g h i m p e d a n c e 4 0 4 1 4 2 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 7 6 5 4 3 2 1 0 7 d a t a o u t 2 * 7 6 5 4 3 2 1 0 * 4 3 5 6 0 = m s b *
w25q256fv publication release date: february 11, 2015 - 44 - preliminary C revision h 8.2.14 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except that data is output on two pins; io 0 and io 1 . this allows data to be transferre d at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code from flash to ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast read instructio n, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24/32 - bit address as shown in figure 18. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io 0 pin should be high - impedance prior to the falling edge of the first data out clock. figure 18. fast read dual output instruction (spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
w25q256fv - 45 - 8.2.15 fast read dual output with 4 - byte address (3ch) the fast read dual output with 4 - byte address instru ction is similar to the fast read dual output instruction except that it requires 32 - bit address instead of 24 - bit address. no matter the device is operating in 3 - byte address mode or 4 - byte address mode, the fast read dual output with 4 - byte address instr uction will always require 32 - bit address to access the entire 256mb memory. the fast read dual output with 4 - byte address (3ch) instruction is only supported in standard spi mode. figure 19. fast read dual output with 4 - byte address instruction (spi mode only) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 c h ) h i g h i m p e d a n c e 8 9 1 0 3 6 3 7 3 8 5 7 5 8 5 9 6 0 6 1 6 2 6 3 3 9 6 4 2 0 3 2 - b i t a d d r e s s 3 1 3 0 2 9 3 2 1 0 * * 3 9 5 6 / c s c l k d i ( i o 0 ) d o ( i o 1 ) d u m m y c l o c k s 0 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 7 5 3 1 h i g h i m p e d a n c e 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 i o 0 s w i t c h e s f r o m i n p u t t o o u t p u t 6 7 d a t a o u t 1 * d a t a o u t 2 * d a t a o u t 3 * d a t a o u t 4 = m s b *
w25q256fv publication release date: february 11, 2015 - 46 - preliminary C revision h 8.2.16 fast read quad output (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . the quad enable (qe) b it in status register - 2 must be set to 1 before the device will accept the fast read quad output instruction . the fast read quad output instruction allows data to be transferred at four times the rate of standard spi devices. the fast read quad output ins truction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24/32 - bit address as shown in figure 20. the dummy clocks allow the device's internal circuits a dditional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io pins should be high - impedance prior to the falling edge of the first data out clock. figure 20. fast read quad output instruction (spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
w25q256fv - 47 - 8.2.17 fast read quad output with 4 - byte address (6ch) the fast read quad output with 4 - byte address instruction is similar to the fast read quad output instruction except that it requires 32 - bit address instead of 24 - bit address. no matter the device is operating in 3 - byte address mode or 4 - byte address mode, the fast read quad output with 4 - byte address instruction will always require 32 - bit address to access the en tire 256mb memory. the fast read quad output with 4 - byte address (6ch) instruction is only supported in standard spi mode. figure 21. fast read quad output with 4 - byte address instruction (spi mode only) / c s c l k m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 6 c h ) h i g h i m p e d a n c e 8 9 1 0 3 6 3 7 3 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 3 9 4 0 3 2 - b i t a d d r e s s 3 1 3 0 2 9 3 2 1 0 * 3 9 4 8 / c s c l k d u m m y c l o c k s 0 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 5 1 h i g h i m p e d a n c e 4 5 b y t e 1 h i g h i m p e d a n c e h i g h i m p e d a n c e 6 2 7 3 h i g h i m p e d a n c e 6 7 h i g h i m p e d a n c e 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 b y t e 2 b y t e 3 b y t e 4 i o 0 s w i t c h e s f r o m i n p u t t o o u t p u t i o 0 i o 1 i o 2 i o 3 i o 0 i o 1 i o 2 i o 3 = m s b *
w25q256fv publication release date: february 11, 2015 - 48 - preliminary C revision h 8.2.18 f ast read dual i/o (bbh) the fast read dual i /o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23/a31 - 0) two bits per clock. this reduced i nstruction overhead may allow for code execution (xip) directly from the d ua l spi in some applications. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further reduce instruction overhead through setting the continuo us read mode bits (m7 - 0) after the input address bits (a23/a31 - 0), as shown in figure 22 a . the upper nibble of the (m7 - 4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read dual i/o instruction ( after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 22 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuo us read mode bits m5 - 4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. it is recommended to input ffffh/fffffh on io0 for the next instruction (16/20 clocks), to ensure m4 = 1 and return the device to normal operation. figure 22 a . fast read dual i/ o instruction (initial instruction or previous m5 - 4 ? 10, spi mode only) 32 - bit address is required when the device is operating in 4 - byte addres s mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
w25q256fv - 49 - figure 22 b . fast read dual i/ o instruction (previous instruction set m5 - 4 = 10, spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 * = msb *
w25q256fv publication release date: february 11, 2015 - 50 - preliminary C revision h 8.2.19 f ast read dual i/o with 4 - byte address (bch) the fast read dual i/o with 4 - byte address instruction is similar to the fast read dual i/o instruction except that it requires 32 - bit address instead of 24 - bit address. no matter the device is operating in 3 - byte address mode or 4 - byte address mode, the fast read dual i/o with 4 - byte address instruction will always require 32 - bit address to access the entire 256mb memory. the fast read dual i/o with 4 - byte address (bch) instruction is only supported in standard spi mode . figure 23a. fast read dual i/ o with 4 - byte addre ss instruction (initial instruction or previous m5 - 4 ? 10, spi mode only) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( b c h ) 8 9 1 0 4 1 4 2 4 3 2 7 2 8 2 9 3 0 3 1 6 4 2 0 * * 4 0 / c s c l k d i ( i o 0 ) d o ( i o 1 ) 0 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * i o s s w i t c h f r o m i n p u t t o o u t p u t 6 7 3 0 2 8 2 6 3 1 2 9 2 7 4 2 0 5 3 1 6 4 2 0 7 5 3 1 2 1 2 2 2 4 2 5 2 6 2 3 2 7 1 m 7 - 0 b y t e 1 b y t e 2 b y t e 3 b y t e 4 = m s b * * 3 2 - b i t a d d r e s s
w25q256fv - 51 - figure 23 b . fast read dual i/ o with 4 - byte address instruction (previous instruction set m5 - 4 = 10, spi mode only) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 1 2 1 3 1 4 1 6 1 7 1 8 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 6 4 2 0 * * 3 2 / c s c l k d i ( i o 0 ) d o ( i o 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * i o s s w i t c h f r o m i n p u t t o o u t p u t 6 7 3 0 2 8 2 6 2 4 3 1 2 9 2 7 2 5 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 1 5 1 9 1 m 7 - 0 b y t e 1 b y t e 2 b y t e 3 b y t e 4 0 1 2 3 3 3 3 4 3 5 2 0 2 1 2 2 1 9 2 3 * = m s b * 3 2 - b i t a d d r e s s
w25q256fv publication release date: february 11, 2015 - 52 - preliminary C revision h 8.2.20 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy clocks are required in spi mode prior to the data output. the quad i/o dramati cally reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status register - 2 must be set to enable the fast read quad i/o instruction . fast read quad i/o with continuo us read mode the fast read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23/a31 - 0), as shown in figure 24 a . the upper nibble of the (m7 - 4) controls the le ngth of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not require the ebh instruction code, as shown in figure 24 b. this reduces the instruction sequ ence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruc tion code, thus returning to normal operation. it is recommended to input ffh/3ffh on io0 for the next instruction (8/10 clocks), to ensure m4 = 1 and return the device to normal operation. figure 24 a . fast read quad i/ o instruction (initial instruction or previous m5 - 4 ? 10, spi mode) 32 - bit address is required when the device is operating in 4 - byte address mode m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
w25q256fv - 53 - figure 24 b . fast read quad i/ o instruction ( previous instruction set m5 - 4 = 10, spi mode ) 32 - bit address is required when the device is operating in 4 - byte address mode fast read quad i/o with 8/16/32/64 - byte wrap around in standard spi mode the fast read quad i/o instruction can a lso be used to access a specific portion within a page by issuing a set burst with wrap (77h) command prior to ebh. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afte rwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 a re used to specify the length of the wrap around section within a page. refer to section 8.2.24 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 dummy dummy
w25q256fv publication release date: february 11, 2015 - 54 - preliminary C revision h fast read quad i/o (ebh) in qpi mode the fast read quad i/o instruction is also supported in qpi mode, as shown in figure 19c. when q pi mode is enabled, the number of dummy clocks is configured by the set read parameters (c0h) instruction to accommodate a wide range of applications with different needs for either maximum fast read frequency or minimum data access latency. depending on the read parameter bits p[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. the default number of dummy clocks upon power up or after a reset instruction is 2 . in qpi mode, the continuous read mode bits m7 - 0 are also con sidered as dummy clocks. in the default setting, the data output will follow the continuous read mode bits immediately. continuous read mode feature is also available in qpi mode for fast read quad i/o instruction. please refer to the description on prev ious pages. wrap around feature is not available in qpi mode for fast read quad i/o instruction. to perform a read operation with fixed data length wrap around in qpi mode, a dedicated burst read with wrap (0ch) instruction must be used. please refer t o 8.2.45 for details. figure 24 c . fast read quad i/ o instruction (initial instruction or previous m5 - 4 ? 10, qpi mode) 32 - bit address is required when the device is operating in 4 - byte address mode m7-0 * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 ebh 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output * "set read parameters" instruction (c0h) can set the number of dummy clocks. byte 3 instruction
w25q256fv - 55 - 8.2.21 fas t read quad i/o with 4 - byte address (ech) the fast read quad i/o with 4 - byte address instruction is similar to the fast read dual i/o instruction except that it requires 32 - bit address instead of 24 - bit address. no matter the device is operating in 3 - byte address mode or 4 - byte address mode, the fast read quad i/o with 4 - byte address instruction will always require 32 - bit address to access the entire 256mb memory. the fast read quad i/o with 4 - byte address (ech) instruction is only supported in standard sp i mode . figure 25 a . fast read quad i/ o with 4 - byte address instruction (initial instruction or previous m5 - 4 ? 10, spi mode only) m 7 - 0 / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 2 3 4 5 2 8 2 4 2 9 2 5 3 0 2 6 3 1 2 7 6 7 8 9 4 0 5 1 6 2 7 3 b y t e 1 b y t e 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 1 4 1 5 1 6 4 5 6 7 i o s s w i t c h f r o m i n p u t t o o u t p u t b y t e 3 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 d u m m y d u m m y i n s t r u c t i o n ( e c h ) 3 2 - b i t a d d r e s s
w25q256fv publication release date: february 11, 2015 - 56 - preliminary C revision h fig ure 25 b . fast read quad i/ o with 4 - byte address instruction ( previous instruction set m5 - 4 = 10, spi mode only ) fast read quad i/o with 8/16/32/64 - byte wrap around in standard spi mode the fast read quad i/o instruction can also be used to access a sp ecific portion within a page by issuing a set burst with wrap (77h) command prior to ech. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following ech commands. when wrap around is enabled, the da ta being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will w rap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed leng th (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the len gth of the wrap around section within a page. refer to section 8.2.24 for detail descriptions. m 7 - 0 / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 6 7 1 6 1 7 8 9 4 0 5 1 6 2 7 3 b y t e 1 b y t e 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 1 0 1 1 1 2 1 3 1 4 4 5 6 7 i o s s w i t c h f r o m i n p u t t o o u t p u t b y t e 3 1 5 d u m m y d u m m y 3 2 - b i t a d d r e s s 2 8 2 4 2 9 2 5 3 0 2 6 3 1 2 7
w25q256fv - 57 - 8.2.22 word read quad i/o (e7h) the word read quad i/o (e7h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lowest address bit (a0 ) must equal 0 and only two dummy clocks are required prior to the data output. the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status reg ister - 2 must be set to enable the word read quad i/o instruction . word read quad i/o with continuous read mode the word read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the in put address bits (a23/a31 - 0), as shown in figure 26 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) a re dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not require the e7h instruction code, as shown in figure 26 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal t o (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. it is recommended to input ffh/3ffh on io0 for the next instruction (8/10 clocks), to ensure m4 = 1 and retur n the device to normal operation. figure 26 a . word read quad i/ o instruction (initial instruction or previous m5 - 4 ? 10, spi mode only) 32 - bit address is required when the device is operating in 4 - by te address mode m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 dummy instruction (e7h)
w25q256fv publication release date: february 11, 2015 - 58 - preliminary C revision h figure 26 b . word read quad i/ o instruction ( previous instruction set m5 - 4 = 10, spi mode only ) 32 - bit address is required when the device is operating in 4 - byte address mode wo rd read quad i/o with 8/16/32/64 - byte wrap around in standard spi mode the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap (77h) command prior to e7h. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows th ree wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap around section within a page. see 8.2.24 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 dummy
w25q256fv - 59 - 8.2.23 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1, a2, a3) must equal 0. as a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (xip). the quad enable bit (qe) of status register - 2 must be set to enable the octal word read quad i/o instruction. octal word read quad i/o with continuous read mode the octal word read q uad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23/a31 - 0), as shown in figure 27a. the upper nibble of the (m7 - 4) controls the length of the next octal word r ead quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. i f the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not require the e3h instruction code, as shown in figure 27 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returnin g to normal operation. it is recommended to input ffh/3ffh on io0 for the next instruction (8/10 clocks), to ensure m4 = 1 and return the device to normal operation. figure 27a. octal word read quad i/o instruction ( initial instruction or previous m5 - 4 ? 10, spi mode only ) 32 - bit address is required when the device is operating in 4 - byte address mode m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 instruction (e3h) 4 0 5 1 6 2 7 3 byte 4
w25q256fv publication release date: february 11, 2015 - 60 - preliminary C revision h figure 27b. octal word read quad i/o instruction ( previous instruction set m5 - 4 = 10, spi mode only ) 32 - bit address is required when the device is operating in 4 - byte address mode m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 byte 4
w25q256fv - 61 - 8.2.24 set burst with wrap (77h) in standard spi mode, the set burst with wrap (77h) instruction is used in conjunction with fast read quad i/o and word read quad i/o instructions to access a fixed length of 8/16/32/64 - by te section within a 256 - byte page. certain applications can benefit from this feature and improve the overall system code execution performance. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24/32 dummy bits and 8 wrap bits, w7 - 0. the instruction sequence is shown in figure 28. wrap bit w7 and the lower nibble w3 - 0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length w rap around wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - byte no n/a once w6 - 4 is set by a set burst with wrap instruction, all the following fast read quad i/o and word read quad i/o instructions w ill use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon pow er on or after a software/hardware reset is 1. in qpi mode, the burst read with wrap (0ch) instruction should be used to perform the read operation with wrap around feature. the wrap length set by w5 - 4 in standard spi mode is still valid in qpi mode an d can also be re - configured by set read parameters (c0h) instruction. refer to 8.2.44 and 8.2.45 for details. figure 28. set burst with wrap instruction (spi mode only) 32 - bit dummy bits are required when the device is operating in 4 - byte address mode wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
w25q256fv publication release date: february 11, 2015 - 62 - preliminary C revision h 8.2.25 page program (02h) the page program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h followed by a 24/32 - bit address (a23/a31 - a0) and at least one data byte, into the di pin. the /cs pin must be held lo w for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 29. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) sho uld be set to 0. if the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having a ny effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /cs is driven high, the self - timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of th e busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status re gister is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (cmp, tb, bp3, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 29a. page pr ogram instruction (spi mode) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q256fv - 63 - figure 29b. page program instruction (qpi mode) 32 - bit address is required when the device is operating in 4 - byte addr ess mode /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 02h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte1 byte 2 byte 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 byte 255 byte 256 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 mode 0 mode 3 516 517 518 519
w25q256fv publication release date: february 11, 2015 - 64 - preliminary C revision h 8.2.26 quad input page program ( 3 2h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance f or prom programmer and applications that have slow clock speeds <5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock - i n the data. to use quad page program the quad enable (qe) bit in status register - 2 must be set to 1. a write enable instruction must be executed before the device will accept the quad page program instruction (status register - 1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 32h followed by a 24/32 - bit address (a23/a31 - a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instruction while data is bei ng sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 30. figure 30. quad input page program instruction (spi mode only) 32 - bit address is r equired when the device is operating in 4 - byte address mode /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
w25q256fv - 65 - 8.2.27 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the d evice will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 20h followed a 24/32 - bit sector address (a23/a31 - a0). the sector erase instru ction sequence is shown in figure 31a & 31b . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self - timed sector eras e instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase i nstruction will not be executed if the addressed page is protected by the block protect (cmp, tb, bp3, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 31a. sector erase instruction (spi mode) 32 - bit address is required when the devi ce is operating in 4 - byte address mode figure 31b. sector erase instruction (qpi mode) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 20h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 mode 0 mode 3
w25q256fv publication release date: february 11, 2015 - 66 - preliminary C revision h 8.2.28 32kb block erase (52h) the block erase instruction sets all memory within a specifie d block (32k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low a nd shifting the instruction code 52h followed a 24/32 - bit block address (a23/a31 - a0). the block erase instruction sequence is shown in figure 32a & 32b. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is no t done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status regist er instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycl e has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (cmp, tb, bp3, bp2, bp1, and bp0) bits or the individual block/ sector locks. figure 32a. 32kb block erase instruction (spi mode) 32 - bit address is required when the device is operating in 4 - byte address mode figure 32b. 32kb block erase instruction (qpi mode) 32 - bit address is required when the device is operat ing in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 52h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 mode 0 mode 3
w25q256fv - 67 - 8.2.29 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block er ase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code d8h followed a 24/32 - bit block address (a23/a31 - a0). the block erase instruction sequence is shown in figure 33a & 33b. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a t ime duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 w hen the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (cmp, tb, bp3, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 33a. 64kb block erase instruction (spi mode) 32 - bit address is required when the device is ope rating in 4 - byte address mode figure 33b. 64kb block erase instruction (qpi mode) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 d8h instruction 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 mode 0 mode 3
w25q256fv publication release date: february 11, 2015 - 68 - preliminary C revision h 8.2.30 chip erase (c7h / 60h ) the chip erase instruction sets all memor y within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low an d shifting the instruction code c7h or 60h . the chip erase instruction sequence is shown in figure 34. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self - timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any memory region is protected by the block protect (cmp, tb, bp3, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 34. chip erase instruction for spi mod e (left) or qpi mode (right) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 c7h/60h instruction mode 0 mode 3
w25q256fv - 69 - 8.2.31 erase / program suspend (75h) the erase/program suspend instruction 75h, allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program/erase data to, any other se ctors or blocks. the erase/program suspend instruction sequence is shown in figure 35a & 35b. the write status register instruction (01h) and erase instructions (20h, 52h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is valid onl y during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write status register instruction (01h) and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the page program or quad page program operation. the erase/program suspend instruction 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a se ctor or block erase or a page program operation is on - going. if the sus bit equals to 1 or the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximum of time of t sus (see ac characteristics) is required to suspend the eras e or program operation. the busy bit in the status register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase/program suspend. for a previously resumed erase/program operation, it is also required that the suspend instruction 75h is not issued earlier than a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off during the erase/program suspend state will reset the device and release th e suspend state. sus bit in the status register will also reset to 0. the data within the page, sector or block that was being suspended may become corrupted. it is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. figure 35a . erase/program suspend instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
w25q256fv publication release date: february 11, 2015 - 70 - preliminary C revision h figure 35b . erase/program suspend instruction (qpi mode) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 75h instruction mode 0 mode 3 tsus accept instructions
w25q256fv - 71 - 8.2.32 erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an erase/program suspend. the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the busy bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program resume instruction sequence is shown in figure 36a & 36b. resume instruction is ignored if the previous erase/program suspen d operation was interrupted by unexpected power off. it is also required that a subsequent erase/program suspend instruction not to be issued within a minimum of time of t sus following a previous resume instruction. figure 36a . erase/program resume in struction (spi mode) figure 36b . erase/program resume instruction (qpi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 7ah instruction mode 0 mode 3 resume previously suspended program or erase
w25q256fv publication release date: february 11, 2015 - 72 - preliminary C revision h 8.2.33 power - down (b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the power - down instruction. the lower pow er consumption makes the power - down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as shown in figure 37a & 37b . the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power - down instruction will not be executed. after /cs is driven high, the power - down state will entered within the time duration of t dp (see ac cha racteristics). while in the power - down state only the release power - down / device id (abh) instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instructio n, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers - up in the normal operation with the standby current of icc1 . figure 37a . deep power - down instruction (spi mode) figure 37b . deep power - down instruction (qpi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 b9h instruction mode 0 mode 3 tdp power-down current stand-by current
w25q256fv - 73 - 8.2.34 release power - down / device id (abh) the release from power - down / device id instruction is a multi - purpose instruction. it can be used to release the device from the power - down state , or obtain the devices electronic identification (id) number. to release the device from the power - down state, the instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in figure 38a & 38b . release from power - down will take the time duration of t res 1 (see ac characteristics) before the device will resume normal operation and other instructions are acce pted. the /cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code abh followed by 3 - dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first. the device id values for the w25q256fv is listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power - down state and obtain the device id, the instruction is the same as previously described, and shown in figure 38c & 38d , except that after /cs is driven high it m ust remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power - down / device id instruction is issued while an erase , program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 38a . release power - down instruction (spi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 abh instruction mode 0 mode 3 tres1 power-down current stand-by current
w25q256fv publication release date: february 11, 2015 - 74 - preliminary C revision h figure 38b . release power - down instruction (qpi mode) figure 38c . release power - down / device id instruction (spi mode) figure 38d . release power - down / device id instruction (qpi mode) tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb * power-down current stand-by current device id /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 abh 2 3 4 5 x x x x x x x x 6 7 8 4 0 5 1 6 2 7 3 ios switch from input to output instruction tres2 mode 0 mode 3 x x x x x x x x x x x x x x x x 3 dummy bytes
w25q256fv - 75 - 8.2.35 read manufacturer / device id (90h) the read manufacturer/device id instruction is an a lternative to the release from power - down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id inst ruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 90h followed by a 24 - bit address (a23 - a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling e dge of clk with most significant bit (msb) first as shown in figure 39 . the device id values for the w25q256fv are listed in manufacturer and device identification table. the instruction is completed by driving /cs high. figure 39 . read manufacturer / device id instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
w25q256fv publication release date: february 11, 2015 - 76 - preliminary C revision h 8.2.36 read manufacturer / device id dual i/o (92h) the read manufacturer / device id dual i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jede c assigned manufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 92h followed by a 24/32 - bit address (a23/a31 - a0) of 000000h, but with the capability to input the address bits two bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edge of clk with most significant bits (msb) first as shown in figure 40 . the device id values for the w25q256fv are listed in manufacturer and device identification table. the manufacturer and device ids can be read continuously, alternating from one to t he other. the instruction is completed by driving /cs high. figure 40 . read manufacturer / device id dual i/o instruction (spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode note: the continuous read mode bi ts m(7 - 0) must be set to fxh to be compatible with fast read dual i/o instruction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
w25q256fv - 77 - 8.2.37 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 4x speed. the read manufacturer / device id quad i/o instruction is similar to the fast read quad i/o instruction. the instruction is initiated by driving the /cs pin low and s hifting the instruction code 94h followed by a four clock dummy cycles and then a 24/32 - bit address (a23/a31 - a0) of 000000h, but with the capability to input the address bits four bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as shown in figure 41 . the device id values for the w25q256fv are listed in manufacturer and device identification table. the manufacturer and d evice ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 41 . read manufacturer / device id quad i/o instruction (spi mode only) 32 - bit address is required when the device is operatin g in 4 - byte address mode note: the continuous read mode bits m(7 - 0) must be set to fxh to be compatible with fast read quad i/o instruction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
w25q256fv publication release date: february 11, 2015 - 78 - preliminary C revision h 8.2.38 read unique id number (4bh) the read unique id number instruction accesses a factory - set read - only 64 - bit numbe r that is unique to each w25q256fv device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instructi on code 4bh followed by a four bytes of dummy clocks. after which, the 64 - bit id is shifted out on the falling edge of clk as shown in figure 42 . figure 42 . read unique id number instruction (spi mode only) 5 dummy bytes are required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
w25q256fv - 79 - 8.2.39 read jedec id (9fh) for compatibility reasons, the w25q256fv provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible with the jedec standard f or spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9fh. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id1 5 - id8) and capacity (id7 - id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 43a & 43b . for memory type and capacity values refer to manufacturer and device identification table. figure 43a . read jedec id instruction (spi mode) figure 43b . read jedec id instruction (qpi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 9fh 2 3 4 5 12 8 13 9 14 10 15 11 efh 6 4 0 5 1 6 2 7 3 id15-8 id7-0 ios switch from input to output instruction mode 0 mode 3
w25q256fv publication release date: february 11, 2015 - 80 - preliminary C revision h 8.2.40 read sfdp register (5ah) the w25q256fv features a 256 - byte serial flash discoverable parameter (sfdp) register that co ntains information about device configurations, available instructions and other features. the sfdp parameters are stored in one or more parameter identification (pid) tables. currently only one pid table is specified, but more may be added in the future. the read sfdp register instruction is compatible with the sfdp standard initially established in 2010 for pc and other applications, as well as the jedec standard jesd216 that is published in 2011. most winbond spiflash memories shipped after june 2011 (da te code 1124 and beyond) support the sfdp feature as specified in the applicable datasheet . the read sfdp instruction is initiated by driving the /cs pin low and shifting the instruction code 5ah followed by a 24 - bit address (a23 - a0) (1) into the di pin. eight dummy clocks are also required before the sfdp register contents are shifted out on the falling edge of the 40 th clk with most significant bit (msb) first as shown in figure 44 . for sfdp register values and descriptions, please refer to the winbon d application note for sfdp definition t able. note: 1. a23 - a8 = 0; a7 - a0 are used to define the starting byte address for the 256 - byte sfdp register. figure 44 . read sfdp register instruction sequence diagram (spi mode only) only 24 - bit address is requ ired when the device is operating in either 3 - byte or 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (5ah) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q256fv - 81 - 8.2.41 erase security registers (44h) the w25q256fv offers three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system ma nufacturers to store security and other important information separately from the main memory array. the erase security register instruction is similar to the sector erase instruction. a write enable instruction must be executed before the device will acce pt the erase security register instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 44h followed by a 24/32 - bit address (a23/a31 - a0) to erase one of the three securi ty registers. address {a23/a31} - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security register #3 00h 0 0 1 1 0 0 0 0 dont care the erase security register instruction se quence is shown in figure 45 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the instruction will not be executed. after /cs is driven high, the self - timed erase security register operation will commence for a time duration of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase c ycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the security register lock bits (lb3 - 1) in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, erase security register instruction to that register will be ignored (refer to section 7.1.8 for detail descriptions). figure 45 . erase security registers instruction (spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q256fv publication release date: february 11, 2015 - 82 - preliminary C revision h 8.2.42 program security registers (42h) the program security regis ter instruction is similar to the page program instruction. it allows from one byte to 256 bytes of security register data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will acce pt the program security register instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24/32 - bit address (a23/a31 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. address {a23/a31} - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byt e address security register #3 00h 0 0 1 1 0 0 0 0 byte address the program security register instruction sequence is shown in figure 46 . the security register lock bits (lb3 - 1) in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, program security register instruction to that register will be ignored (see 7.1.8, 8.2.25 for detail descriptions). figure 46 . program security registers instru ction (spi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q256fv - 83 - 8.2.43 read security registers (48h) the read security register instruction is similar to the fast read instruction and allows one or more data bytes to be seque ntially read from one of the four security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 48h followed by a 24/32 - bit address (a23/a31 - a0) and eight dummy clocks into the di pin. the code and a ddress bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out. once the byte address reaches the last byte of the register (byte address ffh), it will reset to address 00h, the first byte of the register, and continue to increm ent. the instruction is completed by driving /cs high. the read security register instruction sequence is shown in figure 47. if a read security register instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read security register instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). address {a23/a31} - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address figure 47 . read security registers instruction (spi mode only) 32 - bit address is required when the device is operatin g in 4 - byte address mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q256fv publication release date: february 11, 2015 - 84 - preliminary C revision h 8.2.44 set read parameters (c0h) in qpi mode, to accommodate a wide range of applications with different needs for either maximum read frequency or minimum data access latency, set read parameters (c0h) instruction can be used to confi gure the number of dummy clocks for fast read (0bh), fast read quad i/o (ebh) & burst read with wrap (0ch) instructions, and to configure the number of bytes of wrap length for the burst read with wrap (0ch) instruction. in standard spi mode, the set read parameters (c0h) instruction is not accepted. the dummy clocks for various fast read instructions in standard/dual/quad spi mode are fixed, please refer to the instruction table 1 - 3 for details. the wrap length is set by w5 - 4 bit in the set burst with wrap (77h) instruction. this setting will remain unchanged when the device is switched from standard spi mode to qpi mode. the default wrap length after a power up or a reset instruction is 8 bytes, the default number of dummy clocks is 2. th e number of dummy clocks is only programmable for fast read (0bh), fast read quad i/o (ebh) & burst read with wrap (0ch) instructions in the qpi mode. whenever the device is switched from spi mode to qpi mode, the number of dummy clocks should be set again, prior to any 0bh, ebh or 0ch instructions. p5 C p4 dummy clocks maximum read freq. maximum read freq. (a[1:0]=0,0) maximum read freq. (a[1:0]=0,0 vcc=3.0v~3.6v) p1 C p0 wrap length 0 0 2 33mhz 33mhz 40mhz 0 0 8 - byte 0 1 4 55mhz 80mhz 80mhz 0 1 16 - byte 1 0 6 80mhz 80mhz 104mhz 1 0 32 - byte 1 1 8 80mhz 80mhz 104mhz 1 1 64 - byte figure 48 . set read parameters instruction (qpi mode only) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 c0h 2 3 read parameters p4 p0 p5 p1 p6 p2 p7 p3 instruction mode 0 mode 3
w25q256fv - 85 - 8.2.45 burst read with wrap (0ch) the burst read with wrap (0ch) instruct ion provides an alternative way to perform the read operation with wrap around in qpi mode. the instruction is similar to the fast read (0bh) instruction in qpi mode, except the addressing of the read operation will wrap around to the beginning bound ary of the wrap length once the ending boundary is reached. the wrap length and the number of dummy clocks can be configured by the set read parameters (c0h) instruction. figure 49 . burst read with wrap instruction (qpi mode only) 32 - bit address is required when the device is operating in 4 - byte address mode dummy * /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 0ch 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output * "set read parameters" instruction (c0h) can set the number of dummy clocks. byte 3 instruction
w25q256fv publication release date: february 11, 2015 - 86 - preliminary C revision h 8.2.46 enter qpi mode (38h) the w25q256fv support both standard/dual/quad serial peripheral interface (spi) and quad peripheral interface (qpi). however, spi mode and qpi mode cannot be used at the same time. enter qpi (38h) instruction is the only way to switch the device from spi mode to qpi mode. upon power - up, the default state of the device upon is standard/dual/quad spi mode. this provides full backward compatibil ity with earlier generations of winbond serial flash memories. see instruction set table 1 - 3 for all supported spi commands. in order to switch the device to qpi mode, the quad enable (qe) bit in status register - 2 must be set to 1 first, and an enter qpi (38h) instruction must be issued. if the quad enable (qe) bit is 0, the enter qpi (38h) instruction will be ignored and the device will remain in spi mode. see instruction set table 4 - 6 for all the commands supported in qpi mode. when the device is swit ched from spi mode to qpi mode, the existing write enable and program/erase suspend status, and the wrap length setting will remain unchanged. figure 50 . enter qpi instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (38h) high impedance mode 0 mode 3
w25q256fv - 87 - 8.2.47 exit qpi mode (ffh) in order to e xit the qpi mode and return to the standard/dual/quad spi mode, an exit qpi (ffh) instruction must be issued. when the device is switched from qpi mode to spi mode, the existing write enable latch (wel) and program/erase suspend status, and the wrap leng th setting will remain unchanged. figure 51 . exit qpi instruction (qpi mode only) /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 ffh instruction mode 0 mode 3
w25q256fv publication release date: february 11, 2015 - 88 - preliminary C revision h 8.2.48 individual block/sector lock (36h) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/ program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will be determined by the combination of cmp, tb, bp[3:0] bits in the status registers. the individual block/secto r lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to lock a specific block or sector as illustrated in figure 4d, an individual block/sector lock command must be i ssued by driving /cs low, shifting the instruction code 36h into the data input (di) pin on the rising edge of clk, followed by a 24/32 - bit address and then driving /cs high. figure 52a. individual block/sector lock instruction (spi mode) 32 - bit addre ss is required when the device is operating in 4 - byte address mode figure 52b. individual block/sector lock instruction (qpi mode) 32 - bit address is required when the device is operating in 4 - byte address mode / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 6 h ) h i g h i m p e d a n c e 8 9 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 3 2 2 2 1 0 * m o d e 0 m o d e 3 = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 3 6 h i n s t r u c t i o n 2 3 4 5 2 0 1 6 1 2 8 2 1 1 7 2 2 1 8 2 3 1 9 1 3 9 1 4 1 0 1 5 1 1 a 2 3 - 1 6 6 7 4 0 5 1 6 2 7 3 a 1 5 - 8 a 7 - 0 m o d e 0 m o d e 3
w25q256fv - 89 - 8.2.49 individual block/sector unlock (39h) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will be d etermined by the combination of cmp, tb, bp[3:0] bits in the status registers. the individual block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to unloc k a specific block or sector as illustrated in figure 4d, an individual block/sector unlock command must be issued by driving /cs low, shifting the instruction code 39h into the data input (di) pin on the rising edge of clk, followed by a 24/32 - bit addre ss and then driving /cs high. figure 53a. individual block unlock instruction (spi mode) 32 - bit address is required when the device is operating in 4 - byte address mode figure 53b. individual block unlock instruction (qpi mode) 32 - bit address is requ ired when the device is operating in 4 - byte address mode / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 9 h ) h i g h i m p e d a n c e 8 9 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 3 2 2 2 1 0 * m o d e 0 m o d e 3 = m s b * / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 3 9 h i n s t r u c t i o n 2 3 4 5 2 0 1 6 1 2 8 2 1 1 7 2 2 1 8 2 3 1 9 1 3 9 1 4 1 0 1 5 1 1 a 2 3 - 1 6 6 7 4 0 5 1 6 2 7 3 a 1 5 - 8 a 7 - 0 m o d e 0 m o d e 3
w25q256fv publication release date: february 11, 2015 - 90 - preliminary C revision h 8.2.50 read block/sector lock (3dh) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will be determined by the combination of cmp, tb, bp[3:0] bits in the status registers. the individual block/sector lock bits are volatile bits. the default values after devi ce power up or after a reset are 1, so the entire memory array is being protected. to read out the lock bit value of a specific block or sector as illustrated in figure 4d, a read block/sector lock command must be issued by driving /cs low, shifting the i nstruction code 3dh into the data input (di) pin on the rising edge of clk, followed by a 24/32 - bit address. the block/sector lock bit value will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in fi gure 54. if the least significant bit (lsb) is 1, the corresponding block/sector is locked; if lsb=0, the corresponding block/sector is unlocked, erase/program operation can be performed. figure 54a. read block lock instruction (spi mode) 32 - bit address is required when the device is operating in 4 - byte address mode figure 54b. read block lock instruction (qpi mode) 32 - bit address is required when the device is operating in 4 - byte address mode / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 d h ) h i g h i m p e d a n c e 8 9 1 0 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 x x x x x x x 0 2 4 - b i t a d d r e s s 2 3 2 2 2 1 3 2 1 0 l o c k v a l u e o u t * * = m s b * m o d e 0 m o d e 3 / c s c l k m o d e 0 m o d e 3 0 1 i o 0 i o 1 i o 2 i o 3 3 d h 2 3 4 5 2 0 1 6 1 2 8 2 1 1 7 2 2 1 8 2 3 1 9 1 3 9 1 4 1 0 1 5 1 1 a 2 3 - 1 6 6 7 8 9 4 0 5 1 6 2 7 3 a 1 5 - 8 a 7 - 0 l o c k v a l u e x 0 x x x x x x i o s s w i t c h f r o m i n p u t t o o u t p u t i n s t r u c t i o n m o d e 0 m o d e 3
w25q256fv - 91 - 8.2.51 globa l block/sector lock (7eh) all block/sector lock bits can be set to 1 by the global block/sector lock instruction. the command must be issued by driving /cs low, shifting the instruction code 7eh into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 55. global block lock instruction for spi mode (left) or qpi mode (right) 8.2.52 global block/sector unlock (98h) all block/sector lock bits can be set to 0 by the global block/sector unlock instruction. the command must be is sued by driving /cs low, shifting the instruction code 98h into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 56. global block unlock instruction for spi mode (left) or qpi mode (right) / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( 7 e h ) h i g h i m p e d a n c e / c s c l k m o d e 0 m o d e 3 0 1 m o d e 0 m o d e 3 i o 0 i o 1 i o 2 i o 3 7 e h i n s t r u c t i o n / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( 9 8 h ) h i g h i m p e d a n c e / c s c l k m o d e 0 m o d e 3 0 1 m o d e 0 m o d e 3 i o 0 i o 1 i o 2 i o 3 9 8 h i n s t r u c t i o n
w25q256fv publication release date: february 11, 2015 - 92 - preliminary C revision h 8.2.53 enable reset (66h) and reset device (99h) because of the small package and the limitation on the number of pins, the w25q256fv provide a software reset instruction instead of a dedicated reset pin. once the reset instruction is accepted, any on - going internal operations will be terminated and the device will return to its default power - on state and lose all the current volatile settings, such as volatile status register bits, write enable latch (wel) status, program/erase suspend status, read parameter setting (p7 - p0), continuou s read mode bit setting (m7 - m0) and wrap bit setting (w6 - w4). enable reset (66h) and reset (99h) instructions can be issued in either spi mode or qpi mode. to avoid accidental reset, both instructions must be issued in sequence. any other commands othe r than reset (99h) after the enable reset (66h) command will disable the reset enable state. a new sequence of enable reset (66h) and reset (99h) is needed to reset the device. once the reset command is accepted by the device, the device will ta ke approximately trst=30us to reset. during this period, no command will be accepted. data corruption may happen if there is an on - going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommend ed to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 57a . enable reset and reset instruction sequence (spi mode) figure 57b . enable reset and reset instruction sequen ce (qpi mode) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (99h) mode 0 mode 3 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (66h) high impedance mode 0 mode 3 0 1 99h instruction mode 0 mode 3 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 66h instruction
w25q256fv - 93 - 9. electrical character istics 9.1 absolute maximum ratings (1) (2) parameters symbol conditions range unit supply voltage vcc C 0.6 to 4.6v v voltage applied to any pin v io relative to ground C 0.6 to vcc+0.4 v transient voltage on any pin v iot <2 0ns transient relative to ground C 2.0v to vcc+2.0v v storage temperature t stg C 65 to +150 c lead temperature t lead ( 3 ) see note ( 3 ) c electrostatic discharge voltage v esd ( 2 ) human body model C 2000 to +2000 v notes: 1.this device has been designed a nd tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 2. jedec std j esd22 - a114a (c1=100pf, r1=1500 ohms, r2=500 ohms). 3.compliant with jedec standard j - std - 20c for small body sn - pb or pb - free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 9.2 operating ranges parameter symb ol conditions spec unit min ma x supply voltage vcc (1) f r = 104 mhz, f r = 50 mhz 2.7 3.6 v ambient temperature, operating t a industrial C 40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q256fv publication release date: february 11, 2015 - 94 - preliminary C revision h 9.3 power - up timing and write inhibit threshold ( 1 ) parameter symbol spec unit min max vcc (min) to /cs low t vsl 20 s time delay before write instruction t puw 5 ms write inhibit threshold voltage v wi 1.0 2.0 v note: 1. these parameters are characterized only. figure 5 8 . power - up timing and voltage levels figure 58 b. power - up, power - down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time vcc time / cs must track vcc during vcc ramp up / down / cs
w25q256fv - 95 - 9.4 dc electrical characteristics param eter symbol conditions spec unit min typ max input capacitance c in ( 1 ) v in = 0v 6 pf output capacitance cout ( 1 ) v out = 0v 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 10 5 0 a power - down current i cc 2 /cs = vcc, vin = gnd or vcc 1 25 a current read data / dual /quad 50mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 15 ma current read data / dual /quad 80mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 18 ma current read data / dual output read /quad output read 104mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 20 ma current write status register i cc 4 /cs = vcc 8 12 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma cur rent chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il C 0.5 vcc x 0.3 v input high voltage v ih vcc x 0.7 vcc + 0.4 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = C 100 a vcc C 0.2 v notes: 1. tested on sam ple basis and specified through design and characterization data. ta = 25 c, vcc = 3.0 v. 2. checker board pattern.
w25q256fv publication release date: february 11, 2015 - 96 - preliminary C revision h 9.5 ac measurement conditions ( 1 ) parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0. 1 vcc to 0. 9 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0. 5 vcc to 0. 5 vcc v note: 1. output hi - z is defined as the point where data out is no longer driven. figure 5 9 . ac measurement i/o waveform input and output timing reference levels input levels 0.9 vcc 0.1 vcc 0.5 vcc
w25q256fv - 97 - 9.6 ac electrical characteristics (6) description symbol alt spec unit min typ max clock frequency for all other instructions 2.7v - 3.6v vcc & industrial temperature except read data instruction s (03h) f r f c1 d.c. 104 mhz clock frequency for read data instruction ( 03h ) f r f c 2 d.c. 50 mhz clock high, low time for all instructions except for read data (03h) t clh , t cll ( 1) 4 ns clock high, low time for read data (03h) instruction t crlh , t crl l ( 1) 8 ns clock rise time peak to peak t clch ( 2) 0.1 v/ns clock fall time peak to peak t chcl ( 2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 3 ns /cs active hold time relative to clk t chsh 3 ns /cs not active setup time relative to clk t shch 3 ns /cs deselect time (for erase or program ? t shsl t csh 50 ns output disable time t shqz ( 2) t dis 7 ns clock low to output valid t clqv t v 7 ns output hold time t clqx t ho 2 ns /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns continued C next page
w25q256fv publication release date: february 11, 2015 - 98 - preliminary C revision h ac electrical characteristics (contd) description symbol alt spec unit min typ max /hold to output low - z t hhqx ( 2) t lz 7 ns /hold to output high - z t hlqz ( 2) t hz 12 n s write protect setup time before /cs low t whsl ( 3) 20 ns write protect hold time after /cs high t shwl ( 3) 100 ns /cs high to power - down mode t dp ( 2) 3 s /cs high to standby mode without id read t res 1 ( 2) 3 s /cs high to standby mode with i d read t res 2 ( 2) 1.8 s /cs high to next instruction after suspend t sus ( 2) 20 s /cs high to next instruction after reset t sus ( 2) 30 s /reset pin low period to reset the device t r s t ( 2) (5) 1 s write status register time t w 10 15 ms byte program time (first byte) t bp1 (4 ) 30 50 s additional byte program time (after first byte) t bp2 (4 ) 2.5 12 s page program time t pp 0.7 3 ms sector erase time (4kb) w25q 256 fvxxig t se 10 0 400 ms w25q 256 fvxxiq w25q 256 fvxxi f 45 block e rase time ( 32 kb) t be 1 120 1,6 00 ms block erase time (64kb) t be 2 150 2 ,000 ms chip erase time t ce 8 0 4 0 0 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when srp[1:0]=(0,1) . 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes pro grammed. 5. it s possible to reset the device with shorter t reset (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation. 6. 4 - bytes address alignment for qpi/quad read
w25q256fv - 99 - 9.7 serial output timing 9.8 ser ial input timing 9.9 /hold timing 9.10 /wp timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
w25q256fv publication release date: february 11, 2015 - 100 - preliminary C revision h 10. package specificatio ns 10.1 8 - pad wson 8x6 - mm (package code e) symbol millimeters inches min nom max min nom max a 0.70 0.7 5 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.008 ref --- d 7.90 8.00 8.10 0.311 0.315 0.319 d2 3.35 3.40 3.45 0.1 32 0.1 34 0.1 36 e 5.90 6.00 6.10 0.232 0.236 0.240 e2 4.25 4. 30 4.35 0. 167 0. 169 0. 171 e --- 1.27 --- --- 0. 050 --- l 0.45 0.50 0.55 0.018 0.020 0.022 y 0.00 --- 0.050 0.000 --- 0.002
w25q256fv - 101 - symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.008 ref --- d 7.90 8.00 8.10 0.311 0.315 0.319 d2 3.35 3.40 3.45 0.1 32 0.1 34 0.1 36 e 5.90 6.00 6.10 0.232 0.236 0.240 e2 4.25 4.30 4.35 0. 167 0. 169 0. 171 e --- 1.27 --- --- 0. 050 --- l 0.45 0.50 0.55 0.018 0.020 0.022 y 0.00 --- 0.050 0.000 --- 0.002 note: the metal pad area on the bottom center of the package is not connected to any internal electrical signals. it can be left floating or connected to t he device ground (gnd pin). avoid placement of exposed pcb vias under the pad .
w25q256fv publication release date: february 11, 2015 - 102 - preliminary C revision h 10.2 16 - pin soic 300 - mil (package code f) symbol millimeters inches min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 --- 0.30 0.004 --- 0.012 a2 --- 2.31 --- --- 0.091 --- b 0.33 0 .41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e1 7.39 7.49 7.59 0.291 0.295 0.299 e 1.27 bsc 0.050 bsc l 0.38 0.81 1.27 0.015 0.032 0.050 y --- --- 0. 10 --- --- 0.00 4 0 --- 8 0 --- 8
w25q256fv - 103 - 10.3 24 - ball tfbga 8x6 - mm (package code b, 5x5 - 1 ball array) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.010 0.012 0.014 a2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.90 8.00 8.10 0.311 0.315 0.319 d1 4.00 bsc 0.157 bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 4.00 bsc 0.157 bsc se 1.00 typ 0.039 typ sd 1.00 typ 0.039 typ e 1.00 bsc 0.039 bsc n ote: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q256fv publication release date: february 11, 2015 - 104 - preliminary C revision h 10.4 24 - ball tfbga 8x6 - mm (pac kage code c, 6x4 ball array) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.010 0.012 0.014 b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.95 8.00 8.05 0.313 0.315 0.317 d1 5.00 bsc 0.197 bsc e 5.95 6.00 6.05 0.234 0.236 0.238 e1 3.00 bsc 0.118 bsc e 1.00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q256fv - 105 - 11. ordering information notes: 1. the w prefix and the temperature designator i are not included on the part marking. 2. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (shape t) or tray (shape s), when placing orders. 3. for shipments with otp enabled feature , please contact winbond . w (1) 25q 256f v x i (1) w = winbond 25 q = s pi flash serial flash memory with 4 kb se ctors, dual /quad i/o 256f = 256m - bit v = 2.7v to 3.6v f = 16 - pin soic 300 - mil e = 8 - pad wson 8x6 mm b = 24 - ball tfbga 8x6 - mm (5x5 ball array) c = 24 - ball tfbga 8x6 - mm (6x4 ball array) i = industrial ( - 40 c to + 85c) ( 2,3 ) g = green package (lead - free, rohs compliant, halogen - free (tbba), antimony - oxide - free sb 2 o 3 ) f = green package with fast sector erase time (tse) q = green package with qe=1 in status register - 2
w25q256fv publication release date: february 11, 2015 - 106 - preliminary C revision h 11.1 valid part numbers and top side marking the following table provides the va lid part numbers for the w25q256fv spiflash memory. please contact winbond for specific availability by density and package type. winbond spiflash memories use a 12 - digit product number for ordering. however, due to limited space, the top side marking on a ll packages uses an abbreviated 10 - digit number. package type density product number top side marking f soic - 16 300mil 256m - bit w25q256fvfig w25q256fvfi q w25q256fvfi f 25q256fvfg 25q256fvf q 25q256fv ff e wson - 8 8x6mm 256m - bit w25q256fveig w25q256fvei f W25Q256FVEIQ 25q256fveg 25q256fve f 25q256fveq b tfbga - 24 8x6mm (5x5 - 1 ball array) 256m - bit w25q256fvbig w25q256fvbi f 25q256fvbg 25q256fvb f c tfbga - 24 8x6mm (6x 4 ball array) 256m - bit w25q256fvcig w25q256fvci f 25q256fvcg 25q256fvc f
w25q256fv - 107 - 12. revision history version date page description a 0 3 / 2 3 /2011 new create preliminary b 07/ 21 /2011 26 - 27, 29, 92 81 - 82 99 - 100 updated read sector/block lock instruction code upd ated sfdp table updated ac parameters c 0 6 / 06 /2012 9 , 1 3 , 9 8 80 9 8 100 104 - 105 updated reset descriptions referred to sfdp definition application note updated erase time updated wson metal pad size added q order option d 03/15/2013 94 98 104,105 added p ower - down requirement modified the t se of w25q 256 fvxxiq & if added w25q256 fvxxif into order information e 0 4 /1 2 /2013 98 modified the t se of w25q 256 fvxxiq & if f 0 4 / 2 9 /2013 18 19 93 added quad enable default description added description of drv default setting modified the typo of supply voltage g 12/02/2014 6 ,102 101 106 105 - 106 updated soic - 16 package information updated note for metal pad for wson, uson updated W25Q256FVEIQ information updated otp enable, please contact winbond h 02/11/2015 6 - 7 upd ated ball and pin note description trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmen tal damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is p rovided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

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