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lt c3884 1 3884fb for more information www.linear.com/ltc3884 typical application features description dual output polyphase step-down controller with sub-milliohm dcr sensing and digital power system management the ltc ? 3884 is a dual output polyphase dc/dc synchro - nous step-down switching regulator controller with an i 2 c-based pmbus compliant serial interface . the controller employs a constant-frequency current mode architecture, together with a unique scheme to provide excellent perfor - mance for sub-milliohm dcr applications. the ltc3884 is supported by the ltpowerplay ? software development tool with graphical user interface (gui). programmable loop compensation allows the controller to be compensated digitally. switching frequency, channel phas - ing output voltage, and device address can be programmed both by the digital interface as well as external configura - tion resistors. additionally , parameters can be set via the digital inter face or stored in eeprom. both outputs have independent power good indicators and fault function. the ltc3884 can be configured for discontinuous (pulse- skipping) mode or continuous inductor current mode. applications n pmbus/i 2 c compliant serial interface C telemetry read-back includes v in , i in , v out , i out , temperature and faults C programmable voltage, current limit, digital soft- start/stop, sequencing, margining, ov/uv/oc n sub-milliohm dcr current sensing n digitally adjustable loop compensation parameters n 0.5% output voltage accuracy over temperature n integrated input current sense amplifier n internal eeprom and fault logging n integrated n-channel mosfet gate drivers power conversion n wide v in range : 4.5 v to 38 v n v out range : 0.5 v to 3.5 v ( with low dcr setting); 0.5v to 5.5 v ( without low dcr setting) n accurate polyphase ? current sharing for up to 6 phases n available in a 48- lead (7 mm 7 mm) qfn package n telecom, datacom, and storage systems n industrial and point-of-load applications l , lt, ltc, ltm, polyphase, ltpowerplay, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150, 7420359, 8648623, 8786265, 8823352, 7000125. licensed under u.s. patent 7000125 and other related patents worldwide. efficiency and power loss vs load current intv cc tg0 tg1 boost0 boost1 sw0 sw1 bg0 fault management to/from other ltc devices sdascl alert run0 run1 v sense0 + v sense0 C tsns0i th0 i thr0 v sense1 + v sense1 C tsns1 i th1 i thr1 fault0 fault1 pgood0pgood1 bg1 extv cc share_clk 0.22f 1f 220pf 10nf 10nf v out1 1v30a 330f 2 330f 2 3884 ta01a 4700pf v out0 1.5v 30a 2200pf *some details omitted for clarity 0.22f 931 931 i sense0 + i sense1 + i sense0 C i sense1 C pmbus interface 4.7f 10f 2 10f2 2m 1f 270f2 1 v in 4.5v to 15v 0.1f 0.1f dcr= 0.32m l = 0.33h dcr= 0.32m v in ltc3884* sgnd pgnd v dd33 v dd25 i in + i in C 1f 220pf l= 0.33h v in = 12v v out = 1.8v extv cc =0 f sw= 350khz efficiency power loss load current (a) 0 5 10 15 20 25 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 efficiency (%) power loss (w) 3884 ta01b downloaded from: http:///
lt c3884 2 3884fb for more information www.linear.com/ltc3884 table of contents features ..................................................... 1 applications ................................................ 1 typical application ........................................ 1 description.................................................. 1 table of contents .......................................... 2 absolute maximum ratings .............................. 4 order information .......................................... 4 pin configuration .......................................... 4 electrical characteristics ................................. 5 typical performance characteristics .................. 11 pin functions .............................................. 15 block diagram ............................................. 17 operation................................................... 18 overview ................................................................. 18 main control loop .................................................. 19 eeprom ................................................................. 19 power-up and initialization ..................................... 20 soft-start ................................................................ 20 time-based sequencing ......................................... 21 voltage-based sequencing ..................................... 21 shutdown ............................................................... 22 light-load current operation ................................. 22 switching frequency and phase ............................. 22 pwm loop compensation ...................................... 23 output voltage sensing .......................................... 23 intv cc /extv cc power ........................................... 23 output current sensing and sub milliohm dcr current sensing ...................................................... 24 input current sensing ............................................. 25 polyphase load sharing ......................................... 25 external/internal temperature sense ...................... 25 rconfig (resistor configuration) pins .................. 26 fault detection and handling .................................. 27 status registers and alert masking ................. 27 mapping faults to fau lt pins ............................ 29 power good pins ................................................ 29 crc protection ................................................... 29 serial interface ....................................................... 29 communication protection ................................. 29 device addressing .................................................. 29 responses to v out and i in /i out faults ................... 30 output overvoltage fault response ................... 30 output undervoltage response .......................... 31 peak output overcurrent fault response ........... 31 responses to timing faults .................................... 31 responses to v in ov faults .................................... 31 responses to ot/ut faults ..................................... 31 internal overtemperature fault response .......... 31 external overtemperature and undertemperature fault response ................................................... 32 responses to input overcurrent and output undercurrent faults ................................................ 32 responses to external faults .................................. 32 fault logging .......................................................... 32 bus timeout protection .......................................... 32 similarity between pmbus, smbus and i 2 c 2- wire interface ................................................................. 33 pmbus serial digital interface ................................ 33 pmbus command summary ............................ 38 pmbus commands ................................................. 38 *data format .......................................................... 43 applications information ................................ 44 current limit programming .................................... 44 i sen se0 and i sen se1 pins ...................................... 44 inductor dcr sensing ........................................ 45 inductor value calculation ...................................... 46 inductor core selection .......................................... 46 low value resistor current sensing ....................... 46 slope compensation and inductor peak current .... 47 power mosfet and optional schottky diode selection ................................................................. 48 variable delay time, soft-start and output voltage ramping ................................................................. 48 digital servo mode ................................................. 49 soft off (sequenced off) ........................................ 50 intv cc /extv cc power ........................................... 50 topside mosfet driver supply (c b , d b ) ................ 51 undervoltage lockout ............................................. 52 c in and c out selection ........................................... 52 downloaded from: http:///
lt c3884 3 3884fb for more information www.linear.com/ltc3884 table of contents fault indication .................................................... 53 open-drain pins ..................................................... 53 phase-locked loop and frequency synchronization .................................... 54 minimum on-time considerations .......................... 55 external temperature sense ................................... 55 input current sense amplifier ................................. 56 external resistor configuration pins (rconfig) .... 56 voltage selection ................................................ 57 frequency selection ........................................... 57 phase selection .................................................. 58 address selection using rconfig ..................... 58 efficiency considerations ....................................... 59 programmable loop compensation ....................... 59 checking transient response ................................. 60 polyphase configuration .................................... 61 master slave operation ...................................... 61 pc board layout checklist ..................................... 64 pc board layout debugging ................................... 64 design example ...................................................... 65 additional design checks ....................................... 66 connecting the usb to i 2 c/smbus/pmbus controller to the lt c3884 in system ...................................... 66 ltpowerplay : an interactive gui for digital power . 67 pmbus communication and command processing 67 pmbus command details ............................... 70 addressing and write protect ................................. 70 general configuration commands .......................... 72 on/off/margin ........................................................ 73 pwm configuration ................................................ 75 voltage .................................................................... 78 input voltage and limits ..................................... 78 output voltage and limits .................................. 79 output current and limits ...................................... 82 input current and limits .................................... 84 temperature ............................................................ 85 external temperature calibration ........................ 85 timing .................................................................... 86 timing on sequence/ramp ............................. 86 timing off sequence/ramp ............................ 87 precondition for restart ..................................... 88 fault response ....................................................... 88 fault responses all faults .................................. 88 fault responses input voltage ........................... 89 fault responses output voltage ......................... 89 fault responses output current ......................... 92 fault responses ic temperature ........................ 93 fault responses external temperature ............... 94 fault sharing ........................................................... 95 fault sharing propagation .................................. 95 fault sharing response ...................................... 97 scratchpad ............................................................. 97 identification ........................................................... 98 fault warning and status ........................................ 99 telemetry .............................................................. 105 nvm memory commands .................................... 109 store/restore ................................................... 109 fault logging .................................................... 110 block memory write/read ................................ 114 typical applications .................................... 115 package description ................................... 120 revision history ........................................ 121 typical application ..................................... 122 related parts ............................................ 122 downloaded from: http:///
lt c3884 4 3884fb for more information www.linear.com/ltc3884 pin configuration absolute maximum ratings v in , i in + , i in C .............................................. C 0.3v to 40v (v in Ci in + ), (i in + Ci in C ) ................................ C 0.3v to 0.3v boost0, boost1 ...................................... C 0.3v to 46v switch transient voltage (sw0, sw1) .......... C 5v to 40v i sen se0 + , i sen se0 C , i sen se1 + , i sen se1 C , v sen se0 + , v sen se1 + ...................................... C 0.3v to 6v v sen se0 C , v sen se1 C ................................... C 0.3v to 0.3v (boost0-sw0), (boost1-sw1) ................. C 0.3v to 6v extv cc , intv cc ........................................... C 0.3v to 6v pgoo d0 , pgoo d1 .................................... C 0.3v to 3.6v ru n0 , ru n1 , sda, scl, alert ................ C 0.3v to 5.5v ase l0 , ase l1 , v out0_cf g0 , v out1_cfg , freq_cfg , phase_cfg ............................................ C 0.3v to 2.75v fa u lt0 , fa u lt1 , share_clk , wp, sync C 0.3v to 3.6v tsn s0 , tsn s1 .......................................... C 0.3v to 2.2v i t h0 , i t h1 , i th_ r0 , i th_ r1 ........................... C 0.3v to 2.7v operating junction temperature range (notes 2, 17, 18) ....................................... C 40 c to 125 c storage temperature range .................. C 40 c to 125 c (note 1) top view 49 sgnd uk package 48-lead (7mm 7mm) plastic qfn v sense0 + 1 v sense0 C 2 i sense1 + 3 i sense1 C 4 i th_r0 5 i th0 6 i sense0 + 7 i sense0 C 8 tsns1 9 tsns0 10 sync 11 scl 12 36 boost135 tg1 34 sw1 33 pgood1 32 v sense1 + 31 v sense1 C 30 i th_r1 29 i th1 28 v dd33 27 share_clk26 wp 25 v dd25 48 pgood047 i in C 46 i in + 45 sw044 tg0 43 boost0 42 bg0 41 pgnd 40 extv cc 39 v in 38 intv cc 37 bg1 sda 13 alert 14 fault0 15 fault1 16 run0 17 run1 18 asel0 19 asel1 20 v out0_cfg 21 v out1_cfg 22 freq_cfg 23 phase_cfg 24 t jmax = 125c, ja = 31c/w, jc = 3c/w exposed pad (pin 49) is sgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc3884euk#pbf ltc3884euk#trpbf ltc3884 uk 48-lead (7mm 7mm) plastic qfn C40c to 125c ltc3884iuk#pbf ltc3884iuk#trpbf ltc3884 uk 48-lead (7mm 7mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. ( http://www.linear.com/product/ltc3884#orderinfo ) downloaded from: http:///
lt c3884 5 3884fb for more information www.linear.com/ltc3884 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (notes 2, 3). v in = 12v, extv cc = 0v, v run0,1 = 3.3v, f sync = 500khz (externally driven) and all programmable parameters at factory default, unless otherwise specified. symbol parameter condition min typ max units input voltage v in input voltage range (note 11) l 4.5 38 v i q input voltage supply current v run0,1 = 3.3v (note 16) v run0,1 = 0v (note 16) 25 23 ma ma v uvlo undervoltage lockout threshold when v in > 4.3v v intvcc falling v intvcc rising 3.55 3.90 v v t init initialization time time from v in applied until the ton_delay timer starts 65 ms t off(min) short cycle retry time 120 ms control loopv outrl full-scale voltage range set point accuracy (0.6v ~ 2.5v) resolution lsb step size vout_command = 2.75v, mfr_pwm_mode[1] = 1 (notes 9, 10, 13) l l 2.7 C0.5 12 0.688 2.8 0.5 v % bits mv v outrh full-scale voltage range set point accuracy (0.6v ~ 5.0v) resolution lsb step size vout_command = 5.5v, mfr_pwm_mode[1] = 0 (notes 9, 10, 13) l l 5.40 C0.5 12 1.375 5.60 0.5 v % bits mv v linereg line regulation 6v < v in < 38v l 0.02 %/v v loadreg load regulation ? v ith = 1.35v ~ 0.7v ? v ith = 1.35v ~ 2v l l 0.01 C0.01 0.1 C0.1 % % i isense0,1 input pin bias current 0v v pin 5.5v l 1 3 a v senserin0,1 v sense input resistance to gnd 0v v pin 5.5v 50 k v ilimit n 12 steps v ilim_high v ilim_low v rev mfr_pwm_mode [7],[2 ]= 0, 1, i lim [3:0 ]= 1100, v out 3.5v (note 15) mfr_pwm_mode [7],[2 ]= 0, 1, i lim [3:0 ]= 0001, v out 3.5v mfr_pwm_mode [7],[2 ]= 0, 1, v out v ov l 14.5 16.5 9.5 C7.5 18.5 mv mv mv v ilim_high v ilim_low v rev mfr_pwm_mode [7 ][ 2 ]= 1, 1, i lim [3:0 ]=1100,v out 3.5v mfr_pwm_mode [7 ][ 2 ]= 1, 1, i lim [3:0 ]=0001,v out 3.5v mfr_pwm_mode [7 ][ 2 ]= 1, 1, v out v ov l 27.0 29.5 17.0 C15 31.0 mv mv mv v ilim_high v ilim_low v rev mfr_pwm_mode [7 ][ 2 ]= 0, 0, i lim [3:0 ]=1100 mfr_pwm_mode [7 ][ 2 ]= 0, 0, i lim [3:0 ]=0001 mfr_pwm_mode [7 ][ 2 ]= 0, 0, v out v ov l 35 42 25 C18.8 49 mv mv mv v ilim_high v ilim_low v rev mfr_pwm_mode [7 ][ 2 ]= 1, 0, i lim [3:0 ]=1100 mfr_pwm_mode [7 ][ 2 ]= 1, 0, i lim [3:0 ]=0001 mfr_pwm_mode [7 ][ 2 ]= 1, 0, v out v ov l 67.5 74.5 43.5 C37.5 81.5 mv mv mv g m0,1 resolution error amplifier g m(max) error amplifier g m(min) lsb step size i th0,1 = 1.35v, mfr_pwm_config[7:5] = 0 to 7 3 5.76 1 0.68 bits mmho mmho mmho r th0, 1 resolution compensation resistor r th(max) compensation resistor r th(min) mfr_pwm_config[4:0] = 0 to 31 (see figure 1) 5 70 0.5 bits k k gate drivers tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 2.4 downloaded from: http:///
lt c3884 6 3884fb for more information www.linear.com/ltc3884 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (notes 2, 3). v in = 12v, extv cc = 0v, v run0,1 = 3.3v, f sync = 500khz (externally driven) and all programmable parameters at factory default, unless otherwise specified. symbol parameter condition min typ max units bg r down bg pull-down r ds(on) bg low 1.1 tg t r t f tg transition time: rise time fall time (note 4) c load = 3300pf c load = 3300pf 30 30 ns ns bg t r t f bg transition time: rise time fall time (note 4) c load = 3300pf c load = 3300pf 30 30 ns ns tg/bg, t 1d top gate off to bottom gate on delay time (note 4) c load = 3300pf at each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay time (note 4) c load = 3300pf at each driver 30 ns t on(min) minimum on-time 90 ns ov/uv output voltage supervisor channel 0/1 n resolution 9 bits v oustpsp_rl lsb step size mfr_pwm_mode[1] = 1 (note 13) 5.6 mv v oustpsp_rh lsb step size mfr_pwm_mode[1] = 0 (note 13) 11.2 mv v range_rl voltage monitoring range mfr_pwm_mode[1] = 1 0.5 2.7 v v range_rh voltage monitoring range mfr_pwm_mode[1] = 0 1 5.6 v v thac0_rl threshold accuracy 1v < v out < 2.5v mfr_pwm_mode[1] = 1 l 1.5 % v thac1_rh threshold accuracy 2v < v out < 5.5v mfr_pwm_mode[1] = 0 l 1.5 % t propov ov comparator response time v od = 10% of threshold 100 s t propuv uv comparator response time v od = 10% of threshold 100 s v in voltage supervisor n resolution 9 bits v instp lsb step size 76 mv v in full-scale voltage 4.5 38 v v inthaccm threshold accuracy 9v < v in < 38v threshold accuracy 4.5v < v in 9v 3 6.0 % % t propvin comparator response time (vin_on and vin_off) v od = 10% of threshold 100 s output voltage readback n resolution 16 bits v outstp lsb step size 244 v v f/s full-scale sense voltage v run n = 0 (note 8) 8 v v out_tue total unadjusted error v out > 0.6v (note 8) l C0.5 0.5 % v os zero-code offset voltage 500 v t convert update rate (note 6) 100 ms v in voltage readback n resolution (note 5) 10 bits v f/s full-scale input voltage (note 11) 43 v v intue total unadjusted error v vin > 4.5v (note 8) l 0.5 2 % % t convert update rate (note 6) 100 ms downloaded from: http:///
lt c3884 7 3884fb for more information www.linear.com/ltc3884 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (notes 2, 3). v in = 12v, extv cc = 0v, v run0,1 = 3.3v, f sync = 500khz (externally driven) and all programmable parameters at factory default, unless otherwise specified. symbol parameter condition min typ max units output current readback n resolution (note 5) 10 bits v ioutstp lsb step size 0v |v isense + C v isense C | < 16mv 16mv |v isense + C v isense C | < 32mv 32mv |v isense + C v isense C | < 64mv 64mv |v isense + C v isense C | < 128mv 15.63 31.25 62.5 125 v v v v i f/s full-scale input current (note 7) dcr or r isense = 1m 128 a i out_tue total unadjusted error v isense + C v isense C > 6mv (note 8) l 1.25 % v os zero-code offset voltage 50 v t convert update rate (note 6) 100 ms input current readback n resolution (note 5) 10 bits v iinstp lsb step size full-scale range = 16mv lsb step size full-scale range = 32mv lsb step size full-scale range = 64mv gain = 8, 0v |v iin + C v iin C | 5mv gain = 4, 0v |v iin + C v iin C | 20mv gain = 2, 0v |v iin + C v iin C | 50mv 15.26 30.52 61 v v v i in_tue total unadjusted error gain = 8, 2.5mv |v iin + C v iin C | v in = 8v (note 8) gain = 4, 4mv |v iin + C v iin C | v in = 8v (note 8) gain = 2, 6mv |v iin + C v iin C | v in = 8v (note 8) l l l 2 1.3 1.2 % % % v os zero-code offset voltage 50 v t convert update rate (note 6) 100 ms supply current readback n resolution (note 5) 10 bits v ichipstp lsb step size full-scale range = 256mv 244 v i chiptue total unadjusted error |v iin + C v in | 150mv (note 19) l 3 % t convert update rate (note 6) 100 ms temperature readback (t0, t1) t res_t resolution 0.25 c t0_tue external temperature total unadjusted readback error tsns0, tsns1 1.85v (note 8) mfr_pwm_mode_[6] = 0 mfr_pwm_mode_[6] = 1 (note 14) C3 C10 3 10 c c t1_tue internal tsns tue v run0,1 = 0.0, f sync = 0khz (note 8) 1 c t convert update rate (note 6) 100 ms intv cc regulator/extv cc v intvcc internal v cc voltage no load 6v v in 38v 5.25 5.5 5.75 v v ldo_int intv cc load regulation i cc = 0ma to 20ma, 6v v in 38v 0.5 2 % v extvcc extv cc switchover voltage v in 7v, extv cc rising 4.5 4.7 v v ldo_hys extv cc hysteresis 290 mv v ldo_ext extv cc voltage drop i cc = 20ma, v extvcc = 5.5v 50 100 mv v in_thr v in threshold to enable extv cc switchover v in rising 7 v downloaded from: http:///
lt c3884 8 3884fb for more information www.linear.com/ltc3884 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (notes 2, 3). v in = 12v, extv cc = 0v, v run0,1 = 3.3v, f sync = 500khz (externally driven) and all programmable parameters at factory default, unless otherwise specified. symbol parameter condition min typ max units v in_thf v in threshold to disable extv cc switchover v in falling 6.5 v v dd33 regulator v dd33 internal v dd33 voltage 4.5v < v intvcc or 4.8v < v extvcc 3.2 3.3 3.4 v i lim v dd33 current limit v dd33 = gnd, v in = intv cc = 4.5v 100 ma v dd33_ov v dd33 overvoltage threshold 3.5 v v dd33_uv v dd33 undervoltage threshold 3.1 v v dd25 regulator v dd25 internal v dd25 voltage 2.5 v i lim v dd25 current limit v dd25 = gnd, v in = intv cc = 4.5v 80 ma oscillator and phase-locked loopf range pll sync range syncronized with falling edge of sync l 200 1000 khz f osc oscillator frequency accuracy frequency switch = 250.0 to 1000.0 khz l 7.5 % v th(sync) sync input threshold v sync falling v sync rising 1 1.5 v v v ol(sync) sync low output voltage i load = 3ma 0.2 0.4 v i leak(sync) sync leakage current in slave mode 0v v pin 3.6v 5 a sync- 0 sync to ch0 phase relationship based on the falling edge of sync and rising edge of tg0 mfr_pwm_config[2:0] = 0,2,3 mfr_pwm_config[2:0] = 5 mfr_pwm_config[2:0] = 1 mfr_pwm_config[2:0]= 4,6 0 60 90 120 deg deg deg deg sync- 1 sync to ch1 phase relationship based on the falling edge of sync and rising edge of tg1 mfr_pwm_config[2:0] = 3 mfr_pwm_config[2:0] = 0 mfr_pwm_config[2:0] = 2,4,5 mfr_pwm_config[2:0] = 1 mfr_pwm_config[2:0] = 6 120 180 240 270 300 deg deg deg deg deg eeprom characteristics endurance (note 12) 0c < t j < 85c eeprom write operations l 10,000 cycles retention (note 12) t j < 125c l 10 years mass_write mass write operation time store_user_all, 0c < t j < 85c during eeprom write operation l 440 4100 ms leakage current sda, scl, alert , run i ol input leakage current ov v pin 5.5v l 5 a leakage current fault n , pgood n i gl input leakage current ov v pin 3.6v l 2 a digital inputs scl, sda, run n , gpi0 n v ih input high threshold voltage l 2 v v il input low threshold voltage l 1.4 v v hyst input hysteresis scl, sda 0.08 v c pin input capacitance 10 pf digital input wpi puwp input pull-up current wp 10 a open-drain outputs scl, sda, fault n , alert , run n , share_clk, pgood n v ol output low voltage i sink = 3ma 0.4 v downloaded from: http:///
lt c3884 9 3884fb for more information www.linear.com/ltc3884 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (notes 2, 3). v in = 12v, extv cc = 0v, v run0,1 = 3.3v, f sync = 500khz (externally driven) and all programmable parameters at factory default, unless otherwise specified. symbol parameter condition min typ max units digital inputs share_clk, wpv ih input high threshold voltage l 1.5 1.8 v v il input low threshold voltage l 0.6 1 v digital filtering of fault n i fltg input digital filtering fault n 3 s digital filtering of pgood n i fltg output digital filtering pgood n 100 s digital filtering of run n i fltg input digital filtering run 10 s pmbus interface timing characteristics f scl serial bus operating frequency l 10 400 khz t buf bus free time between stop and start l 1.3 s t hd(sta) hold time after repeated start condition after this period, the first clock is generated l 0.6 s t su(sta) repeated start condition setup time l 0.6 10000 s t su(st0) stop condition setup time l 0.6 s t hd(dat) date hold time receiving data transmitting data l l 0 0.3 0.9 s s t su(dat) data setup time receiving data 0.1 s t timeout_smb stuck pmbus timer non-block reads stuck pmbus timer block reads measured from the last pmbus start event 32 255 ms t low serial clock low period l 1.3 10000 s t high serial clock high period l 0.6 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2 : the ltc3884 is tested under pulsed load conditions such that t j t a . the ltc3884 e is guaranteed to meet performance specifications from 0c to 85 c . specifications over the C 40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3884 i is guaranteed over the full C 40 c to 125 c operating junction temperature range. t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula : t j = t a + (p d ? ja ) the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3 : all currents into device pins are positive ; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified note 4: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. c load = 3500pf is guaranteed by design.note 5: the data format in pmbus is 5 bits exponent (signed) and 11 bits mantissa (signed). this limits the output resolution to 10 bits though the internal adc is 16 bits and the calculations use 32-bit words. note 6: the data conversion is done by default in round robin fashion. all inputs signals are continuously converted for a typical latency of 100ms. setting mfr_adc_contrl value to be 0 to 12, ltc3884 can do fast data conversion with only 8ms to 10ms. see section pmbus command for details. note 7: the iout_cal_gain = 1.0m and mfr_iout_tc = 0.0. value as read from read_iout in amperes.note 8: part tested with pwm disabled. evaluation in application demonstrates capability. tue(%) = adc gain error (%) +100 ? (zero code offset + adc linearity error)/actual value. note 9: all v out commands assume the adc is used to auto zero the output to achieve the stated accuracy. ltc3884 is tested in a feedback loop that servos v out to a specified value. downloaded from: http:///
lt c3884 10 3884fb for more information www.linear.com/ltc3884 electrical characteristics note 10: the maximum programmable v out voltage is 5.5v when the output voltage range is high and 2.75v when the output voltage range is low. note 11: the maximum v in voltage is 38v. note 12: eeprom endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. data retention is production tested via a high temperature at wafer level. the minimum retention specification applies for devices whose eeprom has been cycled less than the minimum endurance specification. the restore_user_all command (nvm read) is valid over the entire operating junction temperature range. note 13: mfr_pwm_mode[1]=1 or 0 sets the output voltage range low or high.note 14: mfr_pwm_mode_[6] = 0 or 1 sets the temperature measurement method through ? v be , or through 2v be . note 15 : mfr_pwm_mode [2] = 1 or 0 sets device in low dcr mode or regular dcr mode respectively. mfr_pwm_mode [7 ]= 1 or 0 sets device in high output current range or low current range. see output current sensing and sub milliohm dcr current sensing in operation section for details. note 16: the ltc3884 quiescent current (i q ) equals the i q of v in plus the i q of extv cc . code 0 5 10 15 20 25 30 35 0 6 12 19 25 31 37 43 50 56 62 r th (k) 3884 f01 figure 1. programmable r th note 17: the ltc3884 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 18: write operations above t j = 85c or below 0c are possible although the electrical characteristics are not guaranteed and the eeprom will be degraded. read operations performed at temperatures below 125c will not degrade the eeprom. writing to the eeprom above 85c will result in a degradation of retention characteristics. note 19: properly adjust the input current sensing resistor r vin to set the sensing voltage within the maximum voltage of 150mv. downloaded from: http:///
lt c3884 11 3884fb for more information www.linear.com/ltc3884 typical performance characteristics t a = 25c, v in = 12v, l = 0.33h, dcr = 0.32m, extv cc = 0v unless otherwise noted. efficiency vs load current efficiency vs load current power loss vs load current f sw = 350khz v out =1.8v v out =1.5v v out =1.2v v out =1.0v load current (a) 0 5 10 15 20 25 30 60 66 72 77 83 89 95 efficiency (%) 3884 g01 f sw = 500khz v out =1.8v v out =1.5v v out =1.2v v out =1.0v load current (a) 0 5 10 15 20 25 30 60 66 72 77 83 89 95 efficiency (%) 3884 g02 f sw = 350khz v out =1.8v v out =1.5v v out =1.2v v out =1.0v load current (a) 0 5 10 15 20 25 30 0 1 2 3 4 5 6 powerloss (w) 3884 g03 inductor current at light load soft-start ramp start-up into a prebiased output power loss vs output current load step (forced continuous mode) load step (discontinuous mode) i load 10a/div i l 10a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 10a step 3884 g05 i load 10a/div i l 10a/div v out 100mv/div ac-coupled 50s/div v in = 12v v out = 1.8v 0.3a to 10a step 3884 g06 forced continuous mode 5a/div discontinuous mode 5a/div 1s/div v out = 1.8v i load = 1a 3884 g07 run 2v/div 0v v out 1v/div 0v 5ms/div t rise = 10ms t delay = 5ms v out = 1.8v 3884 g08 run 2v/div 0v v out 1v/div 0v 5ms/div t rise = 10ms v out = 1.8v 3884 g09 f sw = 500khz v out =1.8v v out =1.5v v out =1.2v v out =1.0v load current (a) 0 5 10 15 20 25 30 0 1 2 3 4 5 6 powerloss (w) 3884 g04 downloaded from: http:///
lt c3884 12 3884fb for more information www.linear.com/ltc3884 t a = 25c, v in = 12v, l = 0.33h, dcr = 0.32m, extv cc = 0v unless otherwise noted. typical performance characteristics soft-off ramp dynamic current sharing during a load transient in a 2-phase system dynamic current sharing during a load transient in a 2-phase system run 2v/div 0v v out 1v/div 0v 5ms/div t fall = 5ms t delay = 10ms 3884 g10 10a/div i l 0a 5s/div 3884 g11 10a/div 5s/div 3884 g12 i l 0a dynamic current sharing during a load transient in a 4-phase system phase current matching in two phase systems dynamic current sharing during a load transient in a 4-phase system intv cc line regulation current limit during an output short condition current sense threshold vs duty cycle ch0 ch1 output current (a) 0 8 16 24 32 40 C0.1 1.9 3.9 6.0 8.0 10.0 12.1 14.1 16.2 18.2 20.2 phase current (a) 3884 g16 v in (v) 0 10 20 30 40 4.0 4.3 4.6 4.9 5.2 5.5 5.8 intv cc (v) 3884 g17 mfm_pwm_mode[7][2] = 0,1 iout_oc_fault_limit= 32.5a duty cycle (%) 0 20 40 60 80 100 8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0 over current sense threshold (mv) 3884 g18 5s/div 3884 g13 i l 10a/div 0a 5s/div 3884 g14 i l 10a/div 0a 5s/div v out gnd 0a i l 10a/div 3884 g15 oc_fault limit = 40a, il_peak = 42a downloaded from: http:///
lt c3884 13 3884fb for more information www.linear.com/ltc3884 t a = 25c, v in = 12v, l = 0.33h, dcr = 0.32m, extv cc = 0v unless otherwise noted. typical performance characteristics share_clk frequency vs input voltage quiescent current vs input voltage supply current measurement error vs supply current v in (v) 4 13 22 31 40 93 95 98 100 102 105 107 share_clk frequency (khz) 3884 g19 v in (v) 4 10 16 22 28 34 40 15.0 17.5 20.0 22.5 25.0 27.5 30.0 quiescent current (ma) 3884 g20 r vin = 2 supply current (ma) 20 40 60 80 100 120 C1.0 C0.8 C0.6 C0.4 C0.2 0.0 0.2 0.4 0.6 0.8 1.0 supply current measurement error (%) 3884 g21 v ref vs temperature v out overvoltage threshold vs temperature (target 2v) v out vs temperature v out overvoltage threshold vs temperature (target 4v) share_clk vs temperature v out overvoltage threshold vs temperature (target 1v) temperature (c) C55 C10 35 80 125 1.2190 1.2193 1.2195 1.2198 1.2200 1.2203 1.2205 1.2208 1.2210 1.2213 1.2215 1.2218 1.2220 v ref (v) 3884 g22 temperature (c) C55 C10 35 80 125 0.995 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 v out (v) 3884 g23 temperature (c) C55 C10 35 80 125 0.985 0.990 0.995 1.000 1.005 1.010 1.015 ov threshold (v) 3884 g24 temperature (c) C55 C10 35 80 125 1.970 1.980 1.990 2.000 2.010 2.020 2.030 ov threshold (v) 3884 g25 temperature (c) C55 C10 35 80 125 3.94 3.96 3.98 4.00 4.02 4.04 4.06 ov threshold (v) 3884 g26 temperature (c) C55 C10 35 80 125 93 94 96 97 99 100 101 103 104 106 107 share_clk (khz) 3884 g27 downloaded from: http:///
lt c3884 14 3884fb for more information www.linear.com/ltc3884 typical performance characteristics underlock voltage vs temperature v out command dnl v out command inl v out error vs v out i out error vs i out input current error vs input current rising falling temperature (c) C55 C10 35 80 125 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85 3.90 3.95 4.00 underlock voltage (v) 3884 g28 v out (v) 0.5 1.5 2.5 3.5 4.5 5.5 C0.30 C0.22 C0.15 C0.07 0.00 0.08 0.15 0.23 0.30 dnl (lsb) 3884 g29 v out (v) 0.50 1.50 2.50 3.50 4.50 5.50 C1.00 C0.50 0 0.50 1.00 1.50 2.00 inl (lsb) 3884 g30 v out (v) 0.5 1.5 2.5 3.5 4.5 5.5 C0.30 C0.20 C0.10 0.00 0.10 0.20 0.30 0.40 v out measurement error (mv) 3884 g31 i out (a) 0.1 8.0 16.0 24.0 32.0 40.0 C10.00 C7.14 C4.29 C1.43 1.43 4.29 7.14 10.00 i out measurement error (ma) 3884 g32 r iinsns = 5m input current(a) 0 3 5 8 10 C3 C2 C2 C1 0 0 1 2 2 i input measurement error (ma) 3884 g33 t a = 25c, v in = 12v, l = 0.33h, dcr = 0.32m, extv cc = 0v unless otherwise noted. downloaded from: http:///
lt c3884 15 3884fb for more information www.linear.com/ltc3884 v sense0 + /v sense1 + (pin 1/pin 32) : positive output voltage sense inputs.v sense0 C /v sense1 C (pin 2/pin 31) : negative output volt - age sense inputs.i th0 /i th1 (pin 6/pin 29) : current control threshold and error amplifier compensation nodes. each associated channel s current comparator tripping threshold increases with its i th voltage. i th_r0 /i th_r1 (pin 5/pin 30) : loop compensation nodes. i sense0 + /i sense1 + (pin 7/pin 3) : current sense compara - tor positive inputs, normally connected to dcr sensing networks or current sensing resistors. i sense0 C /i sense1 C (pin 8/pin 4) : current sense comparator negative inputs, normally connected to outputs.sync (pin 11) : external clock synchronization input and open-drain output pin. if an external clock is present at this pin, the switching frequency will be synchronized to the external clock. if clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. a resistor pull-up to 3.3v is required in the application if the ltc3884 is the master. scl (pin 12) : serial bus clock input. open-drain output can hold the output low if clock stretching is enabled. a pull-up resistor to 3.3v is required in the application. sda (pin 13) : serial bus data input and output. a pull-up resistor to 3.3v is required in the application. alert (pin 14) : open-drain digital output. connect the smbalert signal to this pin. a pull-up resistor to 3.3v is required in the application. fault0 / fault1 (pin 15/pin 16) : digital programmable fault inputs and outputs. open-drain output. a pull-up resistor to 3.3v is required in the application. run0/run1 (pin 17/pin 18) : enable run input and out - put. logic high on these pins enables the controller. an open-drain output holds the pin low until the ltc3884 is out of reset. a pull-up resistor to 3.3v is required in the application. pin functions asel0/asel1 (pin 19/pin 20) : serial bus address select inputs. connect optional 1% resistor dividers between v dd25 and sgnd to these pins to select the serial bus interface address. refer to the applications information section for more details. minimize capacitance when the pin is open to assure accurate detection of the pin state. v out0_cfg /v out1_cfg (pin 21/pin 22) : output voltage select pins. connect optional 1% resistor divider be - tween v dd25 vout_cfg and sgnd in order to select output voltage for each channel. if the pin is left open, the ic will use the value programmed in eeprom. refer to the applications information section for more details. minimize capacitance when the pin is open to assure ac - curate detection of the pin state.freq_cfg (pin 23) : frequency select pin. connect op - tional 1% resistor divider between v dd25 and freq_cfg sgnd in order to select pwm switching frequency. refer to the applications information section for more details. minimize capacitance when the pin is open to assure ac - curate detection of the pin state.phase_cfg (pin 24) : phase select pin. connect 1% resistor divider between v dd25 phase_cfg sgnd to this pin to configure the phase of each pwm channel relative to sync. if the pin is left open, the ic will use the value programmed in the nvm. refer to the applications in - formation section for more details. minimize capacitance when the pin is open to assure accurate detection of the pin state. v dd25 (pin 25) : internally generated 2.5v power supply output pin. bypass this pin to sgnd with a low esr 1f capacitor. do not load this pin with external current except for the 1% resistor dividers required for the configura - tion pins.wp (pin 26) : write protect pin active high. an internal 10a current source pulls the pin to v dd33 . if wp is high, the pmbus writes are restricted.share_clk (pin 27) : share clock, bidirectional open- drain clock sharing pin. nominally 100khz . used to synchronize the timing between multiple ltc3884 s. tie all share_clk pins together. all ltc3884 s will synchronize to the fastest clock. a pull-up resistor to 3.3v is required. downloaded from: http:///
lt c3884 16 3884fb for more information www.linear.com/ltc3884 pin functions v dd33 (pin 28) : internally generated 3.3v power supply output pin. bypass this pin to sgnd with a low esr 1f capacitor. do not load this pin with external current except for the pull-up resistors required for fault n , sclk, sync and possibly run n , sda and scl, pgood n . intv cc (pin 38) : internal regulator 5.5v output. the con - trol circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7f low esr tantalum or ceramic capacitor. this regulator is mainly designed for internal circuits, not to be used as supply for the other ics. extv cc (pin 40) : external power input to an internal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal regulator whenever extv cc is higher than 4.7v and v in is higher than 7v . extv cc also powers up v dd33 when extv cc is higher than 4.7v and intv cc is lower than 3.8v . do not exceed 6v on this pin. decouple this pin to pgnd with a minimum of 4.7f low esr tantalum or ceramic capacitor. if the extv cc pin is not used to power intv cc , the extv cc pin must be tied gnd. the extv cc pin may be connected to a higher voltage than the v in pin. v in (pin 39) : main input supply. decouple this pin to pgnd with a capacitor ( 1f to 10f ). for applications where the main input power is 6v or below, tie the v in and intv cc pins together. if the input current sense amplifier is not used, this pin must be shorted to the i in + and i in C pins. bg0/bg1 (pin 42/pin 37) : bottom gate driver outputs. these pins drive the gates of the bottom n-channel mosfets between pgnd and intv cc . boost0/boost1(pin 43/pin 36) : boosted floating driver supplies. the (+) terminal of the booststrap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . tg0/tg1 (pin 44/pin 35) : top gate driver outputs. these are the outputs of the floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltages. sw0/sw1 (pin 45/pin 34) : switch node connections to inductors. voltage swings at the pins are from a diode (internal body diode) voltage drop below ground to v in . tsns0/tsns1 (pin 10/pin 9) : external diode temperature sense. connect to the anode of a diode connected pnp transistor and star-connect the cathode to gnd (pin 49) in order to sense remote temperature. a bypass capaci - tor between the anode and cathode must be located in close proximity to the transistor . if external temperature sense elements are not installed, short pin to ground and set the ut_fault_limit to C275c and the ut_fault_ response to ignore.i in + (pin 46) : positive current sense comparator input. if the input current sense amplifier is not used, this pin must be shorted to the i in C and v in pins. i in C (pin 47): negative current sense comparator input. if the input current sense amplifier is not used, this pin must be shorted to the i in + and v in pins. pgood0/pgood1 (pin 48/pin 33) : power good indicator outputs. open-drain logic output that is pulled to ground when the output exceeds the uv and ov regulation win - dow. the output is deglitched by an internal 100s filter. a pull-up resistor to 3.3v is required in the application.pgnd (pin 41): power ground. sgnd (exposed pad pin 49) : internal signal ground. all small-signal and compensation components should connect to this ground, which in turn connects to pgnd at single point. downloaded from: http:///
lt c3884 17 3884fb for more information www.linear.com/ltc3884 block diagram +C a = n 16-bit adc i chip +C C + i vin_sns1 + i sense1 + i sense1 C v sense1 + v sense1 C pwm0 C + C + + + + ++ C C C C C + 10:1 mux C C tmux 2a i lim dac (3 bits) ov 9-bit ov dac 9-bit uv dac 12-bit set point dac uv ea gm v stby sgnd 1.22v i th0 32a C+ C + ad 7r 7r 10r 4r pwm clock asel1v out0_cfg 11r v sense0 + tsns0 v sense0 C 11r switch logic and anti- shoot- through ov run ss uvlo rev uv prebias on fcnt 2 1 10 20 asel0 19 21 freq_cfg 23 3884 f02 phase_cfg 24 c vcc bg0 d b m1 intv cc extv cc v dd33 42 pgnd 41 i sense0 + i sense0 C 7 8 sw0 45 tg0 c b 44 boost0 43 v dd33 28 intv cc 38 48 extv cc 40 i in + i in C 47 46 r vin r iinsns 39 m2 c out v out0 3.3v subreg 2.5v subreg 5.5vreg C + C + activeclamp uvlo intv cc slope compensation slave v dd33 miso mosi clk master ram eeprom main control program rom v dd33 compare i lim range select hi: 1:1 lo: 1:1.8 5k 35rr i cmp rev 5 i thr0 6 c c1 c c2 c in v in v supply +C +C s q pwm_clock r phase det v co phase selector clock divider sinc 3 uvlo ref osc (32mhz) config detect channel timing management 26 14 13 12 scl sda wp alert pmbus interface (400khz compatible) 27 17 fault0 run0 share_clk 15 sync sgnd v dd33 11 v dd25 25 v dd25 41r v in on/off r 1 5k +C 9-bit v in dac pgood0 ovuv pgood0 r th figure 2. block diagram, one of two channels (channel 0 shown) (uk package) downloaded from: http:///
lt c3884 18 3884fb for more information www.linear.com/ltc3884 operation overview the ltc3884 is a dual channel/dual phase, constant- frequency, analog current mode controller for dc/dc step- down applications with a digital interface. the ltc3884 digital interface is compatible with pmbus which supports bus speeds of up to 400khz . a typical application circuit is shown on the first page of this data sheet.ltc3884 is very similar to ltc3880 , but has numerous new features as shown in bold:major features include: n sub-milliohm dcr sensing n dedicated power good indicators n direct input and chip current sensing n programmable loop compensation parameters n t init start-up time: 65ms n pwm synchronization circuit, (see frequency and phasing section for details) n mfr_adc_control for fast adc sampling of one parameter (as fast as 8ms ) (see pmbus command for details) n fully differential output sensing for both channels ; vout0/1 both programmable up to 5.5v n power-up and program eeprom with extv cc n input voltage up to 38v n dual diode temperature sensing n sync contention circuit (refer to frequency and phase section for details) n fault logging n programmable output voltage n programmable input voltage on and off threshold voltage n programmable current limit n programmable switching frequency n programmable ov and uv threshold voltage n programmable on and off delay times n programmable output rise/fall times n phase-locked loop for synchronous polyphase operation (2, 3, 4 or 6 phases). n integrated gate drivers n nonvolatile configuration memory n optional external configuration resistors for key operating parameters n optional timebase interconnect for synchronization between multiple controllers n wp pin to protect internal configuration n stand along operation after user factory configuration n pmbus, version 1.2, 400khz compliant interface the pmbus interface provides access to important power management data during system operation including: n internal controller temperature n external system temperature via optional diode sense elements n average output current n average output voltage n average input voltage n average input current n average chip input current from v in n configurable, latched and unlatched individual fault and warning status individual channels are accessed through the pmbus using the page command, i.e., page 0 or 1. fault reporting and shutdown behavior are fully con - figurable. two individual fault0 , fault1 outputs are provided, both of which can be masked independently . three dedicated pins for alert , pgoo d0 /1 functions are provided. the shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. individual status commands enable fault reporting over the serial bus to identify the specific fault event. fault or warning detection includes the following: downloaded from: http:///
lt c3884 19 3884fb for more information www.linear.com/ltc3884 operation n output undervoltage/overvoltage n input undervoltage/overvoltage n input and output overcurrent n internal overtemperature n external overtemperature n communication, memory or logic (cml) fault main control loop the ltc3884 is a constant-frequency, current mode step- down controller containing two channels operating with user-defined relative phasing. during normal operation the top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin which is the output of each er - ror amplifier, ea. the ea negative terminal is equal to the differential voltage between v sense + and v sense C divided by 5.5 (or 2.75 if mfr_pwm_mode [1] = 1). the positive terminal of the ea is connected to the output of a 12-bit dac with values ranging from 0v to 1.024v . the output voltage, through feedback of the ea, will be regulated to 5.5 times the dac output (or 2.75 times). the dac value is calculated by the part to synthesize the user's desired output voltage. the output voltage is programmed by the user either with the resistor configuration pins detailed in table?3 or by the pmbus v out command (either from eeprom or by pmbus command). refer to the pmbus command section of the data sheet or the pmbus specifica - tion for more details. the pmbus vout_command can be executed at any time while the device is running. this command will typically have a latency less than 10ms . the user is encouraged to refer to the pmbus power system management protocol specification to understand how to program the ltc3884 . http://www.pmbus.org/specs.html continuing the basic operation description, the current-mode controller will turn off the top gate when the peak current is reached. if the load current increases, sense voltage will slightly droop with respect to the dac reference. this causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on. in continuous conduction mode, the bottom mosfet stays on until the end of the switching cycle. eeprom the ltc3884 contains internal eeprom (nonvolatile memory) to store user configuration settings and fault log information. eeprom endurance retention and mass write operation time are specified in the electrical char - acteristics and absolute maximum ratings sections. write operations above t j = 85c are possible although the electrical characteristics are not guaranteed and the eeprom will be degraded. read operations performed at temperatures between C40c and 125c will not degrade the eeprom. writing to the eeprom above 85c will result in a degradation of retention characteristics. the fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log eeprom locations. if occasional writes to these registers occur above 85c , the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function. it is recommended that the eeprom not be written when the die temperature is greater than 85c . if the die temperature exceeds 130c , the ltc3884 will disable all eeprom write operations. all eeprom write operations will be re-enabled when the die temperature drops below 125c . (the controller will also disable all the switching when the die temperature exceeds the internal overtem - perature fault limit 160c with a 10c hysteresis) the degradation in eeprom retention for temperatures >125c can be approximated by calculating the dimen - sionless acceleration factor using the following equation : af = e ea k ?? ? ?? ? ? 1 t use + 273 ? 1 t stress + 273 ?? ? ?? ? ?? ? ?? ? where:af = acceleration factor ea = activation energy = 1.4ev k = 8.617 ? 10 C5 ev/ k t use = 125c specified junction temperature t stress = actual junction temperature in c downloaded from: http:///
lt c3884 20 3884fb for more information www.linear.com/ltc3884 operation example: calculate the effect on retention when operating at a junction temperature of 135c for 10 hours. t stress = 130c t use = 125c, af = e ([(1.4/8.617 ? 10 C5 ) ? (1/398 C 1/403)] ) = 16.6 the equivalent operating time at 125c = 16.6 hours. thus the overall retention of the eeprom was degraded by 16.6 hours as a result of operating at a junction temperature of 130 c for 10 hours. the effect of the overstress is negligible when compared to the overall eeprom retention rating of 87,600 hours at a maximum junction temperature of 125 c. the integrity of the entire onboard eeprom is checked with a crc calculation each time its data is to be read, such as after a power-on reset or execution of a restore_user_ all command. if a crc error occurs, the cml bit is set in the status_byte and status_word commands, the eeprom crc error bit in the status_mfr_specific command is set, and the alert and run pins pulled low (pwm channels off). at that point the device will only respond at special address 0x 7c, which is activated only after an invalid crc has been detected. the chip will also respond at the global addresses 0x 5a and 0x 5b, but use of these addresses when attempting to recover from a crc issue is not recommended. all power supply rails associated with either pwm channel of a device reporting an invalid crc should remain disabled until the issue is resolved. see the application information section or con - tact the factory for details on efficient in-system eeprom programming, including bulk eeprom programming, which the ltc3884 also supports. p ower-up and initialization the ltc3884 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. it operates from a single input supply (4.5v to 38v) while three on-chip linear regulators generate internal 2.5v, 3.3v and 5.5v . if v in does not exceed 6v , and the extv cc pin is not driven by an external supply, the intv cc and v in pins must be tied together. the controller configuration is initialized by an internal threshold based uvlo where v in must be approximately 4v and the 5.5v, 3.3v and 2.5v linear regulators must be within approximately 20% of the regulated values. in addition to power supply,a pmbus restore_user_all or mfr_reset command can initialize the part too. the extv cc pin is driven by an external regulator to improve efficiency of the circuit and minimize power loss on the ltc3884 when v in is high. the extv cc pin must exceed approximately 4.8v , and v in must exceed 7v before the intv cc ldo operates from the extv cc pin. to minimize application power, the extv cc pin can be supplied by a switching regulator. during initialization, the external configuration resistors are identified and/or contents of the nvm are read into the controller s commands and the bg n , tg n pins are held low. the run n and fault n and pgood n are held low. the ltc3884 will use the contents of tables 12 to 15 to determine the resistor defined parameters. see the resis - tor configuration section for more details. the resistor configuration pins only control some of the preset values of the controller. the remaining values are programmed in nvm either at the factory or by the user. if the configuration resistors are not inserted or if the ignore rconfig bit is asserted (bit 6 of the mfr_config_all configuration command), the ltc3884 will use only the contents of nvm to determine the dc/dc characteristics. the asel0 /1 value read at power-up or reset is always respected unless the pin is open. the ase l0 /1 will set the msb and the lsb from the detected threshold. see the applications information section for more details. after the part has initialized, an additional comparator moni - tors v in . the vin_on threshold must be exceeded before the output power sequencing can begin. after v in is initially applied, the part will typically require 70ms to initialize and begin the ton_delay timer. the readback of voltages and currents may require an additional 200ms to 300ms . soft-start the method of start-up sequencing described below is time based. the part must enter the run state prior to soft-start. the run pins are released by the ltc3884 after the part is initialized and v in is greater than the vin_on threshold. if multiple ltc3884 s are used in an application, they all hold downloaded from: http:///
lt c3884 21 3884fb for more information www.linear.com/ltc3884 operation their respective run pins low until all devices are initialized and v in exceeds the vin_on threshold for every device. the share_clk pin assures all the devices connected to the signal use the same time base. the share_clk pin is held low until the part has been initialized after v in is ap - plied. the ltc3884 can be set to turn-off (or remain off) if share_clk is low (set bit 2 of mfr_chan_config to 1). this allows the user to assure synchronization across numerous ltc ics even if the run pins cannot be con - nected together due to board constraints. in general, if the user cares about synchronization between chips it is best not only to connect all the respective run pins together but also to connect all the respective share_clk pins together and pull up to v dd33 with a 10k resistor. this as - sures all chips begin sequencing at the same time and use the same time base. after the run pins release and prior to entering a constant output voltage regulation state, the ltc3884 performs a monotonic initial ramp or soft-start . soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0v to the commanded voltage set- point. once the ltc3884 is commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay ( ton_delay ) prior to initiat - ing this output voltage ramp. the rise time of the voltage ramp can be programmed using the ton_rise command to minimize inrush currents associated with the start-up voltage ramp. the soft-start feature is disabled by setting the value of ton_rise to any value less than 0.25ms . the ltc3884 pwm always uses discontinuous mode during the ton_rise operation. in discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. this will allow the regulator to start up into a pre-biased load. when the ton_max_fault_limit is reached, the part transitions to continuous mode, if so programmed. if ton_max_fault_limit is set to zero, there is no time limit and the part transitions to the desired conduction mode after ton_rise completes and v out has exceeded the vout_uv_fault_limit and iout_oc is not present. however setting ton_max_fault_limit to a value of 0 is not recommended. time-based sequencing the default mode for sequencing the outputs on and off is time based. each output is enabled after waiting ton_delay amount of time following either a run pin going high, a pmbus command to turn on or the v in rising above a preprogrammed voltage. off sequencing is handled in a similar way. to assure proper sequencing, make sure all ics connect the share_clk pin together and run pins together. if the run pins cannot be connected together for some reasons, set bit 2 of mfr_chan _ config to 1. this bit requires the share_clk pin to be clocking before the power supply output can start. when the run pin is pulled low, the ltc3884 will hold the pin low for the mfr_ restart_delay . the minimum mfr_restart _ delay is toff_delay + toff_fall + 136ms . this delay assures proper sequencing of all rails. the ltc3884 calculates this delay internally and will not process a shorter delay. however, a longer commanded mfr_restart_delay will be used by the part. the maximum allowed value is 65.52 seconds. voltage-based sequencing the sequence can also be voltage based. as shown in figure 3, the pgood n pin is asserted when the uv threshold is exceeded for each output. it is possible to feed the pgood pin from one ltc3884 into the run pin of the next ltc3884 in the sequence, especially across multiple ltc3884 s. the pgood n has a 100s filter. if the v out voltage bounces around the uv threshold for a long period of time it is pos - sible for the pgood n output to toggle more than once. t o minimize this problem, set the ton_rise time under 100ms . ltc3884 voltage-based sequencing by cascading pgs into run pins run 1 run 0 pgood0 pgood1pgood0 pgood1 start ltc3884 3884 f03 run 0 to next channel in the sequence run 1 figure 3. event (voltage) based sequencing downloaded from: http:///
lt c3884 22 3884fb for more information www.linear.com/ltc3884 operation if a fault in the string of rails is detected, only the faulted rail and downstream rails will fault off. the rails in the string of devices in front of the faulted rail will remain on unless commanded off. shutdown the ltc3884 supports two shutdown modes. the first mode is closed-loop shutdown response, with user de - fined turn-off delay ( toff_delay ) and ramp down rate (toff_fall ). the controller will maintain the mode of operation for toff_fall . the second mode is discontinu - ous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current, instead of toff_fall. the shutdown occurs in response to a fault condition or loss of share_clk (if bit 2 of mfr_chan _ config is set to a 1) or v in falling below the vin_off threshold or fault pulled low externally (if the mfr_fault _ response is set to inhibit). under these conditions the power stage is disabled in order to stop the transfer of energy to the load as quickly as possible. the shutdown state can be entered from the soft-start or active regulation states or through user intervention. there are two ways to respond to faults ; which are retry mode and latched off mode. in retry mode, the controller responds to a fault by shutting down and entering the inactive state for a programmable delay time ( mfr_retry_delay ). this delay minimizes the duty cycle associated with autonomous retries if the fault that causes the shutdown disappears once the output is disabled. the retry delay time is determined by the longer of the mfr_retry _ delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if multiple outputs are controlled by the same fault n pin, the decay time of the faulted output determines the retry delay. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_chan_config . alternatively, latched off mode means the controller remains latched-off following a fault and clearing requires user intervention such as toggling run n or commanding the part off then on. light-load current operation the ltc3884 has two modes of operation : high efficiency discontinuous conduction mode or forced continuous conduction mode. mode selection is done using the mfr_pwm _mode command (discontinuous conduc - tion is always the start-up mode, forced continuous is the default running mode). if a controller is enabled for discontinuous operation, the inductor current is not allowed to reverse. the reve rse current comparator s output, i rev , turns off the bottom gate of the external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined solely by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in discontinuous mode operation. however, continuous mode exhibits lower output ripple and less interference with audio circuitry, but may result in reverse inductor current, which can cause the input supply to boost. the vin_ov_fault_limit can detect this and turn off the offending channel. however, this fault is based on an adc read and can take up to t convert to detect. if there is a concern about the input supply boosting, keep the part in discontinuous conduction mode. if the part is set to discontinuous mode operation, as the inductor average current increases, the controller will automatically modify the operation from discontinuous mode to continuous mode. switching frequency and phase the switching frequency of the pwm can be established with an internal oscillator or an external time base. the internal phase-locked loop (pll) synchronizes pwm control to this timing reference with proper phase relation, whether the clock is provided internally or externally. the device can also be configured to provide the master clock to other ics through pmbus command, nvm setting, or external configuration resistors as outlined in table?4. as clock master, the ltc3884 will drive its open-drain sync pin at the selected rate with a pulse width of 500ns . an external pull-up resistor between sync and v dd33 is required in this downloaded from: http:///
lt c3884 23 3884fb for more information www.linear.com/ltc3884 operation case. only one device connected to sync should be designated to drive the pin. but if multiple ltc3884 s programmed as clock masters are wired to the same sync line with a pull- up resistor, just one of the devices is automatically elected to provide clocking, and the others disable their sync outputs. the ltc3884 will automatically revert to an external sync input, disabling its own sync, as long as the external sync frequency is greater than 80% of the programmed sync frequency. the external sync input shall have a duty cycle between 20% and 80%. whether configured to drive sync or not, the ltc3884 can continue pwm operation using its own internal oscillator if an external clock signal is subsequently lost. the device can also be programmed to always require an external oscillator for pwm operation by setting bit 4 of mfr_config_all . the status of the sync driver circuit is indicated by bit 10 of mfr_pads. the mfr_pwm_config command can be used to configure the phase of each channel. desired phase can also be set from eeprom or external configuration resistors as outlined in table 5. designated phase is the relationship between the falling edge of sync and the internal clock edge that sets the pwm latch to turn on the top power switch. additional small propagation delays to the pwm control pins will also apply. both channels must be off before the frequency_switch and mfr_pwm_config commands can be written to the ltc3884. the phase relationships and frequency are independent of each other, providing numerous application options. multiple ltc3884 ics can be synchronized to realize a polyphase array. in this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. pwm loop compensation the internal pwm loop compensation resistors r ith n of the ltc3884 can be adjusted using bit [4:0] of the mfr_pwm_comp command. the transconductance of the ltc3884 pwm error amplifier can be adjusted using bit [7:5] of the mfr_pwm_comp command. these two loop compensation parameters can be programmed when device is in operation. refer to the programmable loop compensation subsection in the applications information section for further details. output voltage sensing both channels in ltc3884 have differential amplifiers, which allow the remote sensing of the load voltage be - tween v sense n + and v sense n C pins. the telemetry adc is also fully differential and makes measurements between v sense n + and v sense n C pins respectively. the maximum allowed sense voltages for both channels is 5.5v. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is shorted to gnd or tied to a voltage less than 4.7v , an internal 5.5v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.8v and v in is higher than 7.0v , the 5.5v regulator is turned off and an internal switch is turned on, connecting extv cc . using the extv cc allows the intv cc power to be derived from a high efficiency external source such as a switching regulator output. extv cc can provide power to the internal 3.3v linear regulator even when v in is not present, which allows the ltc3884 to be initialized and programmed even without main power being applied. each top mosfet driver is biased from the floating bootstrap capacitor, c b , which normally recharges during each off cycle through an external diode when the bottom mosfet turns on. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every three cycles to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the drop-out transition to ensure c b is recharged. downloaded from: http:///
lt c3884 24 3884fb for more information www.linear.com/ltc3884 operation output current sensing and sub milliohm dcr current sensing for dcr current sense applications, a resistor in series with a capacitor is placed across the inductor. in this configu - ration, the resistor is tied to the fet side of the inductor while the capacitor is tied to the load side of the inductor as shown in figure 4. if the rc values are chosen such that the rc time constant matches the inductor time constant (l/dcr, where dcr is the inductor series resistance), the re sultant voltage appearing across the capacitor equa ls the voltage across the inductor series resistance (v dcr ) and thus represents the current flowing through the inductor. in addition to this regular current sensing, the ltc3884 employs a unique architecture to enhance the signal-to- noise ratio by 14db , enabling it to operate with a small sense signal (as low as 2mv ) via a sub-milliohm value of inductor dcr (such as 0.2m ) to improve the power efficiency for the heavy load applications while v out 3.5v . as shown in figure?4, externally the new architecture only requires reducing r by 4/5, i.e., r lowdcr = 1/5rnomdcr. better signal-to-noise ratio helps to reduce jitter at the output with as low as 2mv sensing signal. low dcr improves power efficiency in heavy system loads. so the new dcr sensing scheme provides a perfect solution for larger power, and noise sensitive systems. in the meantime, the current limit threshold is still a function of the inductor peak current and its dcr value, and can be accurately set with the mfr_pwm_mode [2] , mfr_pwm_mode [7]. see figure 26. the rc calculations are based on the room temperature dcr of the inductor. the rc time constant should remain constant as a function of temperature. this assures the transient response of the circuit is the same regardless of the temperature. the dcr of the inductor has a large temperature coefficient, approximately 3900ppm / c. the temperature coefficient of the inductor must be written to the mfr_iout_cal_gain_tc register. the external tem - perature is sensed near the inductor and used to modify the internal current limit circuit to maintain an essentially constant current limit with temperature. in this application, the i sense n + pin is connected to the fet side of the dcr sensing filter capacitor while the i sense n C pin is placed on the load side of the capacitor. the current sensed from the input is then given by the expression v dcr /dcr. v dcr is digitized by the ltc3884 s telemetry adc with an input range of 128mv , a noise floor of 7v rms , and a peak-peak ltc3884 + power stage i th1 i th0 1/2 ltc3884 + power stage i th0 v dd33 note: some connectors and components omitted for clarity both chips have the internal frequency command set to the same desired pwm frequency i sense0 + i sense0 C v sense0 + v sense0 C 10k fault0 run0 run1 alert fault1 sync (enabled) share_clk v dd33 run0 alert fault0 sync (disabled) share_clk i sense0 + i sense0 C i sense1 + i sense1 C v sense1 + v sense1 C sgnd pgnd sgnd gnd 1f 3884 f04 v sense0 + v sense0 C 1f load 10k 10k 4.99k 10k run share_clk alert fault sync l/dcr rr cc r c l/dcrl/dcr figure 4. load sharing connections for 3-phase operation downloaded from: http:///
lt c3884 25 3884fb for more information www.linear.com/ltc3884 operation noise of approximately 46.5v . the ltc3884 computes the inductor current using the dcr value stored in the iout_cal_gain command and the temperature coefficient stored in command mfr_iout_cal_gain_tc . the result - ing current value is returned by the read_iout command. i nput current sensing to sense the total input current consumed by the ltc3884 and the power stage, a resistor is placed between the sup - ply voltage and the drain of the top n-channel mosfet. the i in + and i in C pins are connected to the sense resistor. the filtered voltage is amplified by the internal high side current sense amplifier and digitized by the ltc3884s telemetry adc. the input current sense amplifier has three gain settings of 2x, 4x , and 8x set by the bit [3:2] of the mfr_pwm_mode command. the maximum input sense voltage for the three gain settings is 50mv, 25mv, and 10mv respectively. the ltc3884 computes the input current using the r value stored in the iin_cal_gain command. the resulting measured power stage current is returned by the read_iin command. the ltc3884 uses the rvin resistor to measure the v in pin supply current being consumed by the ltc3884 . this value is returned by the mfr_read_ichip command. the chip current is calculated by using the r value stored in the mfr_rvin command. refer to the subsection titled input current sense amplifier in the applications information section for further details. polyphase load sharing multiple ltc3884 s can be arrayed in order to provide a balanced load-share solution by bussing the necessary pins. figure 4 illustrates the shared connections required for load sharing. if an external oscillator is not provided, the sync pin should only be enabled on one of the ltc3884 s. the other(s) should be programmed to disable sync using bit 4 of mfr_config_all . if an external oscillator is present, the chip with the sync pin enabled will detect the presence of the external clock and disable its output. tsns mmbt3906 ltc3884 10nf sgnd sgnd 3884 f05 figure 5. temperature sense circuit multiple chips need to tie all the v sense + pins together, and all the v sense C pins together, and i th_rth and i th together as well. do not assert bit [5] of mfr_pwm_config except in a polyphase application. external/internal temperature sense external temperature can best be measured using a remote, diode-connected pnp transistor such as the mmbt3906. the emitter should be connected to a tsns pin while the base and collector terminals of the pnp transistor should be returned directly to the ltc3884 sgnd pin. two dif - ferent currents are applied to the diode (nominally 2a and 32a ) and the temperature is calculated from a ? v be measurement made with the internal 16- bit monitor adc (see figure 5). the ltc3884 also supports direct v be based external temperature measurements. in this case the diode or di - ode network is trimmed to a specific voltage at a specific current and temperature. in general this method does not yield as accurate result as the single pnp transistor ?v be method, but may function better in a noisy application. refer to mfr_pwm_mode in the pmbus command de - tails section for additional information on programming the ltc3884 for these two external temperature sense configurations. the calculated temperature is returned by the pmbus read_temperature _1 command. refer to the applications information section for details on proper layout of external temperature sense elements and pmbus commands that can be used to improve the accuracy of calculated temperatures. the read_temperature_2 command returns the internal junction temperature of the ltc3884 using an on-chip diode with a ? v be measure - ment and calculation. downloaded from: http:///
lt c3884 26 3884fb for more information www.linear.com/ltc3884 operation the slope of the external temperature sensor can be modified with the temperature slope coefficient stored in mfr_temp _1_gain. typical pnps require temperature slope adjustments slightly less than 1. the mmbt390 6 has a recommended value in this command of approximately mfr_temp_1_gain = 0.991 based on the ideality factor of 1.01. simply invert the ideality factor to calculate the mfr_temp _1_gain. different manufacturers and differ - ent lots may have different ideality factors. consult with the manufacturer to set this value. the offset of the external temperature sense can be adjusted by mfr_temp_1_off - set. a value of 0 in this register sets the temperature offset to C273.15c. if the pnp cannot be placed in direct contact with the inductor, the slope or offset can be increased to account for temperature mismatches. if the user is adjusting the slope, the intercept point is at absolute zero, C 273.15 c , so small adjustments in slope can change the apparent mea - sured temperature significantly. another way to artificially increase the slope of the temperature term is to increase the mfr_iout_cal_gain_tc term. this will modify the temperature slope with respect to room temperature. rconfig (resistor configuration) pins there are six input pins utilizing 1% resistor dividers between v dd25 and sgnd to select key operating param - eters. the pins are ase l0 , ase l1, freq_cfg , v out0_cfg , v out1_cfg , phase_cfg . if pins are floated, the value stored in the corresponding nvm command is used. if bit 6 of the mfr_config_all configuration command is asserted in nvm, the resistor inputs are ignored upon power-up except for ase l0 and ase l1 which are always respected. the resistor configuration pins are only measured during a power-up reset or after a mfr_reset or after a restore_user_all command is executed. the v outn_cfg pin settings are described in table?3. these pins select the output voltages for the ltc3884 s analog pwm controllers. if the pin is open, the vout_command command is loaded from nvm to determine the output voltage. the default setting is to have the switcher off unless the voltage configuration pins are installed. the following parameters are set as a percentage of the output voltage if the rconfig pins are used to determine the output voltage: n vout_ov_fault_limit ..................................... +10% n vout_ov_warn_limit ................................... +7.5% n vout_max ....................................................... +7.5% n vout_margin_high..........................................+5% n vout_margin_low........................................... C 5% n vout_uv_warn_limit................................... C 6.5% n vout_uv_fault_limit....................................... C 7% the freq_cfg pin settings are described in table?4. this pin selects the switching frequency. the phase rela tionships between the two channels and sync pin are determined by the phase_cfg pin described in table?5. to synchronize to an external clock, the part should be put into external clock mode (sync output disabled but frequency set to the nominal value). if no external clock is supplied, the part will clock at the programmed frequency. if the application is multiphase and the sync signal between chips is lost, the parts will not operate at the designed phase even if they are programmed and trimmed to the same frequency. this may increase the ripple voltage on the output, pos - sibly produce undesirable operation. if the external sync signal is being generated internally and external sync is not selected, bit 10 of mfr_pads will be asserted. if no frequency is selected and the external sync frequency is not present, a pll_fault will occur. if the user does not wish to see the alert from a pll_fault even if there is not a valid synchronization signal at power-up, the alert mask for pll_fault must be written. see the description on smbalert_mask for more details. if the sync pin is connected between multiple ics only one of the ics should have the sync pin enabled, and all other ics should be configured to have the sync pin disabled. the ase l0 ,1 pin settings are described in table?6. ase l1 selects the top 3 bits of the slave address for the ltc3884. asel0 selects the bottom 4 bits of the slave address for the ltc3884 . if ase l1 is floating, the 3 most significant bits are retrieved from the nvm mfr_address com - mand. if ase l0 is floating, the 4 lsb bits stored in nvm mfr_address command are used to determine the 4 lsb bits of the slave address. for more detail, refer to table?6. downloaded from: http:///
lt c3884 27 3884fb for more information www.linear.com/ltc3884 operation note : per the pmbus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of asel which is always honored. do not set any part address to 0x 5a or 0x 5b because these are global addresses and all parts will respond to them. fault detection and handling a variety of fault and warning reporting and handling mechanisms are available. fault and warning detection capabilities include: n input ov fault protection and uv warning n average input oc warn n output ov/uv fault and warn protection n output oc fault and warn protection n internal and external overtemperature fault and warn protection n external undertemperature fault and warn protection n cml fault (communication, memory or logic) n external fault detection via the bidirectional fault n pins. in addition, the ltc3884 can map any combination of fault indicators to their respective fault n pin using the propagate fault n response commands, mfr_fault_ propagate . typical usage of a fault n pin is as a driver for an external crowbar device, overtemperature alert, over - voltage alert or as an interrupt to cause a microcontroller to poll the fault commands. alternatively, the fault n pins can be used as inputs to detect external faults downstream of the controller that require an immediate response. any fault or warning event will always cause the alert pin to assert low unless the fault or warning is masked by the smbalert_mask . the pin will remain asserted low until the clear_faults command is issued, the fault bit is written to a 1 or bias power is cycled or a mfr_reset command is issued, or the run pins are toggled off/on or the part is commanded off/on via pmbus or an ara command operation is performed. the mfr_fault_ propagate command determines if the fault pins are pulled low when a fault is detected. output and input fault event handling is controlled by the corresponding fault response byte as specified in tables?7 to 12. shutdown recovery from these types of faults can either be autonomous or latched. for autonomous recov - ery, the faults are not latched, so if the fault conditions not present after the retry interval has elapsed, a new soft-start is attempted. if the fault persists, the controller will continue to retry. the retry interval is specified by the mfr_retry_delay command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. the mfr_retry_delay must be greater than 120ms. it can not exceed 83.88 seconds. status registers and alert masking figure 6 summarizes the internal ltc3884 status reg - isters accessible by pmbus command. these contain indication of various faults, warnings and other important operating conditions. as shown, the status_byte and status_word commands also summarize contents of other status registers. refer to pmbus command details for specific information. none of the above in status_byte indicates that one or more of the bits in the most-significant nibble of status_word are also set. in general, any asserted bit in a status_x register also pulls the alert pin low. once set, alert will remain low until one of the following occurs. n a clear_faults or mfr_reset command is issued n the related status bit is written to a one n the faulted channel is properly commanded off and back on n the ltc3884 successfully transmits its address during a pmbus ara n bias power is cycled with some exceptions, the smbalert_mask command can be used to prevent the ltc3884 from asserting alert for bits in these registers on a bit-by-bit basis. these mask settings are promoted to status_word and status_byte in the same fashion as the status bits themselves. for example, if alert is masked for all bits downloaded from: http:///
lt c3884 28 3884fb for more information www.linear.com/ltc3884 operation (paged) mfr_pads 1514 13 12 11 10 98 7 6 5 4 3 2 1 0 vdd33 ov fault vdd33 uv fault (reads 0) (reads 0) invalid adc result(s) sync clocked by external source channel 1 is power_good channel 0 is power_good ltc3884 forcing run1 low ltc3884 forcing run0 low run1 pin state run0 pin state ltc3884 forcing fault1 low ltc3884 forcing fault0 low fault1 pin state fault0 pin state status_mfr_specific 76 5 4 3 2 1 0 (paged) 3884 f06 status_input 76 5 4 3 2 1 0 status_word status_byte 76 5 4 3 2 1 0 (paged) mfr_common 76 5 4 3 2 1 0 chip not driving alert low chip not busyinternal calculations not pending output not in transition eeprom initialized (reads 0) share_clk_low wp pin high status_temperature 76 5 4 3 2 1 0 status_cml 76 5 4 3 2 1 0 status_vout* 76 5 4 3 2 1 0 (paged) status_iout 76 5 4 3 2 1 0 (paged) maskable description general fault or warning event dynamic status derived from other bits yes nono generates alert yes no not directly bit clearable yes nono vout_ov fault vout_ov warning vout_uv warning vout_uv fault vout_max warning ton_max fault toff_max warning (reads 0) iout_oc fault(reads 0) iout_oc warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) ot fault ot warning (reads 0) ut fault (reads 0) (reads 0) (reads 0) (reads 0) invalid/unsupported commandinvalid/unsupported data packet error check failed memory fault detected processor fault detected (reads 0) other communication fault other memory or logic fault 1514 13 12 11 10 98 voutiout input mfr_specific power_good# (reads 0) (reads 0) (reads 0) busyoff vout_ov iout_oc (reads 0) temperature cml none of the above vin_ov fault(reads 0) vin_uv warning (reads 0) unit off for insuffcient vin (reads 0) iin_oc warning (reads 0) internal temperature fault internal temperature warning eeprom crc error internal pll unlocked fault log present vdd33 uv or ov fault vout short cycled fault pulled low by external device figure 6. ltc3884 status register summary in channel 0 status_vout , then alert is effectively masked for the vout bit in status_word for page 0. the busy bit in status_byte also asserts alert low and cannot be masked. this bit can be set as a result of various internal interactions with pmbus communication. this fault occurs when a command is received that cannot be safely executed with one or both channels enabled. as discussed in application information, busy faults can be avoided by polling mfr_common before executing some commands. if masked faults occur immediately after power up, alert may still be pulled low because there has not been time to retrieve all of the programmed masking information from eeprom. status information contained in mfr_common and mfr_pads can be used to further debug or clarify the contents of status_byte or status_word as shown, but the contents of these registers do not affect the state of the alert pin and may not directly influence bits in status_byte or status_word. downloaded from: http:///
lt c3884 29 3884fb for more information www.linear.com/ltc3884 operation mapping faults to fault pins channel-to-channel fault (including channels from multiple ltc3884 s) dependencies can be created by connecting fault n pins together. in the event of an internal fault, one or more of the channels is configured to pull the bussed fault n pins low. the other channels are then configured to shut down when the fault n pins are pulled low. for autonomous group retry, the faulted channel is config - ured to let go of the f aul t n pin(s) after a retry interval, assuming the original fault has cleared. all the channels in the group then begin a soft-start sequence. if the fault response is latch_off , the fault n pin remains asserted low until either the run pin is toggled off/on or the part is commanded off/on. the toggling of the run either by the pin or off/on command will clear faults associ - ated with the channel. if it is desired to have all faults cleared when either run pin is toggled or, set bit 0 of mfr_config_all to a 1. the status of all faults and warnings is summarized in the status_word and status_byte commands.additional fault detection and handling capabilities are: power good pins the pgood n pins of the ltc3884 are connected to the open drains of internal mosfets. the mosfets turn on and pull the pgood n pins low when the channel output voltage is not within the channel s uv and ov voltage thresh - olds. during ton_delay and ton_rise sequencing, the pgood n pin is held low. the pgood n pin is also pulled low when the respective run n pin is low. the pgood n pin response is deglitched by an internal 100s digital filter. the pgood n pin and pgood status may be different at times due to communication latency of up to 10s.crc protection the integrity of the nvm memory is checked after a power on reset. a crc error will prevent the controller from leav - ing the inactive state. if a crc error occurs, the cml bit is set in the status_byte and status_word commands, the appropriate bit is set in the status_mfr_specific command, and the alert pin will be pulled low. nvm repair can be attempted by writing the desired configura - tion to the controller and executing a store_user_all command followed by a clear_faults command. the ltc3884 manufacturing section of the nvm is mir - rored. if both copies are corrupted, the nvm crc fault in the status_mfr_specific command is set. if this bit remains set after being cleared by issuing a clear_faults or writing a 1 to this bit, an irrecoverable internal fault has occurred. the user is cautioned to disable both output power supply rails associated with this specific part. there are no provisions for field repair of nvm faults in the manufacturing section. serial interface the ltc3884 serial interface is a pmbus compliant slave device and can operate at any frequency between 10khz and 400khz . the address is configurable using either the nvm or an external resistor divider. in addition the ltc3884 always responds to the global broadcast address of 0x5a (7 bit) or 0x5b (7 bit). the serial interface supports the following protocols de - fined in the pmbus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. 8) write block. all read operations will return a valid pec if the pmbus master requests it. if the pec_required bit is set in the mfr_config_all command, the pmbus write operations will not be acted upon until a valid pec has been received by the ltc3884. communication protectionpec write errors (if pec_required is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a cml fault. the cml bit is set in the status_byte and status_word commands, the appropriate bit is set in the status_cml command, and the alert pin is pulled low. device addressing the ltc3884 offers five different types of addressing over the pmbus interface, specifically : 1) global, 2) device, 3) rail addressing and 4) alert response address (ara). downloaded from: http:///
lt c3884 30 3884fb for more information www.linear.com/ltc3884 operation global addressing provides a means of the pmbus master to address all ltc3884 devices on the bus. the ltc3884 global address is fixed 0x 5a (7 bit) or 0xb4 (8 bit) and cannot be disabled. commands sent to the global address act the same as if page is set to a value of 0x ff. com - mands sent are written to both channels simultaneously. global command 0x 5b (7 bit) or 0xb6 (8 bit) is paged and allows channel specific command of all ltc3884 devices on the bus. other ltc device types may respond at one or both of these global addresses. reading from global addresses is strongly discouraged. device addressing provides the standard means of the pmbus master communicating with a single instance of an ltc3884 . the value of the device address is set by a combination of the ase l0 and ase l1 configuration pins and the mfr_ address command. when this addressing means is used, the page command determines the channel being acted upon. device addressing can be disabled by writing a value of 0x80 to the mfr_address. rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (polyphase). while similar to global addressing, the rail address can be dynamically assigned with the paged mfr_rail_ address command, allowing for any logical grouping of channels that might be required for reliable system control. reading from rail addresses is also strongly discouraged. all four means of pmbus addressing require the user to employ disciplined planning to avoid addressing conflicts. communication to ltc3884 devices at global and rail ad - dresses should be limited to command write operations.responses to v out and i in /i out faults v out ov and uv conditions are monitored by comparators. the ov and uv limits are set in three ways. n as a percentage of the v out if using the resistor configuration pins n in nvm if either programmed at the factory or through the gui n by pmbus command the i in and i out overcurrent monitors are performed by adc readings and calculations. thus these values are based on average currents and can have a time latency of up to t convert . the i out calculation accounts for the dcr or sense resistor and their temperature coefficient. the input current is equal to the voltage measured across the r iinsns resistor divided by the resistors value as set with the mfr_rvin command. if this calculated input current exceeds the in_oc_warn_limit the alert pin is pulled low and the iin_oc_warn bit is asserted in the status_input command.the digital processor within the ltc3884 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). the retry interval is set in mfr_retry _ delay and can be from 120ms to 83.88 seconds in 1ms increments. the shutdown for ov/uv and oc can be done immediately or after a user selectable deglitch time. output overvoltage fault response a programmable overvoltage comparator (ov) guards against transient overshoots as well as long-term over - voltages at the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on. however, the reverse output current is monitored while device is in ov fault. when it reaches the limit, both top and bottom mosfets are turned off. the top and bottom mosfets will keep their state until the overvoltage condition is cleared regardless of the pmbus vout_ov_fault_response command byte value. this hardware level fault response delay is typically 2s from the overvoltage condition to bg asserted high. using the vout_ov_fault_response command, the user can select any of the following behaviors : n ov pull-down only (ov cannot be ignored) n shut down (stop switching) immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay either the latch off or retry fault responses can be de - glitched in increments of (0-7) ? 10s. see table?7. downloaded from: http:///
lt c3884 31 3884fb for more information www.linear.com/ltc3884 operation output undervoltage response the response to an undervoltage comparator output can be the following: n ignore n shut down immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay. the uv responses can be deglitched. see table?8. peak output overcurrent fault response due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle-by- cycle basis. the value of the peak current limit is specified in sense voltage in the ec table. the current limit circuit operates by limiting the i th maximum voltage. if dcr sens - ing is used, the i th maximum voltage has a temperature dependency directly proportional to the tc of the dcr of the inductor. the ltc3884 automatically monitors the external temperature sensors and modifies the maximum allowed i th to compensate for this term. the overcurrent fault processing circuitry can execute the following behaviors: n current limit indefinitely n shut down immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay. the overcurrent responses can be deglitched in increments of (0-7) ? 16ms. see table 9 responses to timing faults ton_max_fault_limit is the time allowed for v out to rise and settle at start-up. the ton_max_fault_limit condition is predicated upon detection of the vout_uv_ fault_limit as the output is undergoing a soft_start sequence. the ton_max_ fault_limit time is started after ton_delay has been reached and a soft_start sequence is started. the resolution of the ton_max_ fault_limit is 10s . if the vout_uv_fault _limit is not reached within the ton_max_fault_limit time, the response of this fault is determined by the value of the ton_max_fault_response command value. this response may be one of the following: n ignore n shut down (stop switching) immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay. this fault response is not deglitched. a value of 0 in ton_max_fault_limit means the fault is ignored. the ton_max_fault_limit should be set longer than the ton_rise time. it is recommended ton_max_fault_ limit always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user. see table 11. responses to v in ov faults v in overvoltage is measured with the adc. the response is naturally deglitched by the 100ms typical response time of the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay . see table?11. responses to ot/ut faults internal overtemperature fault response an internal temperature sensor protects against nvm damage. above 85 c , no writes to nvm are recommended. above 130c ,the internal overtemperature warn threshold is exceeded and the part disables the nvm and does not re- enable until the temperature has dropped to 125c . when the die temperature exceed 160 c the internal temperature fault response is enabled and the pwm is disabled until the die temperature drops below 150c . temperature is measured by the adc. internal temperature faults cannot be ignored. internal temperature limits cannot be adjusted by the user. see table 10. downloaded from: http:///
lt c3884 32 3884fb for more information www.linear.com/ltc3884 operation external overtemperature and undertemperature fault response two external temperature sensors can be used to sense the temperature of critical circuit elements like inductors and power mosfets. the ot_fault _ response and ut_fault _ respose commands are used to determine the appropriate response to an overtemperature and under temperature condition, respectively. if no external sense elements are used (not recommended) set the ut_fault_ response to ignore and set the ut_fault_limit to C275c. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay . see table 9. responses to input overcurrent and output undercurrent faults input overcurrent and output undercurrent are measured with the adc. the fault responses are: n ignore n shut down immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay see table 11. responses to external faults when either fault n pin is pulled low, the other bit is set in the status_word command, the appropriate bit is set in the status_mfr_specific command, and the alert pin is pulled low. responses are not deglitched. each channel can be configured to ignore or shut down then retry in response to its fault n pin going low by modifying the mfr_fault_response command. to avoid the alert pin asserting low when fault is pulled low, assert bit 1 of mfr_chan_config , or mask the alert using the smbalert_mask command. fault logging the ltc3884 has fault logging capability. data is logged into memory in the order shown in table?13. the data is stored in a continuously updated buffer in ram. when a fault event occurs, the fault log buffer is copied from the ram buffer into nvm. fault logging is allowed at tem - peratures above 85c; however, retention of 10 years is not guaranteed. when the die temperature exceeds 130c the fault logging is delayed until the die temperature drops below 125c . the fault log data remains in nvm until a mfr_fault _ log_clear command is issued. issuing this command re-enables the fault log feature. before re-enabling fault log, be sure no faults are present and a clear_faults command has been issued. when the ltc3884 powers-up or exits its reset state, it checks the nvm for a valid fault log. if a valid fault log exists in nvm, the valid fault log bit in the status_ mfr_specific command will be set and an alert event will be generated. also, fault logging will be blocked until the ltc3884 has received a mfr_fault_log_clear command before fault logging will be re-enabled. the information is stored in eeprom in the event of any fault that disables the controller on either channel. a fault n being externally pulled low will not trigger a fault logging event.bus timeout protection the ltc3884 implements a timeout feature to avoid per - sistent faults on the serial interface. the data packet timer begins at the first start event before the device address write byte. data packet information must be completed within 30ms or the ltc3884 will three-state the bus and ignore the given data packet. if more time is required, assert bit 3 of mfr_config_all to allow typical bus timeouts of 255ms . data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the pec byte if applicable. downloaded from: http:///
lt c3884 33 3884fb for more information www.linear.com/ltc3884 operation the ltc3884 allows longer pmbus timeouts for block read data packets. this timeout is proportional to the length of the block read. the additional block read timeout applies primarily to the mfr_fault_log command. the timeout period defaults to 32ms.the user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. the ltc3884 supports the full pmbus frequency range from 10khz to 400khz. similarity between pmbus, smbus and i 2 c 2-wire interface the pmbus 2- wire interface is an incremental extension of the smbus. smbus is built upon i 2 c with some minor differences in timing, dc parameters and protocol. the pmbus/smbus protocols are more robust than simple i 2 c byte commands because pmbus/smbus provide timeouts to prevent persistent bus errors and optional packet error checking (pec) to ensure data integrity. in general, a master device that can be configured for i 2 c communication can be used for pmbus communication with little or no change to hardware or firmware. repeat start (restart) is not supported by all i 2 c controllers but is required for smbus/pmbus reads. if a general purpose i 2 c controller is used, check that repeat start is supported. the ltc3884 supports the maximum smbus clock speed of 100khz and is compatible with the higher speed pm - bus specification (between 100khz and 400khz ) if mfr_ common polling or clock stretching is enabled. for robust communication and operation refer to the note section in the pmbus command summary. clock stretching is enabled by asserting bit 1 of mfr_config_all. for a description of the minor extensions and exceptions pmbus makes to smbus, refer to pmbus specification part 1 revision 1.2: paragraph 5: transport. for a description of the differences between smbus and i 2 c, refer to system management bus (smbus) speci - fication version 2.0 : appendix b differences between smbus and i 2 c. pmbus serial digital interface the ltc3884 communicates with a host (master) using the standard pmbus serial bus interface. the timing diagram, figure 7, shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the ltc3884 is a slave device. the master can communicate with the ltc3884 using the following formats: n master transmitter, slave receiver n master receiver, slave transmitter the following pmbus protocols are supported: n write byte, write word, send byte n read byte, read word, block read, block write n alert response address figures 8- 25 illustrate the aforementioned pmbus pro - tocols. all transactions support pec and gcp (group command protocol). the block read supports 255 bytes of returned data. for this reason, the pmbus timeout may be extended when reading the fault log. figure 8 is a key to the protocol diagrams in this section. pec is optional. a value shown below a field in the following figures is mandator y value for that field. the data formats implemented by pmbus are: n master transmitter transmits to slave receiver. the transfer direction in this case is not changed. n master reads slave immediately after the first byte. at the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. n combined format. during a change of direction within a transfer, the master repeats both a start condition and the slave address but with the r/ w bit reversed. in this case, the master receiver terminates the transfer by generating a nack on the last byte of the transfer and a stop condition. downloaded from: http:///
lt c3884 34 3884fb for more information www.linear.com/ltc3884 operation sda scl t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf start condition stop condition repeated start condition start condition t r t f t r t f t high 3884 f07 table 1. abbreviations of supported data formats pmbus terminology specification reference ltc terminology definition example l11 linear part ii ?7.1 linear_5s_1s floating point 16-bit data: value = y ? 2 n , where n = b[15:1] and y = b[10:0], both twos compliment binary integers. b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 ? 2 C13 = 854e-6 l16 linear vout_mode part ii ?8.2 linear_16u floating point 16-bit data: value = y? ? ?2 C12 , where y = b[15:0], an unsigned integer. b[15:0] = 0x4c00 = 0100_1100_0000_0000 value = 19456 ? 2 C12 = 4.75 cf direct part ii ?7.2 varies 16-bit data with a custom format defined in the detailed pmbus command description. often an unsigned or twos compliment integer. reg register bits part ii ?10.3 reg per-bit meaning defined in detailed pmbus command description. pmbus status_byte command. asc text characters part ii ?22.2.1 ascii iso/iec 8859-1 [a05] ltc (0x4c5443) figure 7. timing diagram refer to figure 8 for a legend. handshaking features are included to ensure robust system communication. please refer to the pmbus communication and command processing subsection of the applications information section for further details. downloaded from: http:///
lt c3884 35 3884fb for more information www.linear.com/ltc3884 operation figure 9. quick command protocol figure 10. send byte protocol figure 11. send byte protocol with pec figure 8. pmbus packet protocol diagram element key figure 13. write byte protocol with pec figure 14. write word protocol figure 15. write word protocol with pec figure 12. write byte protocol 3884 f08 s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition pec packet error code master to slave slave to master continuation of protocol ... slave address rd/wr a p 3884 f09 s 7 1 1 1 1 slave address command code wr a a p 3884 f10 s 7 8 1 1 1 1 1 slave address command code pec wr a a a p 3884 f11 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 3884 f12 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 3884 f13 s 7 8 8 1 pec 8 1 1 1 1 1 1 a slave address command code data byte wr a a a p 3884 f14 s 7 8 8 1 1 1 1 1 1 slave address command code data byte wr a a a p 3884 f15 s 7 8 8 1 pec 8 1 1 1 1 1 1 a downloaded from: http:///
lt c3884 36 3884fb for more information www.linear.com/ltc3884 operation figure 19. read word protocol with pec figure 20. block read protocol figure 18. read word protocol figure 21. block read protocol with pec figure 17. read byte protocol with pec figure 16. read byte protocol slave address command code slave address wr a a sr p 3884 f16 s 7 8 11 data byte 8 1 1 1 1 1 1 1 7 a rd a slave address command code slave address wr a a sr p 3884 f17 s 7 8 7 11 data byte 8 1 1 1 1 1 1 1 a rd a 1 a pec slave address command code slave address wr a a a p 3884 f18 s 7 8 7 1 data byte low 8 data byte high 8 1 1 1 1 sr 1 1 1 1 a 1 rd a slave address command code slave address wr a a a pa 3884 f19 s 7 8 7 1 data byte low 8 data byte high pec 8 8 1 1 1 1 1 11 1 sr 1 a 1 rd a slave address command code slave address wr a a sr s 7 8 7 11 byte count = n 8 1 1 1 1 1 1 a rd a a pa 3884 f22 data byte 1 8 data byte 2 data byte n 8 8 1 1 11 a slave address command code slave address wr a a sr s 7 8 7 11 byte count = n 8 1 1 1 1 1 1 a rd a a data byte 1 8 data byte 2 8 1 1 a a pa 3884 f21 data byte n pec 8 8 1 11 downloaded from: http:///
lt c3884 37 3884fb for more information www.linear.com/ltc3884 operation figure 22. block write C block read process call figure 24. alert response address protocol figure 25. alert response address protocol with pec figure 23. block write C block read process call with pec slave address command code byte count = m wr a a s 7 8 8 1 data byte 1 8 1 1 1 1 1 a a a data byte 2 8 1 a data byte m 8 1 slave address byte count = n rd a a sr 7 8 data byte 1 8 1 1 1 1 1 1 a p 3884 f22 1 a data byte 2 8 1 a data byte n 8 1 slave address command code byte count = m wr a a s 7 8 8 1 data byte 1 8 1 1 1 1 1 a a a data byte 2 8 1 a data byte m 8 1 slave address byte count = n rd a a sr 7 8 data byte 1 8 1 1 1 1 1 1 a a data byte 2 8 1 a data byte n 8 1 p 3884 f23 1 a pec 8 1 alert response address rd a a p 3884 f24 s 7 8 1 1 1 1 1 device address alert response address rd a a s 7 8 1 1 1 1 device address a p 3884 f25 8 1 1 pec downloaded from: http:///
lt c3884 38 3884fb for more information www.linear.com/ltc3884 command name cmd code description type paged data format units nvm default value page page 0x00 provides integration with multi-page pmbus devices. r/w byte n reg 0x00 70 operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte y reg y 0x80 72 on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte y reg y 0x1e 74 clear_faults 0x03 clear any fault bits that have been set. send byte n na 99 page_plus_write 0x05 write a command directly to a specified page. w block n 69 page_plus_read 0x06 read a command directly from a specified page. block r/w n 70 write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte n reg y 0x00 71 store_user_all 0x15 store user operating memory to eeprom. send byte n na 109 restore_user_all 0x16 restore user operating memory from eeprom. send byte n na 109 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte n reg 0xb0 98 smbalert_mask 0x1b mask alert activity block r/w y reg y see cmd 99 vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte y reg 2 C12 0x14 80 vout_command 0x21 nominal output voltage set point. r/w word y l16 v y 1.0 0x1000 81 vout_max 0x24 upper limit on the commanded output voltage including vout_margin_hi. r/w word y l16 v y 2.75 0x2c00 80 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_command. r/w word y l16 v y 1.05 0x10cd 81 vout_margin_low 0x26 margin low output voltage set point. must be less than vout_command. r/w word y l16 v y 0.95 0x0f33 81 table 2. summary ( note: the data format abbreviations are detailed at the end of this table.) pmbus command summary pmbus commandsthe following tables list supported pmbus commands and manufacturer specific commands. a complete description of these commands can be found in the pmbus power system mgt protocol specification C part ii C revision 1.2 . users are encouraged to reference this specification. exceptions or manufacturer specific implementations are listed below in table 2. floating point values listed in the default value column are either linear 16- bit signed (pmbus section 8.3.1) or linear_5s_11s (pmbus section 7.1) format, whichever is appropriate for the command. all commands from 0xd0 through 0x ff not listed in this table are implicitly reserved by the manufacturer. users should avoid blind writes within this range of commands to avoid undesired operation of the part. all commands from 0x 00 through 0x cf not listed in this table are im - plicitly not supported by the manufacturer. attempting to access non-supported or reserved commands may result in a cml command fault event. all output voltage settings and measurements are based on the vout_mode setting of 0x14. this translates to an exponent of 2 C12 . if pmbus commands are received faster than they are be - ing processed, the part may become too busy to handle new commands. in these cir cumstances the part follows the protocols defined in the pmbus specification v1.2, part ii, section 10.8.7, to communicate that it is busy . the part includes handshaking features to eliminate busy errors and simplify error handling software while ensur - ing robust communication and system behavior. please refer to the subsection titled pmbus communication and command processing in the applications information section for further details. downloaded from: http:///
lt c3884 39 3884fb for more information www.linear.com/ltc3884 pmbus command summary command name cmd code description type paged data format units nvm default value page vout_transition_rate 0x27 rate the output changes when vout commanded to a new value. r/w word y l11 v/ms y 0.25 0xaa00 87 frequency_switch 0x33 switching frequency of the controller. r/w word n l11 khz y 425k 0xfb52 78 vin_on 0x35 input voltage at which the unit should start power conversion. r/w word n l11 v y 6.5 0xcb40 79 vin_off 0x36 input voltage at which the unit should stop power conversion. r/w word n l11 v y 6.0 0xcb00 79 iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. for devices using a fixed current sense resistor, it is the resistance value in m. r/w word y l11 m y 0.32 0xaa8b 82 vout_ov_fault_limit 0x40 output overvoltage fault limit. r/w word y l16 v y 1.1 0x119a 80 vout_ov_fault_response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte y reg y 0xb8 89 vout_ov_warn_limit 0x42 output overvoltage warning limit. r/w word y l16 v y 1.075 0x1133 80 vout_uv_warn_limit 0x43 output undervoltage warning limit. r/w word y l16 v y 0.925 0x0ecd 81 vout_uv_fault_limit 0x44 output undervoltage fault limit. r/w word y l16 v y 0.9 0x0e66 81 vout_uv_fault_response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte y reg y 0xb8 90 iout_oc_fault_limit 0x46 output overcurrent fault limit. r/w word y l11 a y 45.0 0xe2d0 83 iout_oc_fault_response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte y reg y 0x00 92 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word y l11 a y 35.0 0xe230 84 ot_fault_limit 0x4f external overtemperature fault limit. r/w word y l11 c y 100.0 0xeb20 85 ot_fault_response 0x50 action to be taken by the device when an external overtemperature fault is detected, r/w byte y reg y 0xb8 94 ot_warn_limit 0x51 external overtemperature warning limit. r/w word y l11 c y 85.0 0xeaa8 85 ut_fault_limit 0x53 external undertemperature fault limit. r/w word y l11 c y C40.0 0xe580 86 ut_fault_response 0x54 action to be taken by the device when an external undertemperature fault is detected. r/w byte y reg y 0xb8 94 vin_ov_fault_limit 0x55 input supply overvoltage fault limit. r/w word n l11 v y 15.5 0xd3e0 78 vin_ov_fault_response 0x56 action to be taken by the device when an input overvoltage fault is detected. r/w byte y reg y 0x80 89 vin_uv_warn_limit 0x58 input supply undervoltage warning limit. r/w word n l11 v y 6.3 0xcb26 79 iin_oc_warn_limit 0x5d input supply overcurrent warning limit. r/w word n l11 a y 10.0 0xd280 84 ton_delay 0x60 time from run and/or operation on to output rail turn-on. r/w word y l11 ms y 0.0 0x8000 86 downloaded from: http:///
lt c3884 40 3884fb for more information www.linear.com/ltc3884 pmbus command summary command name cmd code description type paged data format units nvm default value page ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word y l11 ms y 8.0 0xd200 86 ton_max_fault_limit 0x62 maximum time from the start of ton_rise for vout to cross the vout_uv_fault_limit. r/w word y l11 ms y 10.00 0xd280 87 ton_max_fault_response 0x63 action to be taken by the device when a ton_ max_fault event is detected. r/w byte y reg y 0xb8 92 toff_delay 0x64 time from run and/or operation off to the start of toff_fall ramp. r/w word y l11 ms y 0.0 0x8000 87 toff_fall 0x65 time from when the output starts to fall until the output reaches zero volts. r/w word y l11 ms y 8.00 0xd200 87 toff_max_warn_limit 0x66 maximum allowed time, after toff_fall completed, for the unit to decay below 12.5%. r/w word y l11 ms y 150.0 0xf258 88 status_byte 0x78 one byte summary of the units fault condition. r/w byte y reg na 100 status_word 0x79 two byte summary of the units fault condition. r/w word y reg na 101 status_vout 0x7a output voltage fault and warning status. r/w byte y reg na 101 status_iout 0x7b output current fault and warning status. r/w byte y reg na 102 status_input 0x7c input supply fault and warning status. r/w byte n reg na 102 status_temperature 0x7d external temperature fault and warning status for read_temerature_1. r/w byte y reg na 103 status_cml 0x7e communication and memory fault and warning status. r/w byte n reg na 103 status_mfr_specific 0x80 manufacturer specific fault and state information. r/w byte y reg na 104 read_vin 0x88 measured input supply voltage. r word n l11 v na 106 read_iin 0x89 measured input supply current. r word n l11 a na 106 read_vout 0x8b measured output voltage. r word y l16 v na 106 read_iout 0x8c measured output current. r word y l11 a na 106 read_temperature_1 0x8d external temperature sensor temperature. this is the value used for all temperature related processing, including iout_cal_gain. r word y l11 c na 106 read_temperature_2 0x8e internal die junction temperature. does not affect any other commands. r word n l11 c na 106 read_frequency 0x95 measured pwm switching frequency. r word y l11 hz na 106 read_pout 0x96 measured output power r word y l11 w n/a 106 read_pin 0x97 calculated input power r word y l11 w n/a 107 pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.2. r byte n reg 0x22 98 mfr_id 0x99 the manufacturer id of the ltc3884 in ascii. r string n asc lt c 98 mfr_model 0x9a manufacturer part number in ascii. r string n asc ltc3884 98 mfr_vout_max 0xa5 maximum allowed output voltage including vout_ov_fault_limit. r word y l16 v 5.7 0x5b33 82 mfr_pin_accuracy 0xac returns the accuracy of the read_pin command r byte n % 5.0% 107 user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word n reg y na 98 downloaded from: http:///
lt c3884 41 3884fb for more information www.linear.com/ltc3884 pmbus command summary command name cmd code description type paged data format units nvm default value page user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word y reg y na 98 user_data_02 0xb2 oem reserved. typically used for part serialization r/w word n reg y na 98 user_data_03 0xb3 an nvm word available for the user. r/w word y reg y 0x0000 98 user_data_04 0xb4 an nvm word available for the user. r/w word n reg y 0x0000 98 mfr_ee_unlock 0xbd contact factory. 114 mfr_ee_erase 0xbe contact factory. 114 mfr_ee_data 0xbf contact factory. 114 mfr_chan_config 0xd0 configuration bits that are channel specific. r/w byte y reg y 0x1d 72 mfr_config_all 0xd1 general configuration bits. r/w byte n reg y 0x21 73 mfr_fault_propagate 0xd2 configuration that determines which faults are propagated to the fault pin. r/w word y reg y 0x6993 95 mfr_pwm_comp 0xd3 pwm loop compensation configuration r/w byte y reg y 0xae 76 mfr_pwm_mode 0xd4 configuration for the pwm engine. r/w byte y reg y 0xc7 75 mfr_fault_response 0xd5 action to be taken by the device when the fault pin is externally asserted low. r/w byte y reg y 0xc0 97 mfr_ot_fault_response 0xd6 action to be taken by the device when an internal overtemperature fault is detected. r byte n reg 0xc0 93 mfr_iout_peak 0xd7 report the maximum measured value of read_ iout since last mfr_clear_peaks. r word y l11 a na 107 mfr_adc_control 0xd8 adc telemetry parameter selected for repeated fast adc read back r/w byte n reg 0x00 108 mfr_retry_delay 0xdb retry interval during fault retry mode. r/w word y l11 ms y 350.0 0xfabc 88 mfr_restart_delay 0xdc minimum time the run pin is held low by the ltc3884. r/w word y l11 ms y 500.0 0xfbe8 88 mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word y l16 v na 107 mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word n l11 v na 107 mfr_temperature_1_peak 0xdf maximum measured value of external temperature (read_temperature_1) since last mfr_clear_peaks. r word y l11 c na 107 mfr_read_iin_peak 0xe1 maximum measured value of read_iin command since last mfr_clear_peaks r word n l11 a na 107 mfr_clear_peaks 0xe3 clears all peak values. send byte n na 100 mfr_read_ichip 0xe4 measured supply current of the ltc3884 r word n l11 a na 107 mfr_pads 0xe5 digital status of the i/o pads. r word n reg na 104 mfr_address 0xe6 sets the 7-bit i 2 c address byte. r/w byte n reg y 0x4f 72 mfr_special_id 0xe7 manufacturer code representing the ltc3884 and revision r word n reg 0x4c0x 98 mfr_iin_cal_gain 0xe8 the resistance value of the input current sense element in m. r/w word n l11 m y 5.0 0xca80 84 mfr_fault_log_store 0xea command a transfer of the fault log from ram to eeprom. send byte n na 110 downloaded from: http:///
lt c3884 42 3884fb for more information www.linear.com/ltc3884 pmbus command summary command name cmd code description type paged data format units nvm default value page mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging. send byte n na 114 mfr_fault_log 0xee fault log data bytes. r block n reg y na 110 mfr_common 0xef manufacturer status bits that are common across multiple ltc chips. r byte n reg na 105 mfr_compare_user_all 0xf0 compares current command contents with nvm. send byte n na 109 mfr_temperature_2_peak 0xf4 peak internal die temperature since last mfr_ clear_peaks. r word n l11 c na 108 mfr_pwm_config 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte n reg y 0x10 77 mfr_iout_cal_gain_tc 0xf6 temperature coefficient of the current sensing element. r/w word y cf ppm/ ? c y 3900 0x0f3c 82 mfr_rvin 0xf7 the resistance value of the v in pin filter element in m. r/w word n l11 m y 1000 0x03e8 79 mfr_temp_1_gain 0xf8 sets the slope of the external temperature sensor. r/w word y cf y 1.0 0x4000 85 mfr_temp_1_offset 0xf9 sets the offset of the external temperature sensor with respect to C273.1c r/w word y l11 c y 0.0 0x8000 85 mfr_rail_address 0x fa common address for polyphase outputs to adjust common parameters. r/w byte y reg y 0x80 72 mfr_real_time 0xfb 48-bit share-clock counter value. r block n cf na xx mfr_reset 0xfd commanded reset without requiring a power down. send byte n na 74 note 1: commands indicated with y in the nvm column indicate that these commands are stored and restored using the store_user_all and restore_user_all commands, respectively. note 2: commands with a default value of na indicate not applicable. commands with a default value of fs indicate factory set on a per part basis. note 3: the ltc3884 contains additional commands not listed in this table. reading these commands is harmless to the operation of the ic; however, the contents and meaning of these commands can change without notice. note 4: some of the unpublished commands are read-only and will generate a cml bit 6 fault if written.note 5: writing to commands not published in this table is not permitted. note 6: the user should not assume compatibility of commands between different parts based upon command names. always refer to the manufacturers data sheet for each part for a complete definition of a commands function. ltc strives to keep command functionality compatible between all ltc devices. differences may occur to address specific product requirements. downloaded from: http:///
lt c3884 43 3884fb for more information www.linear.com/ltc3884 pmbus command summary *data format l11 linear_5s_11s pmbus data field b[15:0] value = y ? 2 n where n = b[15:11] is a 5-bit twos complement integer and y = b[10:0] is an 11-bit twos complement integer example: for b[15:0] = 0x9807 = b10011_000_0000_0111 v alue = 7 ? 2 C13 = 854 ? 10 C6 from pmbus spec part ii: paragraph 7.1 l16 linear_16u pmbus data field b[15:0] value = y ? 2 n where y = b[15:0] is an unsigned integer and n = vout_mode_parameter is a 5-bit twos complement exponent that is hardwired to C12 decimal example: for b[15:0] = 0x9800 = b1001_1000_0000_0000 v alue = 19456 ? 2 C12 = 4.75 from pmbus spec part ii: paragraph 8.2 reg register pmbus data field b[15:0] or b[7:0]. bit field meaning is defined in detailed pmbus command description. i16 integer word pmbus data field b[15:0] value = y where y = b[15:0] is a 16 bit unsigned integer example: for b[15:0] = 0x9807 = b1001_1000_0000_0111 v alue = 38919 (decimal) cf custom format value is defined in detailed pmbus command description. this is often an unsigned or twos complement integer scaled by an mfr specific constant. asc ascii format a variable length string of text characters conforming to iso/iec 8859-1 standard. downloaded from: http:///
lt c3884 44 3884fb for more information www.linear.com/ltc3884 applications information the typical application on the back page is a common ltc3884 application circuit. the ltc3884 is mainly designed for low dcr application via pmbus command mfr_pwm_mode[2] = 1 applicable when 0 v out 3.5v , but it can be also configured to be regular dcr or regular resistor sensing by setting mfr_pwm_mode[2] = 0 for 0 v out 5.5v . the choice among them is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. low dcr provides the most power efficient solution, and best signal-to-noise ratio of the input sensing volt - age. the accuracy of the current reading and current limit are typically limited by the accuracy of the dcr resistor (accounted for in the iout_cal_gain parameter of the ltc3884 ). thus current sensing resistors provide the most accurate current sensing and limiting for the ap - plication. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. then the input and output capacitors are selected. to have a stable loop performance and reliability, the loop compensation parameters such as gm of error amplifier programmed by mfr_pwm_ comp[7:5] and rth by mfr_pwm _ comp [4:0] together with current limit value and voltage range set by bit 1 of mfr_ pwm_mode have to be properly selected. all other programmable parameters do not affect the loop gain, al - lowing parameters to be modified without impacting the transient response to load changes. current limit programming the cycle-by-cycle current limit ( = v isense /dcr or v isense /r sense ) is proportional to v ith , which can be programmed from 1.45 to 2.2v using the pmbus command i out _oc_fault_limit . see figure 26. the ltc3884 has four ranges of current limit programming. properly setting the value of mfr_pwm_mode[2] and mfr_pwm_mode [7] , and iout_oc_fault_limit , see the section of the pmbus commands, the device can regulate output voltage with the peak current under the value of iout_oc_fault_limit in normal operation. in case of output current exceeding that current limit, a oc v ith (v) 0 100 8060 40 20 0 C20C40 1.5 2.5 0.5 1 2 3 v isense (mv) 3994 f26 mfr_pwm_mode[2]=0mfr_pwm_mode[7]=1 mfr_pwm_mode[2]=0mfr_pwm_mode[7]=0 mfr_pwm_mode[2]=1mfr_pwm_mode[7]=1 mfr_pwm_mode[2]=1mfr_pwm_mode[7]=0 figure 26. v ith vs v isense fault will be issued. each range in figure 26 effects the loop gain, and subsequently effects the loop stability, so setting range of current limiting is a part of loop design. the ltc3884 will account for the dcr of the inductor if the device is configured for dcr sensing and automati - cally update the current limit as the inductor temperature changes. the temperature coefficient of the dcr is stored in the mfr_iout_tc register. for the best current limit accuracy, use the setting mfr_pwm_mode [2] = 1, mfr_pwm_mode [7] = 0, which will allow for the use of very low dcr inductors or sense resistors, the peak out - put current is up to 16mv /dcr, the application ltc3884 is mainly designed for. keep in mind this operation is on a cycle-by-cycle basis and is only a function of the peak inductor current. the average inductor current is monitored by the adc converter and can provide a warning if too much average output current is detected. the overcurrent fault is detected when the i th voltage hits the maximum value. the digital processor within the ltc3884 provides the ability to either ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). refer to the overcurrent portion of the operation section for mor e detail. i sense0 and i sense1 pins the i sense + and i sense C pins are the inputs to the current comparator and the a/d. the common mode input voltage range of the current comparators is 0v to 5.5v . both the sense pins are high impedance inputs with small input currents typically less than 1a . the high impedance downloaded from: http:///
lt c3884 45 3884fb for more information www.linear.com/ltc3884 applications information inputs to the current comparators enable accurate dcr sensing. do not float these pins during normal operation. filter components connected to the i sense traces should be placed close to the ic. the positive and negative traces should be routed differentially and kelvin connected to the current sense element ; see figure 27. a non-kelvin connec - tion or improper placement can add parasitic inductance and capacitance to the current sense element, degrading the signal at the sense terminals and making the programmed current limit perform poorly. in a polyphase system, poor placement of the sensing element will result in sub-optimal current sharing between power stages. if dcr sensing is used (figure 28a ), sense resistor r1 should be placed close to the inductor to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. any impedance difference between the i sense + and i sense C signal paths can result in loss of accuracy in the current reading of the adc. the current reading accuracy can be improved by matching the impedance of the two signal paths. to accomplish this add a series resistor r3 between v out and i sense C equal to r1 . a capacitor of 1f or greater should be placed in parallel with this resistor. rc = l/(5 ? dcr) @ mfr_pwm_mode [2] = 1 for low dcr rc = l/dcr @ mfr_pwm_mode [2] = 0 for normal dcr where: v sense(max) : maximum sense voltage for a given i th voltage i max : maximum load current ? i l : inductor ripple current l, dcr: output inductor characteristics rc: filter time constant to ensure the load current will be delivered over the full operating temperature range, the temperature coefficient of dcr resistance, approximately 0.4%/ ? c, should be taken into consideration. typically, c is selected in the range of 0.047f to 0.47f. this forces r1 to around 2k @ mfr_pwm_mode[2]=0, 400 @ mfr_pwm_mode [2 ]= 1 reducing error that might have been caused by the i sense pins 1a current ( r3 and c2 are for reducing sensing error caused by input current through r1).there will be some power loss in r that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: p loss r ( ) = v in(max) ? v out ( ) ? v out r ensure that r1 has a power rating higher than this value. however, dcr sensing eliminates the conduction loss of sense resistor ; it will provide better efficiency at heavy loads. to maintain a good signal-to-noise ra - tio for the current sense signal, it is best to enable the low dcr sensing network ( mfr_pwm_mode[2] = 1, rc = 1/5 l/dcr) when ? v sense (voltage across dcr) is as low as 2mv, which provides the ripple voltage is: v sense = v out v in ? v in ? v out rc ? f osc it is optional to choose low dcr or regular dcr sensing scheme if ? v sense is above 10mv. c out to sense filter,next to the controller inductor or r sense 3884 f27 figure 27. sense lines placement with inductor dcr inductor dcr sensing the dcr is the dc winding resistance of the inductor's copper, which is often less than 1m for high current inductors. in high current and low output voltage applica - tions, a conduction loss of a high dcr or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement, choose the inductor with the dcr that satisfies the maximum desirable sense voltage, and uses the relationship of the sense pin filters to output inductor characteristics as depicted in the following: dcr = v sense(max) i max + i l 2 downloaded from: http:///
lt c3884 46 3884fb for more information www.linear.com/ltc3884 applications information a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that the ripple current does not exceed a specified maxi - mum, the inductor should be chosen according to: l v out v in ? v out ( ) v in ? f osc ? i ripple inductor core selection once the inductor value is determined, the type of induc - tor must be selected. core loss is independent of core size for a fixed inductor value, but it is ver y dependent on inductance. as the inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core materials saturate hard, which means that the induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 28b . r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i limit setting. the input common mode range of the current comparator is 0v to 5.5v . the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak- to-peak ripple current ? i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + i l 2 v in v in intv cc boost tg sw bg gnd inductor dcr r3 optional c2 >1f l i sense + i sense C ltc3884 v out 3884 f28a r1 c1* figure 28a. inductor dcr current sense circuit figure 28b. resistor current sense circuit v in v in intv cc boost tg sw bg gnd filter components placed near sense pins i sense + i sense C ltc3884 v out 3884 f25b c f ? 2 rf esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductor peak-to-peak ripple current: i ripple = v out v in ? v out ( ) v in ? f osc ? l lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, at a given frequency, the highest efficiency operation is obtained with a small ripple current, which requires a large inductor. downloaded from: http:///
lt c3884 47 3884fb for more information www.linear.com/ltc3884 applications information due to possible pcb noise in the current sensing loop, the ac current sensing ripple of ? v sense = ? i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 15mv minimum ? v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. for previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mv for the ltc1628 / ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. in the newer and higher current density solutions, the value of the sense resistor can be less than 1m and the peak sense voltage can be less than 20mv . also, inductor ripple currents greater than 50% with operation up to 750khz are becoming more common. under these conditions, the voltage drop across the sense resistor s parasitic inductance is no longer negligible. a typical sensing circuit using a discrete resistor is shown in figure 28b . in previous generations of controllers, a small rc filter placed near the ic was commonly used to reduce the effects of the capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 100 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 200ns . this same rc filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 29a illustrates the voltage waveform across a 2m resistor with a pcb footprint of 2010. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time, t on , and off-time, t off , of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl = v esl(step) i l ? t on ? t off t on + t off (1) if the rc time constant is chosen to be close to the para - sitic inductance divided by the sense resistor (l/r), the resultant waveform looks resistive, as shown in figure 29b . for applications using low maximum sense voltages, check the sense resistor manufacturer s data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use equation 1 to determine the esl. however, do not overfilter the signal. keep the rc time constant less than or equal to the inductor time constant to maintain a sufficient ripple voltage on v rsense for optimal operation of the current loop controller. slope compensation and inductor peak current slope compensation provides stability in constant- frequency current-mode architectures by preventing sub-harmonic oscillations at high duty cycles. this is accomplished internally by adding a compensation ramp to the inductor current signal at duty cycles in excess of 35%. the ltc3884 uses a patented current limit technique that counteracts the compensating ramp. this allows the maximum inductor peak current to remain unaffected throughout all duty cycles. figure 29a. voltage measured directly across r sense figure 29b. voltage measured after the r sense filter 500ns/div v sense 20mv/div 3884 f29a v 500ns/div v sense 20mv/div 3884 f29b downloaded from: http:///
lt c3884 48 3884fb for more information www.linear.com/ltc3884 applications information where is the temperature dependency of r ds(on) and r dr (approximately 2 ) is the effective driver resistance at the mosfet s miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. the optional schottky diodes conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of opera - tion due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. variable delay time, soft-start and output voltage ramping the ltc3884 must enter the run state prior to soft-start. the run n pin is released after the part initializes and v in is greater than the vin_on threshold. if multiple ltc3884 s are used in an application, they should be configured to share the same run n pins. they all hold their respective run n pins low until all devices initialize and v in exceeds the vin_on threshold for all devices. the share_clk pin assures all the devices connected to the signal use the same time base. power mosfet and optional schottky diode selection two external power mosfets must be selected for each controller in the ltc3884 : one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bot - tom (synchronous) switch. the peak-to-peak drive levels are set by the int v cc voltage. this voltage is typically 5.5v . consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input volt - age is expected (v in < 5v ); then, sub-logic level threshold mosfets (v gs(th) < 3v ) should be used. pay close atten - tion to the bv dss specification for the mosfets as well ; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) ? r ds(on) + v in ( ) 2 i max 2 ?? ? ?? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v th(min) + 1 v th(min) ?? ?? ? ?? ? f osc p sync = v in ? v out v in i max ( ) 2 ? 1 + ( ) ? r ds(on) downloaded from: http:///
lt c3884 49 3884fb for more information www.linear.com/ltc3884 applications information after the run n pin releases, the controller waits for the user-specified turn-on delay ( ton_delay ) prior to ini - tiating an output voltage ramp. multiple ltc3884 s and other l tc parts can be configured to start with variable delay times. to work correctly, all devices use the same timing clock ( share_clk ) and all devices must share the run n pin. this allows the relative delay of all parts to be synchronized. the actual variation in the delay will be dependent on the highest clock rate of the devices con - nected to the share_clk pin (all linear technology ics are configured to allow the fastest share_clk signal to control the timing of all devices). the share_clk signal can be 10% in frequency, thus the actual time delays will have proportional variance. soft-start is performed by actively regulating the load volt - age while digitally ramping the target voltage from 0.0v to the commanded voltage set point. the rise time of the voltage ramp can be programmed using the ton_rise command to minimize inrush currents associated with the start-up voltage ramp. the soft-start feature is disabled by setting ton_rise to any value less than 0.250ms. the ltc3884 will perform the necessary math internally to assure the voltage ramp is controlled to the desired slope. however, the voltage slope cannot be any faster than the fundamental limits of the power stage. the shorter ton_rise time is set, the larger the discrete steps in the ton_rise ramp will appear. the number of steps in the ramp is equal to ton_rise/0.1ms. the ltc3884 pwm will always use discontinuous mode during the ton_rise operation. in discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor. this will allow the regulator to start up into a pre-biased load. there is no traditional tracking feature in the ltc3884. however, two outputs can be given the same ton_rise and ton_delay times to effectively ramp up at the same time. if the run pin is released at the same time and both ltc3884 s use the same time base, the outputs will track very closely. if the circuit is in a polyphase configuration, all timing parameters must be the same. the method of start-up sequencing described above is time based. for concatenated events it is possible to control the run n pins based on the pgood n pin of a different controller. there is 100s filtering to the pgood n inside the device. if unwanted transitions still occur on pgood n , place a capacitor to ground on the pgood n pin to filter the waveform. the rc time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. a value of 300s to 500s will provide some additional filtering without significantly delaying the trigger event. digital servo mode for maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the mfr_pwm_mode command. in digital servo mode, the ltc3884 will adjust the regulated output voltage based on the adc voltage reading. every 100ms the digital servo loop will step the lsb of the dac (nominally 1.375mv or 0.6875mv depending on the voltage range bit) until the output is at the correct adc reading. at power-up t his mode engages after ton_max_fault_limit unless the limit is set to 0 (infinite). if the ton_max_fault_limit is set to 0 (infinite), the servo begins after ton_rise is complete and v out has exceeded the vout_uv_fault_limit. this same point in time is when the output changes from discontinuous to the programmed mode as indicated in mfr_pwm_mode bit 0. refer to figure?30 for details on the v out waveform under time-based sequencing. if the ton_max_fault_limit is set to a value greater than 0 and the ton_max_fault_response is set to ignore 0x00, the servo begins: 1. after the ton_rise sequence is complete 2. after the ton_max_fault_limit time is reached ; and 3. after the vout_uv_fault_limit has been exceed or the iout_oc_fault_limit is no longer active. if the ton_max_fault_limit is set to a value greater than 0 and the ton_max_fault_response is not set to ignore 0x00, the servo begins: downloaded from: http:///
lt c3884 50 3884fb for more information www.linear.com/ltc3884 applications information 1. after the ton_rise sequence is complete;2. after the ton_max_fault_limit time has expired and both vout_uv_fault and iout_oc_fault are not present. the maximum rise time is limited to 1.3 seconds. in a polyphase configuration it is recommended only one of the control loops have the digital servo mode enabled. this will assure the various loops do not work against each other due to slight differences in the reference circuits. vout will decay at the natural rate determined by the load impedance. if the controller is in discontinuous mode, the controller will not pull negative current and the output will be pulled low by the load, not the power stage. the maximum fall time is limited to 1.3 seconds. the shorter toff_fall time is set, the larger the discrete steps in the toff_fall ramp will appear. the number of steps in the ramp is equal to toff_fall/0.1ms. toff_fall toff_delay time 3884 f31 v out figure 31. toff_delay and toff_fall soft off (sequenced off) in addition to a controlled start-up, the ltc3884 also sup - ports controlled turn-off. the toff_delay and toff_fall f un ctions are shown in figure 31. toff_fall is processed when the run pin goes low or if the part is commanded off. if the part faults off or fault n is pulled low externally and the part is programmed to respond to this, the output will three-state rather than exhibiting a controlled ramp. the output will decay as a function of the load. the output voltage will operate as shown in figure?31 so long as the part is in forced continuous mode and the toff_fall time is sufficiently slow that the power stage can achieve the desired slope. the toff_fall time can only be met if the power stage and controller can sink sufficient current to assure the output is at zero volts by the end of the fall time interval. if the toff_fall time is set shorter than the time required to discharge the load capacitance, the output will not reach the desired zero volt state. at the end of toff_fall , the controller will cease to sink current and dac voltage error (not to scale) time delay of 200-400ms digital servo mode enabled final output voltage reached ton_max_fault_limit ton_rise time 3884 f30 ton_delay v out figure 30. timing controlled v out rise intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry are derived from the intv cc pin. when the extv cc pin is shorted to gnd or tied to a voltage less than 4.7v , or v in is lower than 7v , an internal 5.5v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7v and v in is higher than 7v , the 5.5v regulator is turned off and an internal switch is turned on connecting extv cc . extv cc can be applied before v in . the regulator can supply a peak current of 100ma . both intv cc and extv cc need to be bypassed to ground with a minimum of 1f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and gnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. high input voltage application in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc3884 to be exceeded. the intv cc current, of which a large percentage is due to the gate charge current, is supplied from either the v in or extv cc pin. if the ltc3884 internal downloaded from: http:///
lt c3884 51 3884fb for more information www.linear.com/ltc3884 applications information regulator is powered from the v in pin, the power through the ic is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations in note 2 of the electrical characteristics. for example, at 70c ambient, the ltc3884 intv cc current is limited to less than 44ma from a 40v supply: t j = 70c + 44ma ? 40v ? 31c/w = 125c to prevent the maximum junction temperature from being exceeded, the ltc3884 internal ldo can be powered from the extv cc pin, providing significant system efficiency improvement and thermal gains. if the extv cc pin is not used to power intv cc , the extv cc pin must be tied to gnd; do not float this pin. the v in current resulting from the gate driver and control circuitry will be reduced to a minimum by supplying the intv cc current from the extv cc : v extvcc v in ?? ? ?? ? 1 efficiency ?? ? ?? ? tying the extv cc pin to a 5.5v supply reduces the junc - tion temperature in the previous example from 125c to : t j = 70 c + 42ma ? 5.5v ? 31 c /w + 2ma ? 40v ? 31 c /w = 80 c do not tie intv cc on the ltc3884 to an external supply because intv cc will attempt to pull the external supply high and hit current limit, significantly increasing the die temperature. for applications where v in is 5v , tie the v in and intv cc pins together to the 5v input through a 1 or 2.2 resis - tor as shown in figure 32. to minimize the voltage drop caused by the gate charge current a low esr capacitor must be connected to the v in /intv cc pins. this configu - ration will override the intv cc linear regulator and will prevent intv cc from dropping too low. make sure the intv cc voltage exceeds the r ds(on) test voltage for the mosfets, which is typically 4.5v for logic level devices. the uvlo on intv cc is set to approximately 4v. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost n pin supplies the gate drive voltages for the topside mos - fets. capacitor c b in the block diagram is charged through external diode d b from intv cc when the sw n pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw n , rises to v in and the boost n pin follows. with the topside mosfet on, the boost voltage is above the input supply : v boost = v in + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . figure 32. setup for a 5v input figure 33. boost circuit to minimize pwm jitter r vin 1 c in 3884 f32 5v c intvcc 4.7 f + intv cc ltc3884 pgnd v in v in tg ltc3884 sw d b intv cc boost c b 0.1f 1 to 5 v in c intvcc 4.7f 3884 f33 bg pgnd downloaded from: http:///
lt c3884 52 3884fb for more information www.linear.com/ltc3884 applications information pwm jitter has been observed in some designs operating at higher v in /v out ratios. this jitter does not substantially affect the circuit accuracy. referring to figure 33, pwm jitter can be removed by inserting a series resistor with a value of 1 to 5 between the cathode of the diode and the boostn pin. a resistor case size of 0603 or larger is recommended to reduce esl and achieve the best results. undervoltage lockout the ltc3884 is initialized by an internal threshold-based uvlo where v in must be approximately 4v and intv cc , v dd33 , and v dd25 must be within approximately 20% of their regulated values. in addition, v dd33 must be within approximately 7% of the targeted value before the run pin is released. after the part has initialized, an additional comparator monitors v in . the vin_on threshold must be exceeded before the power sequencing can begin. when v in drops below the vin_off threshold, the share_clk pin will be pulled low and v in must increase above the vin_on threshold before the controller will restart. the normal start-up sequence will be allowed after the vin_on threshold is crossed. if faultb is held low when v in is applied, alert will be asserted low even if the part is programmed to not assert alert when faultb is held low. if i 2 c communication occurs before the ltc3884 is out of reset and only a portion of the command is seen by the part, this can be interpreted as a cml fault. if a cml fault is detected, alert is asserted low. it is possible to program the contents of the nvm in the application if the v dd33 supply is externally driven directly to v dd33 or through extv cc . this will activate the digital portion of the ltc3884 without engaging the high volt - age sections. pmbus communications are valid in this supply configuration. if v in has not been applied to the ltc3884 , bit?3 (nvm not initialized) in mfr_common will be asserted low. if this condition is detected, the part will only respond to addresses 5a and 5b. to initialize the part issue the following set of commands : global ad - dress 0x 5b command 0x bd data 0x 2b followed by global address 5b command 0x bd and data 0xc4 . the part will now respond to the correct address. configure the part as desired then issue a store_user_all . when v in is ap - plied a mfr_reset command must be issued to allow the pwm to be enabled and valid adc conversions to be read. c in and c out selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ?? ? 1/2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com - monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci - tor , or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3884 , ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question.the benefit of using a ltc3884 in 2- phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power loss is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor s esr. this is why the input capacitor s requirement cal - culated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the sources of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may pro - duce undesirable voltage and current resonances at v in . downloaded from: http:///
lt c3884 53 3884fb for more information www.linear.com/ltc3884 applications information a small ( 0.1f to 1f ) bypass capacitor between the chip v in pin and ground, placed close to the ltc3884 , is also suggested. a 2.2 to 10 resistor placed between c in (c1 ) and the v in pin provides further isolation between the two ltc3884s. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: v out i ripple esr + 1 8 ? f ? c out ?? ? ?? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc - tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. fault indication the ltc3884 fault pins are configurable to indicate a variety of faults including ov, uv, oc, ot, timing faults, and peak over current faults. in addition, the fault pins can be pulled low by external sources indicating a fault in some other portion of the system. the fault response is configurable and allows the following options: n ignore n shut down immediatelylatch off n shut down immediately retry indefinitely at the time interval specified in mfr_retry_delay refer to the pmbus section of the data sheet and the pmbus specification for more details. the ov response is automatic. if an ov condition is de - tected, tg n goes low and bg n is asserted. fault logging is available on the ltc3884 . the fault log - ging is configurable to automatically store data when a fault occurs that causes the unit to fault off. the header portion of the fault logging table contains peak values. it is possible to read these values at any time. this data will be useful while troubleshooting the fault. if the ltc3884 internal temperature is in excess of 85c, writes into the nvm (other than fault logging) are not recommended. the data will still be held in ram, unless the 3.3v supply uvlo threshold is reached. if the die temperature exceeds 130c all nvm communication is disabled until the die temperature drops below 120c.open-drain pins the ltc3884 has the following open-drain pins: 3.3v pins 1. fault 2. sync 3. share_clk 4. pgood n 5v pins ( 5v pins operate correctly when pulled to 3.3v.) 1. run n 2. alert 3. scl 4. sda all the above pins have on-chip pull-down transistors that can sink 3ma at 0.4v . the low threshold on the pins is 1.4v; thus, there is plenty of margin on the digital signals with 3ma of current. for 3.3v pins, 3ma of current is a 1.1k resistor. unless there are transient speed issues associated with the rc time constant of the resistor pull-up and parasitic capacitance to ground, a 10k resistor or larger is generally recommended.for high speed signals such as the sda, scl and sync, a lower value resistor may be required. the rc time con - stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. for a 100pf load and a 400khz pmbus communication rate, the rise time must be less than 300ns . the resistor pull-up on the sda and scl pins with the time constant set to 1/3 the rise time is: r pullup = t rise 3 ? 100pf = 1k downloaded from: http:///
lt c3884 54 3884fb for more information www.linear.com/ltc3884 applications information the closest 1% resistor value is 1k . be careful to minimize parasitic capacitance on the sda and scl pins to avoid communication problems. to estimate the loading capaci - tance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. this is a one time constant. the sync pin has an on-chip pull-down transistor with the output held low for nominally 500ns . if the internal oscil - lator is set for 500khz and the load is 100pf and a 3x time constant is required, the resistor calculation is as follows : r pullup = 2s ? 500ns 3 ? 100pf = 5k the closest 1% resistor is 4.99k.if timing errors are occurring or if the sync frequency is not as fast as desired, monitor the waveform and determine if the rc time constant is too long for the application. if possible reduce the parasitic capacitance. if not reduce the pull-up resistor sufficiently to assure proper timing. the share_clk pull-up resistor has a similar equation with a period of 10s and a pull-down time of 1s . the rc time constant should be approximately 3s or faster. phase-locked loop and frequency synchronization the ltc3884 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. the pll is locked to the falling edge of the sync pin. the phase relationship between the pwm controller and the falling edge of sync is controlled by the lower 3 bits of the mfr_pwm _ config command. for polyphase applications, it is recommended that all the phases be spaced evenly. thus for a 2- phase system the signals should be 180 out of phase and a 4-phase system should be spaced 90. the phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the internal filter network. the pll lock range is guaranteed between 200khz and 1mhz . nominal parts will have a range beyond this; however, operation to a wider frequency range is not guaranteed. the pll has a lock detection circuit. if the pll should lose lock during operation, bit 4 of the status_mfr_specific command is asserted and the alert pin is pulled low. the fault can be cleared by writing a 1 to the bit. if the user does not wish to see the alert pin assert if a pll_fault occurs, the smbalert_mask command can be used to prevent the alert. if the sync signal is not clocking in the application, the nominal programmed frequency will control the pwm circuitry. however, if multiple parts share the sync pins and the signal is not clocking, the parts will not be syn - chronized and excess voltage ripple on the output may be present. bit 10 of mfr_pads will be asserted low if this condition exists. if the pwm signal appears to be running at too high a frequency, monitor the sync pin. extra transitions on the falling edge will result in the pll trying to lock on to noise versus the intended signal. review routing of digital control signals and minimize crosstalk to the sync signal to avoid this problem. multiple ltc3884 s are required to share one sync pin in polyphase configurations. for other configurations, connecting the sync pins to form a single sync signal is optional. if the sync pin is shared between ltc3884 s, only one ltc3884 can be programmed with a frequency output. all the other ltc3884 s should be programmed to disable the sync output. however their frequency should be programmed to the nominal desired value. downloaded from: http:///
lt c3884 55 3884fb for more information www.linear.com/ltc3884 applications information minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3884 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn off the top mosfet. low duty cycle applications may approach this minimum limit and care should be taken to ensure that: t on(min) < v out v in ? f osc if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3884 is approximately 90ns . reasonably good pcb layout, minimum 30% induc - tor current ripple and at least 2mv for low dcr structure or 10mv to 15mv for regular dcr ripple on the current sense signal are required to avoid increasing the minimum on-time. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak current sense voltage decreases, the minimum on-time gradually increases to 130ns . this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. external temperature sense the ltc3884 is capable of measuring the power stage temperature of each channel. multiple methods using silicon junction type remote sensors are supported. the voltage produced by the remote sense circuit is digitized by the internal adc, and the computed temperature value is returned by the paged read_temperature _1 telem - etry command. the most accurate external temperature measurement can be made using a diode-connected pnp transistor such as the mmbt3906 as shown in figure 34 with bit 5 of mfr_pwm_mode should be set to 0 ?v be when using this sensor configuration. the transistor should be placed in contact with or immediately adjacent to the power stage inductor. its emitter should be connected to the tsns n pin while the base and collector terminals of the pnp transistor should be returned to the ltc3884 gnd paddle using a kevin connection. for best noise immunity, the connec - tions should be routed differentially and a 10nf capacitor should be placed in parallel with the diode-connected pnp. parasitic pcb trace inductance between the capacitor and transistor should be minimized. avoid placing pcb vias between the transistor and capacitor. tsns ltc3884 1nf 495a 1.35v at 25c gnd gnd 3884 f35 tsns mmbt3906 ltc3884 10nf gnd gnd 3884 f34 figure 35. 2d+r temperature sense figure 34. external ?v be temperature sense the ltc3884 also supports direct junction voltage mea - surements when bit 5 of mfr_pwm_mode_ltc3884 is set to 1. the factory defaults support a resistor trimmed dual diode network as shown in figure 35. this second measurement method is not generally as accurate as the first, but it supports legacy power blocks or may prove necessary if high noise environments prevent use of the ? v be approach with its lower signal levels. for either method, the slope of the external temperature sensor can be modified with the coefficient stored in mfr_temp _1_gain. with the ? v be approach, typical pnps require temperature slope adjustments slightly less than 1. the mmbt3906 has a recommended value in this command of approximately mfr_temp_1_gain = 0.991 based on the ideality factor of 1.01. simply invert the ideality factor to calculate the mfr_temp_1_gain. downloaded from: http:///
lt c3884 56 3884fb for more information www.linear.com/ltc3884 applications information different manufacturers and different lots may have dif - ferent ideality factors. consult with the manufacturer to set this value. bench characterization over temperature is recommended when adjusting mfr_temp _1_gain for the direct p-n junction measurement. the offset of the external temperature sense can be adjusted by mfr_temp_1_offset. if an external temperature sense element is not used, the tsns n pin must be shorted to gnd. the ut_fault_limit must be set to C275c , and the ut_fault_response must be set to ignore. the user also needs to set the iout_cal_gain_tc to a value of 0. to ensure proper use of these temperature adjustment parameters, refer to the specific formulas given for the two methods by the mfr_pwm_mode command in the later section covering pmbus command details.input current sense amplifier the ltc3884 input current sense amplifier can sense the supply current into the v in pin using an external resis - tor as well as the power stage current using an external sense resistor shown in figure 36. unless care is taken to mitigate the frequency noise caused by the discontinuous input current, significant input current measurement error may occur. the noise will be the greatest in high current applications and at large step-down ratios. careful layout and filtering at the v in pin is recommended to minimize measurement error. the v in pin should be filtered with a resistor and a ceramic capacitor. the filter should be located as close to the v in pin as possible. the supply side of the v in pin filter should be kelvin connected to the supply side of the r iinsns resistor. a 2 resistor should be sufficient for most applications. the resistor will cause an ir voltage drop from the supply to the v in pin due to the current flowing into the v in pin. to compensate for this voltage drop, the mfr_rvin command value should be set to the nominal resistor value. the ltc3884 will multiply the mfr_read_ichip measurement value by the user defined mfr_rvin value and add this voltage to the measured voltage at the v in pin. therefore read_vin = v vin_pin + ( mfr_read_ichip ? mfr_rvin) therefore the read_vin command will return the value of the voltage at the supply side of the v in pin filter. if no v in filter element is used, set mfr_rvin = 0. the capacitor from the drain of m1 to ground should be a low esr ceramic capacitor. it should be placed as close as possible to the drain of m1 to supply high frequency transient input current. this will help prevent noise from the top gate mosfet from feeding into the input current sense amplifier inputs and supply. if the input current sense amplifier is not used, short the v in , i in + , and i in C pins together. figure 36. low noise input current sense circuit 10f r iinsns m1m2 10f tg bg sw i in - i in + v in ltc3884 v in 2 3884 f36 external resistor configuration pins (rconfig) the ltc3884 is factory programmed to use the external resistor configuration. this allows output voltage, pwm frequency, pwm phasing, and the pmbus address to be set by the user without programming the part through the pmbus interface or purchasing custom programmed parts. to use resistor programming, the rconfig pins require a resistor divider between v dd25 and gnd. the rconfig pins are only interrogated at initial power up and during a reset, so modifying their values on the fly while the part is powered will have no effect. however, this does mean that rconfig pins on the same ic can be shared with a single resistor divider if they require identical program - ming. resistors with a tolerance of 1% or better must be used to assure proper operation. in the following tables, r top is connected between v dd25 and the rconfig pin while r bot is connected between the pin and gnd. noisy clock signals should not be routed near these pins. downloaded from: http:///
lt c3884 57 3884fb for more information www.linear.com/ltc3884 applications information voltage selection when an output voltage is set using the vout_cfg n pins (by table 3) the following parameters are set as a percent - age of the output voltage: n vout_ov_fault_limit .................................... +10% n vout_ov_warn_limit ................................... +7.5% n vout_max ....................................................... +7.5% n vout_margin_high..........................................+5% n vout_margin_low........................................... C 5% n vout_uv_warn_limit.................................. C 6.5% n vout_uv_fault_limit...................................... C 7% table 3. vout_cfg n resistor programming r top (k) r bottom (k) v out (v) 0 or open open nvm 10 23.2 5.000 10 15.8 3.300 16.2 20.5 2.500 16.2 17.4 1.800 20 17.8 1.500 20 15 1.350 20 12.7 1.250 20 11 1.200 24.9 11.3 1.150 24.9 9.09 1.100 24.9 7.32 1.050 24.9 5.76 0.900 24.9 4.32 0.750 30.1 3.57 0.650 30.1 1.96 0.600 open 0 power off frequency selection the pwm switching frequency is set according to table?4. the sync pins must be shared in polyphase configura - tions where multiple ltc3884 s or multiple ltc3884 s and ltc3874 s are used to produce the output. if the configu - ration is not polyphase the sync pins do not have to be shared. if the sync pins are shared between ltc3884s only one sync pin should be enabled ; all other sync pins should be disabled. a pull-up resistor to v dd33 is required on the sync pin. table 4. freq_cfg resistor programming r top (k) r bottom (k) frequency (khz) 0 or open open nvm 10 23.2 nvm 10 15.8 nvm 16.2 20.5 nvm 16.2 17.4 nvm 20 17.8 nvm 20 15 nvm 20 12.7 nvm 20 11 1000 24.9 11.3 750 24.9 9.09 650 24.9 7.32 575 24.9 5.76 500 24.9 4.32 425 30.1 3.57 350 30.1 1.96 250 open 0 external clock downloaded from: http:///
lt c3884 58 3884fb for more information www.linear.com/ltc3884 applications information phase selectionthe phase of the channels with respect to the falling edge of sync is set using the values in table?5. table 5. phase_cfg resistor programming r top (k) r bottom (k) sync to ch0 (degrees) sync to ch1 (degrees) sync enable 0 or open open nvm nvm nvm 10 23.2 nvm nvm nvm 10 15.8 nvm nvm nvm 16.2 20.5 120 300 disable 16.2 17.4 60 240 20 17.8 120 240 20 15 0 120 20 12.7 0 240 20 11 90 270 24.9 11.3 0 180 24.9 9.09 120 300 enable 24.9 7.32 60 240 24.9 5.76 120 240 24.9 4.32 0 120 30.1 3.57 0 240 30.1 1.96 90 270 open 0 0 180 for example in a 4- phase configuration clocked at 500khz, all of the ltc3884 s must be set to the desired frequency and phase and only one ltc3884 should be set to the desired frequency with the sync pin enabled. all phasing is with respect to the falling edge of sync. for ltc3884 chip 1, set the frequency to 500khz with 90 and 270 phase shift with the sync pin enabled: frequency r top = 24.9k and r bot = 5.76k phase r top = 30.1k and r bot = 1.96k for ltc3884 chip 2, set the frequency to 500khz with 0and 180 phase shift and the sync pin disabled: frequency 24.9k and r bot = 5.76k phase r top = 24.9k and r bot = 11.3k address selection using rconfig the ltc3884 address is selected based on the programming of the two configuration pins ase l0 and ase l1 according to table?6. ase l0 programs the bottom four bits of the device address for the ltc3884 , and ase l1 programs the three most significant bits. either portion of the address can also be retrieved from the mfr_address value in eeprom. if both pins are left open, the full 7-bit mfr_address value stored in eeprom is used to determine the device address. the ltc3884 always responds to 7- bit global addresses 0x 5a and 0x5b. mfr_address should not be set to either of these values because these are global addresses and all parts will respond to them. table 6. asel n resistor programming r top (k) r bottom (k) asel1 asel0 ltc3884 device address bits[6:4] ltc3884 device address bits [3:0] binary hex binary hex 0 or open open eeprom eeprom 10 23.2 1111 f 10 15.8 1110 e 16.2 20.5 1101 d 16.2 17.4 1100 c 20 17.8 1011 b 20 15 1010 a 20 12.7 1001 9 20 11 1000 8 24.9 11.3 111 7 0111 7 24.9 9.09 110 6 0110 6 24.9 7.32 101 5 0101 5 24.9 5.76 100 4 0100 4 24.9 4.32 011 3 0011 3 30.1 3.57 010 2 0010 2 30.1 1.96 001 1 0001 1 open 0 000 0 0000 0 downloaded from: http:///
lt c3884 59 3884fb for more information www.linear.com/ltc3884 applications information efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as : %efficiency = 100% C ( l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3884 circuits : 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur - rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, and current sense resistor. in continuous mode, the average out - put current flows through the inductor and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resis - tance of one mosfet can simply be summed with the resistances of the inductor and r sense to obtain i 2 r losses. for example, if each r ds(on) = 10m, r l = 10m , r sense = 5m , then the total resistance is 25m . this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) ? v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad - equate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. the ltc3884 2- phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky con - duction losses during dead time and inductor core losses generally account for less than 2% total additional loss. programmable loop compensation the ltc3884 offers programmable loop compensation to optimize the transient response without any hardware change. the error amplifier gain g m varies from 1.0mmho to 5.73mmho , and the compensation resistor r th varies from 0k to 62k inside the controller. two compensation capacitors, c th and c thp , are required in the design and the typical ratio between c th and c thp is 10. downloaded from: http:///
lt c3884 60 3884fb for more information www.linear.com/ltc3884 applications information adjusting the r th will change the pole and zero location, as shown in figure 38. it is recommended that the user determines the appropriate value for the g m and r th using the ltpowercad tool. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i thr external capacitor shown in the typical application circuit will provide an adequate starting point for most applications. the programmable parameters that affect loop gain are the voltage range, bit[1] of the mfr_pwm_config command, the current range, bit [2] and bit [7] of the mfr_pwm_mode com - mand, the g m of the pwm channel amplifier bits [7:5] of mfr_pwm_comp , and the internal r th compensation resistor, bits [4:0] of mfr_pwm_comp . be sure to es - tablish these settings prior to compensation calculation.the i th series internal r th external c th filter sets the dominant pole-zero loop compensation. the internal r th value can be modified (from 0 to 62k ) using bits [4:0] of the mfr_pwm _ comp command. adjust the value of r th to optimize transient response once the final pcb layout is done and the particular c th filter capacitor and output capacitor type and value have been determined. the output capacitors need to be selected because the various C + v ref fb 3884 f36 c thp c th ith r th ith_r g m figure 36. programmable loop compensation figure 37. error amp g m adjust figure 38. r th adjust increase r th frequency 3884 f38 gain type ii compensation by adjusting the g m and r th only, the ltc3884 can provide a flexible type ii compensation network to optimize the loop over a wide range of output capacitors. adjusting the g m will change the gain of the compensation over the whole frequency range without moving the pole and zero location, as shown in figure 37. increase g m frequency 3884 f37 gain type ii compensation downloaded from: http:///
lt c3884 61 3884fb for more information www.linear.com/ltc3884 applications information types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output volt - age and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce to a load step. the mosfet + r series will produce output currents approximately equal to v out /r series . r series values from 0.1 to 2 are valid depending on the current limit settings and the programmed output voltage. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r th and the bandwidth of the loop will be increased by decreasing c th . if r th is increased by the same factor that c th is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the gain of the loop will be proportional to the transconductance of the error amplifier which is set using bits [7:5] of the mfr_pwm_comp command. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f ) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1 : 50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. polyphase configurationwhen configuring a polyphase rail with multiple ltc3884s, the user must share the sync, i th , share_clk, fault , and alert pins of these parts. be sure to use pull-up resistors on fault , share_clk and alert . one of the part s sync pins must be set to the desired switching frequency, and all other frequency_switch commands must be set to external clock. if an external oscillator is provided, set the frequency_switch command to external clock for all parts. the relative phasing of all the channels should be spaced equally. the mfr_rail_ address of all the devices should be set to the same value. when connecting a polyphase rail with ltc3884 s, connect the v in pins of the ltc3884 s directly back to the supply voltage through the v in pin filter networks. master slave operation ltc3884 (as master) can work with ltc3874 (as slave) very efficiently to deliver very large output current. ltc3874 is a very small simple device, which has two current loops, but no pmbus, and no voltage loops. both ltc3884 and ltc3874 devices are mainly designed for low dcr application, and with the same relationship between v ith vs v isense (see figure 39). figure 39 is the schematic of a 3+1 application using a ltc3884 and a ltc3874. ltc3884 channel 0 provides v out0 of 1.5v and 30a output current, and channel 1 together with channel 0 and channel 1 in the ltc3874 to provide v out1 of 1.0v , with 90a output current. both chips are programmed to be low dcr configuration, and channel1 of ltc3884 and channel 0/1 of the ltc3874 are programmed to have the same current limit. connecting i th1 of ltc3884 with i th0 and i th1 of ltc3874 together forms three current loops. the voltage loop inside the ltc3884 regulates i th1 , which then regulates all three current loops with the same gain and current limit, and ultimately delivers the same amount of current per phase. programming the phase of each channel properly, these three channels form a perfect polyphase configuration. downloaded from: http:///
lt c3884 62 3884fb for more information www.linear.com/ltc3884 applications information figure 39. master/slave 3 +1 high efficiency, dual-output, 1.5v/30a and 1.0v/90a buck converter (ltc3884/ltc3874) 10nf 150pf 11% 0.1f d1 q1 bsc050ne2ls 0.1f d2 q3 bsc010ne2lsi q2 bsc050ne2ls q4 bsc010ne2lsi 2m 270f16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k 10k 10k l1 0.33h 9311% 220nf 330f6.3v x2 100f 6.3v x2 1500pf 2.2f 1f 10nf 47pf 1500pf 10f x2 4.7f l2 0.25h 7151% 220nf 330f 6.3v x2 100f 6.3v x2 24.9k 4.32k 20k 17.8k q6 bsc050ne2ls 0.1f d3 q7 bsc010ne2lsi 10f x2 0.1f d4 q8 bsc050ne2ls q9 bsc010ne2lsi 10fx2 10fx2 4.7f l3 0.25h 7151% 220nf 330f 6.3v x2 100f 6.3v x2 l4 0.25h 7151% 330f6.3v x2 100f6.3v x2 220nf 100k 10k 20k 2m intv cc ltc3884 v in v dd33 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 tg1 boost1 sw1 bg1 vout0_cfg vout1_cfg asel0 asel1 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc 7v to 14v v in 1f c3 v dd33 744301033 dcr=0.32 m v out0 mmbt3906-al3-r d1, d2, d3, d4: cmdsh3-tr 3884 ta05 744301025 dcr=0.32 m v dd33 v dd25 1.5v / 30a v in run0 run1 fault0 fault1 i th0 sync i th1 freq phasmd mode1 mode0 gnd ltc3874 i lim i sense1 C i sense0 C i sense0 + i sense1 + intv cc extv cc tg0 boost0 sw0 tg1 boost1 sw1 bg0 bg1 744301025 dcr=0.32 m 1.0v / 90a 744301025 falut i th1 sync fault run0 run1 run1 sync pgood0 pgood1 pgood1 intv cc1 intv cc1 v out1 sda scl alert share_ clk v dd25 downloaded from: http:///
lt c3884 63 3884fb for more information www.linear.com/ltc3884 applications information r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l0 d0 bold lines indicatehigh switching current. keep lines to a minimum length. l0 sw0 3884 f40b r sense0 v out0 c out0 figure 40b. branch current waveforms ltc3884 pgnd/sgnd i in C i sense + i sense C v in v dd25 v dd33 i th i th_r v sense C v sense + run sync tsns tg sw boost bg intv cc i in + c1 v in r iinsns + q1 l m1 1f ceramic c b 3884 f40a c in + c intvcc m2 d1 c out v out r sense + c vin r vin figure 40a. recommended printed circuit layout diagram, single phase shown downloaded from: http:///
lt c3884 64 3884fb for more information www.linear.com/ltc3884 applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 40a . figure 40b illustrates the current waveforms present in the various branches of a synchronous regulator operating in continuous mode. check the following in your layout: 1. is the top n-channel mosfet, m1 , located within 1cm of c in ? 2. are signal ground and power ground kept separate ? the ground return of c intvcc must return to the combined c out ( C ) terminals. 3. the i th trace should be as short as possible. 4. the loop formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. 5. the output capacitor ( C ) terminals should be connected as close as possible to the ( C ) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described in item 4. 6. are the i sense + and i sense C leads routed together with minimum pc trace spacing ? the filter capacitor between i sense + and i sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 7. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins ? this capacitor carries the mosfet driver current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and gnd pins can help improve noise performance substantially. 8. keep the switching nodes (sw n ), top gate nodes (tg n ), and boost nodes (boost n ) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3884 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 25a, r1 ) close to the switching node. pc board layout debugging it is helpful to use a dc- 50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw n pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation.investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost n , sw n , tg n , and possibly bg n connections and the sensitive volt - age and current pins. the capacitor placed across the cur - rent sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. downloaded from: http:///
lt c3884 65 3884fb for more information www.linear.com/ltc3884 applications information design exampleas a design example for a 2- channel medium current regulator, assume v in = 12v nominal, v in = 20v maximum, v out0 = 3.3v , v out1 = 1.5v , i max0,1 = 30a and f = 500khz. the regulated output is established by the vout_ command stored in nvm or placing the following resis - tor divider between v dd25 the rconfig pin and sgnd: 1. v out0_cfg , r top = 10k, r bottom = 15.8k 2. v out1_cfg , r top = 20k, r bottom = 17.8k the frequency and phase are set by nvm or by setting the resistor divider between v dd25 freq_cfg and sgnd and v dd25 phase_cfg and sgnd. frequency r top = 24.9k and r bottom = 5.76k phase r top = open and r bottom = 0 the address is set to xf where x is the msb stored in nvm. the following parameters are set as a percentage of the output voltage if the resistor configuration pins are used to determined output voltage: n vout_ov_fault_limit ..................................... +10% n vout_ov_warn_limit ................................... +7.5% n vout_max ....................................................... +7.5% n vout_margin_high..........................................+5% n vout_margin_low........................................... C 5% n vout_uv_warn_limit................................... C 6.5% n vout_uv_fault_limit....................................... C 7% all other user defined parameters must be programmed into the nvm. the gui can be utilized to quickly set up the part with the desired operating parameters. the inductance values are based on a 28% maximum ripple current assumption ( 8.4a ). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? i l(max) 1? v out v in(max) ? ? ?? ? ? ?? channel 0 will require 0.68h and channel 1 will require 0.33h . respectively. at the nominal input the ripple will be : i l(nom) = v out f ? l 1? v out v in(nom) ?? ?? ?? ?? channel 0 will have 8.1a (27%) ripple, and channel 1 will have 8.4a (28%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current or 34a for channel 0 and 34.2a for channel 1. the minimum on time occurs on channel 1 at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) ? f = 1.5v 20v ? 500khz = 150ns the next design focuses on only channel1.the wrth 744301033 0.33h ( 0.32m dcr typ at 25 c) is used for channel 1. so iout_cal_gain = 0.32m.based on the output current and inductor value, it is con - sidered to be a perfect example of low dcr application. set : mfr_pwm_mode[2] = 1 then choose c = 220nf, r1 = l/(dcr ? c ? 5) = 937 choose r1 = 931.the maximum power loss in r1 is related to the duty cycle, and will occur in continuous mode at the maximum input voltage: p lossr1 = v in(max) ? v out ( ) ? v out r1 = 20 ? 1.5 ( ) ? 1.5 931 = 29.8mw the current limit will be set 20% higher than the peak value to assure variation in components and noise in the system do not limit the average current. v ilimit = i peak ? r dcr(max) = (1 + 20%) ? 34.2a ? 0.32m = 13.1mv based on figure 26, set mfr_pwm_mode[2], [7] = 1,0 and iout_cal_gain = 0.32m in gui, and enter the value with iout_oc_fault_limit = 41.04a , the ltc3884 will automatically set the current limit to 40.64a , based on the iout_fault_limit table, (see pmbus command for details). downloaded from: http:///
lt c3884 66 3884fb for more information www.linear.com/ltc3884 applications information the power dissipation on the topside mosfet can be eas - ily estimated. choose a infineon b sc050ne2 ls topside mosfet. r ds(on) = 7.1m , c miller = 35pf . at maximum input voltage with t estimated = 75c and a bottom side mosfet a infineon b sc010ne2 lsi, r ds(on) = 1.1m: p main = 1.5v 20v ? 30a ( ) 2 ? 1 + 0.005 ( ) 75 c ? 25 c ( ) ? ?? ? 0.0071 + 20v ( ) 2 30a / 2 ( ) 2 ( ) 1 5.5 ? 2.8 + 1 2.8 ?? ? ?? ? 35pf ( ) 500khz ( ) = 751mw the loss in the bottom side mosfet is: p sync = 20v ? 1.5v 20v ? 30a ( 2 ? 1 0.005 ( 75 co ? 25 c ( ) ?? ?? ? 0.001 = 11.04w both mosfets have i 2 r losses while the pmain equation includes an additional term for transition losses, which are highest at high input voltages. c in is chosen for an rms current rating of: c in required i rms = 34.2/12 ? (3.3 ? (12 C 3.3)) 1/2 = 15a c out is chosen with an esr of 0.006 for low output ripple. the output ripple in continuous mode will b e highest at the maximum input voltage. the output voltage ripple due to esr is: v oripple = r esr ? (?i l ) = 0.006 ? 8.1 48.6mv additional design checks tie fault0 and fault1 together and pull up to v dd33 with a 10k resistor. tie ru n0 and ru n1 together and pull up to v dd33 with a 10k resistor. if there are other ltc psm parts, connect the run pins between chips and connect the fault pins between chips. be sure all pmbus pins have resistor pull-up to v dd33 and connect these inputs across all ltc psm parts in the application. tie share_clk high with a 4.99k resistor to v dd33 and share between all ltc psm parts in the application. be sure a unique address for each chip can be decoded with the ase l0 and ase l1 pins. refer to table?6. for maximum flexibility, allow board space for r top and r bottom for any parameter that is set with resistors such as ase l0 and ase l1 . connecting the usb to i 2 c/smbus/pmbus controller to the ltc3884 in system the ltc usb-to-i 2 c/smbus/pmbus adapter ( dc1613 a or equivalent) can be interfaced to the ltc3884 on the user s board for programming, telemetry and system debug. the adapter, when used in conjunction with ltpowerplay, provides a powerful way to debug an entire power sys - tem. faults are quickly diagnosed using telemetry, fault status commands and the fault log. the final configura - tion can be quickly developed and stored to the ltc3884 eeprom. figure 41 illustrates the application schematic for powering, programming and communication with one or more ltc3884 s via the ltc i 2 c/smbus/pmbus adapter regardless of whether or not system power is present. if system power is not present the dongle will power the ltc3884 through the v dd33 supply pin. to initialize the part when v in is not applied and the v dd33 pin is powered use global address 0x 5b command 0x bd data 0x 2b fol - lowed by address 0x 5b command 0x bd data 0xc4.the lt c3884 can now communicate with, and the project file can be updated. to write the updated project file to the nvm issue a store_user _all command. when v in is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read.because of the adapter s limited current sourcing capability, only the ltc3884 s, their associated pull-up resistors and the i 2 c pull-up resistors should be powered from the ored 3.3v supply. in addition any device sharing the i 2 c bus connections with the ltc3884 should not have body diodes between the sda/scl pins and their respective v dd node because this will interfere with bus communication in the absence of system power. if v in is applied, the dc1613a will not supply the power to the ltc3884 s on the board. it is recommended the run n pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured. downloaded from: http:///
lt c3884 67 3884fb for more information www.linear.com/ltc3884 applications information the ltc3884 is fully isolated from the host pc s ground by the dc1613a.the 3.3v from the adapter and the ltc3884 v dd33 pin must be driven to each ltc3884 with a separate pfet. if both v in and extv cc are not applied, the v dd33 pins can be in parallel because the on-chip ldo is off. the controller 3.3v current limit is 100ma but typical v dd33 currents are under 15ma . the v dd33 does back drive the intv cc /extv cc pin. normally this is not an issue if v in is open.lt powerplay: an interactive gui for digital power ltpowerplay (figure 42) is a powerful windows-based development environment that supports linear technol - ogy digital power system management ics including the ltc3884 . the software supports a variety of different task s. ltpowerplay can be used to evaluate linear technology ics by connecting to a demo board or the user applica - tion. ltpowerplay can also be used in an offline mode (with no hardware present) in order to build multiple ic configuration files that can be saved and reloaded at a later time. ltpowerplay provides unprecedented diagnostic and debug features. it becomes a valuable diagnostic tool during board bring-up to program or tweak the power system or to diagnose power issues when bring up rails. l tpowerplay utilizes linear technology s usb-to-i 2 c/ smbus/pmbus adapter to communication with one of the many potential targets including the dc2165 a demo board, the dc2298 a socketed programming board, or a customer target system. the software also provides an automatic update feature to keep the revisions current with the latest set of device drivers and documentation. a great deal of context sensitive help is available with ltpower play along with several tutorial demos. complete information is available at: http ://www.linear.com/ltpowerplay pmbus communication and command processing the ltc3884 has a one deep buffer to hold the last data written for each supported command prior to processing as shown in figure 43, write command data processing. when the part receives a new command from the bus, it copies the data into the write command data buffer, indicates to the internal processor that this command v in v in v dd33 v dd25 sda 1f 1f vgs max on the tp0101k is 8v if v in > 16v change the resistor divider on the pfet gate 1f 1f 3884 f41 10k 100k tp0101k isolated 3.3v sdascl tp0101k 100k lt c controller header to ltc dc1613 usb to i 2 c/smbus/pmbus controller scl wp pgnd/sgnd ltc3884 v in v dd33 sdascl wp pgnd/sgnd ltc3884 10k v dd25 figure 41. controller connection downloaded from: http:///
lt c3884 68 3884fb for more information www.linear.com/ltc3884 applications information figure 42. ltpowerplay screen shot decoder cmd internal processor write command data buffer page cmds 0x000x21 0xfd 3884 f43 x1 ?? ? ? ? ? mfr_reset vout_command s calculations pending pmbus write r fetch, convert data and execute data mux figure 43. write command data processing data needs to be fetched, and converts the command to its internal format so that it can be executed. two distinct parallel blocks manage command buffering and comman d processing (fetch, convert, and execute) to ensure the last data written to any command is never lost. com - mand data buffering handles incoming pmbus writes by storing the command data to the write command data buffer and marking these commands for future process - ing. the internal processor runs in parallel and handles the sometimes slower task of fetching, converting and executing commands marked for processing. some computationally intensive commands (e.g., timing param - eters, temperatures, voltages and currents) have internal processor execution times that may be long relative to pmbus timing. if the part is busy processing a command, and new command(s) arrive, execution may be delayed or processed in a different order than received. the part indicates when internal calculations are in process via bit downloaded from: http:///
lt c3884 69 3884fb for more information www.linear.com/ltc3884 applications information 5 of mfr_common ( calculations not pending ). when the part is busy calculating, bit 5 is cleared. when this bit is set, the part is ready for another command. an example polling loop is provided in figure?44 which ensures that commands are processed in order while simplifying error handling routines. when the part receives a new command while it is busy, it will communicate this condition using standard pmbus protocol. depending on part configuration it may either nack the command or return all ones ( 0x ff) for reads. it may also generate a busy fault and alert notification, or stretch the scl clock low. for more information refer to pmbus specification v1.1, part ii, section 10.8.7 and smbus v2.0 section 4.3.3. clock stretching can be enabled by asserting bit 1 of mfr_config _ all. clock stretch - ing will only occur if enabled and the bus communication speed exceeds 100khz. // wait until chip is not busy do { mfrcommonvalue = pmbus_read_byte(0xef); partready = (mfrcommonvalue & 0x68) == 0x68; }while(!partready) // now the part is ready to receive the next command pmbus_write_word(0x21, 0x2000); //write vout_command to 2v figure 44. example of a command write of vout_command pmbus busy protocols are well accepted standards, but can make writing system level software somewhat com - plex. the part provides three hand shaking status bits which reduce complexity while enabling robust system level communication. the three hand shaking status bits are in the mfr_ common register. when the part is busy executing an internal operation, it will clear bit 6 of mfr_common ( chip not busy ). when the part is busy specifically be - cause it is in a transitional v out state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of mfr_common ( output not in transition ). when internal calculations are in process, the part will clear bit?5 of mfr_common ( calculations not pending ). these three status bits can be polled with a pmbus read byte of the mfr_common register until all three bits are set. a command immediately following the status bits being set will be accepted without nacking or generating a busy fault/ alert notification. the part can nack commands for other reasons, however, as required by the pmbus spec (for instance, an invalid command or data). an example of a robust command write algorithm for the vout_command register is provided in figure 44. it is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted alert notification. a simple way to achieve this is to create a safe_write_byte () and safe_write_ word () subroutine. the above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. for a detailed discussion of these topics and other special cases please refer to the application note section located at: www.linear.com/designtools/ app_notes when communicating using bus speeds at or below 100khz , the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. at bus speeds in excess of 100khz , it is strongly recommended that the part be configured to en - able clock stretching. this requires a pmbus master that supports clock stretching. system software that detects and properly recovers from the standard pmbus nack/ busy faults as described in the pmbus specification v1.1, part ii, section 10.8.7 is required to communicate the ltc3884 is not recommended in applications with bus speeds in excess of 400khz. downloaded from: http:///
lt c3884 70 3884fb for more information www.linear.com/ltc3884 pmbus command details addressing and write protect command name cmd code description type paged data format units nvm default value page 0x00 provides integration with multi-page pmbus devices. r/w byte n reg 0x00 page_plus_write 0x05 write a supported command directly to a pwm channel. w block n page_plus_read 0x06 read a supported command directly from a pwm channel. block r/w n write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte n reg y 0x00 mfr_address 0xe6 sets the 7-bit i 2 c address byte. r/w byte n reg y 0x4f mfr_rail_address 0x fa common address for polyphase outputs to adjust common parameters. r/w byte y reg y 0x80 page the page command provides the ability to configure, control and monitor both pwm channels through only one physi - cal address, either the mfr_address or global device address. each page contains the operating commands for one p wm channel. pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively , in this device. setting page to 0x ff applies any following paged commands to both outputs. with page set to 0x ff the ltc3884 will respond to read commands as if page were set to 0x00 (channel 0 results). this command has one data byte. page_plus_write the page_plus_write command provides a way to set the page within a device, send a command, and then send the data for the command, all in one communication packet. commands allowed by the present write protection level may be sent with page_plus_write. the value stored in the page command is not affected by page_plus_write . if page_plus_write is used to send a non-paged command, the page number byte is ignored.this command uses write block protocol. an example of the page_plus_write command with pec sending a com - mand that has two data bytes is shown in figure 45. slave address page_plus command code block count (= 4) w a a s 7 8 8 1 page number 8 1 1 1 1 1 a a command code 8 1 a upper data byte a a p 3884 f45 a 8 8 1 1 1 1 pec byte lower data byte 8 figure 45. example of page_plus_write page_plus_read the page_plus_read command provides the ability to set the page within a device, send a command, and then read the data returned by the command, all in one communication packet . downloaded from: http:///
lt c3884 71 3884fb for more information www.linear.com/ltc3884 pmbus command details the value stored in the page command is not affected by page_plus_read . if page_plus_read is used to access data from a non-paged command, the page number byte is ignored.this command uses the process call protocol. an example of the page_plus_read command with pec is shown in figure 46. p 1 slave address page_plus command code block count (= 2) w a a s 7 8 8 1 page number 8 1 1 1 1 1 a a command code 8 1 a slave address block count (= 2) lower data byte r a a sr 7 8 8 1 upper data byte 8 1 1 1 1 1 a a pec byte 8 1 na 3884 f46 figure 46. example of page_plus_read note: page_plus commands cannot be nested. a page_plus command cannot be used to read or write another page_plus command. if this is attempted, the ltc3884 will nack the entire page_plus packet and issue a cml fault for invalid/unsupported data.write_protect the write_protect command is used to control writing to the ltc3884 device. this command does not indicate the status of the wp pin which is defined in the mfr_common command. the wp pin takes precedence over the value of this command. byte meaning 0x80 disable all writes except to the write_protect, page, mfr_ ee_unlock, and store_user_all commands. 0x40 disable all writes except to the write_protect, page, mfr_ee_unlock, mfr_clear_peaks, store_user_all, operation and clear_faults command. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. 0x20 disable all writes except to the write_protect, operation, mfr_ee_unlock, mfr_clear_peaks, clear_faults, page, on_off_config, vout_command and store_user_ all. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. 0x10 reserved, must be 0 0x08 reserved, must be 0 0x04 reserved, must be 0 0x02 reserved, must be 0 0x01 reserved, must be 0 enable writes to all commands when write_protect is set to 0x00. if wp pin is high, page, operation, mfr_clear_peaks, mfr_ee_unlock, write_protect and clear_faults commands are supported. individual fault bits can be cleared by writing a 1 to the respective bits in the status commands. downloaded from: http:///
lt c3884 72 3884fb for more information www.linear.com/ltc3884 pmbus command details mfr_addressthe mfr_address command byte sets the 7 bits of the pmbus slave address for this device. setting this command to a value of 0x 80 disables device addressing. the global device address, 0x 5a and 0x5b, cannot be deactivated. if rconfig is set to ignore, the ase l0 and ase l1 pins are still used to determine the lsb and msb, respectively, of the channel address. if the ase l0 and ase l1 pins are both open, the ltc3884 will use the address value stored in nvm. if the ase l0 pin is open, the ltc3884 will use the lower 4 bits of the mfr_address value stored in nvm to construct the effective address of the part. if the ase l1 pin is open, the ltc3884 will use the upper 4 bits of the mfr_address value stored in nvm to construct the effective address of the part.this command has one data byte. mfr_rail_address the mfr_rail_address command enables direct device address access to the page activated channel. the value of this command should be common to all devices attached to a single power supply rail. the user should only perform command writes to this address. if a read is performed from this address and the rail devices do not respond with exactly the same value, the ltc3884 will detect bus contention and may set a cml communications fault.setting this command to a value of 0x80 disables rail device addressing for the channel. this command has one data byte. general configuration commands command name cmd code description type paged data format units nvm default value mfr_chan_config 0xd0 configuration bits that are channel specific. r/w byte y reg y 0x10 mfr_config_all 0xd1 general configuration bits. r/w byte n reg y 0x21 mfr_chan_config general purpose configuration command common to multiple ltc products. bit meaning 7 reserved 6 reserved 5 reserved 4 disable run low. when asserted the run pin is not pulsed low if commanded off. 3 enable short cycle recognition if this bit is set to a 1. 2 share_clock control. if share_clock is held low, the output is disabled. 1 no fault alert , alert is not pulled low if fault is pulled low externally. assert this bit if either power_good or vout_uvuf are propagated on fault . 0 disables the v out decay value requirement for mfr_retry_time and t off(min) processing. when this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an off/on command, or a toggle of run from high to low to high. this command has one data byte. downloaded from: http:///
lt c3884 73 3884fb for more information www.linear.com/ltc3884 pmbus command details a shortcycle event occurs whenever the pwm channel is commanded back on, or reactivated, after the part has been commanded off and is processing either the toff_delay or the toff_fall states. the pwm channel can be turned on and off through either the run pin and or the pmbus operation command. if the pwm channel is reactivated during the toff_delay, the part will perform the following: 1. immediately tri-state the pwm channel output; 2. start the retry delay timer as specified by the t off(min) . 3. after the t off(min) value has expired, the pwm channel will proceed to the ton_delay state and the status_ mfr_specific bit #1 will assert. if the pwm channel is reactivated during the toff_fall, the part will perform the following: 1. stop ramping down the pwm channel output; 2. immediately tri-state the pwm channel output; 3. start the retry delay timer as specified by the t off(min) . 4. after the t off(min) value has expired, the pwm channel will proceed to the ton_delay state and the status_ mfr_spefific bit #1 will assert. if the short cycle event occurs and the shortcycle mfr_chan_config bit is not set, the pwm channel state machine will complete its toff_delay and toff_fall operations as previously commanded by the user. mfr_config_all general purpose configuration command common to multiple ltc products. bit meaning 7 enable fault logging 6 ignore resistor configuration pins 5 mask pmbus, partii, section 10.9.1 violations 4 disable sync output 3 enable 255ms pmbus timeout 2 a valid pec required for pmbus writes to be accepted. if this bit is not set, the part will accept commands with invalid pec. 1 enable the use of pmbus clock stretching 0 execute clear_faults on rising edge of either run pin. this command has one data byte.on/off/margin command name cmd code description type paged data format units nvm default value on_off_config 0x02 run pin and pmbus bus on/off command configuration. r/w byte y reg y 0x1e operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte y reg y 0x80 mfr_reset 0xfd commanded reset without requiring a power-down. send byte n na downloaded from: http:///
lt c3884 74 3884fb for more information www.linear.com/ltc3884 pmbus command details on_off_config the on_off_config command specifies the combination of run n pin input state and pmbus commands needed to turn the pwm channel on and off. supported values: value meaning 0x1f operation value and run n pin must both command the device to start/run. device executes immediate off when commanded off. 0x1e operation value and run n pin must both command the device to start/run. device uses toff_ command values when commanded off. 0x17 run n pin control with immediate off when commanded off. operation on/off control ignored. 0x16 run n pin control using toff_ command values when commanded off. operation on/off control ignored. programming an unsupported on_off_config value will generate a cml fault and the command will be ignored.this command has one data byte. operation the operation command is used to turn the unit on and off in conjunction with the input from the run n pins. it is also used to cause the unit to set the output voltage to the upper or lower margin voltages. the unit stays in the commanded operating mode until a subsequent operation command or change in the state of the run n pin instructs the device to change to another mode. if the part is stored in the margin_low /high state, the next reset or power_on cycle will ramp to that state. if the operation command is modified, for example on is changed to margin_low , the output will move at a fixed slope set by the vout_transition_rate . the default operation command is sequence off. if v in is applied to a part with factory default programming and the vout_config resistor configuration pins are not installed, the outputs will be commanded off. the part defaults to the sequence off state. this command has one data byte. supported values: value meaning 0xa8 margin high. 0x98 margin low. 0x80 on (v out back to nominal even if bit 3 of on_off_config is not set). 0x40* soft off (with sequencing). 0x00* immediate off (no sequencing). *device does not respond to these commands if bit 3 of on_off_config is not set. programming an unsupported operation value will generate a cml fault and the command will be ignored. this command has one data byte. mfr_reset this command provides a means to reset the ltc3884 from the serial bus. this forces the ltc3884 to turn off both pwm channels, load the operating memory from internal eeprom, clear all faults and then perform a soft-start of both pwm channels, if enabled. this write-only command has no data bytes. downloaded from: http:///
lt c3884 75 3884fb for more information www.linear.com/ltc3884 pmbus command details pwm configuration command name cmd code description type paged data format units nvm default value mfr_pwm_comp 0xd3 pwm loop compensation configuration r/w byte y reg y 0xae mfr_pwm_mode 0xd4 configuration for the pwm engine. r/w byte y reg y 0xc7 mfr_pwm_config 0xf5 set numerous parameters for the dc/dc controller including phasing. r/w byte n reg y 0x10 frequency_switch 0x33 switching frequency of the controller. r/w word n l11 khz y 425 0xfb52 mfr_pwm_mode the mfr_pwm_mode command sets important pwm controls for each channel. the mfr_pwm_mode command allows the user to program the pwm controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. bit meaning 7 0b1b use high range of i limit low current rangehigh current range 6 enable servo mode 5 external temperature sense: 0: ?v be measurement. 1: direct voltage measurement. [4:3] reserved 2 enable ultra-low dcr current sense 1 1b0b v out range the maximum output voltage is 2.75vthe maximum output voltage is 5.5v bit[0] 0b1b modediscontinuous forced continuous bit [7] of this command determines if the part is in high range or low range of the iout_oc_fault_limit command. changing this bit value changes the pwm loop gain and compensation. this bit value should not be changed when the channel output is active. writing this bit when the channel is active will generate a cml fault. bit [6] the ltc3884 will not servo while the part is off, ramping on or ramping off. when set to a one, the output servo is enabled. the output set point dac will be slowly adjusted to minimize the difference between the read_vout_adc and the vout_command (or the appropriate margined value). when bit [5] is cleared, the ltc3884 computes temperature in c from ? v be measured by the adc at the tsns n pin as t = (g ? ?v be ? q/(k ? ln(16))) C 273.15 + o when bit[5] is set, the ltc3884 computes temperature in c from tsns n voltage measured by the adc as t = (g ? (1.35 C v tsns n + o)/4.3e-3) + 25 downloaded from: http:///
lt c3884 76 3884fb for more information www.linear.com/ltc3884 pmbus command details for both equations, g = mfr_temp_1_gain ? 2 C14 , and o = mfr_temp_1_offset bit[2] determines if the part uses sub-milliohm dcr for sensing the output current. this is a very critical selection in terms of overcurrent limit. it is highly recommend that bit[2] should not be changed when device is in operation. bit[1] of this command determines if the part is in high range or low voltage range. changing this bit value changes the pwm loop gain and compensation. this bit value should not be changed when the channel output is active. writing this bit when the channel is active will generate a cml fault. b it[0] determines if the pwm mode of operation is discontinuous (pulse-skipping mode), or forced continuous con - duction mode. whenever the channel is ramping on, the pwm mode will be discontinuous, regardless of the value of this bit. this command has one data byte. mfr_pwm_comp the mfr_pwm_comp command sets the g m of the pwm channel error amplifiers and the value of the internal r ithn compensation resistors. this command affects the loop gain of the pwm output which may require modifications to the external compensation network. bit meaning bit [7:5] error amplifier gm adjust (ms) 000b 1.00 001b 1.68 010b 2.35 011b 3.02 100b 3.69 101b 4.36 110b 5.04 111b 5.73 bit [4:0] r ith (k ) 00000b 0 00001b 0.25 00010b 0.5 00011b 0.75 00100b 1 00101b 1.25 00110b 1.5 00111b 1.75 01000b 2 01001b 2.5 01010b 3 01011b 3.5 01100b 4 01101b 4.5 01110b 5 downloaded from: http:///
lt c3884 77 3884fb for more information www.linear.com/ltc3884 pmbus command details 01111b 5.5 10000b 6 10001b 7 10010b 8 10011b 9 10100b 11 10101b 13 10110b 15 10111b 17 11000b 20 11001b 24 11010b 28 11011b 32 11100b 38 11101b 46 11110b 54 11111b 62 this command has one data byte.mfr_pwm_config the mfr_pwm_config command sets the switching frequency phase offset with respect to the falling edge of the sync signal. the part must be in the off state to process this command. either the run pins must be low or the channels must be commanded off. if either channel is in the run state and this command is written, the command will be nackd and a busy fault will be asserted. bit meaning 7 reserved [6:5] 00b01b 10b 11b input current sense gain.2x gain. 0mv to 50mv range. 4x gain. 0mv to 25mv range. 8x gain. 0mv to 12.5mv range. reserved 4 share clock enable : if this bit is 1, the share_clk pin will not be released until v in > vin_on. the share_clk pin will be pulled low when v in < vin_off. if this bit is 0, the share_clk pin will not be pulled low when vin < vin_off except for the initial application of vin. bit [2:0] channel 0 (degrees) channel 1 (degrees) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 downloaded from: http:///
lt c3884 78 3884fb for more information www.linear.com/ltc3884 pmbus command details frequency_switch the frequency_switch command sets the switching frequency, in khz, of the ltc3884. supported frequencies: value [15:0] resulting frequency (typ) 0x0000 external oscillator 0xf3e8 250khz 0xfabc 350khz 0xfb52 425khz 0xfbe8 500khz 0x023f 575khz 0x028a 650khz 0x02ee 750khz 0x03e8 1000khz the part must be in the off state to process this command. the run pin must be low or both channels must be commanded off. if the part is in the run state and this command is written, the command will be nack'd and a busy fault will be asserted. when the part is commanded off and the frequency is changed, a pll_unlock status may be detected as the pll locks onto the new frequency. this command has two data bytes and is formatted in linear_5s_11s format. voltage input voltage and limits command name cmd code description type paged data format units nvm default value vin_ov_fault_limit 0x55 input supply overvoltage fault limit. r/w word n l11 v y 15.5 0xd3e0 vin_uv_warn_limit 0x58 input supply undervoltage warning limit. r/w word n l11 v y 6.3 0xcb26 vin_on 0x35 input voltage at which the unit should start power conversion. r/w word n l11 v y 6.5 0xcb40 vin_off 0x36 input voltage at which the unit should stop power conversion. r/w word n l11 v y 6.0 0xcb00 mfr_rvin 0xf7 the resistance value of the v in pin filter element in milliohms r/w word n l11 m y 1000 0x03e8 vin_ov_fault_limit the vin_ov_fault_limit command sets the value of the input voltage measured by the adc, in volts, that causes an input overvoltage fault. this command has two data bytes in linear_5s_11s format. downloaded from: http:///
lt c3884 79 3884fb for more information www.linear.com/ltc3884 pmbus command details vin_uv_warn_limit the vin_uv_warn_limit command sets the value of input voltage measured by the adc that causes an input under - voltage warning. this warning is disabled until the input exceeds the input startup threshold value set by the vin_on command and the unit has been enabled. if the v in voltage drops below the vin_ov_warn_limit the device: ? sets the input bit is the status_word ? sets the v in undervoltage warning bit in the status_input command ? notifies the host by asserting alert , unless masked vin_on the vin_on command sets the input voltage, in volts, at which the unit starts power conversion. this command has two data bytes and is formatted in linear_5s_11s format. vin_off the vin_off command sets the input voltage, in volts, at which the unit stops power conversion. this command has two data bytes and is formatted in linear_5s_11s format. mfr_rvin the mfr_rvin command is used to set the resistance value of the v in pin filter element in milliohms. (see also read_vin). set mfr_rvin equal to 0 if no filter element is used.this command has two data bytes and is formatted in linear_5s_11s format. output voltage and limits command name cmd code description type paged data format units nvm default value vout_mode 0x20 output voltage format and exponent (2 C12 ). r byte y reg 2 C12 0x14 vout_max 0x24 upper limit on the output voltage the unit can command regardless of any other commands. r/w word y l16 v y 2.75 0x2c00 vout_ov_fault_ limit 0x40 output overvoltage fault limit. r/w word y l16 v y 1.1 0x119a vout_ov_warn_ limit 0x42 output overvoltage warning limit. r/w word y l16 v y 1.075 0x1133 vout_margin_high 0x25 margin high output voltage set point. must be greater than vout_command. r/w word y l16 v y 1.05 0x10cd vout_command 0x21 nominal output voltage set point. r/w word y l16 v y 1.0 0x1000 vout_margin_low 0x26 margin low output voltage set point. must be less than vout_command. r/w word y l16 v y 0.95 0x0f33 vout_uv_warn_ limit 0x43 output undervoltage warning limit. r/w word y l16 v y 0.925 0x0ecd vout_uv_fault_ limit 0x44 output undervoltage fault limit. r/w word y l16 v y 0.9 0x0e66 mfr_vout_max 0xa5 maximum allowed output voltage. r word y l16 v 5.7 0x5b33 downloaded from: http:///
lt c3884 80 3884fb for more information www.linear.com/ltc3884 pmbus command details vout_modethe data byte for vout_mode command, used for commanding and reading output voltage, consists of a 3- bit mode (only linear format is supported) and a 5- bit parameter representing the exponent used in output voltage read/write commands.this read-only command has one data byte. vout_max the vout_max command sets an upper limit on any voltage, including vout_margin_high , the unit can com - mand regardless of any other commands or combinations. the maximum allowed value of this command is 5.8v. the maximum output voltage the ltc3884 can produce is 5.5v including vout_margin_high . however, the vout_ov_fault_limit can be commanded as high as 5.7v.this command has two data bytes and is formatted in linear_16u format. vout_ov_fault_limit the vout_ov_fault_limit command sets the value of the output voltage measured by the ov supervisor compara - tor at the sense pins, in volts, which causes an output overvoltage fault. if the vout_ov_fault_limit is modified and the part is in the run state, allow 10ms after the command is modi - fied to assure the new value is being honored. the part indicates if it is busy making a calculation. monitor bits 5 and 6 of mfr_common . either bit is low if the part is busy. if this wait time is not honored and the vout_command is modified above the old overvoltage limit, an ov condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher. if vout_ov_fault_response is set to ov_pulldown or 0x 00, the fault pin will not assert if vout_ov_fault is propagated. the ltc3884 will pull the tg low and assert the bg bit as soon as the overvoltage condition is detected. this command has two data bytes and is formatted in linear_16u format.vout_ov_warn_limit the vout_ov_warn_limit command sets the value of the output voltage measured by the adc at the sense pins, in volts, which causes an output voltage high warning. the mfr_vout_peak value can be used to determine if this limit has been exceeded.in response to the vout_ov_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout overvoltage warning bit in the status_vout command ? notifies the host by asserting alert pin, unless masked this condition is detected by the adc so the response time may be up to t convert . this command has two data bytes and is formatted in linear_16u format. downloaded from: http:///
lt c3884 81 3884fb for more information www.linear.com/ltc3884 pmbus command details vout_margin_high the vout_margin_high command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin high . the value should be greater than vout_command . the maximum guaranteed value on vout_margin_high is 5.5v.this command will not be acted on during ton_rise and toff_fall output sequencing. the vout_transition_rate will be used if this command is modified while the output is active and in a steady-state condition.this command has two data bytes and is formatted in linear_16u format. vout_command the vout_command consists of two bytes and is used to set the output voltage, in volts. the maximum guaranteed value on vout is 5.5v.this command will not be acted on during ton_rise and toff_fall output sequencing. the vout_transition_rate will be used if this command is modified while the output is active and in a steady-state condition.this command has two data bytes and is formatted in linear_16u format. vout_margin_low the vout_margin_low command loads the unit with the voltage to which the output is to be changed, in volts, when the operation command is set to margin low. the value must be less than vout_command. this command will not be acted on during ton_rise and toff_fall output sequencing. the vout_transition_rate will be used if this command is modified while the output is active and in a steady-state condition.this command has two data bytes and is formatted in linear_16u format. vout_uv_warn_limit the vout_uv_ warn_limit command reads the value of the output voltage measured by the adc at the sense pins, in volts, which causes an output voltage low warning.in response to the vout_uv_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout undervoltage warning bit in the status_vout command ? notifies the host by asserting alert pin, unless masked this command has two data bytes and is formatted in linear_16u format.vout_uv_fault_limit the vout_uv_fault_limit command reads the value of the output voltage measured by the uv supervisor com - parator at the sense pins, in volts, which causes an output undervoltage fault. this command has two data bytes and is formatted in linear_16u format. downloaded from: http:///
lt c3884 82 3884fb for more information www.linear.com/ltc3884 pmbus command details mfr_vout_max the mfr_vout_max command is the maximum output voltage in volts for each channel, including vout_ov_fault_ limit . if the output voltages are set to high range (bit 6 of mfr_pwm_config set to a 0) mfr_vout_max is 5.5v . if the output voltage is set to low range (bit 6 of mfr_pwm_config set to a 1) the mfr_vout_max is 2.75v . entering a vout_command value greater than this will result in a cml fault and the output voltage setting will be clamped to the maximum level. this will also result in bit 3 vout_max_warning in the status_vout command being set.this read only command has 2 data bytes and is formatted in linear_16u format. output current and limits command name cmd code description type paged data format units nvm default value iout_cal_gain 0x38 the ratio of the voltage at the current sense pins to the sensed current. for devices using a fixed current sense resistor, it is the resistance value in m. r/w word y l11 m y 0.32 0xaa8b mfr_iout_cal_gain_tc 0xf6 temperature coefficient of the current sensing element. r/w word y cf y 3900 0x0f3c iout_oc_fault_limit 0x46 output overcurrent fault limit. r/w word y l11 a y 45.0 0xe2d0 iout_oc_warn_limit 0x4a output overcurrent warning limit. r/w word y l11 a y 34.0 0xe230 iout_cal_gain the iout_cal_gain command is used to set the resistance value of the current sense resistor in milliohms. (see also mfr_iout_cal_gain_tc).this command has two data bytes and is formatted in linear_5s_11s format. mfr_iout_cal_gain_tc the mfr_iout_cal_gain_tc command allows the user to program the temperature coefficient of the iout_cal_gain sense resistor or inductor dcr in ppm/c.this command has two data bytes and is formatted in 16- bit 2 s complement integer ppm. n = C 32768 to 32767 ? 10 C6 . nominal temperature is 27c. the iout_cal_gain is multiplied by: [1.0 + mfr_iout_cal_gain_tc ? (read_temperature_1-27)]. dcr sensing will have a typical value of 3900. the iout_cal_gain and mfr_iout_cal_gain_tc impact all current parameters including : read_iout , mfr_iout_peak, iout_oc_fault_limit and iout_oc_warn_limit. downloaded from: http:///
lt c3884 83 3884fb for more information www.linear.com/ltc3884 pmbus command details iout_oc_fault_limit the iout_oc_fault_limit command sets the value of the peak output current limit, in amperes. when the control - ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. the following table lists the progammable peak output current limit value in mv between i sense + and i sense C . the actual value of current limit is (i sense + C i sense C )/iout_cal_gain in amperes. mfr_pwm_mode[2]=1 (sub-milli dcr) mfr_pwm_mode[2]=0 (normal value of dcr) mfr_pwm_mode[7]=1 high current range mfr_pwm_mode[7]=0 low current range mfr_pwm_mode[7]=1 high current range mfr_pwm_mode[7]=0 low current range 15.45 8.59 38.64 21.46 16.59 9.22 41.48 23.04 17.73 9.85 44.32 24.62 18.86 10.48 47.16 26.20 20.42 11.34 51.04 28.36 21.14 11.74 52.84 29.36 22.27 12.37 55.68 30.93 23.41 13.01 58.52 32.51 24.55 13.64 61.36 34.09 25.68 14.27 64.20 35.67 26.82 14.90 67.05 37.25 27.95 15.53 69.89 38.83 29.09 16.16 72.73 40.40 30.23 16.79 75.57 41.98 31.36 17.42 78.41 43.56 32.50 18.06 81.25 45.14 note: this is the peak of the current waveform. the read_iout command returns the average current. the peak output current limits are adjusted with temperature based on the mfr_iout_cal_gain_tc using the equation: peak current limit = iout_cal_gain ? (1 + mfr_iout_cal_gain_tc ? (read_temperture_1-27.0)). the ltc3884 automatically convert currents to the appropriate internal bit value.the i out range is set with bit 7 of the mfr_pwm_mode command. the iout_oc_fault_limit is ignored during ton_rise and toff_fall.if the iout_oc_fault_limit is exceeded, the device: ? sets the iout bit in the status word ? sets the iout overcurrent fault bit in the status_iout ? notifies the host by asserting alert , unless masked downloaded from: http:///
lt c3884 84 3884fb for more information www.linear.com/ltc3884 pmbus command details this command has two data bytes and is formatted in linear_5s_11s format.iout_oc_warn_limit this command sets the value of the output current measured by the adc that causes an output overcurrent warning in amperes. the read_iout value will be used to determine if this limit has been exceeded. in response to the iout_oc_warn_limit being exceeded, the device: ? sets the none_of_the_above bit in the status_byte ? sets the iout bit in the status_word ? sets the iout overcurrent warning bit in the status_iout command, and ? notifies the host by asserting alert pin, unless masked the iout_oc_fault_limit is ignored during ton_rise and toff_fall.this command has two data bytes and is formatted in linear_5s_11s format input current and limits command name cmd code description type data format units nvm default value mfr_iin_cal_gain 0xe8 the resistance value of the input current sense element in m. r/w word l11 m y 5.000 0xca80 mfr_iin_cal_gain the mfr_iin_cal_gain command is used to set the resistance value of the input current sense resistor in milliohms. (see also read_iin).this command has two data bytes and is formatted in linear_5s_11s format. command name cmd code description type paged data format units nvm default value iin_oc_warn_limit 0x5d input overcurrent warning limit. r/w word n l11 a y 10.0 0xd280 iin_oc_warn_limit the iin_oc_warn_limit command sets the value of the input current measured by the adc, in amperes, that causes a warning indicating the input current is high. the read_iin value will be used to determine if this limit has been exceeded.in response to the iin_oc_warn_limit being exceeded, the device: ? sets the other bit in the status_byte ? sets the input bit in the upper byte of the status_word ? sets the iin overcurrent warning bit[1] in the status_input command, and ? notifies the host by asserting alert pin this command has two data bytes and is formatted in linear_5s_11s format. downloaded from: http:///
lt c3884 85 3884fb for more information www.linear.com/ltc3884 pmbus command details temperature external temperature calibration command name cmd code description type paged data format units nvm default value mfr_temp_1_gain 0xf8 sets the slope of the external temperature sensor. r/w word y cf y 1.0 0x4000 mfr_temp_1_offset 0xf9 sets the offset of the external temperature sensor. r/w word y l11 c y 0.0 0x8000 mfr_temp_1_gain the mfr_temp _1_gain command will modify the slope of the external temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in 16- bit 2 s complement integer. the effective gain adjustment is n ? 2 C14 . the nominal value is 1. mfr_temp_1_offset the mfr_temp _1_offset command will modify the offset of the external temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor. this command has two data bytes and is formatted in linear_5s_11s format. external temperature limits command name cmd code description type paged data format units nvm default value ot_fault_limit 0x4f external overtemperature fault limit. r/w word y l11 c y 100.0 0xeb20 ot_warn_limit 0x51 external overtemperature warning limit. r/w word y l11 c y 85.0 0xeaa8 ut_fault_limit 0x53 external undertemperature fault limit. r/w word y l11 c y C40.0 0xe580 ot_fault_limit the ot_fault_limit command sets the value of the external sense temperature measured by the adc, in degrees celsius, which causes an overtemperature fault. the read_temperature _1 value will be used to determine if this limit has been exceeded.this command has two data bytes and is formatted in linear_5s_11s format. ot_warn_limit the ot_warn_limit command sets the value of the external sense temperature measured by the adc, in degrees celsius, which causes an overtemperature warning. the read_temperature _1 value will be used to determine if this limit has been exceeded. downloaded from: http:///
lt c3884 86 3884fb for more information www.linear.com/ltc3884 pmbus command details in response to the ot_warn_limit being exceeded, the device:? sets the temperature bit in the status_byte ? sets the overtemperature warning bit in the status_temperature command, and ? notifies the host by asserting alert pin, unless masked this command has two data bytes and is formatted in linear_5s_11s format.ut_fault_limit the ut_fault_limit command sets the value of the external sense temperature measured by the adc, in degrees celsius, which causes an undertemperature fault. the read_temperature _1 value will be used to determine if this limit has been exceeded.note : if the temp sensors are not installed, the ut_fault_limit can be set to C275c and ut_fault_limit response set to ignore to avoid alert being asserted. this command has two data bytes and is formatted in linear_5s_11s format.timing timingon sequence/ramp command name cmd code description type paged data format units nvm default value ton_delay 0x60 time from run and/or operation on to output rail turn-on. r/w word y l11 ms y 0.0 0x8000 ton_rise 0x61 time from when the output starts to rise until the output voltage reaches the vout commanded value. r/w word y l11 ms y 8.0 0xd200 ton_max_fault_limit 0x62 maximum time from the start of ton_ rise for vout to cross the vout_uv_fault_limit. r/w word y l11 ms y 10.0 0xd280 vout_transition_rate 0x27 rate the output changes when vout commanded to a new value. r/w word y l11 v/ms y 0.25 0xaa00 ton_delay the ton_delay command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. values from 0ms to 83 seconds are valid. the resulting turn-on delay will have a typical delay of 270s for ton_delay = 0 and an uncertainty of 50s for all values of ton_delay.this command has two data bytes and is formatted in linear_5s_11s format. ton_rise the ton_rise command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. values from 0 to 1.3 seconds are valid. the part will be in discontinuous mode during ton_rise events. if ton_rise is less than 0.25ms , the ltc3884 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the pwm switcher. the number of steps in ton_rise is equal to ton_rise (in ms)/0.1ms with an uncertainty of 0.1ms.this command has two data bytes and is formatted in linear_5s_11s format. downloaded from: http:///
lt c3884 87 3884fb for more information www.linear.com/ltc3884 pmbus command details ton_max_fault_limit the ton_max_fault_limit command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. a data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. the maximum limit is 83 seconds.this command has two data bytes and is formatted in linear_5s_11s format. vout_transition_rate when a pmbus device receives either a vout_command or operation (margin high, margin low) that causes the output voltage to change this command set the rate in v/ms at which the output voltage changes. the commanded rate of change does not apply when the unit is commanded on or off. the maximum allowed slope is 4v/ms. this command has two data bytes and is formatted in linear_5s_11s format. timingoff sequence/ramp command name cmd code description type paged data format units nvm default value toff_delay 0x64 time from run and/or operation off to the start of toff_fall ramp. r/w word y l11 ms y 0.0 0x8000 toff_fall 0x65 time from when the output starts to fall until the output reaches zero volts. r/w word y l11 ms y 8.0 0xd200 toff_max_warn_limit 0x66 maximum allowed time, after toff_fall completed, for the unit to decay below 12.5%. r/w word y l11 ms y 150 0xf258 toff_delay the toff_delay command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. values from 0 to 83 seconds are valid. the resulting turn off delay will have a typical delay of 270s for toff_delay = 0 and an uncertainty of 50s for all values of toff_delay. toff_delay is not applied when a fault event occursthis command has two data bytes and is formatted in linear_5s_11s format. toff_fall the toff_fall command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt - age is commanded to zero. it is the ramp time of the v out dac. when the v out dac is zero, the pwm output will be set to high impedance state.the part will maintain the mode of operation programmed. for defined toff_fall times, the user should set the part to continuous conduction mode. loading the max value indicates the part will ramp down at the slowest possible rate. the minimum supported fall time is 0.25ms . a value less than 0.25ms will result in a 0.25ms ramp. the maximum fall time is 1.3 seconds. the number of steps in toff_fall is equal to toff_fall (in ms)/ 0.1ms with an uncertainty of 0.1ms.in discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. this command has two data bytes and is formatted in linear_5s_11s format. downloaded from: http:///
lt c3884 88 3884fb for more information www.linear.com/ltc3884 pmbus command details toff_max_warn_limit the toff_max_warn_limit command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. the output is considered off when the v out voltage is less than 12.5% of the programmed vout_command value. the calculation begins after toff_fall is complete. a data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage indefinitely. other than 0, values from 120ms to 524 seconds are valid. this command has two data bytes and is formatted in linear_5s_11s format. precondition for restart command name cmd code description type paged data format units nvm default value mfr_restart_ delay 0xdc minimum time the run pin is held low by the ltc3884. r/w word y l11 ms y 500 0xfbe8 mfr_restart_delaythis command specifies the minimum run off time in milliseconds. this device will pull the run pin low for this length of time once a falling edge of run has been detected. the minimum recommended value is 136ms. note: the restart delay is different than the retry delay. the restart delay pulls run low for the specified time, after which a standard start-up sequence is initiated. the minimum restart delay should be equal to toff_delay + toff_ fall + 136ms . valid values are from 136ms to 65.52 seconds in 16ms increments. to assure a minimum off time, set the mfr_restart_delay 16ms longer than the desired time. the output rail can be off longer than the mfr_ restart_delay after the run pin is pulled high if the output decay bit 0 is enabled in mfr_chan_config and the output takes a long time to decay below 12.5% of the programmed value.this command has two data bytes and is formatted in linear_5s_11s format. f ault response fault responses all faults command name cmd code description type paged data format units nvm default value mfr_retry_ delay 0xdb retry interval during fault retry mode. r/w word y l11 ms y 350 0xfabc mfr_retry_delay this command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. this command value is used for all fault responses that require retry. the retry time starts once the fault has been detected by the offending channel. valid values are from 120ms to 83.88 seconds in 10s increments. note: the retry delay time is determined by the longer of the mfr_retry_delay command or the time required for the regulated output to decay below 12.5% of the programmed value. if the natural decay time of the output is too long, it is possible to remove the voltage requirement of the mfr_retry_delay command by asserting bit 0 of mfr_chan_config.this command has two data bytes and is formatted in linear_5s_11s format. downloaded from: http:///
lt c3884 89 3884fb for more information www.linear.com/ltc3884 pmbus command details fault responses input voltage command name cmd code description type paged data format units nvm default value vin_ov_fault_response 0x56 action to be taken by the device when an input supply overvoltage fault is detected. r/w byte y reg y 0x80 vin_ov_fault_response the vin_ov_fault_response command instructs the device on what action to take in response to an input over - voltage fault. the data byte is in the format given in table 11. the device also:? sets the none_of_the_above bit in the status_byte ? set the input bit in the upper byte of the status_word ? sets the vin overvoltage fault bit in the status_input command, and ? notifies the host by asserting alert pin, unless masked this command has one data byte. fault responses output voltage command name cmd code description type paged data format units nvm default value vout_ov_fault_response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte y reg y 0xb8 vout_uv_fault_response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte y reg y 0xb8 ton_max_fault_ response 0x63 action to be taken by the device when a ton_max_fault event is detected. r/w byte y reg y 0xb8 vout_ov_fault_response the vout_ov_fault_response command instructs the device on what action to take in response to an output overvoltage fault. the data byte is in the format given in table 7. the device also: ? sets the vout_ov bit in the status_byte ? sets the vout bit in the status_word ? sets the vout overvoltage fault bit in the status_vout command ? notifies the host by asserting alert pin, unless masked the only values recognized for this command are: 0x00Cpart performs ov pull down only, or ov_pulldown. 0x80C the device shuts down (disables the output) and the unit does not attempt to retry. (pmbus, part ii, section 10.7). downloaded from: http:///
lt c3884 90 3884fb for more information www.linear.com/ltc3884 pmbus command details 0xb8C the device shuts down (disables the output) and device attempts to retry continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x 4n the device shuts down and the unit does not attempt to retry. the output remains disabled until the part is com - manded off then on or the run pin is asserted low then high or reset through the command or removal of vin. the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. 0x 78+n the device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded off then on or the run pin is asserted low then high or reset through the command or removal of vin. the ov fault must remain active for a period of n ? 10s, where n is a value from 0 to 7. any other value will result in a cml fault and the write will be ignored.this command has one data byte. table 7. vout_ov_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3884:? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3884. 00 part performs ov pull down only or ov_pulldown (i.e., turns off the top mosfet and turns on lower mosfet while v out is > vout_ov_fault). 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. vout_uv_fault_response the vout_uv_fault_response command instructs the device on what action to take in response to an output undervoltage fault. the data byte is in the format given in table 8. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the vout undervoltage fault bit in the status_vout command ? notifies the host by asserting alert pin, unless masked downloaded from: http:///
lt c3884 91 3884fb for more information www.linear.com/ltc3884 pmbus command details the uv fault and warn are masked until the following criteria are achieved: 1) the ton_max_fault_limit has been reached 2) the ton_delay sequence has completed 3) the ton_rise sequence has completed 4) the vout_uv_fault_limit threshold has been reached 5) the iout_oc_fault_limit is not present the uv fault and warn are masked whenever the channel is not active. the uv fault and warn are masked during ton_rise and toff_fall sequencing. this command has one data byte. table 8. vout_uv_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3884:? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? the device receives a restore_user_all command. ? the device receives a mfr_reset command. ? the device supply power is cycled. 00 the pmbus device continues operation without interruption. (ignores the fault functionally) 01 the pmbus device continues operation for the delay time specified by bits [2:0] and the delay time unit specified for that particular fault. if the fault condition is still present at the end of the delay time, the unit responds as programmed in the retry setting (bits [5:3]). 10 the device shuts down (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the delay time in 10s increments. this delay time determines how long the controller continues operating after a fault is detected. only valid for deglitched off state. downloaded from: http:///
lt c3884 92 3884fb for more information www.linear.com/ltc3884 pmbus command details ton_max_fault_response the ton_max_fault_response command instructs the device on what action to take in response to a ton_max fault. the data byte is in the format given in table 11. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the vout bit in the status_word ? sets the ton_max_fault bit in the status_vout command, and ? notifies the host by asserting alert pin, unless masked a value of 0 disables the ton_max_fault_response. it is not recommended to use 0. note: the pwm channel remains in discontinues mode until the ton_max_fault_limit has been exceeded. this command has one data byte. fault responses output current command name cmd code description type paged data format units nvm default value iout_oc_fault_response 0x47 action to be taken by the device when an output overcurrent fault is detected. r/w byte y reg y 0x00 iout_oc_fault_response the iout_oc_fault_response command instructs the device on what action to take in response to an output overcurrent fault. the data byte is in the format given in table 9. the device also: ? sets the none_of_the_above bit in the status_byte ? sets the iout_oc bit in the status_byte ? sets the iout bit in the status_word ? sets the iout overcurrent fault bit in the status_iout command, and ? notifies the host by asserting alert pin, unless masked this command has one data byte. downloaded from: http:///
lt c3884 93 3884fb for more information www.linear.com/ltc3884 pmbus command details table 9. iout_oc_fault_response data byte contents bits description value meaning 7:6 response for all values of bits [7:6], the ltc3884:? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? the device receives a restore_user_all command. ? the device receives a mfr_reset command. ? the device supply power is cycled. 00 the ltc3884 continues to operate indefinitely while maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage (known as constant- current or brick-wall limiting). 01 not supported. 10 the ltc3884 continues to operate, maintaining the output current at the value set by iout_oc_fault_limit without regard to the output voltage, for the delay time set by bits [2:0]. if the device is still operating in current limit at the end of the delay time, the device responds as programmed by the retry setting in bits [5:3]. 11 the ltc3884 shuts down immediately and responds as programmed by the retry setting in bits [5:3]. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared by cycling the run pin or removing bias power. 111 the device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. note: the retry interval is set by the mfr_retry_delay command. 2:0 delay time 000-111 the number of delay time units in 16ms increments. this delay time is used to determine the amount of time a unit is to continue operating after a fault is detected before shutting down. only valid for deglitched off response. fault responses ic temperature command name cmd code description type paged data format units nvm default value mfr_ot_fault_response 0xd6 action to be taken by the device when an internal overtemperature fault is detected. r byte n reg 0xc0 mfr_ot_fault_response the mfr_ot_fault_response command byte instructs the device on what action to take in response to an internal overtemperature fault. the data byte is in the format given in table 10. the ltc3884 also: ? sets the none_of_the_above bit in the status_byte ? sets the mfr bit in the status_word, and ? sets the overtemperature fault bit in the status_mfr_specific command ? notifies the host by asserting alert pin, unless masked this command has one data byte. downloaded from: http:///
lt c3884 94 3884fb for more information www.linear.com/ltc3884 pmbus command details table 10. data byte contents mfr_ot_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltc3884:? sets the corresponding fault bit in the status commands and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? bias power is removed and reapplied to the ltc3884. 00 not supported. writing this value will generate a cml fault. 01 not supported. writing this value will generate a cml fault 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 the devices output is disabled while the fault is present. operation resumes and the output is enabled when the fault condition no longer exists. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001-111 not supported. writing this value will generate cml fault. 2:0 delay time xxx not supported. value ignored fault responses external temperature command name cmd code description type paged data format units nvm default value ot_fault_ response 0x50 action to be taken by the device when an external overtemperature fault is detected, r/w byte y reg y 0xb8 ut_fault_ response 0x54 action to be taken by the device when an external undertemperature fault is detected. r/w byte y reg y 0xb8 ot_fault_response the ot_fault_response command instructs the device on what action to take in response to an external overtem - perature fault on the external temp sensors. the data byte is in the format given in table 11. the device also : ? sets the temperature bit in the status_byte ? sets the overtemperature fault bit in the status_temperature command, and ? notifies the host by asserting alert pin, unless masked this command has one data byte.ut_fault_response the ut_fault_response command instructs the device on what action to take in response to an external under - temperature fault on the external temp sensors. the data byte is in the format given in table 11. the device also : ? sets the temperature bit in the status_byte ? sets the undertemperature fault bit in the status_temperature command, and ? notifies the host by asserting alert pin, unless masked downloaded from: http:///
lt c3884 95 3884fb for more information www.linear.com/ltc3884 pmbus command details this condition is detected by the adc so the response time may be up to t convert . this command has one data byte. table 11. data byte contents: ton_max_fault_response, vin_ov_fault_response, ot_fault_response, ut_fault_response bits description value meaning 7:6 response for all values of bits [7:6], the ltc3884:? sets the corresponding fault bit in the status commands, and ? notifies the host by asserting alert pin, unless masked. the fault bit, once set, is cleared only when one or more of the following events occurs: ? the device receives a clear_faults command. ? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? the device receives a restore_user_all command. ? the device receives a mfr_reset command. ? the device supply power is cycled. 00 the pmbus device continues operation without interruption. 01 not supported. writing this value will generate a cml fault. 10 the device shuts down immediately (disables the output) and responds according to the retry setting in bits [5:3]. 11 not supported. writing this value will generate a cml fault. 5:3 retry setting 000 the unit does not attempt to restart. the output remains disabled until the fault is cleared until the device is commanded off bias power is removed. 111 the pmbus device attempts to restart continuously, without limitation, until it is commanded off (by the run pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down without retry. note : the retry interval is set by the mfr_retry_delay command. 2:0 delay time xxx not supported. values ignored fault sharing fault sharing propagation command name cmd code description type paged data format units nvm default value mfr_fault_ propagate 0xd2 configuration that determines which faults are propagated to the fault pins. r/w word y reg y 0x6993 mfr_fault_propagate the mfr_fault_propagate command enables the faults that can cause the fault n pin to assert low. the com - mand is formatted as shown in table 12. faults can only be propagated to the fault n pin if they are programmed to respond to faults.this command has two data bytes. downloaded from: http:///
lt c3884 96 3884fb for more information www.linear.com/ltc3884 table 12: fault n propagate fault configuration the fault0 and fault1 pins are designed to provide electrical notification of selected events to the user. some of these events are common to both output channels. others are specific to an output channel. they can also be used to share faults between channels. bit(s) symbol operation b[15] vout disabled while not decayed. this is used in a polyphase configuration when bit 0 of the mfr_chan_config_ltc3884 is a zero. if the channel is turned off, by toggling the run pin or commanding the part off, and then the run is reasserted or the part is commanded back on before the output has decayed, vout will not restart until the 12.5% decay is honored. the fault pin is asserted during this condition if bit 15 is asserted. b[14] mfr_fault_propagate_short_cmd_cycle 0: no action 1: asserts low if commanded off then on before the output has sequenced off. re-asserts high t off(min) after sequence off. b[13] mfr_fault_propagate_ton_max_fault 0: no action if a ton_max_fault fault is asserted 1: associated output will be asserted low if a ton_max_fault fault is asserted fault0 is associated with page 0 ton_max_fault faults fault1 is associated with page 1 ton_max_fault faults b[12] reserved b[11] mfr_fault0_propagate_int_ot, mfr_fault1_propagate_int_ot 0: no action if the mfr_ot_fault_limit fault is asserted1: associated output will be asserted low if the mfr_ot_fault_limit fault is asserted b[10] reserved b[9] reserved b[8] mfr_fault0_propagate_ut, mfr_fault1_propagate_ut 0: no action if the ut_fault_limit fault is asserted1: associated output will be asserted low if the ut_fault_limit fault is asserted fault0 is associated with page 0 ut faults fault1 is associated with page 1 ut faults b[7] mfr_fault0_propagate_ot, mfr_fault1_propagate_ot 0: no action if the ot_fault_limit fault is asserted1: associated output will be asserted low if the ot_fault_limit fault is asserted fault0 is associated with page 0 ot faults fault1 is associated with page 1 ot faults b[6] reserved b[5] reserved b[4] mfr_fault0_propagate_input_ov, mfr_fault1_propagate_input_ov 0: no action if the vin_ov_fault_limit fault is asserted1: associated output will be asserted low if the vin_ov_fault_limit fault is asserted b[3] reserved b[2] mfr_fault0_propagate_iout_oc, mfr_fault1_propagate_iout_oc 0: no action if the iout_oc_fault_limit fault is asserted1: associated output will be asserted low if the iout_oc_fault_limit fault is asserted fault0 is associated with page 0 oc faults fault1 is associated with page 1 oc faults b[1] mfr_fault0_propagate_vout_uv, mfr_fault1_propagate_vout_uv 0: no action if the vout_uv_fault_limit fault is asserted1: associated output will be asserted low if the vout_uv_fault_limit fault is asserted fault0 is associated with page 0 uv faults fault1 is associated with page 1 uv faults b[0] mfr_fault0_propagate_vout_ov, mfr_fault1_propagate_vout_ov 0: no action if the vout_ov_fault_limit fault is asserted1: associated output will be asserted low if the vout_ov_fault_limit fault is asserted fault0 is associated with page 0 ov faults fault1 is associated with page 1 ov faults pmbus command details downloaded from: http:///
lt c3884 97 3884fb for more information www.linear.com/ltc3884 fault sharing response command name cmd code description type paged data format units nvm default value mfr_fault_response 0xd5 action to be taken by the device when the fault pin is asserted low. r/w byte y reg y 0xc0 mfr_fault_response the mfr_fault_response command instructs the device on what action to take in response to the fault n pin being pulled low by an external source. supported values: value meaning 0xc0 fault_inhibit the ltc3884 will three-state the output in response to the fault pin pulled low. 0x00 fault_ignore the ltc3884 continues operation without interruption. the device also:? sets the mfr bit in the status_word. ? sets bit 0 in the status_mfr_specific command to indicate fault n is being pulled low ? notifies the host by asserting alert , unless masked this command has one data byte. scratchpad command name cmd code description type paged data format units nvm default value user_data_00 0xb0 oem reserved. typically used for part serialization. r/w word n reg y na user_data_01 0xb1 manufacturer reserved for ltpowerplay. r/w word y reg y na user_data_02 0xb2 oem reserved. typically used for part serialization. r/w word n reg y na user_data_03 0xb3 a nvm word available for the user. r/w word y reg y 0x0000 user_data_04 0xb4 a nvm word available for the user. r/w word n reg y 0x0000 pmbus command details downloaded from: http:///
lt c3884 98 3884fb for more information www.linear.com/ltc3884 pmbus command details user_data _00 through user_data_04 these commands are non-volatile memory locations for customer storage. the customer has the option to write any value to the user_data_nn at any time. however, the ltpowerplay software and contract manufacturers use some of these commands for inventory control. modifying the reserved user_data_nn commands may lead to undesirable inventory control and incompatibility with these products. these commands have 2 data bytes and are in register format. identification command name cmd code description type paged data format units nvm default value pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.2. r byte n reg fs 0x22 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte n reg 0xb0 mfr_id 0x99 the manufacturer id of the ltc3884 in ascii. r string n asc lt c mfr_model 0x9a manufacturer part number in ascii. r string n asc ltc3884 mfr_special_id 0xe7 manufacturer code representing the ltc3884. r word n reg 0x4c0x pmbus_revision the pmbus_revision command indicates the revision of the pmbus to which the device is compliant. the ltc3884 is pmbus version 1.2 compliant in both part i and part ii. this read-only command has one data byte. capability this command provides a way for a host system to determine some key capabilities of a pmbus device. the ltc3884 supports packet error checking, 400khz bus speeds, and alert pin. this read-only command has one data byte.mfr_id the mfr_id command indicates the manufacturer id of the ltc3884 using ascii characters. this read-only command is in block format. mfr_model the mfr_model command indicates the manufacturers part number of the ltc3884 using ascii characters. this read-only command is in block format. mfr_special_id the 16- bit word representing the part name and revision. 0x 4c denotes the part is an ltc3884 , xx is adjustable by the manufacturer. this read-only command has two data bytes. downloaded from: http:///
lt c3884 99 3884fb for more information www.linear.com/ltc3884 pmbus command details fault warning and status command name cmd code description type paged format units nvm default value clear_faults 0x03 clear any fault bits that have been set. send byte n na smbalert_mask 0x1b mask activity. block r/w y reg y see cmd details mfr_clear_peaks 0xe3 clears all peak values. send byte y na status_byte 0x78 one byte summary of the units fault condition. r/w byte y reg na status_word 0x79 two byte summary of the units fault condition. r/w word y reg na status_vout 0x7a output voltage fault and warning status. r/w byte y reg na status_iout 0x7b output current fault and warning status. r/w byte y reg na status_input 0x7c input supply fault and warning status. r/w byte n reg na status_ temperature 0x7d external temperature fault and warning status for read_temerature_1. r/w byte y reg na status_cml 0x7e communication and memory fault and warning status. r/w byte n reg na status_mfr_ specific 0x80 manufacturer specific fault and state information. r/w byte y reg na mfr_pads 0xe5 digital status of the i/o pads. r word n reg na mfr_common 0xef manufacturer status bits that are common across multiple ltc chips. r byte n reg na clear_faults the clear_faults command is used to clear any fault bits that have been set. this command clears all bits in all status commands simultaneously. at the same time, the device negates (clears, releases) its alert pin signal output if the device is asserting the alert pin signal. if the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the alert pin low. clear_faults can take up to 10s to process. if a fault occurs within that time frame it may be cleared before the status register is set.this write-only command has no data bytes. the clear_faults does not cause a unit that has latched off for a fault condition to restart. units that have shut down for a fault condition are restarted when:? the output is commanded through the run pin, the operation command, or the combined action of the run pin and operation command, to turn off and then to turn back on, or ? mfr_reset command is issued. ? bias power is removed and reapplied to the integrated circuit smbalert_mask the smbalert_mask command can be used to prevent a particular status bit or bits from asserting alert as they are asserted. figure 44 shows an example of the write word format used to set an alert mask, in this case without pec. the bits in the mask byte align with bits in the specified status register. for example, if the status_temperature command code is sent in the first data byte, and the mask byte contains 0x 40, then a subsequent external overtemperature warning downloaded from: http:///
lt c3884 100 3884fb for more information www.linear.com/ltc3884 pmbus command details would still set bit 6 of status_temperature but not assert alert . all other supported status_temperature bits would continue to assert alert if set. figure 45 shows an example of the block write C block read process call protocol used to read back the present state of any supported status register, again without pec. smbalert_mask cannot be applied to status_byte, status_word, mfr_common or mfr_pads_ltc3884. factory default masking for applicable status registers is shown below. providing an unsupported command code to smbalert_mask will generate a cml for invalid/unsupported data. smbalert_mask default setting: (refer also to figure 2) status resister alert mask value masked bits status_vout 0x00 none status_iout 0x00 none status_temperature 0x00 none status_cml 0x00 none status_input 0x00 none status_mfr_specific 0x11 bit 4 (internal pll unlocked), bit 0 ( fault pulled low by external device) slave address smbalert_mask command code block count (= 1) w a a s 7 8 8 1 status_x command code 8 1 1 1 1 1 a a sr 1 block count (= 1) a na p 3884 f48 a 8 8 1 1 1 1 mask byte slave address 7 r 1 p 1 slave address smbalert_mask command code status_x command code w a a s 7 8 8 1 8 1 1 1 1 1 a a mask byte 3884 f47 figure 47. example of writing smbalert_mask figure 48. example of reading smbalert_mask mfr_clear_peaks the mfr_clear_peaks command clears the mfr_*_peak data values. a mfr_reset command will also clear the mfr_*_peak data values.this write-only command has no data bytes. status_byte the status_byte command returns one byte of information with a summary of the most critical faults. this is the lower byte of the status word. downloaded from: http:///
lt c3884 101 3884fb for more information www.linear.com/ltc3884 pmbus command details status_byte message contents: bit status bit name meaning 7* busy a fault was declared because the ltc3884 was unable to respond. 6 off this bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 vout_ov an output overvoltage fault has occurred. 4 iout_oc an output overcurrent fault has occurred. 3 vin_uv not supported (ltc3884 returns 0). 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0* none of the above a fault not listed in bits[7:1] has occurred. * alert can be asserted if either of these bits is set. they may be cleared by writing a 1 to their bit position in the status_byte , in lieu of a clear_ faults command. this command has one data byte.status_word the status_word command returns a two-byte summary of the channel's fault condition. the low byte of the status_word is the same as the status_byte command. status_word high byte message contents: bit status bit name meaning 15 v out an output voltage fault or warning has occurred. 14 i out an output current fault or warning has occurred. 13 input an input voltage fault or warning has occurred. 12 mfr_specific a fault or warning specific to the ltc3884 has occurred. 11 power_good# the power_good state is false if this bit is set. 10 fans not supported (ltc3884 returns 0). 9 other not supported (ltc3884 returns 0). 8 unknown not supported (ltc3884 returns 0). if any of the bits in the upper byte are set, none_of_the_above is asserted.this command has two data bytes. status_vout the status_vout command returns one byte of v out status information. status_vout message contents: bit meaning 7 v out overvoltage fault. 6 v out overvoltage warning. 5 v out undervoltage warning. 4 v out undervoltage fault. 3 v out max warning. 2 ton max fault. 1 toff max fault. 0 not supported (ltc3884 returns 0). downloaded from: http:///
lt c3884 102 3884fb for more information www.linear.com/ltc3884 pmbus command details the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte.status_iout the status_iout command returns one byte of i out status information. status_iout message contents: bit meaning 7 i out overcurrent fault. 6 not supported (ltc3884 returns 0). 5 i out overcurrent warning. 4:0 not supported (ltc3884 returns 0). the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. status_inputthe status_input command returns one byte of v in (vinsns) status information. status_input message contents: bit meaning 7 v in overvoltage fault. 6 not supported (ltc3884 returns 0). 5 v in undervoltage warning. 4 not supported (ltc3884 returns 0). 3 unit off for insufficient v in . 2 not supported (ltc3884 returns 0). 1 i in overcurrent warning. 0 not supported (ltc3884 returns 0). the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. bit 3 of this command is not latched and will not generate an alert even if it is set. this command has one data byte. downloaded from: http:///
lt c3884 103 3884fb for more information www.linear.com/ltc3884 pmbus command details status_temperature the status_temperature commands returns one byte with status information on temperature. this is a paged command and is related to the respective read_temperature_1 value. status_temperature message contents: bit meaning 7 external overtemperature fault. 6 external overtemperature warning. 5 not supported (ltc3884 returns 0). 4 external undertemperature fault. 3:0 not supported (ltc3884 returns 0). .the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. this command has one data byte. status_cml the status_cml command returns one byte of status information on received commands, internal memory and logic. status_cml message contents: bit meaning 7 invalid or unsupported command received. 6 invalid or unsupported data received. 5 packet error check failed. 4 memory fault detected. 3 processor fault detected. 2 reserved (ltc3884 returns 0). 1 other communication fault. 0 other memory or logic fault. if either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. continued operation of the part is not recommended if these bits are continuously set. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. any supported fault bit in this command will initiate an alert event. this command has one data byte. downloaded from: http:///
lt c3884 104 3884fb for more information www.linear.com/ltc3884 pmbus command details status_mfr_specificthe status_mfr_specific commands returns one byte with the manufacturer specific status information. the format for this byte is: bit meaning 7 internal temperature fault limit exceeded. 6 internal temperature warn limit exceeded. 5 factory trim area nvm crc fault. 4 pll is unlocked 3 fault log present 2 v dd33 uv or ov fault 1 shortcycle event detected 0 fault pin asserted low by external device if any of these bits are set, the mfr bit in the status_word will be set, and alert may be asserted. the user is permitted to write a 1 to any bit in this command to clear a specific fault. this permits the user to clear status by means other than using the clear_faults command. however, the fault log present bit can only be cleared by issuing the mfr_fault_log_clear command.any supported fault bit in this command will initiate an alert event. this command has one data byte.mfr_pads this command provides the user a means of directly reading the digital status of the i/o pins of the device. the bit assignments of this command are as follows: bit assigned digital pin 15 v dd33 ov fault 14 v dd33 uv fault 13 reserved 12 reserved 11 adc values invalid, occurs during start-up. may occur briefly on current measurement channels during normal operation 10 sync clocked by external device (when ltc3884 configured to drive sync pin) 9 channel 1 power good 8 channel 0 power good 7 ltc3884 driving run1 low 6 ltc3884 driving run0 low 5 run1 pin state 4 run0 pin state 3 ltc3884 driving fault1 low 2 ltc3884 driving fault0 low 1 fault1 pin state 0 fault0 pin state a 1 indicates the condition is true.this read-only command has two data bytes. downloaded from: http:///
lt c3884 105 3884fb for more information www.linear.com/ltc3884 pmbus command details mfr_common the mfr_common command contains bits that are common to all ltc digital power and telemetry products. bit meaning 7 chip not driving alert low 6 ltc3884 not busy 5 calculations not pending 4 ltc3884 outputs not in transition 3 nvm initialized 2 reserved 1 share_clk timeout 0 wp pin status this read-only command has one data byte. telemetry command name cmd code description type paged format units nvm default value read_vin 0x88 measured input supply voltage. r word n l11 v na read_iin 0x89 measured input supply current. r word n l11 a na read_vout 0x8b measured output voltage. r word y l16 v na read_iout 0x8c measured output current. r word y l11 a na read_temperature_1 0x8d external diode junction temperature. this is the value used for all temperature related processing, including iout_cal_gain. r word y l11 c na read_temperature_2 0x8e internal junction temperature. does not affect any other commands. r word n l11 c na read_frequency 0x95 measured pwm switching frequency. r word y l11 hz na read_pout 0x96 calculated output power. r word y l11 w na read_pin 0x97 calculated input power. r word n l11 w na mfr_pin_accuracy 0xac returns the accuracy of the read_pin command r byte n % 5.0% mfr_iout_peak 0xd7 report the maximum measured value of read_iout since last mfr_clear_peaks. r word y l11 a na mfr_vout_peak 0xdd maximum measured value of read_vout since last mfr_clear_peaks. r word y l16 v na mfr_vin_peak 0xde maximum measured value of read_vin since last mfr_clear_peaks. r word n l11 v na mfr_temperature_1_peak 0xdf maximum measured value of external temperature (read_temperature_1) since last mfr_clear_peaks. r word y l11 c na mfr_read_iin_peak 0xe1 maximum measured value of read_iin command since last mfr_clear_peaks. r word n l11 a na mfr_read_ichip 0xe4 measured current used by the ltc3884. r word n l11 a na mfr_temperature_2_peak 0xf4 peak internal die temperature since last mfr_clear_peaks. r word n l11 c na mfr_adc_control 0xd8 adc telemetry parameter selected for repeated fast adc read back. r/w byte n n reg na downloaded from: http:///
lt c3884 106 3884fb for more information www.linear.com/ltc3884 pmbus command details read_vin the read_vin command returns the measured v in pin voltage, in volts added to read_ichip ? mfr_rvin . this compensates for the ir voltage drop across the v in filter element due to the supply current of the ltc3884. this read-only command has two data bytes and is formatted in linear_5s_11s format.read_vout the read_vout command returns the measured output voltage by the vout_mode command. this read-only command has two data bytes and is formatted in linear_16u format. read_iin the read_iin command returns the input current, in amperes, as measured across the input current sense resistor (see also mfr_iin_cal_gain).this read-only command has two data bytes and is formatted in linear_5s_11s format. read_iout the read_iout command returns the average output current in amperes. the iout value is a function of: a) the differential voltage measured across the i sense pins b) the iout_cal_gain value c) the mfr_iout_cal_gain_tc value, and d) read_temperature_1 value e) the mfr_temp_1_gain and the mfr_temp_1_offset this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_1 the read_temperature_1 command returns the temperature, in degrees celsius, of the external sense element. this read-only command has two data bytes and is formatted in linear_5s_11s format. read_temperature_2 the read_temperature _2 command returns the ltc3884 s die temperature, in degrees celsius, of the internal sense element.this read-only command has two data bytes and is formatted in linear_5s_11s format. read_frequency the read_frequency command is a reading of the pwm switching frequency in khz. this read-only command has 2 data bytes and is formatted in linear_5s_11s format. read_pout the read_pout command is a reading of the dc/dc converter output power in watts. pout is calculated based on the most recent correlated output voltage and current reading.this read-only command has 2 data bytes and is formatted in linear_5s_11s format. downloaded from: http:///
lt c3884 107 3884fb for more information www.linear.com/ltc3884 pmbus command details read_pin the read_pin command is a reading of the dc/dc converter input power in watts. pin is calculated based on the most recent input voltage and current reading.this read-only command has 2 data bytes and is formatted in linear_5s_11s format. mfr_pin_accuracy the mfr_pin_accuracy command returns the accuracy, in percent, of the value returned by the read_pin command. there is one data byte. the value is 0.1% per bit which gives a range of 0.0% to 25.5%. this read-only command has one data byte and is formatted as an unsigned integer. mfr_iout_peak the mfr_iout_peak command reports the highest current, in amperes, reported by the read_iout measurement. this command is cleared using the mfr_clear_peaks command.this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_vout_peak the mfr_vout_peak command reports the highest voltage, in volts, reported by the read_vout measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_16u format. mfr_vin_peak the mfr_vin_peak command reports the highest voltage, in volts, reported by the read_vin measurement. this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_temperature_1_peak the mfr_temperature _1_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_1 measurement.this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_read_iin_peak the mfr_read_iin_peak command reports the highest current, in amperes, reported by the read_iin measurement. this command is cleared using the mfr_clear_peaks command.this command has two data bytes and is formatted in linear_5s_11s format. mfr_read_ichip the mfr_read_ichip command returns the measured input current, in amperes, used by the ltc3884. this command has two data bytes and is formatted in linear_5s_11s format. downloaded from: http:///
lt c3884 108 3884fb for more information www.linear.com/ltc3884 pmbus command details mfr_temperature_2_peak the mfr_temperature _2_peak command reports the highest temperature, in degrees celsius, reported by the read_temperature_2 measurement.this command is cleared using the mfr_clear_peaks command. this read-only command has two data bytes and is formatted in linear_5s_11s format. mfr_adc_control the mfr_adc_control command determines the adc read back selection. a default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t convert . the user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. this command has a latency of up to 2 adc conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 adc conversion or approximately 24ms ). it is recommended the part remain in standard telemetry mode except for special cases where fast adc updates of a single parameter is required. the part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. if this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. when round robin is reasserted, all warnings and faults and servo mode are re-enabled. commanded value telemetry command name description 0x0f reserved 0x0e reserved 0x0d reserved 0x0c read_temperature_1 channel 1 external temperature 0x0b reserved 0x0a read_iout channel 1 measured output current 0x09 read_vout channel 1 measured output voltage 0x08 read_temperature_1 channel 0 external temperature 0x07 reserved 0x06 read_iout channel 0 measured output current 0x05 read_vout channel 0 measured output voltage 0x04 read_temperature_2 internal junction temperature 0x03 read_iin measured input supply current 0x02 mfr_read_ichip measured supply current of the ltc3884 0x01 read_vin measured input supply voltage 0x00 standard adc round robin telemetry if a reserved command value is entered, the telemetry will default to internal ic temperature and issue a cml fault. cml faults will continue to be issued by the ltc3884 until a valid command value is entered. the accuracy of the measured input supply voltage is only guaranteed if the mfr_adc_control command is set to standard round robin telemetry. this write-only command has 1 data byte and is formatted in register format. downloaded from: http:///
lt c3884 109 3884fb for more information www.linear.com/ltc3884 pmbus command details nvm memory commands store/restore command name cmd code description type paged format units nvm default value store_user_all 0x15 store user operating memory to eeprom. send byte n na restore_user_all 0x16 restore user operating memory from eeprom. send byte n na mfr_compare_user_all 0xf0 compares current command contents with nvm. send byte n na store_user_all the store_user_all command instructs the pmbus device to copy the non-volatile user contents of the operating memory to the matching locations in the non-volatile user nvm memory. executing this command if the die temperature exceeds 85c or is below 0c is not recommended and the data reten - tion of 10 years cannot be guaranteed. if the die temperature exceeds 130c , the store_user_all command is disabled. the command is re-enabled when the ic temperature drops below 125c. communication with the ltc3884 and programming of the nvm can be initiated when extv cc or v dd33 is available and vin is not applied. to enable the part in this state, using global address 0x 5b write mfr_ee_unlock to 0x2b followed by 0xc4 . the ltc3884 will now communicate normally, and the project file can be updated. to write the updated project file to the nvm issue a store_user_all command. when vin is applied, a mfr_reset must be issued to allow the pwm to be enabled and valid adcs to be read. this write-only command has no data bytes. restore_user_all the restore_user_all command instructs the ltc3884 to copy the contents of the non-volatile user memory to the matching locations in the operating memory. the values in the operating memory are overwritten by the value retrieved from the user commands. the ltc3884 ensures both channels are off, loads the operating memory from the internal eeprom, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both pwm channels if applicable. store_user_all, mfr_compare_user_all and restore_user_all commands are disabled if the die exceeds 130c and are not re-enabled until the die temperature drops below 125c.this write-only command has no data bytes. mfr_compare_user_all the mfr_compare_user_all command instructs the pmbus device to compare current command contents with what is stored in non-volatile memory. if the compare operation detects differences, a cml bit 0 fault will be generated. this write-only command has no data bytes. downloaded from: http:///
lt c3884 110 3884fb for more information www.linear.com/ltc3884 pmbus command details fault logging command name cmd code description type paged data format units nvm default value mfr_fault_log 0xee fault log data bytes. r block n cf y na mfr_fault_log_ store 0xea command a transfer of the fault log from ram to eeprom. send byte n na mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging. send byte n na mfr_fault_log the mfr_fault_log command allows the user to read the contents of the fault_log after the first fault occur - rence since the last mfr_fault_log_clear command was written. the contents of this command are stored in non-volatile memor y , and are cleared by the mfr_fault_log_clear command. the length and content of this command are listed in table 13. if the user accesses the mfr_fault_log command and no fault log is present, the command will return a data length of 0. if a fault log is present, the mfr_fault_log will return a block of data 147 bytes long. if a fault occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data. note: the approximate transfer time for this command is 3.4ms using a 400khz clock. this read-only command is in block format. mfr_fault_log_store the mfr_fault_log_store command forces the fault log operation to be written to nvm just as if a fault event occurred. this command will set bit 3 of the status_mfr_specific fault if bit 7 enable fault logging is set in the mfr_config_all command.if the die temperature exceeds 130c , the mfr_fault_log_store command is disabled until the ic temperature drops below 125c. this write-only command has no data bytes. downloaded from: http:///
lt c3884 111 3884fb for more information www.linear.com/ltc3884 pmbus command details table 13. fault logging this table outlines the format of the block data from a read block data of the mfr_fault_log command. data format definitions lin 11 = pmbus = rev 1.2, part 2, section 7.1lin 16 = pmbus rev 1.2, part 2, section 8. mantissa portion only byte = 8 bits interpreted per definition of this command d ata bits data format byte num block read command block length byte 147 the mfr_fault_log command is a fixed length of 147 bytes the block length will be zero if a data log event has not been captured header information fault log preface [7:0] asc 0 returns ltxx beginning at byte 0 if a partial or complete fault log exists. word xx is a factory identifier that may vary part to part. [7:0] 1 [15:8] reg 2 [7:0] 3 fault source [7:0] reg 4 refer to table 13a. mfr_real_time [7:0] reg 5 48 bit share-clock counter value when fault occurred (200s resolution). [15:8] 6 [23:16] 7 [31:24] 8 [39:32] 9 [47:40] 10 mfr_vout_peak (page 0) [15:8] l16 11 peak read_vout on channel 0 since last power-on or clear_peaks command. [7:0] 12 mfr_vout_peak (page 1) [15:8] l16 13 peak read_vout on channel 1 since last power-on or clear_peaks command. [7:0] 14 mfr_iout_peak (page 0) [15:8] l11 15 peak read_iout on channel 0 since last power-on or clear_peaks command. [7:0] 16 mfr_iout_peak (page 1) [15:8] l11 17 peak read_iout on channel 1 since last power-on or clear_peaks command. [7:0] 18 mfr_vin_peak [15:8] l11 19 peak read_vin since last power-on or clear_peaks command. [7:0] 20 read_temperature1 (page 0) [15:8] l11 21 external temperature sensor 0 during last event. [7:0] 22 read_temperature1 (page 1) [15:8] l11 23 external temperature sensor 1 during last event. [7:0] 24 read_temperature2 [15:8] l11 25 ltc3884 die temperature sensor during last event. [7:0] 26 downloaded from: http:///
lt c3884 112 3884fb for more information www.linear.com/ltc3884 cyclical data event n (data at which fault occurred; most recent data) event n represents one complete cycle of adc reads through the mux at time of fault. example: if the fault occurs when the adc is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to eeprom read_vout (page 0) [15:8] lin 16 27 [7:0] lin 16 28 read_vout (page 1) [15:8] lin 16 29 [7:0] lin 16 30 read_iout (page 0) [15:8] lin 11 31 [7:0] lin 11 32 read_iout (page 1) [15:8] lin 11 33 [7:0] lin 11 34 read_vin [15:8] lin 11 35 [7:0] lin 11 36 read_iin [15:8] lin 11 37 [7:0] lin 11 38 status_vout (page 0) byte 39 status_vout (page 1) byte 40 status_word (page 0) [15:8] word 41 [7:0] word 42 status_word (page 1) [15:8] word 43 [7:0] word 44 status_mfr_specific (page 0) byte 45 status_mfr_specific (page 1) byte 46 pmbus command details downloaded from: http:///
lt c3884 113 3884fb for more information www.linear.com/ltc3884 event n-1(data measured before fault was detected) read_vout (page 0) [15:8] lin 16 47 [7:0] lin 16 48 read_vout (page 1) [15:8] lin 16 49 [7:0] lin 16 50 read_iout (page 0) [15:8] lin 11 51 [7:0] lin 11 52 read_iout (page 1) [15:8] lin 11 53 [7:0] lin 11 54 read_vin [15:8] lin 11 55 [7:0] lin 11 56 read_iin [15:8] lin 11 57 [7:0] lin 11 58 status_vout (page 0) byte 59 status_vout (page 1) byte 60 status_word (page 0) [15:8] word 61 [7:0] word 62 status_word (page 1) [15:8] word 63 [7:0] word 64 status_mfr_specific (page 0) byte 65 status_mfr_specific (page 1) byte 66 ** * event n-5 (oldest recorded data) read_vout (page 0) [15:8] lin 16 127 [7:0] lin 16 128 read_vout (page 1) [15:8] lin 16 129 [7:0] lin 16 130 read_iout (page 0) [15:8] lin 11 131 [7:0] lin 11 132 read_iout (page 1) [15:8] lin 11 133 [7:0] lin 11 134 read_vin [15:8] lin 11 135 [7:0] lin 11 136 read_iin [15:8] lin 11 137 [7:0] lin 11 138 status_vout (page 0) byte 139 status_vout (page 1) byte 140 status_word (page 0) [15:8] word 141 [7:0] word 142 status_word (page 1) [15:8] word 143 [7:0] word 144 status_mfr_specific (page 0) byte 145 status_mfr_specific (page 1) byte 146 pmbus command details downloaded from: http:///
lt c3884 114 3884fb for more information www.linear.com/ltc3884 pmbus command details table 13a: explanation of position_fault values position_fault value source of fault log 0xff mfr_fault_log_store 0x00 ton_max_fault 0x01 vout_ov_fault 0x02 vout_uv_fault 0x03 iout_oc_fault 0x05 temp_ot_fault 0x06 temp_ut_fault 0x07 vin_ov_fault 0x0a mfr_temp_2_ot_fault mfr_fault_log_clear the mfr_fault_log_clear command will erase the fault log file stored values. it will also clear bit 3 in the status_mfr_specific command. after a clear is issued, the status can take up to 8ms to clear. this write-only command is send bytes. block memory write/read command name cmd code description type paged data format units nvm default value mfr_ee_unlock 0xbd unlock user eeprom for access by mfr_ee_erase and mfr_ee_data commands. r/w byte n reg na mfr_ee_erase 0xbe initialize user eeprom for bulk programming by mfr_ee_data. r/w byte n reg na mfr_ee_data 0xbf data transferred to and from eeprom using sequential pmbus word reads or writes. supports bulk programming. r/w word n reg na all the nvm commands are disabled if the die temperature exceeds 130c . nvm commands are re-enabled when the die temperature drops below 125c.mfr_ee_xxxx the mfr_ee_xxxx commands facilitate bulk programming of the ltc3884 internal eeprom. contact the factory for details. downloaded from: http:///
lt c3884 115 3884fb for more information www.linear.com/ltc3884 typical applications high efficiency, dual-output 1.5v/30a and 1.0v/30a, buck converter 10nf 150pf 11% 0.1f d1 q1 bsc050ne2ls 0.1f d2 q3 bsc010ne2lsi q2 bsc050ne2ls q4 bsc010ne2lsi 2m 1f 270f16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k l1 0.33h 9311% 220nf 330fx2 6.3v 100fx2 6.3v 1500pf 2.2f 1f 10nf 150pf 1500pf 10f x2 4.7f l2 0.25h 715 1% 220nf 330fx2 6.3v 100fx2 6.3v 20k 17.8k 24.9k 4.32k 10f x2 intv cc ltc3884 v in v dd33 v dd33 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd gnd v dd25 v dd25 tg1 boost1 sw1 bg1 v out0 _cfg v out1 _cfg asel0 asel1 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc v in 4.5v to 14v v dd33 744301033 dcr=0.32 m v out0 1.5v/30a mmbt3906-al3-r mmbt3906-al3-r d1, d2: cmdsh3-tr 744301025 dcr=0.32 m v dd25 v out1 1.0v/30a downloaded from: http:///
lt c3884 116 3884fb for more information www.linear.com/ltc3884 typical applications 10nf 100pf 0.1f d1 q1 bsc050ne2ls 0.1f d2 q3 bsc010ne2lsi q2 bsc050ne2ls q4 bsc010ne2lsi 2m 1f 270 f 16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k l1 025h l2 025h 7151% 220nf 330fx2 6.3v 100f x2 6.3v 4.7nf 2.2f 1f 10nf 10fx2 10fx2 715 1% 715 1% 220nf 330f 6.3v x2 100f 6.3v x2 30.1k 1.96k 10nf 1 0.1f d3 q7 bsc050ne2ls 0.1f d4 q8 bsc010ne2lsi q9 bsc050ne2ls q10 bsc010ne2lsi 2m 270f16v x2 l3 0.25h l4 0.25h 220nf 330f6.3v x2 100f6.3v x2 2.2f 1f 10nf 10fx2 4.7f 7151% 220nf 330f6.3v x2 100f6.3v x2 4.7f 10fx2 24.9k 4.32k 30.1k 3.57k 24.9k 5.76k 20k 11k intv cc ltc3884 v in v dd33 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 tg1 boost1 sw1 bg1 v out0 _cfg v out1 _cfg asel1 asel0 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc 4.5v to 14v v in 1 1% c3 v dd33 744301025 dcr=0.32 m mmbt3906-al3-r mmbt3906-al3-r 744301025 dcr=0.32 m v dd33 v dd25 intv cc ltc3884 v in v dd33 tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 tg1 boost1 sw1 bg1 tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc 1% 1f c3 744301025 dcr=0.32 m mmbt3906-al3-r mmbt3906-al3-r d1, d2, d3, d4: cmdsh3-tr 3889 f39 744301025 dcr=0.32 m v dd33 sync run fault alert pgood sync run share clk share clk pgood alert fault sda scl sda scl v out0 _cfg v out1 _cfg asel1 asel0 freq_cfg phase_cfg i in + i in C v dd25 v dd25_1 v dd25_1 v out 1.0v/120a 4 phase, high efficiency, single-output, 1.0v/160a buck converter downloaded from: http:///
lt c3884 117 3884fb for more information www.linear.com/ltc3884 high efficiency, dual-output, 2.5v/30a and 3.3v/30a buck converter typical applications 10nf 150pf 11% 0.1f d1 q1 bsc032ne2ls 0.1f d2 q3 bsc010ne2lsi q2 bsc024ne2ls q4 bsc010ne2lsi 2m 1f 270f16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k l1 0.68h 9761% 220nf 330f6.3v x2 1500pf 2.2f 1f 10nf 150pf 1500pf 10fx2 4.7f l2 0.9h 9091% 220nf 330f 6.3v x2 10f x2 16.2k 20.5k 10k 15k 30.1k 1.96k 2m 100f 6.3v x2 100f6.3v x2 intv cc ltc3884 v in v dd33 v dd33 v dd25 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 tg1 boost1 sw1 bg1 vout0_cfg vout1_cfg asel0 asel1 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc v in 7v to 14v v dd33 ser2009-681ml dcr=0.63 m v out0 2.5v/25a mmbt3906-al3-r mmbt3906-al3-r ser2010-901ml dcr=0.9 m v dd25 v out1 3.3v/25a d1, d2: cmdsh3-tr downloaded from: http:///
lt c3884 118 3884fb for more information www.linear.com/ltc3884 high efficiency, single-output, 5v/60a buck converter typical applications 10nf 150pf 11% 0.1f d1 q1 bsc024ne2ls 0.1f d2 q3 bsc010ne2lsi q2 bsc024ne2ls q4 bsc010ne2lsi 2m 1f 270f16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k l1 1h 3.74k1% 220nf 330f6.3v x2 100f6.3v x2 3.3nf 2.2f 1f 10nf 10f x2 4.7f l2 1h 3.74k1% 220nf 330f 6.3v x2 100f 6.3v x2 10k 23.2k 30.1k 1.96k 10fx2 2m intv cc ltc3884 v in v dd33 v dd33 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 tg1 boost1 sw1 bg1 v out0 _cfg v out1 _cfg asel0 asel1 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc v in 10v to 14v c3 v dd33 ser2011-102ml dcr=1.2 m mmbt3906-al3-r mmbt3906-al3-r d1, d2: cmdsh3-tr 3884 ta08 dcr=1.2 m v dd25 v out 5.0v/60a ser2011-102ml 30.1k 1.96k v dd25 downloaded from: http:///
lt c3884 119 3884fb for more information www.linear.com/ltc3884 typical applications high efficiency, single-output 1.0/80a buck converter with power blocks intv cc intv cc 10nf 150pf 11% 1f 270f16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k 47nf 330f 6.3v x2 100f 6.3v x2 3.3nf 2.2f 1f 10nf 4.7f 47nf 330f6.3v x2 100f6.3v x2 24.9k 30.1k 4.32k 2m 0.1f 0.1f 10fx4 10f x4 intv cc ltc3884 v in v dd33 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 v dd25 tg1 boost1 sw1 bg1 v out0 _cfg v out1 _cfg asel1 asel0 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc v in 6v to 14v v dd33 mmbt3906-al3-r mmbt3906-al3-r v dd25 v in1 v in2 pwmh pwml v gate gnd gnd gnd gnd temp_p temp_n c_n c_p v out1 v out2 vra001-4c0g v in1 v in2 pwmh pwml vgate gnd gnd gnd gnd temp_p temp_n c_n c_p v out1 v out2 vra001-4c0g v out 1.0v/80a intv cc v dd33 3.57k downloaded from: http:///
lt c3884 120 3884fb for more information www.linear.com/ltc3884 package description 7.00 0.10 (4 sides) note:1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark(see note 6) pin 1 chamfer c = 0.35 0.40 0.10 48 47 12 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) please refer to http://www.linear.com/product/ltc3884#packaging for the most recent package drawings. downloaded from: http:///
lt c3884 121 3884fb for more information www.linear.com/ltc3884 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/15 added note 19. changed operation default value. 10 38, 73 b 2/16 corrected top mark. modified i in C switch circuitry. 4 17 downloaded from: http:///
lt c3884 122 3884fb for more information www.linear.com/ltc3884 ? linear technology corporation 2015 lt 0216 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3884 related parts typical application licensed under u.s. patent 7000125 and other related patents worldwide. part number description comments ltm4676a dual 13a or single 26a step-down dc/dc module regulator with digital power system management 4.5v v in 17v ; 0.5v v out ( 0.5%) 5.5v , i 2 c/pmbus interface, 16mm 16mm 5mm , bga package ltm4675 dual 9a or single 18a module regulator with digital power system management 4.5v v in 17v; 0.5v v out (0.5%) 5.5v, i 2 c/pmbus interface, 11.9mm 16mm 5mm, bga package ltm4677 dual 18a or single 36a module regulator with digital power system management 4.5v v in 16v; 0.5v v out (0.5%) 1.8v, i 2 c/pmbus interface, 16mm 16mm 5.01mm, bga package ltc3874 multiphase step-down synchronous slave controller with sub milliohm dcr sensing 4.5v v in 38v, v out up to 5.5v, very high output current, accurate current sharing, current mode applications ltc3887/ltc3887-1 dual output multiphase step-down dc/dc controller with digital power system management, 70ms start-up 4.5v v in 24v, 0.5v v out0,1 (0.5%) 5.5v, 70ms start-up, i 2 c/ pmbus interface, C1 version uses drmos or power blocks ltc3882/ltc3882-1 dual output multiphase step-down dc/dc voltage mode controller with digital power system management 3v v in 38v, 0.5v v out1,2 5.25v, (0.5%) v out accuracy i 2 c/ pmbus interface, uses drmos or power blocks ltc3886 60v dual output step-down controller with digital power system management 4.5v v in 60v, 0.5v v out0,1 (0.5%) 13.8v, 70ms start-up, i 2 c/ pmbus interface, input current sense ltc3815 6a monolithic synchronous dc/dc step-down converter with digital power system management 2.25v v in 5.5v, 0.4v v out 0.72v in , programmable v out range 25% with 0.1% resolution, up to 3mhz operation with 13-bit adc high efficiency, single-output, 1.2v/60a buck converter 10nf 150pf 11% 0.1f d1 q1 bsc050ne2ls 0.1f d2 q3 bsc010ne2lsi q2 bsc050ne2ls q4 bsc010ne2lsi 2m 270f16v x2 4.99k 10k 10k 10k 10k 10k 10k 10k l1 0.25h 715 1% 220nf 330f6.3v x2 100f6.3v x2 3.3nf 2.2f 1f 10nf 10fx2 4.7f l2 0.25h 7151% 220nf 330f 6.3v x2 100f 6.3v x2 20k 11k 24.9k 4.32k 30.1k 1.96k 10fx2 intv cc ltc3884 v in v dd33 v dd33 i in + i in C tg0 boost0 sw0 bg0 sync pgood0 pgood1 sda scl alert fault0 fault1 share_clk run0 run1 wp tsns0 i sense0 + i sense0 C v sense0 + v sense0 C i th0 i thr0 pgnd sgnd v dd25 v dd25 tg1 boost1 sw1 bg1 v out0 _cfg v out1 _cfg asel0 asel1 freq_cfg phase_cfg tsns1 i sense1 C i sense1 + v sense1 + v sense1 C i th1 i thr1 extv cc v in 4.5v to 14v 1f c3 v dd33 744301025 dcr=0.32m mmbt3906-al3-r mmbt3906-al3-r d1, d2: cmdsh3-tr 3884 ta10 744301025 dcr=0.32 m v dd25 v out 1.2v/60a downloaded from: http:///

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