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no. ea-054-160 701 12345 4-wire serial interface rx5c348a/b outline the rx5c348a/b are cmos real-time cl ock ics connected to the cpu by f our signal lines, ce, sclk, si, so, and configured to perform serial transmission of time and calendar data to the cpu. the periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. the 2 alarm interrupt circuits generate interrupt signals at preset times. as the oscillation circuit is driven under c onstant voltage, fluctuat ion of the oscillator frequency due to supply voltage is small, and the time keeping current is small (typ. 0.35 a at 3v: rx5c348a, typ.0.55 a at 3v : rx5c348b). the oscillation halt s ensing circuit can be used to judge the validity of inter nal data in such events as power-on; the supply voltage monitoring circuit is configured to record a drop in s upply voltage below two selectable supply voltage monitoring threshold settings. the 32.768khz clock output func tion (n-channel open drain output) is intended to output sub-clock pulses for the external microcomputer. the 32- khz clock circuit can be disabled by certain register s ettings for the rx5c348a but cannot be disabled by any register settings for the rx5c348b. the oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. these models come in an ultra-compact ssop10 (RS5C348A/b), ssop10g (rv5c348a/b), tssop10g (rt5c348b) package 32-khz clock output RS5C348A controllable by command rs5c348b ssop10 (pin pitch 0.5mm, height1.25mm, 6.4mm 3.5mm) keeping output enabled rv5c348a controllable by command rv5c348b ssop10g (pin pitch 0.5mm, height1.2mm, 4.0mm 2.9mm) keeping output enabled rt5c348b tssop10g (pin pitch 0.5mm, height0.85mm, 4.0mm 2.9mm) keeping output enabled features timekeeping supply voltage ranging from 1.45 to 5.5v low power consumption rx5c348a: 0.35 a typ (0.8 a max) at vdd=3v rx5c348b: 0.55 a typ (1.0 a max) at vdd=3v only four signal lines (ce, sclk, si, and so) required for connection to the cpu. maximum clock frequency of 2 mhz (with vdd = 5v) time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in bcd format) interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the cpu and provided with an interrupt flag and an interrupt halt 2 alarm interrupt circuits (alarm_w for week, hour , and minute alarm settings and alarm_d for hour and minute alarm settings) 32-khz clock output circuit (nch. open drain output) the rx5c348a is designed to disable 32-khz clock output in response to a command from the host computer and the rx5c348b is designed to keep 32-khz output enabled. oscillation halt sensing circuit which can be used to judge the validity of internal data supply voltage monitoring circuit with two supply voltage monitoring threshold settings automatic identification of leap years up to the year 2099 selectable 12-hour and 24-hour mode settings built-in oscillation stabilization capacitors (cg and cd) high precision oscillation adjustment circuit ultra-compact ssop10 (RS5C348A/b), ssop10g (rv5c348a/b), tssop10g (rt5c348b) cmos process 12345 - 1 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b pin configuration sclk so /intr vss vdd oscin ce 1 2 3 4 56 7 9 top view rx5c348a/b 32kout 10 8 si oscout block diagram 32khz output control osc comparator_d alarm_d register (min,hour) address decoder address register voltage detect div time counter (sec,min,hour,week,day,month,year) shift register i/o control 32kout interrupt control sclk divider correc -tion vdd vss comparator_w alarm_w register (min,hour, week) ce osc detect si /intr so oscin oscout 12345 - 2 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b pin description symbol item description ce chip enable input the ce pin is used for interfacing wi th the cpu. should be held high to allow access to the cpu. incorpor ates a pull-down resistor. should be held low or open when the cpu is powered off. allows a maximum input voltage of 5.5v regardless of supply voltage. sclk serial clock input the sclk pin is used to input cl ock pulses synchronizing the input and output of data to and from the si and so pins. allows a maximum input voltage of 5.5v regardless of supply voltage. si serial input the si pin is used to input data intended for writing in synchronization with the sclk pin. cmos input. allows a maximum input voltage of 5.5v regardless of supply voltage. so serial output the so pin is used to output data intended for reading in synchronization with the sclk pin. cmos output. /intr interrupt output the /intr pin is used to output alarm interrupt (alarm_w) and alarm interrupt (alarm_d) and output periodic interrupt signals to the cpu signals. disabled at power-on from 0v. n-channel open drain output. allows a maximum pull-up voltage of 5.5v regardless of supply voltage. 32kout 32khz clock output the 32kout pin is used to output 32. 768-khz clock pulses. enabled at power-on from 0 volts. nch. open drain output. the rx5c348a is designed to disable 32-khz clock output in response to a command from the host computer and the rx5c348b is des igned to keep 32-khz output enabled. oscin oscout oscillation circuit input / output the oscin and oscout pins are used to connect the 32.768-khz crystal oscillator (with all other oscillation circuit components built into the rx5c348a/b). vdd vss positive/negative power supply input the vdd pin is connected to the power supply. the vss pin is grounded. 12345 - 3 - part number is designated as follows: r v 5c348 a - e2 - f ? part number ? ? ? ? r a 5c348 b - cc - d codee description a designation of the package. s: ssop10 v: ssop10g t: tssop10g b designation of the function of 32-khz clock output. a: controllable by command b: keeping output enabled cc designation of the taping type. only e2 is available. d designation of the lead plating. f: lead free plating fb: sn-bi plating selection guide ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b absolute maximum ratings (vss=0v) symbol item pin name description unit vdd supply voltage 2 vdd -0.3 to +6.5 v vi input voltage ce, sclk, si -0.3 to +6.5 v output voltage 1 so -0.3 to vdd + 0.3 v vo output voltage 2 /intr, 32kout -0.3 to +6.5 v pd power dissipation topt = 25 c 300 mw topt operating temperature -40 to +85 c tstg storage temperature -55 to +125 c recommended operating conditions (vss=0v, topt=-40 to +85 c) symbol item pin name min. typ. max. unit vaccess supply voltage power supply voltage for interfacing with cpu 2.0 5.5 v vclk time keeping voltage 1.45 5.50 v fxt oscillation frequency 32.768 khz vpup pull-up voltage /intr, 32kout 5.5 v 12345 - 4 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b dc electrical characteristics (unless otherwise specified: vss=0v, vdd=3.0v, topt=-40 to +85 c, crystal oscillator 32768hz,cl=7pf,r1=30k ? ) symbol item pin name conditions min. typ. max. unit vih ?h? input voltage 0.8x vdd 5.5 vil ?l? input voltage ce, sclk, si vdd=2.0 to 5.5v -0.3 0.2x vdd v ioh ?h? output current so voh=vdd-0.5v -0.5 ma iol1 /intr, 32kout(rx5c348a ) 2.0 iol2 ?l? output current so, 32kout(rx5c348b ) vol=0.4v 0.5 ma iil input leakage current si, sclk vi=5.5v or vss vdd=5.5v -1.0 1.0 a rdnce pull-down resistance ce 40 120 400 k ? ioz1 so vo=5.5v or vss vdd=5.5v -1 1 ioz2 output off-state current /intr, 32kout vo=5.5v vdd=5.5v -1 1 a idd (rx5c34 8a) vdd vdd=3v, ce= open output = open 32kout=off *1) 0.35 0.80 idd (rx5c34 8b) time keeping current vdd vdd=3v, ce= open output = open 32kout=on 0.55 1.00 a vdeth supply voltage monitoring voltage ?h? vdd topt=-30 to +70 c 1.90 2.10 2.30 vdetl supply voltage monitoring voltage ?l? vdd topt=-30 to +70 c 1.45 1.60 1.80 v cg internal oscillation capacitance 1 oscin 12 cd internal oscillation capacitance 2 oscout 12 pf *1) for time keeping current when outputting 32. 768khz from the 32kout pin, see ?p.40. typical characteristics?. 12345 - 5 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b ac electrical characteristics unless otherwise specified: vss=0v,topt=-40 to +85 c input and output conditions: vih=0.8 vdd,vil=0.2 vdd,voh=0.8 vdd,vol=0.2 vdd,cl=50pf vdd 2.0v vdd 4.5v symbol item condi- tions min. typ. max. min. typ. max. unit t ces ce set-up time 400 200 ns t ceh ce hold time 400 200 ns t cr ce recovery time 62 62 s f sclk sclk clock frequency 1.0 2.0 m hz t ckh sclk clock high time 400 200 ns t ckl sclk clock low time 400 200 ns t cks sclk set-up time 200 100 ns t rd data output delay time 300 150 ns t rz data output floating time 300 150 ns t cez data output delay time after falling of ce 300 150 ns t ds input data set-up time 200 100 ns t dh input data hold time 200 100 ns sclk t ces si ce t rd t ckl t cez t ds t dh t rd t ceh t ckh t cks t cr t rz so *) for reading/writing timing, see ?p.28. adjustment of oscillation frequency?. 12345 - 6 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b package dimensions RS5C348A/b (ssop10) 10 6 1 m 5 4.4 0.2 6.4 0.2 0.5 0.2 0.9max 0.5 0 to 10 1.35max 0.1 0.1 0.1 0.1 0.2 0.1 0.15 +0.1 - 0 . 05 3.5 0.2 1.15 0.1 unit: mm rv5c348a/b (ssop10g) m 2.8 to 10 2.9 -0.1 5 10 1 +0.3 0.15 0.127 -0.05 4.0 0.1 +0.1 0.5 1.1 0.1 0.1 - 00 5 +0 1 6 0.55 12345 - 7 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b rt5c348b (tssop10g) m 2.80 0.2 0 to 10 2.9 0.2 5 10 1 0.15 0.13 -0.05 4.0 0. 2 0.1 0.2 0.1 +0.1 0.5 (0.75) 0.1 - 00 5 +0 1 6 0.55 0.2 0.85 0.15 unit: mm 12345 - 8 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b general description interface with cpu the rx5c348a/b is connected to the cpu by four signal lines ce (chip enable) , sclk (serial clock), si (serial input), and so (serial output), thr ough which it reads and writes data from and to the cpu. the cpu can be accessed when the ce pin is held high. access cl ock pulses have a maximum frequency of 1 mhz allowing high-speed data transfer to the cpu. clock and calendar function the rx5c348a/b reads and writes time data from and to t he cpu in units ranging from seconds to the last two digits of the calendar year . the calendar year will autom atically be identified as a leap year when its last two digits are a multiple of 4. consequently, leap years up to the year 2099 can automatically be identified as such. *) the year 2000 is a leap year while the year 2100 is not a leap year. alarm function the rx5c348a/b incorporates the alar m interrupt circuit configured to gener ate interrupt signals to the cpu at preset times. the alarm interrupt circuit allows two ty pes of alarm settings specifi ed by the alarm_w registers and the alarm_d registers. the alarm_w registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "monday, w ednesday, and friday" and "saturday and sunday". the alarm_d registers allow hour and minute al arm settings. the alarm_w outputs from /intr pin, and the alarm_d outputs also from /intr pin. each alarm function can be checked from the cpu by using a polling function. high-precision oscillation adjustment function the rx5c348a/b has built-in oscillation stabilization capacitors (cg and cd), which can be connected to an external crystal oscillator to configure an oscillation circ uit. to correct deviations in the oscillator frequency of the crystal, the oscillation adjustment ci rcuit is configured to allow correction of a time count gain or loss (up to 1.5ppm at 25 c) from the cpu. the maximum range is approximately 189ppm in increments of approximately 3ppm. such oscillation frequency adjustment in each system has the following advantages: * allows timekeeping with much higher precision t han conventional rtcs while using a crystal oscillator with a wide range of precision variations. * corrects seasonal frequency deviations through seasonal oscillation adjustment. * allows timekeeping with higher precision particular ly with a temperature sensing function out of rtc, through oscillation adjustment in tune with temperature fluctuations. power-on reset, oscillation halt sensing function and supply voltage monitoring function the rx5c348a/b incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt. power on reset function reset the control resisters when t he system is powered on from 0v. at the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are pow ered on from 0v or battery backed-up. the rx5c348a/b also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. supply voltage-monitoring threshold settings can be selected between 2.1v and 1.6v th rough internal register settings. the sampling rate is normally 1s. the oscillation halt sensing circuit and the power-on re set flag are configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. further, the supply voltage m onitoring circuit can be applied to battery supply voltage monitoring. periodic interrupt function the rx5c348a/b incorporates the per iodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm interr upt circuit for output from the /intr pin. periodic interrupt signals have five selectable frequency settings of 2 hz (once per 0.5 seconds), 1 hz (once per 1 second), 1/60 hz (once per 1 minute), 1/3600 hz (once per 1 hour), and monthly (the first day of every month). further, periodic interrupt signals also have two selectabl e waveforms, a normal pulse form (with a frequency of 2 hz or 1 hz) and special form adapted to interruption from the cpu in the level mode (with second, minute, hour, and month interrupts). the condition of periodic interrupt signals can be monitored with using a polling function. 32khz clock output the rx5c348a/b incorporates a 32-khz clock circuit c onfigured to generate clock pulses with the oscillation 12345 - 9 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b frequency of a 32.768khz crystal oscillator for output fr om the 32kout pin. the 32-khz clock output can be disabled by certain register settings but cannot be dis abled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the cpu. the pin is n-channel open drain output. 12345 - 10 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b address mapping address reg ister name d a t a a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 second counter - *2) s40 s20 s10 s8 s4 s2 s1 1 0 0 0 1 minute counter - m40 m20 m10 m8 m4 m2 m1 2 0 0 1 0 hour counter - - h20 p ? /a h10 h8 h4 h2 h1 3 0 0 1 1 day-of-week counter - - - - - w4 w2 w1 4 0 1 0 0 day-of-month counter - - d20 d10 d8 d4 d2 d1 5 0 1 0 1 month counter and century bit /19 ? 20 - - mo10 mo8 mo4 mo2 mo1 6 0 1 1 0 year counter y80 y40 y20 y10 y8 y4 y2 y1 7 0 1 1 1 oscillation adjustment register *3) (0) *4) f6 f5 f4 f3 f2 f1 f0 8 1 0 0 0 alarm_w (minute register) - wm40 wm20 wm10 wm8 wm4 wm2 wm1 9 1 0 0 1 alarm_w (hour register) - - wh20 wp ? / a wh10 wh8 wh4 wh2 wh1 a 1 0 1 0 alarm_w (day-of-week register) - ww6 ww5 ww4 ww3 ww2 ww1 ww0 b 1 0 1 1 alarm_d (minute register) - dm40 dm20 dm10 dm8 dm4 dm2 dm1 c 1 1 0 0 alarm_d (hour register) - - dh20 dp ? /a dh10 dh8 dh4 dh2 dh1 d 1 1 0 1 - - - - - - - - e 1 1 1 0 control register 1 *3) wale dale /12 ? 24 /clen2 *5) test ct2 ct1 ct0 f 1 1 1 1 control register 2 *3) vdsl vdet scra tch1 xstp /clen1 *5) ctfg wafg dafg notes: * 1) all the data listed above a ccept both reading and writing. * 2) the data marked with "-" is invalid for writing and reset to 0 for reading. * 3) when the xstp bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register, control register 1 and control register 2 excluding the xstp bit. * 4) writing to the oscillation adjustm ent register requires filling the (0) bit. * 5) these bit names apply to the rx5c348a. for the rx5c348b the bit names are scratch2 and scratch3. 12345 - 11 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b register settings control register 1 (address eh) d7 d6 d5 d4 d3 d2 d1 d0 wale dale /12 ? 24 /clen2 *2) test ct2 ct1 ct0 (for writing) wale dale /12 ? 24 /clen2 *2) test ct2 ct1 ct0 (for reading) 0 0 0 0 0 0 0 0 default settings *1) *1) default settings: default value means read / wr itten values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping *2) this bit name applies to the rx5c348a only. for the rx5c348b the bit name is scratch3.. (1) wale, dale alarm_w enable bit, alarm_d enable bit wale,dale description 0 disabling the alarm interrupt circui t (under the control of the settings of the alarm_w registers and the alarm_d registers). (default) 1 enabling the alarm interrupt circui t (under the control of the settings of the alarm_w registers and the alarm_d registers) (2) /12 ? 24 /12-24-hour mode selection bit /12 ? 24 description 0 selecting the 12-hour mode with a. m. and p.m. indications. (default) 1 selecting the 24-hour mode setting the /12 ? 24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. 24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) setting the /12 ? 24 bit should precede writing time data (3) /clen2 (rx5c348a) 32khz clock output bit 2 /clen2 description 0 enabling the 32-khz clock circuit (default) 1 disabling the 32-khz clock circuit setting the /clen2 bit or the /clen1 bit (d3 in the cont rol register 2) to 0, s pecifies generating clock pulses with the oscillation frequency of the 32.768-khz crys tal oscillator for output from the 32kout pin. conversely, setting both the /clen1 and /clen2 bit to 1 disabling (?h?) such output. scratch3 (rx5c348b) scratch bit 3 scratch3 description 0 (default) 1 for the rx5c348b, this bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch3 bit will be set to 0 when the xstp bit is set to 1 in control register 2. 12345 - 12 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b (4) test test bit test description 0 normal operation mode. (default) 1 test mode. the test bit is used only for testing in the factory and should normally be set to 0. (5) ct2, ct1, and ct0 periodic interrupt selection bits description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ?l? 0 1 0 pulse mode *1) 2hz (duty50%) 0 1 1 pulse mode *1) 1hz (duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) * 1) pulse mode: 2-hz and 1-hz clock pulses are out put in synchronization with the increment of the second counter as illustrated in the timing chart below. /intr pin rewriting of the second counter ctfg bit a pprox. 92 s (increment of second counter) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time r eadings immediately after the falling edge of clock pulses may appear to lag behind the time counts of t he real-time clocks by appr oximately 1 second. rewriting the second counter will reset the other time counters of less t han 1 second, driving the /intr pin low. * 2) level mode: periodic interrupt signals are output with selectable inte rrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of t he second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below. 12345 - 13 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b setting ctfg bit to 0 ctfg bit /intr pin (increment of second counter) (increment of second counter) (increment of second counter) setting ctfg bit to 0 *1), *2) when the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or 60sec. as follows: pulse mode: the ?l? period of output pulses w ill increment or decrement by a maximum of 3.784 ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 sec ond will increment or decrement by a maximum of 3.784 ms. control register 2 (address fh) d7 d6 d5 d4 d3 d2 d1 d0 vdsl vdet scra tch1 xstp /clen1 ctfg wafg dafg (for writing) vdsl vdet scra tch1 xstp /clen1 ctfg wafg dafg (for reading) 0 0 0 1 0 0 0 0 default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping (1) vdsl vdd supply voltage monitoring threshold selection bit vdsl description 0 selecting the vdd supply voltage monitoring threshold setting of 2.1v. (default) 1 selecting the vdd supply voltage monitoring threshold setting of 1.6v. the vdsl bit is intended to select the v dd supply voltage monitoring threshold settings. (2) vdet supply voltage monitoring result indication bit vdet description 0 indicating supply voltage above the supply voltage monitoring threshold settings. (default) 1 indicating supply voltage below the supply voltage monitoring threshold settings. once the vdet bit is set to 1, the supply voltage m onitoring circuit will be disabled while the vdet bit will hold the setting of 1. the vdet bit accepts only t he writing of 0, which restarts the supply voltage monitoring circuit. conversely, setting the vdet bit to 1 causes no event. (3) scratch1 scratch bit 1 scratch1 description 0 (default) 1 this bit is intended for scratching and accepts the r eading and writing of 0 and 1. the scratch1 bit will be set to 0 when the xstp bit is set to 1 in control register 2. (4) xstp oscillation halt sensing bit xstp description 0 sensing a normal condition of oscillation 1 sensing a halt of oscillation (default) the xstp bit is for sensing a halt in the oscillation of t he crystal oscillator. oscillation halt sensing circuit operates only when ce pin is low. * the xstp bit will be set to 1 once a halt in the oscillati on of the crystal oscillator is caused by such events as power-on from 0 volts and a drop in supply voltage. the xstp bit will hold the setting of 1 even af ter the 12345 - 14 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b restart of oscillation. as such, the xstp bit can be applied to judge the validity of clock and calendar data after power-on or a drop in supply voltage. * when the xstp bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1, and control register 2, stopping the output from /intr pi n and starting the output of 32.768-khz clock pulses from the 32kout pin. * the xstp bit accepts only the writing of 0, which rest arts the oscillation halt sensing circuit. conversely, setting the xstp bit to 1 causes no event. * it is recommendable to frequently check the xstp bi t for setting errors or data garbles, which may seriously affect the operat ion of the rx5c348a/b. 12345 - 15 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b (5) /clen1 32khz clock output bit 1 (rx5c348a) /clen1 description 0 enabling the 32-khz clock circuit (default) 1 disabling the 32-khz clock circuit setting the /clen1 bit or the /clen2 bit (d4 in the cont rol register 1) to 0, s pecifies generating clock pulses with the oscillation frequency of the 32.768-khz crys tal oscillator for output from the 32kout pin. conversely, setting both the /clen1 and /clen2 bit to 1 disabling (?h?) such output. scratch2 (rx5c348b) scratch bit 2 scratch2 description 0 (default) 1 for the rx5c348b, this bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch3 bit will be set to 0 when the xstp bit is set to 1 in control register 2. (6) ctfg periodic interrupt flag bit ctfg description 0 periodic interrupt output = ?h? (default) 1 periodic interrupt output = ?l? the ctfg bit is set to 1 when the periodic interrupt signals are output from the /intr pin (?l?). the ctfg bit accepts only the writing of 0 in the level mode, which disables (?h?) the /intr pin until it is enabled (?l?) again in the next interrupt cycle. conversely , setting the ctfg bit to 1 causes no event. (7) wafg,dafg alarm_w flag bit and alarm_d flag bit wafg,dafg description 0 indicating a mismatch between current time and preset alarm time (default) 1 indicating a match between current time and preset alarm time the wafg and dafg bits are valid only when the wale and dale have the setting of 1, which is caused approximately 61 s after any match between current time and pres et alarm time specified by the alarm_w registers and the alarm_d registers. the wafg (daf g) bit accepts only the writing of 0. /intr pin outputs off (?h?) when this bit is set to 0. and /intr pin outputs ?l? again at the next preset alarm time. conversely, setting the wafg and dafg bits to 1 causes no event. the wafg and dafg bits will have the reading of 0 when the alarm interrupt circuit is di sabled with the wale and dale bits set to 0. the settings of the wafg and dafg bits are synchronized with the output of the /intr pin as shown in the timing chart below. /intr pin writing of 0 to wafg(dafg) bit wafg(dafg) bit (match between current time and preset alarm time) a pprox. 61 s a pprox. 61 s writing of 0 to wafg(dafg) bit (match between current time and preset alarm time) (match between current time and preset alarm time) 12345 - 16 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b time counter (address 0-2h) second counter (address 0h) d7 d6 d5 d4 d3 d2 d1 d0 - s40 s20 s10 s8 s4 s2 s1 (for writing) 0 s40 s20 s10 s8 s4 s2 s1 (for reading) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) minute counter (address 1h) d7 d6 d5 d4 d3 d2 d1 d0 - m40 m20 m10 m8 m4 m2 m1 (for writing) 0 m40 m20 m10 m8 m4 m2 m1 (for reading) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) hour counter (address 2h) d7 d6 d5 d4 d3 d2 d1 d0 - - p ? /a or h20 h10 h8 h4 h2 h1 (for writing) 0 0 p ? /a or h20 h10 h8 h4 h2 h1 (for reading) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping * time digit display (bcd format) as follows: the second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. the minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. the hour digit s range as shown in "p12 control register 1 (address eh) (2) /12 ? 24: /12-24-hour mode selection bit" and are carried to the day-of-m onth and day-of-week digits in transition from pm11 to am12 or from 23 to 00. * any writing to the second counter resets divider units of less than 1 second. * any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. therefore, such inco rrect writing should be replaced with the writing of existent time data. day-of-week counter (address 3h) d7 d6 d5 d4 d3 d2 d1 d0 - - - - - w4 w2 w1 (for writing) 0 0 0 0 0 w4 w2 w1 (for reading) 0 0 0 0 0 indefinite indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping * the day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. * day-of-week display (incremented in septimal not ation): (w4, w2, w1) = (0, 0, 0) (0, 0, 1) ? (1, 1, 0) (0, 0, 0) * correspondences between days of the week and t he day-of-week digits are user-definable (e.g. sunday = 0, 0, 0) * the writing of (1, 1, 1) to (w4, w2, w1) is prohibited except when days of the week are unused. 12345 - 17 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b calendar counter (address 4-6h) day-of-month counter (address 4h) d7 d6 d5 d4 d3 d2 d1 d0 - - d20 d10 d8 d4 d2 d1 (for writing) 0 0 d20 d10 d8 d4 d2 d1 (for reading) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) month counter + century bit (address 5h) d7 d6 d5 d4 d3 d2 d1 d0 /19 ? 20 - - mo10 mo8 mo4 mo2 mo1 (for writing) /19 ? 20 0 0 mo10 mo8 mo4 mo2 mo1 (for reading) indefinite 0 0 indefinite indefinite indefinite indefinite indefinite default settings *) year counter (address 6h) d7 d6 d5 d4 d3 d2 d1 d0 y80 y40 y20 y10 y8 y4 y2 y1 (for writing) y80 y40 y20 y10 y8 y4 y2 y1 (for reading) indefinite indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping * the calendar counters are configured to display t he calendar digits in bcd format by using the automatic calendar function as follows: the day-of-month digits (d20 to d1) range from 1 to 31 for january, march, may, july, august, october, and december; from 1 to 30 for april, june, september, and november; from 1 to 29 for february in leap years; from 1 to 28 for february in ordinary years. the day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. the month digits (mo10 to mo1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. the year digits (y80 to y1) range from 00 to 99 (00, 04, 08, , 92, and 96 in leap years) and are carried to the /19 ? 20 digits in reversion from 99 to 00. the /19 ? 20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. * any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. therefore, such incorre ct writing should be replaced with the writing of existent calendar data. oscillation adjustment register (address 7h) d7 d6 d5 d4 d3 d2 d1 d0 (0) f6 f5 f4 f3 f2 f1 f0 (for writing) (0) f6 f5 f4 f3 f2 f1 f0 (for reading) 0 0 0 0 0 0 0 0 default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping (0) bit the (0) bit should be set to 0 to allow writing to the oscillation adjustment register. the (0) bit will be set to 0 when the xstp bit is set to 1 in the control register 2. f6 to f0 bits the oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register w hen the second digit s read 00, 20, or 40 seconds. normally, the second counter is incremented onc e per 32768 32.768-khz clock pulses generated by the crystal oscillator. writing to the f6 to f0 bits activates the oscillation adjustment circuit. * the oscillation adjustment circuit will not operate wi th the same timing (00, 20, or 40 seconds) as the timing of writing to the oscillation adjustment register. * the f6 bit setting of 0 causes an increment of time counts by ((f5, f4, f3, f2, f1, f0) - 1) x 2. the f6 bit setting of 1 causes a decrement of time count s by ((/f5, /f4, /f3, /f2, /f1, /f0) + 1) x 2. the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the f6, f5, f4, f3, f2, f1, and f0 bits 12345 - 18 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b cause neither an increment nor decrement of time counts. example: when the second digits read 00, 20, or 40, the settings of "0 , 0, 0, 0, 1, 1, 1" in the f6, f5, f4, f3, f2, f1, and f0 bits cause an increment of the current time count s of 32768 by (7 - 1) x 2 to 32780 (a current time count loss). when the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 0, 0, 1" in the f6, f5, f4, f3, f2, f1, and f0 bits cause neither an increment nor a decrement of the current time counts of 32768. when the second digits read 00, 20, or 40, the settings of "1 , 1, 1, 1, 1, 1, 0" in the f6, f5, f4, f3, f2, f1, and f0 bits cause a decrement of the current time counts of 32768 by (- 2) x 2 to 32764 (a current time count gain). an increase of two clock pulses once per 20 seconds c auses a time count loss of approximately 3 ppm (2 / (32768 x 20 = 3.051 ppm). conversely, a decrease of tw o clock pulses once per 20 seconds causes a time count gain of 3 ppm. consequently, deviations in ti me count s can be corrected with a precision of 1.5 ppm. note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-khz clock pulses. for further details, see "p.30 oscillation adjustment circuit". alarm_w registers (address 8-ah) alarm_w minute register (address 8h) d7 d6 d5 d4 d3 d2 d1 d0 - wm40 wm20 wm10 wm8 wm4 wm2 wm1 (for writing) 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 (for reading) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) alarm_w hour register (address 9h) d7 d6 d5 d4 d3 d2 d1 d0 - - wh20 wp ? /a wh10 wh8 wh4 wh2 wh1 (for writing) 0 0 wh20 wp ? /a wh10 wh8 wh4 wh2 wh1 (for reading) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) alarm_w day-of-week register (address ah) d7 d6 d5 d4 d3 d2 d1 d0 - ww6 ww5 ww4 ww3 ww2 ww1 ww0 (for wr iting) 0 ww6 ww5 ww4 ww3 ww2 ww1 ww0 (for reading) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping * the d5 bit of the alarm_w hour register repr esents wp/a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and wh20 when the 24-hour mode is selected (tens in the hour digits). * the alarm_w registers should not have any non-existent alarm time settings. (note that any mismatch between current time and preset alarm time specified by the alarm_w registers may disable the alarm interrupt circuit.) * when the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively. (see "p12 control register 1 (address eh) (2) /12 ? 24: 12-/24-hour mode selection bit") * ww0 to ww6 correspond to w4, w2, and w1 of t he day-of-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). * ww0 to ww6 with respective settings of 0 disable the outputs of t he alarm_w registers. 12345 - 19 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b example of alarm time setting alarm day-of-week 12-hour mode 24-hour mode preset alarm time sun. mon. tue. wed. th. fri. sat. 10 hr. 1 hr. 10 min. 1 min. 10 hr. 1 hr. 10 min. 1 min. ww0 ww1 ww2 ww3 ww4 ww5 ww6 00:00 a.m. on all days 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 a.m. on all days 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 a.m. on all days 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 p.m. on mon. to fri. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 01:30 p.m. on sun. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 p.m. on mon. ,wed., and fri. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 note that the correspondence between ww0 to ww6 and the days of the week shown in the above table is only an example and not mandatory. alarm_d register (address b-ch) alarm_d minute register (address bh) d7 d6 d5 d4 d3 d2 d1 d0 - dm40 dm20 dm10 dm8 dm4 dm2 dm1 (for writing) 0 dm40 dm20 dm10 dm8 dm4 dm2 dm1 (for reading) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) alarm_d hour register (address ch) d7 d6 d5 d4 d3 d2 d1 d0 - - dh20 dp ? /a dh10 dh8 dh4 dh2 dh1 (for writing) 0 0 dh20 dp ? /a dh10 dh8 dh4 dh2 dh1 (for reading) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the xstp bit is set to ?1? due to vdd power-on from 0v or oscillation stopping * the d5 bit represents dp/a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and dh20 when the 24-hour mode is selected (tens in the hour digits). * the alarm_d registers should not have any non-existent alarm time settings. (note that any mismatch between current time and preset alarm time specified by the alarm_d registers may disable the alarm interrupt circuit.) * when the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (see "p12 control register 1 (address eh) (2) /12 ? 24: 12-/24-hour mode selection bit") 12345 - 20 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b interfacing with the cpu data transfer formats (1) timing between ce pin transition and data input / output the rx5c348a/b adopts a 4-wire serial in terface by which they use the ce (chip enable), sclk (serial clock), si (serial input), and so (serial out put) pins to receive and send data to and from the cpu. the 4-wire serial interface provides two types of i nput/output timings with which the so pin output and the si pin input are synchronized with the rising or falling edges of the sc lk pin input, respectively, and vice versa. the rx5c348a/b is configured to select either one of two different input/out put timings depending on the level of the sclk pin in the low to high transition of the ce pin. namely, when the sclk pin is held low in the low to high transition of the ce pin, the models w ill select the timing with which the so pin output is synchronized with the rising edge of the sclk pin input, and the si pin input is synchronized with the falling edge of the sclk pin input, as illustrated in the timing chart below. sclk so t ds si ce t ces t dh t rd conversely, when the sclk pin is held high in the low to high transition of the ce pin, the models will select the timing with which the so pin output is synchronized wi th the falling edge of the sclk pin input, and the si pin input is synchronized with the rising edge of the sclk pin input, as illustrated in the timing chart below. sclk so t ds si ce t ces t dh t rd (2) data transfer formats data transfer is commenced in the low to high transition of the ce pin input and completed in its high to low transition. data transfer is conducted serially in multiple units of 1 byte (8 bits). the former 4 bits are used to specify in the address pointer a head address with whic h data transfer is to be commenced from the host. the latter 4 bits are used to select either reading data transfe r or writing data transfer, and to set the transfer format register to specify an appropriate dat a transfer format. all data transfer formats are designed to transfer the most significant bit (msb) first. a2 ce scl k so 6 a1 a0 c3 c2 c1 c0 d7 d6 d3 d2 d1 d0 a3 7 582 3 1 23 1 4 d7 d6 d3 d2 d1 d0 reading data transfer setting the address pointe r writing data transfer setting the transfer format register si two types of data transfer formats are available fo r reading data transfer and writing data transfer each. 12345 - 21 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b writing data transfer formats (1) 1-byte writing data transfer format the first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with wh ich writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. this 1-byte writing data transfer can be completed by driving the ce pin low or conti nued by specifying a new head address in the address pointer and setting the data transfer format. 1 1 data data example of 1-byte writing data transfer (for writing data to addresses fh and 7h) data transfer from the host ce data transfer from the rtcs so specifying 7h in the a ddress pointer 0 1 0 0 1 1 setting 8h in the transfer format register writing data to address fh writing data to address 7h 0 1 1 0 0 0 1 1 specifying fh in the a ddress pointer setting 8h in the transfer format register si (2) burst writing data transfer format the second type of writing data transfer format is des igned to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the tr ansfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst writing data transfer can be completed by driving the ce pin low. 1 0 data data example of burst writing data transfer (for writing data to addresses eh, fh, and 0h) ce so 0 0 0 0 1 1 si data data transfer from the host data transfer from the rtcs writing data to address eh specifying eh in the a ddress pointer setting 0h in the transfer format register writing data to address fh writing data to address 0h 12345 - 22 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b reading data transfer formats (1) 1-byte reading data transfer format the first type of reading dat a transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then the setting of writing ch to the trans fer format register. this 1-byte reading data transfer can be completed by driving the ce pin low or continued by specifying a new head address in the address pointer and selecting this type of reading data transfer format. 1 0 data data example of 1-byte reading data transfer (for reading data from addresses eh and 2h) ce so 1 1 0 0 1 1 0 1 0 1 0 0 0 1 si data transfer from the host data transfer from the rtcs specifying 2h in the a ddress pointer setting ch in the transfer format register reading data from address eh reading data from address 2h specifying eh in the a ddress pointer setting ch in the transfer format register (2) burst reading data transfer format the second type of reading data transfer format is des igned to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the tr ansfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst reading data transfer can be completed by driving the ce pin low. 1 1 data data example of burst reading data transfer (for reading data from addresses fh, 0h, and 1h) ce so 1 0 0 0 1 1 data si data transfer from the host data transfer from the rtcs reading data from address fh specifying fh in the a ddress pointer setting 4h in the transfer format register reading data from address 0h reading data from address 1h 12345 - 23 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b (3) combination of 1-byte reading and writing data transfer formats the 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format. 1 1 data example of reading modify writing data transfer (for reading and writing data from and to address fh) ce so 1 1 0 0 1 1 1 1 1 0 0 0 1 1 data si data transfer from the host data transfer from the rtcs writing data to address fh specifying fh in the a ddress pointer setting 8h in the transfer format register specifying fh in the a ddress pointer setting ch in the transfer format register reading data from address fh the reading and writing data transfer formats correspond to t he settings in the transfer format register as shown in the table below. 1 byte burst writing data transfer 8h (1,0,0,0) 0h (0,0,0,0) reading data transfer ch (1,1,0,0) 4h (0,1,0,0) 12345 - 24 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b considerations in reading and writing time data under special condition any carry to the second digits in the process of r eading or writing time data may cause reading or writing erroneous time data. for example, suppose a carry out of 13:59:59 into 14:00:00 o ccurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. at this moment, the second digits, the minute digits, and the hour digits read 59 se conds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. a similar error also occurs in writing time data. to prevent such errors in reading and writing time data, the rx5c348a/b has the function of temporarily locking any carry to the second digits during the high interval of the ce pin and unlocking such a carry in its high to low transition. note that a carry to the second digits can be locked for only 1 second, during which time the ce pin should be driven low. ce time counts within rtc 14:00:01 actual time 13:59:59 max.62 s 14:00:00 13:59:59 14:00:00 14:00:01 the effective use of this function requires the follo wing considerations in reading and writing time data: (1) hold the ce pin high in each session of reading or writing time data. (2) ensure that the high interval of the ce pin lasts within 1 second. s hould there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the ce pin low or open at the mom ent that the host actually goes down. (3) leave a time span of 31 s or more from the low to high transition of the ce pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the ti me digits may be completed within this time span. (4) leave a time span of 62 s or more from the high to low transition of the ce pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of t he ce pin may be adjusted within this time span. the considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits. (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). good and bad examples of reading and writing time data are illustrated on the next page. 12345 - 25 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b so 0ch data data bad example (1) (where the ce pin is once driven low in the process of reading time data) less than 62 s so f0h ce time span of less than 31 s writing to a ddress 0h (sec.) 0ch ce bad example (3) (where a time span of less than 61 s is left between the adjacent processes of reading time data) good example so data f4h data data ce a ddress pointer = 1h transfer format register = 4h time span of 31 s or more reading from a ddress 1h (min.) data so 0ch data data 31 s or more reading from a ddress 1h (min.) data 14h 31 s or more ce data transfer from rtcs 0ch data data transfer from the host bad example (2) (where a time span of less than 31 s is left until the start of the process of writing time data) a ny address other than addresses 0h to 6h permits of immediate reading or writing without requiring a time span of 31 s. si si si si data data data data reading from a ddress fh (control2) reading from a ddress 0h (sec.) reading from a ddress 2h (hr.) a ddress pointer = fh transfer format register = 4h a ddress pointer = fh transfer format register = 0h reading from a ddress 0h (sec.) reading from a ddress 2h (hr.) a ddress pointer = 0h transfer format register = ch writing to a ddress 1h (min.) writing to a ddress 2h (hr.) writing to a ddress fh (contorl2) a ddress pointer = 0h transfer format register = ch reading from a ddress 0h (sec.) reading from a ddress 0h (sec.) a ddress pointer = 0h transfer format register = ch 12345 - 26 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b configuration of oscillation circuit and correction of time count deviations configuration of oscillation circuit oscin oscout vdd vdd 32khz rd rf cg cd a typical externally-equipped element x?tal : 32.768khz (r1=30k ? typ) (cl=6pf to 8pf) standard values of internal elements rf 15m ? typ rd 120k ? typ cg,cd 12pf typ the oscillation circuit is driven at a constant voltage of approximately 1.2v relative to the level of the vss pin input. as such, it is configured to generate an oscilla ting waveform with a peak-to-peak volt age on the order of 1.2v on the positive side of the vss pin input. < considerations in handling crystal oscillators > generally, crystal oscillators have basic characteristics including an equivalent series resistance (r1) indicating the ease of their oscillation and a load capacitance (c l) indicating the degree of their center frequency. particularly, crystal oscillators intended for use in t he rx5c348a/b are recommended to have a typical r1 value of 30k ? and a typical cl value of 6 to 8pf. to confir m these recommended values, contact the manufacturers of crystal oscillators intended for use in these particular models. < considerations in installing components around the oscillation circuit > 1) install the crystal oscillator in the closest possible vicinity to the real-time clock ics. 2) avoid laying any signal lines or power lines in the vici nity of the oscillation circuit (p articularly in the area marked "a" in the above figure). 3) apply the highest possible insulation resistance betw een the oscin and oscout pins and the printed circuit board. 4) avoid using any long parallel lines to wire the oscin and oscout pins. 5) take extreme care not to cause condensation, which leads to various problems such as oscillation halt. < other relevant considerations > 1) for external input of 32.768-khz clock pulses to the oscin pin: dc coupling: prohibited due to an input level mismatch. ac coupling: permissible except that the oscillati on halt sensing circuit does not guarantee perfect operation because it may cause sensing errors due to such factors as noise. 2) to maint ain stable characteristics of the crystal o scillator, avoid driving any ot her ic through 32.768-khz clock pulses output from the oscout pin. 12345 - 27 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b measurement of oscillation frequency frequency counter oscin oscout 32kout vss 32768hz vdd * 1) the rx5c348a/b is configured to generate 32.768-kh z clock pulses for output from the 32kout pin. * 2) a frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscilla tion frequency of the oscillation circuit. adjustment of oscillation frequency the oscillation frequency of the oscillation circuit c an be adjusted by varying procedures depending on the usage of model rx5c348a/b in the system into which they are to be built and on the allowable degree of time count errors. the flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system. start course (b) use 32-khz clock output without regard to its frequency precision no yes use 32-khz clock output? yes no course (c) course (a) course (d) yes yes no no a llowable time count precision on order of osc illation frequency variations of crystal osc illator (*1) plus frequency variations of rtc (*2)? (*3) a llowable time count precision on order of osc illation frequency variations of crystal osc illator (*1) plus frequency variations of rtc (*2)? (*3) * 1) generally, crystal oscillators for commercial us e are classified in terms of their center frequency depending on their load capacitance (cl) and furt her divided into ranks on the order of 10, 20, and 50ppm depending on the degree of their oscillation frequency variations. * 2) basically, model rx5c348a/b is configured to cause frequency variations on the order of 5 to 10ppm at 25 c. * 3) time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics and other properties of crystal oscillators. 12345 - 28 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b course (a) when the time count precision of each rtc is not to be adjusted, the crystal oscillator intended for use in that rtc may have any cl value requiring no presetting. the crystal oscillator may be subject to frequency variations which are selectable within the allowable range of time count precision. several crystal oscillators and rtcs should be used to find the center frequency of the cr ystal oscillators by the method described in "p.28 adjustment of oscillation frequency" and then calculat e an appropriate oscillation adjustment value by the method described in "p.30 oscillation adjustment circuit" for wr iting this value to the rx5c348a/b. course (b) when the time count precision of each rtc is to be adj usted within the oscillation frequency variations of the crystal oscillator plus the frequency variations of the r eal-time clock ics, it becom es necessary to correct deviations in the time count of each rtc by the method described in " p .30 oscillation adjustment circuit". such oscillation adjustment provides crystal oscillators wi th a wider range of allowable settings of their oscillation frequency variations and their cl values. the real-time clock ic and the crystal oscillator intended for use in that real-time clock ic should be used to find the c enter frequency of the crystal oscillator by the method described in " p28 measurement of oscillation frequency " and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. at normal temperatur e, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately 0.5ppm. course (c) course (c) together with course (d) requires adjusting the time count precision of each rtc as well as the frequency of 32.768-khz clock pulses output from the 32kout pin. normally, the oscillation frequency of the crystal oscillator intended for use in the rtcs shoul d be adjusted by adjusting the oscillation stabilizing capacitors cg and cd connected to both ends of the crysta l oscillator. the rx5c348a/b, which incorporate the cg and the cd, require adjusting the oscillation frequency of the crystal oscillator through its cl value. generally, the relationship between the cl value and t he cg and cd values can be represented by the following equation: cl = (cg cd)/(cg + cd) + cs where "cs" represents the fl oating capacity of the printed circuit board. the crystal oscillator intended for use in the rx5c348a/b is recommended to have the cl value on the order of 6 to 9pf. its oscillation frequency should be measured by the method described in " p.28 measurement of oscillation frequency ". any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater cl value, respectively until another one having an optimum cl value is selected. in this case, the bit settings disabling the oscillation adjustment circuit (see " p.30 oscillation adjustment circuit") should be written to the oscillation adjustment register. incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor cgout as illustrated in the diagram below. 32khz rd cg cd oscin oscout cgout oscillator circuit *1) the cgout should have a capacitance ranging from 0 to 15 pf. course (d) it is necessary to select the crystal oscillator in the same manner as in course (c) as well as correct errors in the time count of each rtc in the same manner as in course (b) by the method described in " p.30 oscillation adjustment circuit ". 12345 - 29 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b oscillation adjustment circuit the oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds . the oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the f6, f5, f4, f3, f2, f1, and f0 bits in the oscillation adjustment circuit. conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit. (1) when oscillation frequency (* 1) is higher than ta rget frequency (* 2) (causing time count gain) oscillation adjustment value (*3) = (oscillation frequency - target frequency + 0.1) oscillation frequency 3.051 10 -6 (oscillation frequency ? target frequency) 10 + 1 * 1) oscillation frequency: frequency of clock pulse output from the 32k out pin at normal temperature in the manner described in " p.28 measurement of oscillation frequency ". * 2) target frequency: desired frequency to be set. generally, a 32.768-khz crystal oscillator has such temperature characteristics as to have the highest oscillati on frequency at normal temperature. consequently, the crystal oscillator is recommended to have ta rget frequency settings on the order of 32.768 to 32.76810 khz (+3.05ppm relative to 32.768 khz). note that the target frequency differs depending on the environment or location where the equipment incorporating the rtc is expected to be operated. * 3) oscillation adjustment value: value that is to be finally written to the f0 to f6 bits in the oscillation adjustment register and is represented in 7-bit coded decimal notation. (2) when oscillation frequency is equal to target frequency (causing time count neither gain nor loss) oscillation adjustment value = 0, +1, -64, or ?63 (3) when oscillation frequency is lower than ta rget frequency (causing time count loss) oscillation adjustment value = (oscillation frequency - target frequency) oscillation frequency 3.051 10 -6 (oscillation frequency ? target frequency) 10 oscillation adjustment value calculations are exemplified below (a) for an oscillation frequency = 32768.85hz and a target frequency = 32768.05hz oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 3.051 10 -6 ) (32768.85 - 32768.05) 10 + 1 = 9.001 9 in this instance, write the settings ((0),f6,f5,f4,f3,f2 ,f1,f0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. thus, an appropriate oscillation adjustment val ue in the presence of any time count gain represents a distance from 01h. (b) for an oscillation frequency = 32762.22hz and a target frequency = 32768.05hz oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 3.051 10 -6 ) (32762.22 - 32768.05) 10 = -58.325 -58 to represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3ah) from 128 (80h) to obtain 46h. in this instance, write the settings of ((0),f6,f5,f4,f3,f2,f1,f0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. thus, an appropriate osc illation adjustment value in the presence of any time count loss represents a distance from 80h. 12345 - 30 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b notes: 1) oscillation adjustment does not affect the fr equency of 32.768-khz clock pulses output from the 32kout pin. 2) if following 3 conditions are completed, actual cl ock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. using oscillator adjustment function 2. access to rx5c348a/b at random , or synchronized with external clock that has no relation to rx5c348a/b, or synchronized with periodic interrupt in pulse mode. 3. access to rx5c348a/b more than 2 times per each second on average. for more details, please cont act to ricoh. how to evaluate the clock gain or loss the oscillator adjustment circuit is configured to change ti me counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds or 60 seconds. the oscillation adjustment circuit does not effect the frequency of 32768hz-clock pulse output from the 32kout pin. theref ore, after writing the oscillation adjustment register, we cannot measure the clock error with probing 32kout clock pulses. the way to measure the clock error as follows: (1) output a 1hz clock pulse of pulse mode with interrupt pin set (0,0,x,x,0,0,1,1) to cont rol register 1 at address eh. (2) after setting the oscillation adjustment register, 1hz clock period changes every 20seconds ( or every 60 seconds) like next page figure. 1hz clock pulse t0 t0 t0 t1 1 time 19 times measure the interval of t0 and t1 with frequency count er. a frequency counter with 7 or more digits is recommended for the measurement. (3) calculate the typical period from t0 and t1 t = (19 t0+1 t1)/20 calculate the time error from t. 12345 - 31 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b oscillation halt sensing, and supply voltage monitoring xstp and vdet the oscillation halt sensing circuit is configured to reco rd a halt on oscillation by 32.768-khz clock pulses. the supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.6v. each function has a monitor bit. i.e. xstp bit is for the oscillation halt sensing circuit, and vdet is for the supply voltage monitoring circuit. xstp and vdet bits ar e activated to ?h?. the xstp and vdet accept only the writing of 0. the xstp bit is set to 1, w hen vdd power-up from 0v, but vdet is set to 0. the functions of these two monitor bits are shown in the table below. oscillation halt sensing circuit operates only when ce pin is low. sensing result is maintained after ce pin changes from ?l? to ?h?. xstp vdet conditions of supply voltage and oscillation 0 0 no drop in supply voltage below threshold voltage and no halt in oscillation 0 1 drop in supply voltage below threshold voltage and no halt in oscillation 1 * halt on oscillation 32768hz oscillation oscillation halt sensing flag (xstp) threshold voltage (2.1v or 1.6v) vdd supply voltage monitor flag (vdet) internal initialization period (1 to 2 sec.) vdet 0 xstp 0 vdet 0 vdet 0 xstp 0 internal initialization period (1 to 2 sec.) when the xstp bit is set to 1 in the control regi ster 2, the (0), f6 to f0, wale, dale, /12 ? 24, /clen2, test, ct2, ct1, ct0, vdsl, vdet, /clen1, ctfg, wa fg, dafg, scratch1/2/3 bits are reset to 0 in the oscillation adjustment register, the control regist er 1, and the control register 2. < considerations in using oscillation halt sensing circuit > be sure to prevent the oscillation halt sensing circ uit from malfunctioning by preventing the following: 1) instantaneous power-down on the vdd 2) condensation on the crystal oscillator 3) on-board noise to the crystal oscillator 4) applying to individual pins voltage exc eeding their respective maximum ratings in particular, note that the xstp bit may fail to be se t to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery inst alla tion. further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit. vdd 12345 - 32 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b voltage monitoring circuit the supply monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6v for the vdsl bit setting of 0 (the default setting) or 1, respectively, in the control r egister 2, thus minimizing supply current requirements as illustrated in the timing chart below. this circuit suspends a sampling operation once the vdet bit is set to 1 in the control register 2. the supply voltage monitor is useful for back-up battery checking. vdet ( d6 in address fh ) xstp vdd 2.1v or 1.6v 1s vdet 0 7.8ms sampling timing fo r vdd supply voltage internal initialization period ( 1 to 2sec. ) xstp 0 vdet 0 12345 - 33 - after writing to the second counter, reset a vdet flag (writing 0) once for defining a value of vdet flag. ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b alarm and periodic interrupt the rx5c348a/b incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the /intr pin as described below. (1) alarm interrupt circuit the alarm interrupt circuit is configured to generate alar m signals for output from the /intr, which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the al arm registers (the alarm_w registers intended for the day-of-week, hour , and minute digit settings and the alarm_d registers intended for the hour and minute digit settings). (2) periodic interrupt circuit the periodic interrupt circuit is configured to generate eit her clock pulses in the pulse mode or interrupt signals in the level mode for output from the /intr pin depending on the ct2, ct1, and ct0 bit settings in the control register 1. the above two types of interrupt signals are monitored by the flag bits (i.e. the wafg, dafg, and ctfg bit s in the control register 2) and enabled or disabled by the enable bits (i.e. the wale, dale, ct2, ct1, and ct0 bits in the control register 1) as listed in the table below. flag bits enable bits alarm_w wafg (d1 at address fh) wale (d7 at address eh) alarm_d dafg (d0 at address fh) dale (d6 at address eh) peridic interrupt ctfg (d2 at address fh) ct2=ct1=ct0=0 (these bit setting of ?0? disable the periodic interrupt) (d2 to d0 at address eh) * at power-on, when the wale, dale, ct2, ct1, and ct 0 bits are set to 0 in the control register 1, the /intr pin is driven high (disabled). * when two types of interrupt signals are output simult aneously from the /intr pin, the output from the /intr pin becomes an or waveform of their negative logic. example: combined output to /intr pin under control of /alarm_d and periodic interrupt periodic interrupt /intr /alarm_d in this event, which type of interrupt signal is output from the /intr pin can be confirmed by reading the dafg, and ctfg bit settings in the control register 2. alarm interrupt the alarm interrupt circuit is controlled by the enable bits (i.e. the wale and dale bits in the control register 1) and the flag bits (i.e. the wafg and dafg bits in the control register 2). the enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. when intended for reading, the flag bits can be used to monitor alarm interrupt signals. when intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. the enable bits will not be affected even when the flag bits ar e set to 0. in this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time. 12345 - 34 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b the alarm function can be set by prese tting desired alarm time in the alarm registers (the alarm_w registers for the day-of-week digit settings and both the alarm_w registers and the alarm_d registers for the hour and minute digit settings) with the wale and dale bits once set to 0 and then to 1 in the control register 1. note that the wale and dale bits should be once set to 0 in order to disable the alarm interrupts circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function. current time = preset alarm time wale 1 (dale) interval (1min.) during which a match between current time and preset alarm time occurs current time = preset alarm time wafg 1 (dale) current time = preset alarm time wale setting of the periodic selection bits (ct2 to ct0) enables periodic interrupt to the cpu. there are two waveform modes: pulse mode and level mode. in the pulse mode, the output has a waveform duty cycle of around 50%. in the level mode, the output is cyclic ally driven low and, when the ctfg bit is set to 0, the output is return to high (off). description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ?l? 0 1 0 pulse mode *1) 2hz(duty50%) 0 1 1 pulse mode *1) 1hz(duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) *1) pulse mode: 2-hz and 1-hz clock pulses are output in sync hronization with the increment of the second counter as illustrated in the timing chart below . /intr pin rewriting of the second counter ctfg bit a pprox. 92 s (increment of second counter) 12345 - 35 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of t he real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the /intr pin low. *2) level mode: periodic interrupt signals are output with sele ctable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic in terrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increm ent of the second counter as illustrated in the timing chart below. setting ctfg bit to 0 ctfg bit /intr pin (increment of second counter) (increment of second counter) (increment of second counter) setting ctfg bit to 0 *1), *2) when the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: pulse mode: the ?l? period of output pulses w ill increment or decrement by a maximum of 3.784ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 sec ond will increment or decrement by a maximum of 3.784 ms. 32-khz clock output for the rx5c348a, 32.768-khz clock pulses are output from the 32kout pin when either the /clen1 bit in the control register 2 or the /clen2 bit in the cont rol register 1 is set to 0. when both the /clen1 and /clen2 bits are set to 0, the 32kout pin output is driven high (off). /clen1 (d3 at address fh) /clen2 (d4 at address eh) 32kout pin (n-channel open drain) 1 1 off(h) 0(default) * * 0(default) clock pulses the 32kout pin output is synchronized with the /clen1 and /clen2 bit settings as illustrated in the timing chart below. 32kout pin max.62.0 s /clen1or2 for the rx5c348b, 32.768-khz clock pulses are output fr om the 32kout pin regardless of such internal register settings. 12345 - 36 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b typical applications typical power circuit configurations sample circuit configuration 1 vdd oscin oscout vss 32768hz system power supply *1) *1) install bypass capacitors for high-frequency and low-frequency applications in parallel in close vicinity to the rx5c348a/b. sample circuit configuration 2 *1) oscin oscout vss 32768hz system power supply vdd primary battery *1) when using an or diode as a power supply fo r the rx5c348a/b ensure that voltage exceeding the absolute maximum rating o f vdd+0.3v is not applied the 32kout pin. 12345 - 37 - *1) oscin oscout vss 32768hz system power supply vdd secondary battery ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b connection of /intr and 32kout pin the /intr pin follows the n-channel open drain output logic and contains no protective diode on the power supply side. as such, it can be connected to a pull-up resistor of up to 5.5v regardless of supply voltage. the 32kout pin follows the n-channel open drain output logic, too. however, it contains protective diode on the power supply side. as such, it cannot be connected to a pull-up resistor over vdd+0.3v. such connection involves considerations for the supply current requirem ents of a pull-up resistor, which can be roughly calculated by the following equation: i = 0.5 (vdd or vcc) / rp vsb oscin oscout /intr or 32kout *1) 32768hz b a backup power supply (vcc) system power supply (vdd) vss *1) depending on whether the /intr or 32kou t pins are to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) position a in the left diagram when it is not to be used during battery backup. (2) position b in the left diagram when it is to be used during battery backup. connection of ce pin connection of the ce pin requires the following considerations: 1) the ce pin is configured to enable the oscillation hal t sensing circuit only when driven low. as such, it should be driven low or open at power-on from 0v. 2) the ce pin should also be driven low or open immediately upon the host going down (see "p.25 considerations in reading and writing time data under special condition"). i/o control so sclk ce si ce min.0 s vdd lower limit operating voltage for the cpu min.0 smin.0 s 0.2 vdd backup power supply 12345 - 38 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b connection with 3-wire serial interface bus to connect the rx5c348a/b with 3-wire serial interface bus, shorten the si and so pins and connect them to the data line as shown in the figure below. ce the other peripheral ic ce1 scl k dat a host sclk sio so ce0 ce sclk si rx5c348a/b 12345 - 39 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b typical characteristics test circuit frequency counter vdd oscin oscout 32kout vss 32768hz x?tal : 32.768khz (r1=30k ? typ) (cl=6pf to 8pf) topt : 25 c output pins : open timekeeping current vs. supply voltage timekeeping current vs. supply voltage (with no 32-khz clock output) (with 32-khz clock output) (ce=open, output=open, topt=25 c,rx5c348a) (ce=open, output=open,topt=25 c) 0 0.2 0.4 0.6 0.8 1 0123456 supply voltage vdd(v) timekeeping current idd (ua) 0 0.5 1 1.5 2 0123456 supply voltage vdd(v) timekeeping current idd(ua) rx5c348a rx5c348b cpu access current vs. sclk clock frequency timekeeping current vs. operating temperature (output=open, topt=25 c) (with no 32-khz clock output) (ce=open, output=open) 0 10 20 30 40 50 0 500 1000 1500 2000 sclk clock frequency (khz) cpu access current idd(ua) 0 0.5 1 1.5 2 -60 -40 -20 0 20 40 60 80 100 operating temperature topt( c) timekeeping current idd(ua) vdd=5v vdd=3v 12345 - 40 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b oscillation frequency deviation vs. external cg oscillation frequency deviation vs. supply voltage (vdd=3v,topt=25 c, (topt=25 c,vdd=3v as standard) external cg=0pf as standard) -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 0 5 10 15 20 external cg (pf) oscillation frequency devitation (ppm) -5 -4 -3 -2 -1 0 1 2 3 4 5 0123456 supply voltage vdd(v) oscillation frequency devitation (ppm) oscillation frequency deviation vs. operating temperature oscillation start time vs. supply voltage (vdd=3v, topt=25 c external cg=0pf as standard) (topt=25 c) -140 -120 -100 -80 -60 -40 -20 0 20 -60 -40 -20 0 20 40 60 80 10 0 operating temperature topt( c) oscillation frequency devitation (ppm) 0 100 200 300 400 500 0123456 supply voltage vdd(v) oscillation start time (ms) vol vs. iol v ol vs. iol (32kout pin of the rx5c348a and /intr pi n) (32kout pin of the rx5c348b) (topt=25 c) (topt=25 c) 0 5 10 15 20 25 30 0 0.2 0.4 0.6 0.8 1 vol (v) iol (ma) 0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1 vol (v) iol (ma) vdd=5v vdd=5v vdd=3v vdd=3v 12345 - 41 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b typical software-based operations initialization at power-on start *1) yes no vdet=0? warning back-up batter y run-down set oscillation adjustment register and control register 1 and 2, etc. power-on *2) *4) *3) xstp=1? yes no *1) after power-on from 0 volt, the start of oscillation and the process of internal initialization require a time span on 1to 2seconds, so that access should be done after the lapse of this time span or more. *2) the xstp bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0v . for further details, see "p .32 xstp and vdet". *3) this step is not required when the supply voltage monitoring circuit is not used. when using this circuit, note as follows. after writing to the second counter, reset a vdet flag (writing 0) once for defining a value of vdet flag. *4) this step involves ordinary initialization includi ng the oscillation adjustment register and interrupt cycle settings, etc. writing of time and calendar data write to time counter and calendar counter *2) ce l *3) ce h *1) *1) when writing to clock and calendar counters, do not drive ce to ?l? until all times from second to year have been written to prevent error in writing time. (detailed in "p.24 considerations in reading and writing time data under special condition ". *2) any writing to t he second counter will reset divider units lower than the second digits. after wiritng to the second counter, reset a vdet flag (writing 0) once for defining a value of vdet flag. *3) take care so that process from ce driving to ?h? to driving to ?l? will be complete within 1.0sec. (detailed in "p.24 a djustment of oscillation frequency ". the rx5c348a/b may also be initialized not at power-on but in the process of writing time and calendar data. 12345 - 42 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b reading time and calendar data (1) ordinary process of reading time and calendar data read from time counter and calendar counter *2) ce l ce h *1) *1) when writing to clock and calendar counters, do not insert stop condition until all times from second to year have been written to prevent error in writing time. (detailed "p.24 considerations in reading and writing time data under special condition ". *2) take care so that process from start condition to stop condition will be complete within 0.5sec. (detailed in "p.24 considerations in reading and writing time data under special condition ". (2) basic process of reading time and calendar data with periodic interrupt function *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 1.0 second. *3) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu. *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? read from time counter and calendar counte r yes no control register 2 (x1x1x011) generate interrupt in cpu *1) *3) 12345 - 43 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b (3) applied process of reading time and calendar data with periodic interrupt function time data need not be read from all the time counters when used for such ordinary purposes as time count indication. this applied process can be used to read ti me and calendar data with subst antial reductions in the load involved in such reading. for time indication in "day-of-month, day- of-week, hour, minute, and second" format: *2) other interrupts processes sec.=00? yes no generate interrupt to cpu *1) *3) ctfg=1? control register 2 (x1x1x011) yes read min.,hr.,day, and day-of-week *4) no control register 1 (xxxx 0100) control register 2 (x1x1x011) use previous min.,hr., day, and day-of-week data *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 1.0 sec. *3) this step is intended to read time data from all the time counters only in the first session of reading time data afte r writing time data. *4) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu. 12345 - 44 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
rx5c348a/b interrupt process (1) periodic interrupt *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? conduct periodic interru p t yes no control register 2 (x1x1x011) generate interrupt to cpu *1) *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu. (2) alarm interrupt *3) other interrupt processes set alarm min., hr., and day-of-week registers wafg or dafg=1? conduct alarm interrupt yes no control register 2 (x1x1x101) generate interrupt to cpu *1) wale or dale 0 *2) wale or dale 1 *1) this step is intended to once disable the alarm interrupt circuit by setting the w ale or dale bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) this step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) this step is intended to once cancel the alarm interrupt function by writing the settings of "x,1,x, 1,x,1,0,1" and "x,1,x,1,x,1,1,0" to the alarm_w registers and the alarm_d registers, respectively. 12345 - 45 - ?
rt5c348b (tssop10g) and rs5c348b (ssop10) are the discontinued products. as of july in 2016.
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