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| surface mount package super high density cell design for extremely low r ds(on) c c f l i n v e r t e r drain-source voltage v ds 4 0 v gate-source voltage v gs 20 v continuous drain current (note 1) i d 8 a pulsed drain current (tp=10us) i dm 32 a continous source-drain diode current i s 8 a drain-source voltage v ds - 4 0 v gate-source voltage v gs 20 v continuous drain current (note 1) i d - 7 a pulsed drain current (tp=10us) i dm - 28 a continous source-drain diode current i s - 7 a power dissipation p d w thermal resistance from junction to ambient (note 1) r ja /w junction temperature t j 150 storage temperature t stg -55~+150 lead temperature for soldering purposes(1/8 from case for 10 s) t l 260 equivalent circuit v (br) dss r ds(on) max i d 4 19 8 2 9 4 35 7 45 1 jul 6 soli d dot = green molding compound device, if none,the normal device. q4 614 = device co de yy = code solid dot = pin1 indicator q 4614 yy
( "# , -.& ! /(!01! /!23 04!!0 546/ ! / 2/ " 5 "< drain-source breakdo w n voltage v (br)dss v gs = 0v, i d =250a 0 v zero gate voltage drain curren t i dss v ds = 0v,v gs = 0v 1 a gate-body leakage curr ent i gss v gs =20v, v ds = 0v 100 na gate threshold voltage (note 2) v gs(th) v ds =v gs , i d =250a 1 v drain-source on-resista n ce (note 2) r ds(on) v gs =10v, i d = a m v gs =4.5v, i d = a m forwa r d tranc onductance (note 2) g fs v ds = v, i d = a s diode forwar d voltag e v sd i s = a, v gs = 0v 1.2 v " , /! %3 input capacitance c iss v ds = v,v gs =0v,f =1mhz pf output capacitance c oss pf reverse tr ansfer capac itance c rss pf = , /! >%3 turn-on delay t i me t d(on) v gen = v,v dd = 0v, r g = ? r l = . ? ns turn-on rise time t r ns turn-off delay t ime t d(of f ) 5 ns turn-off fall time t f ns total gate charge q g v ds = 0v,i d = a, v gs = v nc gate-source charge q gs nc gate-drain charge q gd nc ( "# , -.& ! /(!0 1 ! /!23 04!!0 546/ ! / 2 / " 5 "< drain-source breakdo w n voltage v (br)dss v gs = 0v, i d =-250a - 0 v zero gate voltage drain curren t i dss v ds =- 0v,v gs = 0v -1 a gate-body leakage curr ent i gss v gs =20v, v ds = 0v 100 na gate threshold voltage (note 2) v gs(th) v ds =v gs , i d =-250a -1 - v drain-source on-resista n ce (note 2) r ds(on) v gs =-10v, i d =- a m v gs =-4.5v, i d =- a m forwa r d tranc onductance (note 2) g fs v ds =-5v, i d =- a s diode forwar d voltag e v sd i s =- a, v gs = 0v -1.2 v " , /! %3 input capacitance c iss v ds =- v,v gs =0v,f =1mhz 0 pf output capacitance c oss pf reverse tr ansfer capac itance c rss pf = , /! >%3 turn-on delay t i me t d(on) v gen =- v,v dd =- 0v, r g = r l = . ? ns turn-on rise time t r ns turn-off delay t ime t d(of f ) ns turn-off fall time t f ns total gate charge q g v ds =- 0v,i d =- a, v gs =- v 1 nc gate-source charge q gs . nc gate-drain charge q gd 3. nc /! ? 1.surface mounted on fr 4 board us ing the minimum recommended pad size. 2. pulse test : pulse width=300s, duty cycle2%. 3. switching characteristics are independent of operating junction temperature. 4. graranted by design not subject to producting. - x o "# 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.01 0.1 1 8 012345 0 5 10 15 20 25 30 12345678 0 10 20 30 40 246810 0 10 20 30 40 50 60 012345 0 4 8 12 16 20 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 pulsed pulsed t a =100 v sd i s ?? t a =25 source current i s (a) source to drain voltage v sd (v) v gs =10v v gs =3.5v v gs =3v v gs =4.5v output characteristics v gs =2.5v drain current i d (a) drain to source voltage v ds (v) t a =25 pulsed v gs =10v v gs =4.5v t a =25 pulsed on-resistance r ds(on) (m : ) drain current i d (a) i d ?? r ds(on) t a =100 t a =25 on-resistance r ds(on) (m : ) gate to source voltage v gs (v) v gs ?? r ds(on) i d =8a v ds =5v pulsed drain current i d (a) gate to source voltage v gs (v) transfer characteristics t a =25 i d =250ua threshold voltage threshold voltage v th (v) junction temperature t j ( ) 7 \ s l f d o & k d u d f w h u l v w l f v n-cha n nel " - x o -0.0 -0.4 -0 .8 -1 .2 -1.6 -0.1 -1 -10 -0 -1 -2 -3 -4 -5 -0 -10 -20 -3 0 -40 -50 -2 -4 -6 -8 0 20 40 60 80 -3 -4 -5 -6 -7 -8 -9 -10 0 50 100 150 -0 -1 -2 -3 -4 -0 -10 -20 -3 0 -40 -50 25 50 75 100 125 -1.0 -1 .2 -1 .4 -1.6 -1.8 -2.0 pulsed t a =100 v sd i s ? ? t a =25 source current i s (a) source to drain voltage v sd (v) v gs =-3.5v v gs =-3v v gs =-4v,-7v,-10v v gs =-2.5v out p ut characteristics drain current i d (a) drain to source voltage v ds (v) t a =25 pulsed v gs =-4.5v v gs =-10v t a =25 pulsed on- r esistance r ds(o n) (m ? ) drain current i d (a) i d ?? r ds(on) pulsed t a =100 t a =25 on- r esistance r ds(o n) (m ? ) gate to source voltage v gs (v) v gs ?? r ds(on) i d =-8a v ds =-5v pulsed drain current i d (a) gate to source voltage v gs (v) t r an sf er characteristics t a =25 i d =-250ua thre s hold voltage threshold vo lt age v th (v) junction temperature t j ( ) 7 \ s l f d o & k d u d f w h u l v w l f v -cha nne l 1jul6 www.cj-elec.com 5 a- 1 , jul ,2016 sop8 package outline dimensions so p8 suggested pad layout mi n max mi n max a a1 0.100 0.250 0.004 0.010 a2 1.3 50 1.5 5 0 0.053 0.0 61 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.007 0.010 d 4.800 5.000 0.189 0.197 e e 5.800 6.200 0.228 0.244 e1 3.800 4.000 0.150 0.157 l 0.400 1.270 0.016 0.050 0 8 0 8 sy m bo l dimensions in millimeters dimensions in inches 0.050bsc 1.270bsc 1.350 1.750 0.053 0.069 sop8 6 jul 1 l l 1 l 1 ll 1 1 1 1 11 1 1 |
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