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rev 1.0 9/14 copyright ? 2014 by silicon laboratories em346 em346 high-performance, integrated dual zigbee pro & rf4ce network coprocessor features - 32-bit arm? cortex -m3 processor - 2.4 ghz ieee 802.15.4-2003 transceiver & lower mac - 192 kb flash, with optional read protection - 12 kb ram memory - aes128 encryption accelerator - uart/spi serial communications - 16 gpios industry-leading arm? cortex -m3 processor - leading 32-bit processing performance - highly efficient thumb-2 instruction set - operation at 6, 12, or 24 mhz - flexible nested vectored interrupt controller low power consumption, advanced management - rx current (w/ cpu): 26 ma - tx current (w/ cpu, +3 dbm tx): 31 ma - low deep sleep current, with retained ram and gpio: 400 na without/800 na with sleep timer - low-frequency internal rc oscillator for low-power sleep timing - high-frequency internal rc oscillator for fast (110 s) processor start-up from sleep exceptional rf performance - normal mode link budget up to 103 db; configurable up to 110 db - ?100 dbm normal rx sensit ivity; configurable to ? ?102 dbm (1% per, 20 byte packet) - configurable up to +8 dbm - robust wi-fi and bluetooth coexistence innovative network and processor debug - packet trace port for non-intrusive packet trace with ember development tools - serial wire/j tag interface - standard arm debug capabilities: flash patch & break - point; data watchpoint & trace; instrumentation trace macrocell application flexibility - single voltage operation: 2.1?3.6 v with internal 1.8 and 1.25 v regulators - optional 32.768 khz crystal for higher timer accuracy - low external component count with single 24 mhz ? crystal - support for external power amplifier - small 7x7 mm 48-pin qfn package adc rf_p,n program flash 192kb data sram 12kb hf crystal osc lf crystal osc serial wire and jtag debug internal lf rc-osc gpio multiplexor switch chip manager 1.8v regulator bias 2 nd level interrupt controller rf_tx_alt_p,n osca oscb encryption acclerator if always powered domain arm ? cortex-m3 tm cpu with nvic and mpu vreg_out watchdog pa select lna pa pa dac mac + baseband sleep timer bias_r por nreset gpio registers uart/spi synth internal hf rc-osc tx_active swclk, jtck calibration adc packet trace cpu debug tpiu/itm/ fpb/dwt 1.25v regulator vdd_core pa4 pa5 pa7 pb0 pc5 pc4 pc3 pc2 pc1 pc0 pb4 pb3 pb2 pb1 pc6 pc7
em346 2 rev 1.0 table of contents 1. typical application ........... .................................................................................. ............... ..4 2. electr ical specifications................. .......................................... ............... ............................ 7 2.1. absolute maximum ratings... ............................................................................. ............7 2.2. recommended operating conditions .... ............... ............................................. ............7 2.3. environmental characteristics ........ ................................................................................8 2.4. dc electrical char acteristics. .............. ............................................................... ............8 2.5. digital i/o specifications .. .................................................................................. .......... 1 3 2.6. non-rf system electrical characteristics . ......... ............................................... .......... 14 2.7. rf electrical characteristics ........ ...................................................................... .......... 1 5 3. functional description ........ .................................................................................. ............ 2 1 4. radio module .................. .................................................................................. ............... .. 24 4.1. receive (rx) path..... ......................................................................................... ..........2 4 4.2. transmit (tx) path ........... .................................................................................. .......... 2 4 4.3. calibration .......... ................................................................. ............... .............. ............ 24 4.4. integrated mac module ........ ............................................................................. .......... 2 5 4.5. packet trace interface (pti) . ............................................................................. .......... 2 5 4.6. random number generator.. ............................................................................. .......... 2 5 5. arm? cortex?-m3 and memory modules .................. .......................................... .......... 2 6 5.1. arm? cortex?-m3 microprocessor... ............................................................... ..........2 6 5.2. embedded memory ............... ............................................................................. .......... 2 6 5.3. memory protection unit...... ................................................................................ .......... 3 2 6. system modules................ .................................................................................. ............... 33 6.1. power domains ................ .................................................................................. .......... 3 4 6.2. resets ........... .............................................................................................................. .35 6.3. clocks ................... ......................................................................................... ............. .. 38 6.4. system timers ............... .................................................................................. ............ 4 3 6.5. power management ................ ........................................................................... .......... 4 4 6.6. security accelerator ....... .................................................................................. ............ 4 7 7. gpio (general purpose i nput/output) . ............ ........................................................ ........ 48 7.1. gpio ports .............. ........................................................................................... .......... 4 9 7.2. configuration ............. ......................................................................................... .......... 4 9 7.3. forced functions................ ................................................................................ .......... 5 0 7.4. reset .................... ......................................................................................... ............. .. 50 7.5. boot configuration .......... .................................................................................. ............5 1 7.6. gpio modes.............. ......................................................................................... .......... 5 1 7.7. wake monitoring .............. .................................................................................. .......... 5 2 7.8. external interrupts .......... .................................................................................. ............5 3 7.9. debug control and status ..... ............................................................................. .......... 5 3 7.10. gpio signal assignment summary...... ............................................................. .......... 5 5 7.11. registers............................................................................. ............... .............. ............ 56 8. serial controllers ..... ........................................................................................... ............. ..68 8.1. overview ................. ............................................................ ............... .............. ............6 8 8.2. configur ation ............. ......................................................................................... .......... 6 9 8.3. spi?slave mode ............... ................................................. ............... .............. ............ 74
em346 rev 1.0 3 8.4. uart?universal asynchronous rece iver/transmitter.... ................................. .......... 78 8.5. dma channels ................... ................................................................................ .......... 8 6 9. interrupt system ............. .................................................................................. ............... 1 00 9.1. nested vectored interrupt controll er (nvic).............. .............. .............. ............ ........ 100 9.2. event manager ................. ................................................................................ .......... 1 02 9.3. non-maskable interrupt (nmi)........ .................................................................. .......... 1 04 9.4. faults.................. ....................................................................................................... .10 5 9.5. registers ............ ................................................................. ............... .............. ..........1 06 10. trace port interface unit (tpiu)..... .......................................... ............... .............. .......... 1 13 11. instrumentation trace macrocell (itm ) .............. .................................................. ..........114 12. data watchpoint and trace (dwt) ..... .................................................................. ..........1 15 13. flash patch and breakpoint (fpb) ... ................................................................. .............1 16 14. integrated voltage regulator......... .......................................... ............... .............. .......... 1 17 15. serial wire and jtag (swj) interf ace .................. ................ ............................... .......... 119 16. ordering information ........... .................................................................................. .......... 1 20 17. pin definitions............... .................................................................................. ............... .. 121 17.1. pin definitions ......... ............................................................ ............... .............. .......... 1 21 18. package ............... ............................................................... ............... ........................... .... 128 19. top marking.............. ................ ......................................................................... ............. .. 131 appendix aregister address table............ .............................. ............... .............. ..........132 appendix babbreviations and acrony ms.............. ................ ............................... .......... 137 appendix creferences ......... .................................................................................. .......... 1 41 document change list ........ .......................................................... ............... .............. .......... 1 42 contact information ........... .................................................................................. ............... .. 143
em346 4 rev 1.0 1. typical application figure 1.1 illustrates the typical application circuit, and table 1.1 contains an example bill of materials (bom) for the off-chip components required by the em346. note: the circuit shown in figure 1.1 is for example purposes only, and the bom is for budgetary quotes only. for a complete reference design, please download one of the latest ember ha rdware reference designs from the silicon labs website ( www.silabs.com/zigbee-support ). the balun provides an impedance transformation from the antenna to the em346 for both tx and rx modes. l1 tunes the impedance presented to the rf port for maximum transmit power and receive sensitivity. the harmonic filter (l2, l3, c5, c6 and c9) provides addit ional suppression of the second harmonic, which increases the margin over the fcc limit. the 24 mhz crystal y1 with loading cap a citors is required and provides the high-frequency crystal oscillator source for the em346's main syst em clock. the 32.768 khz crystal with loading capacitors generates a highly accurate low - frequency crystal oscillator for us e with peripherals, but it is not mand atory as the low-fr equency internal rc oscillator can be used. loading capacitance and esr (c1 and r3) provides st ability for the internal 1.8 v regulator. loading capacitance c2 provides stability for the internal 1.25 v re gulator, no esr is required because it is cont ained within the chip. resistor r1 reduces the operating voltage of the flash m e mory, this reduces current consumption and improves sensitivity by 1 db when compared to not using it. various decoupling capacitors are required, these should be p laced as close to th eir corresponding pins as possible. for values and locations see one of the latest reference designs. an antenna matched to 50 ? is required.
em346 rev 1.0 5 figure 1.1. typical application circuit dc vdd_24mhz 1 vdd_vco 2 rf_p 3 rf_n 4 vdd_rf 5 rf_tx_alt_p 6 rf_tx_alt_n 7 vdd_if 8 nc 9 vdd_padsa 10 pc5 11 nreset 12 pc6 13 pc7 14 vreg_out 15 vdd_pads 16 vdd_core 17 pa7 18 pb3 19 pb4 20 nc 21 nc 22 vdd_pads 23 nc 24 osca 48 oscb 47 vdd_synth 46 vdd_pre 45 vdd_core 44 nc 43 nc 42 nc 41 pc0 40 vdd_mem 39 pc1 38 vdd_pads 37 pb0 36 pc4 35 pc3 34 pc2 33 jtck 32 pb2 31 pb1 30 nc 29 vdd_pads 28 pa5 27 pa4 26 nc 25 gnd 49 harmonic filter antenna ceramic balun em34x y1 y2 r1 r3 l1 c1 l2 c2 c3 c4 c5 c6 c7 c8 vbrd optional pc2 pc0 pc3 jtck pc4 nreset pa4 pa5 programing and debug interface (these pins should be routed to test points) l3 c9
em346 6 rev 1.0 ta b l e 1.1 contains a typical bill of material s for the applic ation circuit shown in figure 1.1 . the information within this table should be used for a rough cost analysis. for a mo re detailed bom, please refer to one of ember em357- based reference designs at the silicon labs website ( www.silabs.com/zigbee-support ). table 1.1. bill of materials for typical application circuit item qty reference description manufacturer 1 1 c2 capacitor, 1 f, 6.3 v, x5r, 10%, 0402 2 1 c1 capacitor, 2.2 f, 10 v, x5r, 10%, 0603 3 1 c7 capacitor, 22 pf, 5%, 50 v, npo, 0402 4 2 c3,c4 capacitor, 18 pf, 5%, 50 v, npo, 0402 5 1 c8 capacitor, 33 pf, 5%, 50 v, npo, 0402 6 2 c5, c9 capacitor, 1 pf, 0.25 pf, 50 v, 0402, npo 7 1 c6 capacitor, 1.8 pf, 0.25 pf, 50 v, 0402, npo 8 1 l1 inductor, 5.1 nh, 0.3 nh, 0402 multilayer murata lqg15hs5n1 9 2 l2, l3 inductor, 2.7 nh, 0.3 nh, 0402, multilayer murata lqg15hs2n7 10 1 r1 resistor, 10 ? , 5%, 0 402 11 1 r3 resistor, 1 ? , 5%, 040 2 12 1 u1 em346 dual zigbee pro & rf4ce network copro - cessor ember em346 13 1 y1 crystal, 24.000 mhz, 25 ppm stability o ver ?4 0 to +85 oc, 18 pf ilsi, abracon, kds, epson 14 1 y2 (optional) crystal, 32.768 khz, 20 ppm initial toler - ance at +25oc, 12.5 pf abracon, kds, epson 15 1 bln1 balun, ceramic 50/100 ? wurth 748421245 johanson 245 0bl1 5b100e murata ldb212g4010c 16 1 ant1 antenna johanson 2450at18b100e
em346 rev 1.0 7 2. electrical specifications 2.1. absolute maximum ratings ta b l e 2.1 lists the absolute maxi mum ratings for the em346. 2.2. recommended operating conditions ta b l e 2.2 lists the rated operating conditions of the em346. table 2.1. absolute maximum ratings parameter test condition min max unit regulator input voltage (vdd_pads) ?0.3 +3.6 v analog, memory and core voltage (vdd_24mhz, vdd_v c o, vdd_rf, vdd_if, vdd_padsa, vdd_mem, vdd_pre, vdd_synth, vdd_core) ?0.3 +2.0 v voltage on rf_p,n; rf_tx_alt_p,n ?0.3 +3.6 v rf input power ? (for max level for correc t p a cket reception see ta b l e 2.7 ) rx signal into a lossless bal un ? +15 dbm v oltage on any gpio, swclk, nreset, vreg_out ?0.3 vdd_pads +0.3 v voltage on osca, oscb, nc ?0.3 vdd_padsa +0.3 v storage temperature ?40 +140 c note: exposure to absolute-maximum-rated conditions fo r extended periods may affect device reliability. table 2.2. operating conditions parameter test condition min typ max unit regulator input voltage (vdd_pads) 2.1 ? 3.6 v analog and memory input voltage (vdd_24mhz, v dd_vco, vd d_rf, vdd_if, vdd_padsa, vdd_mem, vdd_pre, vdd_synth) 1.7 1.8 1.9 v core input voltage when su pplie d from internal regulator (vdd_core) 1.18 1.25 1.32 v core input voltage when supplied externally (vdd_core) 1.18 ? 1.9 v operating temperature range, t a ?40 ? +85 c note: exposure to absolute-maximum-rated conditions for extende d periods may affect device reliability.
em346 8 rev 1.0 2.3. environmental characteristics ta b l e 2.3 lists the rated environmental characteristics of the em346. 2.4. dc electrical characteristics ta b l e 2.4 lists the dc electrical characteristics of the em346. table 2.3. environmental characteristics parameter symbol test condition min typ max unit esd (human body model) on any pin ? ? 2 kv esd (charged device model) non-rf pins ? ? 400 v esd (charged device model) rf pins ? ? 225 v package thermal resistance* ? ja 27.1 c/w *note: thermal resistance assumes multi-layer pcb with exposed pad soldered to a pcb board. table 2.4. dc characteristics measured on silicon labs? em 357 reference design with t a = 25 c and v dd = 3 v, unless otherwise noted. parameter test condition min typ max unit regulator input voltage (v dd_p ads) 2.1 ? 3.6 v power supply range (vdd_mem) regulator output or external input 1.7 1.8 1.9 v power supply range (vdd_core) regulator output 1.18 1.25 1.32 v deep sleep current quiescent current, internal rc oscillator disabled ?40 c, vdd_pads=3.6 v ? 0.4 ? ? a +25 c, vdd_pads=3.6 v ? 0.4 ? ? a +85 c, vdd_pads=3.6 v ? 0.7 ? ? a quiescent current, including ? internal rc oscillator ?40 c, vdd_pads=3.6 v ? 0.7 ? ? a +25 c, vdd_pads=3.6 v ? 0.7 ? ? a +85c, vdd_pads=3.6 v ? 1.1 ? ? a quiescent current, including 32 .7 68 khz oscillator ?40 c, vdd_pads=3.6 v ? 0.8 ? ? a +25 c, vdd_pads=3.6 v ? 1.0 ? ? a +85 c, vdd_pads=3.6 v ? 1.5 ? ? a quiescent current, including ? internal rc oscillator and 32 .7 68 khz oscillator ?40 c, vdd_pads=3.6 v ? 1.1 ? ? a +25 c, vdd_pads=3.6 v ? 1.3 ? ? a +85 c, vdd_pads=3.6 v ? 1.8 ? ? a simulated deep sleep (debug mo de) current with no debugger activity ? 300 ? ? a
em346 rev 1.0 9 reset current quiescent current, nreset asserted typ at 25 c/3.0 v max at 85 c/3.6 v ? 1.2 2.0 ma processor and peripheral currents arm ? cortex tm -m3, ram, and flash memory 25 c, 1.8 v memory and 1.25 v core ar m ? cortex tm -m3 running at 12 mhz from crystal oscillator radio and all peripherals off ? 6.5 ? ma arm ? cortex tm -m3, ram, and flash memory 25 c, 1.8 v memory and 1.25 v core ar m ? cortex tm -m3 running at 24 mhz from crystal oscillator radio and all peripherals off ? 7.5 ? ma arm ? cortex tm -m3, ram, and flash memory sleep current 25 c, 1.8 v memory and 1.25 v core arm ? cortex tm -m3 sleeping, cpu clock set to 12 mhz from the crystal oscillator radio and all peripherals off ? 3.0 ? ma arm ? cortex tm -m3, ram, and flash memory sleep current 25 c, 1.8 v memory and 1.25 v core arm ? cortex tm -m3 sleeping, cpu clock set to 6 mhz from the high fre - quency rc oscillator radio and all peripherals off ? 2.0 ? ma serial controller current for each controller at maximum data ra te ? 0.2 ? ma rx current radi o receiver, mac, and base - band arm ? cortex tm -m3 sleeping, cpu clock set to 12 mhz ? 22.0 ? ma total rx current ( = i radio receiver, mac and baseband, cpu + iram, and flash memory ) 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 12 mhz ? 25.5 ? ma 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 24 mhz ? 26.5 ? ma boost mode total rx current ( = i radio receiver, mac and base - band, cpu+ iram, and flash me mor y ) 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 12 mhz ? 27.5 ? ma 25 c, vdd_pads=3.0 v arm ? cortex tm -m3 running at 24 mhz ? 28.5 ? ma table 2.4. dc characteristics (continued) measured on silicon labs? em 357 reference design with t a = 25 c and v dd = 3 v, unless otherwise noted. parameter test condition min typ max unit
em346 10 rev 1.0 tx current radio transmitter, mac, and base - band 25 c and 1.8 v core; max. power out (+3 dbm typical) arm ? cortex tm -m3 sleeping, cpu clock set to 12 mhz ? 26.0 ? ma total tx current ( = i radio transmit - ter, mac and baseband, cpu + iram , an d flash memory) 25 c, vdd_pads=3.0 v; maximum power s e tting (+8 dbm); arm ? cortex tm -m3 running at 12 mhz ? 42.5 ? ma 25 c, vdd_pads=3.0 v; +3 dbm power se tting; arm ? cortex tm -m3 running at 12 mhz ? 30.0 ? ma 25 c, vdd_pads=3.0 v; 0 dbm power setting; a r m ? cortex tm -m3 running at 12 mhz ? 27.5 ? ma 25 c, vdd_pads=3.0 v; minimum power se tting; arm ? cortex tm -m3 running at 12 mhz ? 21.5 ? ma 25 c, vdd_pads=3.0 v; maximum power s e tting (+8 dbm); arm ? cor - tex tm -m3 running at 24 mhz ? 43.5 ? ma 25 c, vdd_pads=3.0 v; +3 dbm power se tting; arm ? cortex tm -m3 running at 24 mhz ? 31.0 ? ma 25 c, vdd_pads=3.0 v; 0 dbm power setting; a r m ? cortex tm -m3 running at 24 mhz ? 28.5 ? ma 25 c, vdd_pads=3.0 v; minimum power se tting; arm ? cortex tm -m3 running at 24 mhz ? 22.5 ? ma table 2.4. dc characteristics (continued) measured on silicon labs? em 357 reference design with t a = 25 c and v dd = 3 v, unless otherwise noted. parameter test condition min typ max unit
em346 rev 1.0 11 figure 2.1 shows the variation of current in transmit mode (with the arm ? cortex tm -m3 running at 12 mhz). figure 2.1. transmit power consumption
em346 12 rev 1.0 figure 2.2 shows typical output power against power se tting on the silicon l abs reference des ign. figure 2.2. transmit output power
em346 rev 1.0 13 2.5. digital i/o specifications ta b l e 2.5 lists the digital i/o specifications for the em346. the digital i/o power (named vdd_pads) comes from three dedicated pins (pins 23, 28 and 37). the voltage applied to these pins sets the i/o voltage. table 2.5. digital i/o specifications parameter test condition min typ max unit voltage supply (regulator input voltage) 2.1 ? 3.6 v low schmitt switching threshold v swil schmitt input threshold going from high to low 0.42 x vdd_p ads ? 0. 50 x vdd_pads v h igh schmitt switching threshold v swih schmitt input threshold going from low to high 0.62 x vdd_p ads ? 0. 80 x vdd_pads v in put current for logic 0 i il ? ? ?0.5 a input current for logic 1 i ih ? ? +0.5 a input pull-up resistor value r ipu 24 29 34 k? input pull-down resistor value r ipd 24 29 34 k? output voltage for logic 0 v ol (i ol = 4 ma for standard pads, 8 ma for high current pads) 0 ? 0.18 x vdd_p ads v outp ut voltage for logic 1 v oh (i oh = 4 ma for standard pads, 8 ma for high current pads) 0.82 x vdd_p ads ? vdd_p ads v output source current ? (standard current pad) i ohs ? ? 4 ma output sink current ? (standard current pad) i ols ? ? 4 ma output source current high current pad: pa 7 , pc0 i ohh ? ? 8 ma output sink current high current pad: pa 7 , pc0 i olh ? ? 8 ma total output current (for i/o pads) i oh + i ol ? ? 40 ma
em346 14 rev 1.0 ta b l e 2.6 lists the nreset pin specificatio ns for the em346. the digit al i/o power (named vdd_pads) comes from three dedicated pins (pins 23, 28 and 37). the voltage applied to these pins sets the i/o voltage. 2.6. non-rf system electrical characteristics ta b l e 2.7 lists the non-rf system leve l character istics for the em346. table 2.6. nreset pin specifications parameter test condition min typ max unit low schmitt switching threshold v swil schmitt input threshold going from high to low 0.42 x vdd_p ads ? 0.50 x vdd_pa ds v high schmitt switching threshold v swih schmitt input threshold going from low to high 0.62 x vdd_p ads ? 0.80 x vdd_pa ds v input current for logic 1 i ih ? ? +0.5 a input pull-up resistor value r ipu pull-up value while the chip is not reset 24 29 34 k ? input pull-up resistor value r ipureset pull-up value while the chip is reset 12 14.5 17 k ? table 2.7. non-rf system electrical characteristics measured on silicon labs? em357 reference design with t a = 25 c and v dd = 3 v, unless otherwise noted. parameter test condition min typ max unit system wake time from deep sl e ep from wakeup event to first arm ? cor - tex tm -m3 instruction running from 6 mhz internal rc clock includes supply ramp time and oscillator star tup time ? 110 ? s shutdown time going into deep sl e ep from last arm ? cortex tm -m3 instruction to deep sleep mode ? 5 ? s
em346 rev 1.0 15 2.7. rf electric al characteristics 2.7.1. receive ta b l e 2.8 lists the key parameters of the integrated ieee 802.15.4-2003 receiver on the em346. receive measurements were collected with the silicon labs em357 ceramic balun reference design (version a0) at 2440 mhz. the typical number indicates one standard de via tion above the mean, measured at room temperature (25 ? ? c). the min and max numbers were measured over process corners at room temperature. table 2.8. receive characteristics parameter test condition min typ max unit frequency range 2400 ? 2500 mhz sensitivity (boost mode) 1% per, 20 byte packet defined by ieee 802.15.4-2003; ? ?102 ?96 dbm sensitivity 1% per, 20 byte packet defined by ieee 802.15.4-2003; ? ?100 ?94 dbm high-side adjacent channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?8 2 dbm ? 35 ? db l ow-side adjacent channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?8 2 dbm ? 35 ? db 2 nd high-side adjacent channel rejec - tion ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 46 ? db 2 nd low-side adjacent channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 46 ? db high -side adjacent channel rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2 003 signal at ?82 dbm ? 39 ? db low-side adjacent channel rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2 003 signal at ?82 dbm ? 47 ? db 2 nd high-side adjacent channel ? rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2 003 signal at ?82 dbm ? 49 ? db 2 nd low-side adjacent channel rejection filtered ieee 802. 15.4-2003 inter - ferer signal, wanted ieee 802.15.4- 2 003 signal at ?82 dbm ? 49 ? db high-side adjacent channel rejection cw interferer signal, wanted ieee 80 2.15 .4-2003 signal at ?82 dbm ? 44 ? db low-side adjacent channel rejection cw interferer signal, wanted ieee 80 2.15 .4-2003 signal at ?82 dbm ? 47 ? db
em346 16 rev 1.0 2 nd high-side adjacent channel ? rejection cw interferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 59 ? db 2 nd low-side adjacent channel rejection cw interferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 59 ? db channel rejection fo r all other channels ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 40 ? db 8 02.11g rejection centered at +12 mhz or ? 13 mhz ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?82 dbm ? 36 ? db m aximum input signal level for correct o per ation 0 ? ? dbm co-channel rejection ieee 802.15.4-2003 in terferer signal, wanted ieee 802.15 .4-2003 signal at ?8 2 dbm ? ?6 ? db c relative frequency error (50% greater than the 2x40 ppm required by ieee 802.15.4-2003) ?120 ? +120 ppm relative timing error (50% greater than the 2x40 ppm required by ieee 802.15.4-2003) ?120 ? +120 ppm linear rssi range as defined by ieee 802.15.4-2003 40 ? ? db rssi range ?90 ? ?40 dbm table 2.8. receive characteristics (continued) parameter test condition min typ max unit
em346 rev 1.0 17 figure 2.3 shows the variation of receive sensitivity with temp eratur e for boost mode and normal mode for a typical chip. figure 2.3. receive sensitivity vs. temperature
em346 18 rev 1.0 2.7.2. transmit ta b l e 2.9 lists the key parameters of the integrated ieee 802.15.4-2003 transmitter on the em346. transmit measurements were collected with the silicon labs em346 ceramic balun reference design (version a0) a t 2440 mhz. the typical number indicates one standard deviation below the mean, measured at room tem per ature (25 ? ? c ). the min and max numbers were measured over process corners at room temperature. in ter ms of impedance, this reference design presents a 3n3 inductor in parallel with a 100:50 ? balun to the rf pins. table 2.9. transmit characteristics parameter test condition min typ max unit maximum output power ? (boost mode) at highest boost mode power setting (+8) ? 8 ? dbm maximum output power at highest normal mode power setting (+3) 1 5 ? dbm minimum output power at lowest power setting ? ?55 ? dbm error vector magnitude ? (offset-evm) as defined by ieee 802.15.4-2003, whic h sets a 35% maximum ? 5 15 % carrier frequency error ?40 ? +40 ppm psd mask relative 3.5 mhz away ?20 ? ? db psd mask absolute 3.5 mhz away ?30 ? ? dbm
em346 rev 1.0 19 figure 2.4 shows the variation of transmit power with temper ature for ma ximum boost mode power, and normal mode for a typical chip. figure 2.4. transmit power vs. temperature
em346 20 rev 1.0 2.7.3. synthesizer ta b l e 2.10 lists the key parameters of the integrated synthesizer on the em346. table 2.10. synthesizer characteristics measured on silicon labs? em357 reference design with t a = 25 c and v dd = 3 v, unless otherwise noted. parameter test condition min typ max unit frequency range 2400 ? 2500 mhz frequency resolution ? 11.7 ? khz lock time from off ? ? 100 s relock time channel change or rx/tx turnaround (ieee 802.15.4-20 03 defines 192 s t ur naround time) ? ? 100 s phase noise at 100 khz offset ? ?75 ? dbc/hz phase noise at 1 mhz offset ? ?100 ? dbc/hz phase noise at 4 mhz offset ? ?108 ? dbc/hz phase noise at 10 mhz offset ? ?114 ? dbc/hz
em346 rev 1.0 21 3. functional description the em346 is a fully integrated system-on-chip that integrates a 2.4 ghz, ieee 802.15.4-2003-compliant transceiver, 32-bit arm ? cortex-m3 microprocessor, flash and ram me mory, and peripherals of use to designers of zigbee-based rf4ce systems. the transceiver uses an efficient architecture t hat exceeds th e dynamic range requiremen ts imposed by the ieee 802.15.4-2003 standard by over 15 db. the integrated rece ive channel filteri ng allows for robust co-existence with other communication standards in the 2.4 ghz spectrum, such as ieee 8 02.11-2007 and bluetoot h. the integrated regulator, vco, loop filter, and po wer amplifier keep the external component count low. an optional high performance radio mode (boost mode) is so ftware-selectable to boost dynamic range. the integrated 32-bit arm ? cortex ? -m3 microprocessor is highly optimized for high performance, low power consumption, and efficient memory ut ilization. including an integrated mpu, it supports two different modes of operation?privileged mode and user mo de. this architecture could allow fo r separation of the networking stack from the application code, and prevents unwanted modi fication of restricted area s of memory and registers resulting in increased stability and reliability of deployed solutions. the em346 has 192 kb of embedded flash memory. it has 12 kb of in tegrated ram for data and program storage. the ember software for the em346 employs an effective we ar-leveling algorithm that optimizes the lifetime of the embedded flash. to maintain the strict timing requirements imposed by the zigbe e rf4ce and ieee 802.15.4-2003 standards, the em346 integrates a number of mac functions, aes128 en cryption accelerator, and automatic crc handling into the hardware. the mac hardware handles automatic ack tr ansmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. the ember packet trace interface is also integrated with the mac, a llowing complete, non-intrusive capture of all packets to and from the em346 with ember development tools. the em346 offers a number of advanced power managem e n t features that enable long battery life. a high- frequency internal rc oscillator allows the processor core to begin code execution quickly upon waking. various deep sleep modes are available with less than 1 a powe r consumption while retainin g ram contents. to support user-defined applications, on-chip peripherals include ua rt, spi (slave only), as well as up to 16 gpios. additionally, an integrated voltage regulator, power -on-reset circuit, and sleep timer are available. finally, the em346 utilizes standard serial wire and jt ag interfaces fo r powerful sof t ware debugging and programming of the arm cortex ? -m3 core. the em346 integrates the st andard arm system debug components: flash patch and breakpoint (fpb), data watchpoint and tr ace (dwt), and instrumentation trace macrocell (itm). target applications for the em346 include the following: ?? rf4ce ?? home automation and control ?? security and monitoring ?? general zibbee wireless sensor networking ? the technical data sheet details the em346 features availa ble to customers using it with ember software.
em346 22 rev 1.0 figure 3.1 shows a detailed block diagram of the em346. figure 3.1. em346 block diagram the em346 radio receiver is a low-if, super-heterodyne rece iver. the architecture has been chosen to optimize co- existence with other devices in the 2.4 ghz band (namely wi-fi and bluetooth), and to minimize power co ns umption. the receiver uses differential signal paths to reduce sensitivity to noise interference. following rf amplification, the signal is downconv erted by an image-rejecting mixer, filtered, and then digitized by an adc. the digital section of the receiver uses a coherent demo dula t or to generate symbols for the hardware-based mac. the digital receiver also contains the analog radio calibra tion routines, and controls the gain within the receiver path. the radio transmitter uses an efficient architecture in which the dat a stream directly modulates the vco frequency. an integrated pa provides the output power. digital logi c controls tx path and out put power calibration. if the em346 is to be used with an external pa, use the tx_a ctive or ntx_active signal to control the timing of the external switching logic. the integrated 4.8 ghz vco and loop filter minimize off-chip circuitry. only a 24 mhz crystal with its loading cap a citors is required to estab lish the pll local oscillator signal. the mac interfaces the on-chip ram to the rx and tx baseband modules. the mac provides hardware-based ieee 802.15.4-2003 p acket-le vel filtering. it supplies an accurate symbol time ba se that minimizes the synchronization effort of the ember software and meets the protocol timing requirements. in addition, it provides timer and synchroniz ation assistance for the ieee 802 .15.4-2003 csma-c a algorithm. the em346 integrates hardware support for a packet trac e mod u le, which allows robust packet-based debug. this element is a critical component of ember desktop, the ember development environmen t, and provides advanced network debug capability when used with the ember debu g adapter (isa3). the em346 integrates an arm ? cortex tm -m3 microprocessor, revision r1p1. this industry-leading core provides 32-bit performance and is very power-efficien t. it has excellent code density using the arm ? thumb-2 instruction adc rf_p,n program flash 192kb data sram 12kb hf crystal osc lf crystal osc serial wire and jtag debug internal lf rc-osc gpio multiplexor switch chip manager 1.8v regulator bias 2 nd level interrupt controller rf_tx_alt_p,n osca oscb encryption acclerator if always powered domain arm ? cortex-m3 tm cpu with nvic and mpu vreg_out watchdog pa select lna pa pa dac mac + baseband sleep timer bias_r por nreset gpio registers uart/spi synth internal hf rc-osc tx_active swclk, jtck calibration adc packet trace cpu debug tpiu/itm/ fpb/dwt 1.25v regulator vdd_core pa4 pa5 pa7 pb0 pc5 pc4 pc3 pc2 pc1 pc0 pb4 pb3 pb2 pb1 pc6 pc7
em346 rev 1.0 23 set. the processor can be operated at 12 or 24 mhz when using the high-frequency crystal oscillator , or at 6 mhz or 12 mh z when using the high-f requency internal rc oscillator. the em346 has 192 kb of flash memory. the chip has 12 kb of ram on-chip, and the arm configurable memory protection unit (mpu). the em346 implements both the arm serial wire and jtag debug interfaces. these interfaces provide real time, non-intrusiv e program ming and debugging capa bilities. serial wire and jtag pr ovide the same functionality, but are mutually exclusive. the serial wire interface uses two pins; the jtag interface uses five. serial wire is preferred, since it uses fewer pins. the em346 contains 16 gpio pins shared with other periphe ra l or alternate function s. the integrated serial controller sc1 can be configured for spi (master or slave) or uart operation. the em346 contains four osc illators: a high-frequency 24 mhz external crystal oscilla tor, a high-frequency 12 mhz internal rc oscillator , an op tional low-frequency 32.768 khz external crystal oscillator, and a low-frequency 10 khz internal r c oscillator . the em346 has an ultra low power, deep sleep state with a ch oice of clocking modes. the sleep timer can be clocked with either the external 32.768 khz crystal oscillator or with a 1 khz cl ock derived from the internal 10 k h z rc oscillator. alternatively, all clocks can be disabled fo r the lowest power mode. in the lowest power mode, only external events on gpio pins will wake up the chip. the em346 has a fast startup time (typically 110 s) from deep slee p to the execution of the first arm ? cortex tm -m3 instruction. the em346 contains three power domains. the always-on hi gh voltage supply powers the gpio pads and critical chip functions. regulated low voltage supplies power the rest of the chip. the low voltage supplies are disabled during deep sleep to reduce power consumption. integrated voltage regulators generate regulated 1.25 v and 1. 8 v voltages from an unregulated supply voltage. the 1.8 v regulator output is decoupled and routed externally to sup p ly analog blocks, ram, and flash memories. the 1.25 v regulator output is decoupled externally and supplies the core logi c .
em346 24 rev 1.0 4. radio module the radio module consists of an analog front end and digital baseband as shown in figure 3.1 on page 22 . 4.1. receive (rx) path the rx path uses a low-if, super-heterodyne receiver that rejects the image frequency using complex mixing and polyphase filtering. in the analog domain, the input rf signal from the antenna is first amplified and mixed down to a 4 mhz if frequency. the mixers? out put is filtered, co mbined, and amplifie d before being sampled by a 12 msps adc. the digitized signal is then demodulated in the digi tal baseband. the filtering wi thin the rx path improves the em346?s co-existence wit h other 2.4 ghz transceivers such as zig bee/ 802.15 .4-2003, ieee 802. 11-2007, and bluetooth radios. the digital baseband also provides gain c ontrol of the rx path, both to enable the reception of small and large wanted signals and to tolerate large interferers. 4.1.1. rx baseband the em346 rx digital baseband implements a coher ent dem odulator for optimal performance. the baseband demodulates the o-qpsk signal at the chip level and synch ronizes with the ieee 802.15.4-2003 -defined preamble. an automatic gain control (agc) module adjusts the analog gain continuously every ? symbol until the preamble is detected. once detected, the gain is fixed for the remainder of the packet. the baseband despreads the demodulated data into 4-bit symbols. these symbols are buffered and passed to the hardware-based mac module for packet assembly and filtering. in addition, the rx baseband provides the calibration and c o ntrol interface to the analog rx modules, including the lna, rx baseband filter, and modulati on modules. the ember software includes calibration algorithms that use this interface to re duce the effects of silicon pr ocess and temper ature variation. 4.1.2. rssi and cca the em346 calculates the rssi over every 8-symbol period as well a s at the end of a received packet. the linear range of rssi is specified to be at least 40 db over temperature. at room temper ature, the linear range is approximately 60 db (?90 dbm to ?30 dbm input signal). the em346 rx baseband provides support for the ieee 802.15 .4-2003 rss i cca method. clear channel reports busy medium if rssi exceeds its threshold. 4.2. transmit (tx) path the em346 tx path produces an o- qpsk-modulated signal usin g the analog front end and digital baseband. the area- and power-efficient tx architecture uses a tw o-point modulation scheme to modulate the rf signal generated by the synthesizer. the modulated rf signal is fed to the integrated pa and then out of the em346. 4.2.1. tx baseband the em346 tx baseband in the digital domain spreads the 4-bit symbol into it s i eee 802.15.4-20 03-defined 32- chip sequence. it al so provides the interface for th e ember sof tware to calibrate th e tx module to reduce silicon process, temperature, and voltage variations. 4.2.2. tx_active and ntx_active signals for applications requiring an external pa, two signal s ar e pro vided called tx_active and ntx_active. these signals are the inverse of each other. they can be us ed for external pa power management and rf switching logic. in transmit mode the tx baseband drives tx_active high, as described in ta b l e 7.4 on page 55 . in receive mode the tx_active signal is low. tx_active is the alte r nate fu nction of pc5, and ntx_active is the alternate function of pc6. see "7. gpio (general purpose input/ output )" on page 48 for details of the alternate gpio functions. the digital i/o that pr ovide these signals have a 4 ma output sink and source capa bility. 4.3. calibration the ember software calibrates the radio using dedicated hardware resources.
em346 rev 1.0 25 4.4. integrated mac module the em346 integrates most of the ieee 802.15.4-2003 mac requirements in hardware. this allows the arm ? cortex tm -m3 cpu to provide greater bandwidth to application and network operations. in addition, the hardware acts as a first-line filter for unwanted packets. the em34 6 mac uses a dma interface to ram to further reduce the overall arm ? cortex tm -m3 cpu interaction when transmitting or receiving packets. when a packet is ready for transmission, the ember soft ware configures the tx mac dma by indicating the packet buffer ram location. the mac waits for the backoff period, then switches the baseband to tx mode and performs channel assessment. when the channel is clear the mac reads data from the ram buffer, calculates the crc, and provides 4-bit symbols to the baseband. when the final byte has been read and sent to the baseband, the crc remainder is read and transmitted. the mac is in rx mode most of the time. in rx mode va r i ous format and address filters keep unwanted packets from using excessive ram buffers, and prevent the cpu fr om being unnecessarily interrupted. when the reception of a packet begins, the mac reads 4-bit symbols from the baseband and calculates the crc. it then assembles the received data for storage in a ram buffer. rx mac dma provides direct access to ram. once the packet has been received additional data, which provides statistica l information on the packet to the ember software, is appended to the end of the packet in the ram buffer space. the primary features of the mac are as follows: ?? crc generation, append ing, and checking ?? hardware timers and interrupts to achieve the mac symbol timing ?? automatic preamble and sfd pre-pending on tx packets ?? address recognition and packet filtering on rx packets ?? automatic acknowledgment transmission ?? automatic transmission of packets from memory ?? automatic transmission after backoff time if channel is clear (cca) ?? automatic acknowledgment checking ?? time stamping received and transmitted messages ?? attaching packet information to received packets (l qi, rssi, gain, time stamp, and packet status) ?? ieee 802.15.4-2003 timing a nd slotted/unslotted timing 4.5. packet trac e interface (pti) the em346 integrates a true phy-level pti for effective network-level debugging. it monitors all the phy tx and rx packets between the mac and baseband modules without af fecting their normal operation. it cannot be used to inject packets into the ph y/mac interface. this 500 kbps asynchronous interface comprises the frame signal (pti_en, pa4) and the data signal (pti_data, pa5) . pti is supported by the ember development tools. 4.6. random number generator thermal noise in the analog circuitry is digitized to provide entropy for a true random number generator (trng). the trng produces 16-bit uniformly distributed numbers. the ember software uses the trng to seed a pseudo random number generator (prng). the trng is also used directly for cryptographic key generation.
em346 26 rev 1.0 5. arm ? cortex?-m3 and memory modules this chapter discusses the arm ? cortex tm -m3 microprocessor, and reviews the em346?s flash and ram memory modules as well as the memo ry protection unit (mpu). 5.1. arm ? cortex?-m3 microprocessor the em346 integrates the arm ? cortex tm -m3 microprocessor, revision r1p1, developed by arm ltd., making the em346 a true system-on-chip solution. the arm ? cortex tm -m3 is an advanced 32-bit modified harvard architecture processor that has separate internal program and data bu ses, but presents a unified program and data address space to software. the word width is 32 bi ts for both the program and data sides. the arm ? cortex tm -m3 allows unaligned word and half-word data accesses to support efficiently-packed data structures. the arm ? cortex tm -m3 in the em346 has also been enhanced to s upport two separate memory protection levels. basic protection is available without using the mpu, but normal operation uses the mpu. the mpu allows for protecting unimplemented areas of the memory map to prevent common software bugs from interfering with software operation. the architecture could also allow for separation of the networking stack from the application code using a fine granularity ram protection module. errant writes are captured and details are reported to the developer to assist in tracking down and fixing issues. 5.2. embedded memory figure 5.1 shows the em346 arm ? cortex tm -m3 memory map.
em346 rev 1.0 27 figure 5.1. em346 arm ? cortex tm -m3 memory map 5.2.1. flash memory main flash block (192kb) lower mapping (normal mode) 0x00000000 0x0002ffff ram (12kb) mapped onto system interface 0x20000000 0x20002fff ram bit band alias region mapped onto system interface (not used) 0x22000000 0x22002000 flash ram peripheral registers mapped onto system interface register bit band alias region mapped onto system interface (not used) 0x40000000 0x40000xxx 0x42000000 0x42002xxx not used private periph bus (internal) not used private periph bus (external) not used not used not used 0xe0000000 itm dwt fpb nvic tpiu rom table 0xe0001000 0xe0002000 0xe0003000 0xe000e000 0xe000f000 0xe003ffff 0xe0040000 0xe0041000 0xe0042000 0xe00ff000 0xe00fffff 0xe0000000 0x00000000 0x20000000 0x40000000 0x60000000 0xa0000000 0xffffffff 0xdfffffff 0x9fffffff 0x5fffffff 0x3fffffff 0x1fffffff fixed info block (2kb) 0x08040000 0x080407ff 0x08040fff 0x08040800 main flash block (192kb) upper mapping (boot mode) 0x08000000 0x0802ffff fixed info block (2kb) optional boot mode maps fixed info block to the start of memory 0x000007ff not used not used customer info block (2kb)
em346 28 rev 1.0 5.2.1.1. flash overview the em346 provides a total of 192 kb of flash memory. the flash memory is provide d in three separate blocks: ?? main flash block (mfb) ?? fixed information block (fib) ?? customer information block (cib) ? the mfb is divided into 2048-byte pages. the em346 has 96 pages . the cib is a single 2048-byte page. the fib is a single 2048-byte page. the smallest erasable unit is one page and the smallest writable unit is an aligned 16- bit half-word. the flash is rated to have a guaranteed 20,000 write/erase cycles. the flash cell has been qualified for a data retention time of >100 years at room temperature. flash may be programmed either through the serial wire/jtag interface or through bootloader software. programming flash thro ugh s erial wire/jtag requires the assistan ce of ram-based utilit y code. programming through a bootloader requires ember software for over-the-air loading or serial link loading. 5.2.1.2. main flash block the start of the mfb is mapped to both address 0x00000000 and address 0x08000000 in normal boot mode, but is ma pp ed only to address 0x08000000 in fib monitor mode (see also "7.5. boot configuration" on page 51 ). consequently, it is recommended that software intended to execu t e from the mfb is designed to operate from the upper address, 0x08000000, sinc e this address mapping is always available in all modes. the mfb stores all program instructions and constant data . a small p o rtion of the mfb is devoted to non-volatile token storage using the em ber simulated eeprom system. 5.2.1.3. fixed information block the 2 kb fib is used to store fixed manufacturing data in clud ing serial numbers and calibration values. the start of the fib is mapped to address 0x08040000. this block can only be programmed during production by silicon labs. the fib also contains a monitor program, which is a seri al-link-only way of performin g low -level memory accesses. in fib monitor mode (see "7.5. boot configuration" on page 51 ), the start of the fib is mapped to both address 0x00000000 and address 0x08040000 so the monitor may be executed out of reset. 5.2.1.4. customer information block the 2048 byte cib can be used to store customer data. th e st art of the cib is mapped to address 0x08040800. the cib cannot be executed. the first eight half-words of the cib are de dicated to special storage called option bytes. an option byte is a 16 bit quantity of flash where the lower 8 bits contain the data and the upper 8 contain the inverse of the lower 8 bits. the upper 8 bits are automatically generated by hardwa re and cannot be written to by the user, see ta b l e 5.1 . the option byte hardware also verifies the inverse of ea ch op tio n byte when exiting from reset and generates an error, which prevents the cpu from executing code, if a disc repancy is found. all of this is transparent to the user.
em346 rev 1.0 29 ta b l e 5.2 shows the mapping of the option bytes that are used for read and write prot ection of the flash. each bit of the flash write protection option bytes pr ote c ts a 4 page region of the main flash block. the em346 has 24 regions and therefore option bytes 4, 5, and 6 control flash write protecti on.these write protection bits are active low, and therefore the erased state of 0xff disabl es write protection. like read protection, write protection only takes effect after a reset. write protection not only prevents a write to the region, but also prevents page erasure. option byte 0 controls flash read protecti on. whe n option byte 0 is set to 0xa5, read protection is disabled. all other values, including the erased state 0xff, enable read protection when coming out of reset. the internal state of read protection (active versus disabled) can only be changed by applying a full chip reset. if a debugger is connected to the em346, the intrusion state is latched. read protection is combined with this latched intrusion signal. when both read protection and intrusion are set, all flash is disconn ected from the internal bus. as a side effect, the cpu cannot execute code since all flash is disconnected from the bus. this functionality prevents a debug tool from being able to read the contents of any flash. the only me ans of clearing the intrusion signal is to disconnect the debugger and re set the entire chip usi ng the nreset pin. by requiring a chip reset, a debugger cannot install or execute malicious code that could allow the contents of the flash to be read. the only way to disable read protection is to program option byte 0 with the value 0xa5. option byte 0 must be er as ed before it can be programmed. erasing option byte 0 while read protection is active automatically mass- erases the main flash block. by automatically erasing ma in flash, a debugger cannot disable read protection and readout the contents of main flas h without destroying its contents. when read protection is active, the bottom four fl ash p ages, addresses 0x08000000 to 0x08001fff, are automatically write-protected. write protecting the bottom fo ur flash pages of main flash prevents an attacker from reprogramming the reset vector and executing arbitrary code. in general, if read protection is active then wr ite protection shoul d also be active. this prevents an attacker from reprogramming flash with malicious code that could readout the flash after the debugger is disconnected. even though read protection automatically protects the reset vector, the same technique of reprogramming flash could be performed at an address outside the bottom four flas h pages. to obtain fully protected flash, both read protection and write protection should be active. table 5.1. option byte storage address bits [15:8] bits [7:0] notes 0x08040800 inverse option byte 0 option byte 0 configures flash read protection 0x08040802 inverse option byte 1 option byte 1 reserved 0x08040804 inverse option byte 2 option byte 2 available for customer use 1 0x08040806 inverse option byte 3 option byte 3 available for customer use 1 0x08040808 inverse option byte 4 option byte 4 configures flash write protection 0x0804080a inverse option byte 5 option byte 5 configures flash write protection 0x0804080c inverse option byte 6 option byte 6 configures flash write protection 0x0804080e inverse option byte 7 option byte 7 reserved notes: 1. option bytes 2 and 3 do not link to any specific har dw are functionality other than the option byte loader. therefore, they are best used for storing data that requires a hardware verification of the data integrity.
em346 30 rev 1.0 table 5.2. option byte write protection bit map option byte bit notes option byte 0 bit [7:0] read protection of all flash (mfb, fib, cib) option byte 1 bit [7:0] reserved for silicon labs use option byte 2 bit [7:0] available for customer use option byte 3 bit [7:0] available for customer use option byte 4 bit [0] write protection of address ra nge 0x08000000 ? 0x08001fff bit [1] write protection of address ra nge 0x08002000 ? 0x08003fff bit [2] write protection of address ra nge 0x08004000 ? 0x08005fff bit [3] write protection of address ra nge 0x08006000 ? 0x08007fff bit [4] write protection of address ra nge 0x08008000 ? 0x08009fff bit [5] write protection of address ra nge 0x0800a000 ? 0x0800bfff bit [6] write protection of address ra nge 0x0800c000 ? 0x0800dfff bit [7] write protection of address ra nge 0x0800e000 ? 0x0800ffff option byte 5 bit [0] write protection of address ra nge 0x08010000 ? 0x08011fff bit [1] write protection of address ra nge 0x08012000 ? 0x08013fff bit [2] write protection of address ra nge 0x08014000 ? 0x08015fff bit [3] write protection of address ra nge 0x08016000 ? 0x08017fff bit [4] write protection of address ra nge 0x08018000 ? 0x08019fff bit [5] write protection of address ra nge 0x0801a000 ? 0x0801bfff bit [6] write protection of address ra nge 0x0801c000 ? 0x0801dfff bit [7] write protection of address ra nge 0x0801e000 ? 0x0801ffff option byte 6 bit [0] write protection of address ra nge 0x08020000 ? 0x08021fff bit [1] write protection of address ra nge 0x08022000 ? 0x08023fff bit [2] write protection of address ra nge 0x08024000 ? 0x08025fff bit [3] write protection of address ra nge 0x08026000 ? 0x08027fff bit [4] write protection of address ra nge 0x08028000 ? 0x08029fff bit [5] write protection of address ra nge 0x0802a000 ? 0x0802bfff bit [6] write protection of address ra nge 0x0802c000 ? 0x0802dfff bit [7] write protection of address ra nge 0x0802e000 ? 0x0802ffff option byte 7 bit [7:0] reserved for silicon labs use
em346 rev 1.0 31 5.2.1.5. simulated eeprom ember software reserves 8 kb of the main flash block as a simu late d eeprom storage area for stack and customer tokens. the simula ted eeprom storage area im plements a wear-leveling algorithm to extend the number of simulated eeprom write cycles beyond the phys ical limit of 20,000 write cycles for which each flash cell is qualified. 5.2.2. ram 5.2.2.1. ram overview the em346 has 12 kb of static ram on-chip. the star t of ram is m apped to addre ss 0x20000000. although the arm ? cortex tm -m3 allows bit band accesses to this address region, the standard mpu configuration does not permit use of the bit-band feature. the ram is physically connected to the ahb system bu s and is therefore accessible to both the arm ? cortex tm - m3 microprocessor and the debugger. the ram can be access ed for both instruction and data fetches as bytes, half words, or words. the standard mpu configuration doe s not permit execution from the ram, but for special purposes the mpu may be disabled. to the bus, the ram appears as 32-bit wide memory and in most situations has zero wait state read or write access. in the higher cp u clock mode the ram requires two wait states. this is handled by hardware transparent to the user application with no configuration required. 5.2.2.2. direct memory access (dma) to ram several of the peripherals are equipped with dma controllers allowing them to transfer data into and out of ram a u tonomously. this applies to the radio (802.15.4-2003 ma c) and serial controller. in the case of the serial controller, the dma is full duplex so that a read and a wr ite to ram may be requested at the same time. thus there are six dma channels in total. see "8.5. dma channels" on page 86 and "10.1.4. dma" on page 173 for a description of how to configure the serial controller for d m a operation. th e dma channels do not use ahb system bus bandwidth as they access the ram directly. the em346 integrates a dma arbiter that ensures fair a ccess to the micro processor as well as the peripherals through a fixed priority scheme appropriate to the memory bandwidth requirements of each master. the priority scheme is as follows, with the top peri pheral being the highest priority: 1. mac 2. serial controller 1 receive 3. serial controller 1 transmit 5.2.2.3. ram memory protection the em346 integrates two memory protection mechanisms . the first memory protection mechanism is through the arm ? cortex tm -m3 memory protection unit (mpu) described in ?5.3. memory protection unit? . the mpu may be used to protect any area of memory. mpu configuratio n is normally handled by ember software. the second memory protection mechanism is through a fine granularit y ram protection module. this allows segmentation of the ram into 32-byte blocks where any block can be marked as write protected. an attempt to write to a protected ram block using a user mode write results in a bus erro r being signaled on the ahb system bus. a privileged mode write is allowed at any time and reads are allowed in either mode. the main purpose of this fine granularity ram protection module is to notify the software of erroneo us writes to system areas of memory. ram protection is configured using a group of registers that provide a bit m ap. each bit in the map represents a 32-byte block of ram. when the bit is set the block is write-protected. the fine granularity ram memory protection mechanism is also a v ailable to the peripheral dma controllers. a register bit enables protection from dma writes to protected memory. if a dma wr ite is made to a protected location in ram, a management interrupt is generated. at the same time the faulting address and the identification of the peripheral is captured for later debugging. note that only peripherals capable of writing data to ram, such as received packet data or a received serial port character, can generate this interrupt.
em346 32 rev 1.0 5.2.3. registers appendix a, register address table provides a short desc ription of all application-acce ssible registers within the em346. complete descriptions are provided at the end of each applicable peripheral?s description. the registers are mapped to the system address space starting at address 0x40000000. these registers allow for the control and configuration of the various peripherals and modules. the cpu only performs word-aligned accesses on the system bu s. the cpu performs a word aligned read-modify-w rite for all byte, half-word, and unaligned writes and a word-aligned read for all reads. s ilicon labs recommends accessing all peri pheral registers using word-aligned addressing. as with the ram, the peripheral registers fall within an ad dr ess range that allows for bit-band access by the arm ? cortex tm -m3 , but the standard mpu configuration does not allow access to this alias address range. 5.3. memory protection unit the em346 includes the arm ? cortex tm -m3 memory protection unit, or mpu. the mpu controls access rights and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions. refer to the arm ? cortex tm -m3 technical reference manual (ddi 0337a) for a detailed description of the mpu. ember software configures the mpu in a standard configur ation a nd application software should not modify it. the configuration is designed for optimal detection of illegal instruction or data access es. if an illegal access is attempted, the mpu captures information about the access type, the address being accessed, and the location of the offending software. this simplifies software debugging and increases the re liability of deployed devices. as a consequence of this mpu configuration, accessing ram and register bit-band address alias regions is not permitted, and generates a bus fault if attempted.
em346 rev 1.0 33 6. system modules system modules encompass power domains, resets, cloc ks, system timers, power management, and encryption. figure 6.1 shows these modules and how they interact. figure 6.1. system module block diagram nreset vdd_pads vreg_out vdd_core vdd_mem por hv por lvcore por lvmem vreg_1v8 vreg_1v25 always-on supply mem supply core supply por lv por hv reset filter reset generation external regulator optional connections for external regulator oscrc osc32k div10 clk1k clk32k osc32a osc32b jrst always-on domain poreset sysreset dapreset mem domain arm? cortex ? -m3 debug ahb-ap sysresetreq core domain arm? cortex ? -m3 cpu flitf option byte error flash ram osc24m oschf osca oscb clock switch sysclk cdbgrstreq power management watchdog sleep timer watchdog deep sleep wakeup reg_en recomended connections for internal regulator preset hv preset lv registers registers security accelerator swj reset recording wakeup recording gpio wake monitoring pb2 irqd sleep timer compare b wake_core cdbgpwrupreq csyspwrupreq sleep timer compare a sleep timer wrap
em346 34 rev 1.0 6.1. power domains the em346 contains three power domains: ?? an ?always-on domain? containing all logic and analog cells required to manage the em346?s power modes, including the gpio controller and sleep timer. this domain must remain powered. ?? a ?core domain? containing the cpu, nested vectored interrupt controller (nvic), and peripherals. to save power, this domain can be powered down using a mode called deep sleep. ?? a ?memory domain? containing the ram and flash memories. this domain is managed by the power management controller. when in deep sleep, the ram po rtion of this domain is powered from the always- on domain supply to retain the ram contents while the regulators are disabled. during deep sleep the flash portion is completely powered down. 6.1.1. internally regulated power the preferred and recommended power configuration is to use the internal regulated power supplies to provide p o wer to the core and memory domains. the internal regulators (vreg_1v25 and vreg_1v8) generate nominal 1.25 and 1.8 v supplies. the 1.25 v supply is internally routed to the core domain and to an external pin. the 1.8 v su pp ly is routed to an external pin where it can be externally routed back into the chip to supply the memory domain. the internal regulators are described in "14. integrated voltage regulator" on page 117 . when using the internal regulators, the always-on domain must be powered between 2.1 and 3.6 v at all four vdd_p ads pins. whe n using the internal regulators, the vreg_1v8 regulator outpu t pin (vreg_out) must be connected to the vdd_mem, vdd_padsa, vdd_vco, vdd_rf, vdd_if, vdd_pre, and vdd_synth pins. when using the internal regulators, the vreg_1v25 regu lator ou tput and supply re quires a connection between both vdd_core pins. 6.1.2. externally regulated power optionally, the on-chip regulators may be left unused, and the core and memory domains may instead be powered fro m external supplies. for simplicity, the voltage for the core domain can be raised to nominal 1.8 v, requiring only o ne exter nal regulator, or the core domain can be powered from the on-chip regulators while the other domains are powered externally. note that if the core domain is powered at a higher voltage (1.8 v instead of 1.25 v) then po we r consumption increases. a regulator enable signal, re g_en, is provided for contro l of external regulators. this is an open-drain signal that requires an external pull- up resistor. if reg_en is not required to control external regulators it can be disabled (see "7.3. forced functions" on page 50 ). using an external regulator requires the always-on domain to be powered between 2.1 and 3.6 v at all four vdd_p ads pins. whe n using an external regulator, th e vreg _1v8 regulator output pin (v reg_out) must be left unconnected. when using an external regulator, this external nominal 1.8 v supply ha s to be connected to both vdd_core pins and to the vdd_mem, vdd_pad sa, vdd_vco, vdd_rf, vdd_if, vdd_pre and vdd_synth pins.
em346 rev 1.0 35 6.2. resets the em346 resets are generated from a number of sources. each of these reset source s feeds into central reset detection logic that causes various parts of the system to be reset depending on the state of the system and the nature of the reset event. 6.2.1. reset sources 6.2.1.1. power-on-resets (por hv and por lv) the em346 measures the voltage levels supplied to the three power domains. if a supply voltage drops below a lo w thr eshold, then a reset is applied. the reset is released if the supply voltage rises above a high threshold. there are three detection circuits for power-on-reset as follows: ?? por hv monitors the always -on domain supply voltage. thresholds are given in ta b l e 6.1 . ?? por lv core monitors the core domain supply voltage. thresholds are given in ta b l e 6.2 . ?? por lv mem monitors the memory supply voltage. thresholds are given in ta b l e 6.3 . the por lvcore and por lvmem reset sources are merged to provide a single reset source, por lv, to the reset ge ner ation module, since the detection of eith er event needs to reset the same system modules. table 6.1. por hv thresholds parameter test conditions min typ max unit always-on domain release 0.62 0.95 1.20 v always-on domain assert 0.45 0.65 0.85 v supply rise time from 0.5 v to 1.7 v 250 s table 6.2. por lvcore thresholds parameter test conditions min typ max unit 1.25 v domain release 0.9 1.0 1.1 v 1.25 v domain assert 0.8 0.9 1.0 v table 6.3. por lvmem thresholds parameter test conditions min typ max unit 1.8 v domain release 1.35 1.5 1.65 v 1.8 v domain assert 1.26 1.4 1.54 v
em346 36 rev 1.0 6.2.1.2. nreset pin a single active low pin, nreset, is provided to reset the sys tem. this pin has a schmitt triggered input. to afford good noise immunity and resistance to switch bounc e, the pin is filtered with the reset filter module and g enerates the pin reset source, nreset, to the reset generation module. ta b l e 6.4 contains the specification for the filter. 6.2.1.3. watchdog reset the em346 contains a watchdog timer (see also "6.4.1. watchdog timer" on page 43 ) that is clocked by the internal 1 khz timing reference. when the timer expires it g ene rates the reset source watchdog_reset to the reset generation module. 6.2.1.4. software reset the arm ? cortex tm -m3 cpu can initiate a reset unde r software control. this is indicated with the reset source sysresetreq to the reset generation module. 6.2.1.5. option byte error the flash memory controller contains a st ate machin e that reads configurat ion information from the information blocks in the flash at system start time. an error check is performed on the option bytes that are read from flash and, if the check fails, an error is signaled that provides the reset source opt_byte_error to the reset generation module. if an option byte error is detected, the system restarts and the read and check process is repeated. if the error is de te cted again the process is repeated but stops on the 3 rd failure. the system is then placed into an emulated deep sleep where recovery is possible. in this state, flas h memory readout protection is forced active to prevent secure applications from being compromised. 6.2.1.6. debug reset the serial wire/jtag interface (swj) provides access to th e swj de bug port (swj-dp) registers. by setting the register bit cdbgrstreq in the swj-dp, the reset s ource cdbgrstreq is provided to the reset generation module. 6.2.1.7. jrst one of the em346?s pins can function as th e jt ag reset, conforming to th e requirements of the jtag standard. this input acts independently of all other reset sources and, when asserted, does not reset any on-chip hardware except for the jtag tap. if the em346 is in the serial wire mode or if the swj is disabled, this input has no effect. table 6.4. reset filter specification for nreset parameter min typ max unit reset filter time constant 2.1 12.0 16.0 s reset pulse width to guarantee a reset 26.0 ? ? s reset pulse width guaranteed not to cause a reset 0 ? 1.0 s
em346 rev 1.0 37 6.2.1.8. deep sleep reset the power management module informs the reset generation module of entry into and exit from the deep sleep states. the deep sleep reset is applied in the following st ates: before entry into deep sleep, while removing power from the memory and core domain, while in deep sleep, while waking from deep sleep, and while reapplying power until reliable power levels ha ve been detect by por lv. the power management module allows a special emulated deep sleep state that retains memory and core domain power while in deep sleep. 6. 2.2. reset recording the em346 records the last reset condition that generated a restart to the system. the reset conditions recorded ar e as follows: ?? por hv always-on domain power supply failure ?? por lv core domain (por lvcore) or memory domain (por lvmem) power supply failure ?? nreset pin reset asserted ?? watchdog watchdog timer expired ?? sysresetreq software reset by sysersetreq from arm ? cortex tm -m3 cpu ?? deep sleep wakeup wake-up from deep sleep ?? option byte error error check failed when reading option bytes from flash ? note: while cpu lockup is shown as a reset condition in software, cpu lockup is not specifically a reset event. cpu lockup is set to indicate that the cpu entered an unrecoverable exception. execution stops but a reset is not applied. this is so that a debugger can interpret the cause of the error. silicon labs recommends that in a live application (in other words, no debugger attached) the watchdog be enabled by default so that the em346 can be restarted. 6.2.3. reset generation module the reset generation module responds to reset sources and generates the following reset signals : ?? poreset reset of the arm ? cortex tm -m3 cpu and arm ? cortex tm -m3 system debug components (flash patch and breakpoint, data watchpoint and trace, instrumentation trace macrocell, nest ed vectored interrupt controller). arm defines poreset as the region that is reset when power is applied. ?? sysreset reset of the arm ? cortex tm -m3 cpu without resetting the core debug and system debug components, so that a live system can be reset without disturbing the debug configuration. ?? dapreset reset to the swj?s ahb access port (ahb-ap) ?? preset hv peripheral reset for always-on power domain, for peripherals that are required to ret ain their configuration across a deep sleep cycle ?? preset lv peripheral reset for core power domain, for peripherals that are not required to ret ain their configuration across a deep sleep cycle
em346 38 rev 1.0 ta b l e 6.5 shows which reset sources gene rate certain resets. 6.3. clocks the em346 integrates four oscillators: ?? 12 mhz rc oscillator ?? 24 mhz crystal oscillator ?? 10 khz rc oscillator ?? 32.768 khz crystal oscillator ? figure 6.2 shows a block diagram of the clocks in the em346. this simplified view s h ows all the clock sources and the general areas of the chip to which they are routed. table 6.5. generated resets reset source reset generation module output poreset sysreset dapreset preset hv preset lv por hv x x x x x por lv (due to waking from nor mal d eep sleep) x x x x por lv (not due to waking fr om no rmal deep sleep) x x x x x nreset x x x x watchdog x x x sysresetreq x x x option byte error x x x normal deep sleep x x x x emulated deep sleep x x debug reset x
em346 rev 1.0 39 figure 6.2. clocks block diagram pclk osc32k bus sysclk oscrc clk1k oscillator failover monitor (selects rc when xtal fails) oschf osc24m fclk cpu bus ram ctrl ram bus bus flitf flash osc24m_ctrl[0] osc24m_ctrl[1] cpu_clksel[0] st_csr[2] sleeptmr_cfg[0] sleeptmr_cfg[7:4] debug_emcr[24] 12mhz rc 24mhz xtal 10khz rc 32khz digital in /2 /2 /(2^n) oscillator sleeptmr_clken[0] 32khz xtal mac timer counter scx rategen systick counter sleep timer counter watchdog counter and traceclk digital out scxsclk digital i/o /n (nominal 10)
em346 40 rev 1.0 6.3.1. high-frequency internal rc oscillator (oschf) the high-frequency rc oscillator (osc hf) is used as the default system cl ock source when power is applied to the core domain. the nominal frequency coming out of reset is 12 mhz and ember software calibrates this clock to 12 mhz. ta b l e 6.6 contains the specification for the high frequency rc oscillator. most peripherals, excluding the radio peripheral, are fu lly fu nctional using the oschf clock source. application software must be aware that peripherals are clocked at different speeds depending on whether oschf or osc24m is being used. since the frequency step of oschf is 0.3 mhz and the high-frequency crystal oscillator is us ed for calibration, the calibra ted accuracy of oschf is 150 khz 40 ppm. the uart peripheral may not be u s able due to the lower accuracy of the oschf frequency. 6.3.2. high-frequency crystal oscillator (osc24m) the high-frequency crystal osc illator (osc 24m) r equires an external 24 mhz crystal with an accuracy of 40 ppm. based upon the applic at ion?s bill of materials and current consumpt ion requirements, the external crystal may cover a range of esr requirements. ta b l e 6.7 contains the specification for t he high frequency cry stal oscillator. the crystal oscillator has a software-pro grammable bias circuit to minimize current consumption. ember soft ware configures the bias circuit for minimum current consumption. all peripherals including the radio peripheral are fully fu nctio nal using the osc24m clock source. application software must be aware that peripherals are clocked at different speeds depending on whether oschf or osc24m is being used. if the 24 mhz crystal fails, a hardware failove r me chanism forces the system to switch back to the high-frequency rc oscillator as the main clock s ource, and a non-maskab le interrupt (nmi) is signaled to the arm ? cortex tm -m3 nvic. table 6.6. high-frequency rc oscillator specification parameter test conditions min typ max unit frequency at reset 6 12 20 mhz frequency steps ? 0.3 ? mhz duty cycle 40 ? 60 % supply dependence change in supply = 0.1 v test at supply changes: 1.8 to 1.7 v ? ? 5 %
em346 rev 1.0 41 6.3.3. low-frequency internal rc oscillator (oscrc) a low-frequency rc oscillator (oscrc) is provided as an internal timing reference. the nomina l frequency coming out of reset is 10 khz, and ember software ca librates this cloc k to 10 khz. from the tuned 10 khz oscillator (oscr c) ember software calibrates a fractional-n divider to produce a 1 khz reference clock, clk1k. table 6.8 contains the specification for the low frequenc y rc oscillator. table 6.7. high-frequency crystal oscillator specification parameter test conditions min typ max unit frequency ? 24 ? mhz accuracy ?40 ? +40 ppm duty cycle 40 ? 60 % start-up time at max bias ? ? 1 ms start up time at optimal bias ? ? 2 ms current consumption ? 200 300 a current consumption at max bias ? ? 1 ma crystal with high esr ? ? 100 ? load capacitance ? ? 10 pf crystal capacitance ? ? 7 pf crystal power dissipation ? ? 200 w crystal with low esr ? ? 60 ? load capacitance ? ? 18 pf crystal capacitance ? ? 7 pf crystal power dissipation ? ? 1 mw table 6.8. low-frequency rc oscillator specification parameter test condition min typ max unit nominal frequency after trimming 9 10 11 khz analog trim step size ? 0.5 ? khz supply dependence for a voltage drop from 3.6 v to 3.1 v or 2.6 v to 2.1 v (without re-calibration) ? 1 ? % temperature ? dependence frequency variation with temperature for a change from ?40 to +85 o c (without re-calibration) ? 2 ? %
em346 42 rev 1.0 6.3.4. low-frequency crystal oscillator (osc32k) a low-frequency 32.768 khz crystal oscillator (osc32k) is provided as an optional timing referenc e for on-chip timers. this oscillator is desig ned for use with an external watc h crystal. when using the 32.768 khz crystal, you mu st conn ect it to gpio pc6 and pc7 and must configur e these two gpios for analog input. alternatively, when pc7 is configured as a digital input, pc7 can accept an external digital clock input instead of a 32.786 khz crystal. th e d igital clock input signal must be a 1 v peak-to-peak sine wave with a dc bias of 0.5 v. refer to "7. gpio (general purpose input/output)" on page 48 for gpio configuration details. us ing the low-frequenc y oscillator, crystal or digital clock, is enabled through ember software. ta b l e 6.9 contains the specification for th e low frequency crystal oscillator. 6.3.5. clock switching the em346 has two switching mechanisms for the ma in s ystem clock, providing four clock modes. ta b l e 6.10 shows these clock modes and how t hey af fect the internal clocks. the register bit osc24m_ctrl_osc24m_sel in the osc24m _ctrl register s witches between the high- frequency rc oscillator (oschf) and th e high-frequency crystal oscillator (osc24m) as the main system clock (sysclk). the peripheral cl ock (pclk) is always half the frequency of sysclk. the register bit cpu_clksel_field in the cpu_clksel regi ster switches betwee n pclk and sysclk to produce the arm ? cortex tm -m3 cpu clock (fclk). the default and preferred mode of operation is to run the cpu at the higher pclk frequency, 24 mhz, to give higher processing pe rfor man ce for all applications and improved duty cycling for applications using sleep modes. in addition to these modes, further au to matic contr ol is invoked by hardware when flash programming is enabled. to ensure accuracy of the flash controller?s timers, the fclk frequency is forced to 12 mhz during flash p r ogramming and erase operations. table 6.9. low-frequency crystal oscillator specification parameter test conditions min typ max unit frequency ? 32.768 ? khz accuracy at 25 oc ?20 ? +20 ppm load capacitance osc32a ? 27 ? pf load capacitance osc32b ? 18 ? pf crystal esr ? ? 100 k? start-up time ? ? 2 s current consumption at 25 c, vdd_pads=3.0 v ? ? 0.5 a table 6.10. system clock modes osc24m_ctrl_osc24m_ sel cpu_clksel_ field sysclk pclk fclk flash program/ eras e in active flash program/ erase ac tive 0 (oschf) 0 (normal cpu) 12 mhz 6 mhz 6 mhz 12 mhz 0 (oschf) 1 (fast cpu) 12 mhz 6 mhz 12 mhz 12 mhz 1 (osc24m) 0 (normal cpu) 24 mhz 12 mhz 12 mhz 12 mhz 1 (osc24m) 1 (fast cpu) 24 mhz 12 mhz 24 mhz 12 mhz
em346 rev 1.0 43 6.4. system timers 6.4.1. watchdog timer the em346 integrates a watchdog timer which can be enabled to pr ovide protection ag ainst software crashes and arm ? cortex tm -m3 cpu lockup. by default, it is disabled at power up of the always-on power domain. the watchdog timer uses the calibrated 1 khz clock (clk1k ) as its reference and provides a nominal 2.048 s timeout. a low wa te r mark interrupt occurs at 1.792 s and triggers an nmi to the arm ? cortex tm -m3 nvic as an early warn ing. when the watchdog is enabled, the timer must be periodically reset before it expires. the watchdog timer is paused when the debugger halts the arm ? cortex tm -m3. additionally, the ember software that implements deep sleep functionality disables the watchdog when entering deep sleep and restores the watchdog, if it was enabled, when exiting deep sleep. ember software provides an api for enabling, resetting, and disabling the watchdog timer. 6.4.2. sleep timer the em346 integrates a 32-bit timer dedicated to system tim i ng and waking from sleep at specific times. the sleep timer can use either the calibrated 1 khz reference (clk1k), or the 32 khz crystal clock (clk32k). the default clock source is t he internal 1 khz clock. the sleep timer has a prescaler, a divider of the form 2^n, wh ere n can be programmed from 1 to 2^15. this divider allows for very long periods of sleep to be time d. ember software?s default configuration is to use the prescaler to always produce a 1024 hz sleep timer tick. the timer prov ides two co mpare outputs and wrap detection, all of which can be used to generate an interrupt or a wake up event. while it is possible to do so, by default the sleep timer is no t paused when the debugger halts the arm ? cortex tm - m3. silicon labs does not advis e pausing the sleep timer when the debugger halts the cpu. to save current during deep sleep, the low-frequency internal r c oscillator (oscrc) can be turned off. if oscrc is turned off during deep sleep and a low-frequency 32.768 khz crystal oscillator is not being used, then the sleep time r wi ll not operate during deep sleep and sleep timer wake events cannot be used to wake up the em346. ember software provides the system timer software api fo r int eracting with the sleep timer as well as using the sleep timer and rc oscilla tor during deep sleep. note: because the system timer software module handles all interactions with the sleep timer, the module will return the cor - rect value in all situations. in the situation where the chip perform s a deep sleep that ma intains the system time and is woken up from an external event (that is, not a sleep time r event), the deep sleep module in the ember software delays until the next sleep timer clock tick (up to 1 ms) to guarantee that the sle ep timer updates correctly. 6.4.3. event timer the systick timer is an arm ? standard system timer in the nvic. the systick timer can be clocked from either the fclk (the clock going into the cpu) or the sleep timer clock. fclk is ei ther the sysclk or pclk as selected by cpu_clksel register (see ?6.3.5. clock switching? ).
em346 44 rev 1.0 6.5. power management the em346?s power management system is designed to achieve the lowest deep sleep current consumption possible while still providing flexible wakeup sources, timer activity, and de bugger operation. t he em346 has four main sleep modes: ?? idle sleep: puts the cpu into an idle state where execution is suspended until any interrupt occurs. all power domains remain fully powered and nothing is reset. ?? deep sleep 1: the primary deep sleep state. in this state, the core power domain is fully powered down and the sleep timer is active. ?? deep sleep 2: the same as deep sl eep 1 except that the sleep timer is inactive to save power. in this mode the sleep timer cannot wake up the em346. ?? deep sleep 0 (also known as emulated deep sleep) : the chip emulates a true deep sleep without powering down the core domain. instead, the core domain remains powered and all peripherals except the system debug components (itm, dwt, fpb, nvic) are held in reset. the purpose of this sleep state is to allow em346 software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints. ? csyspwrupreq, cdbgpwrupreq, and the corresponding csyspw rupack and cdbgpwrupack are bits in the debug port?s ctrl/stat register in the swj. for further information on these bits and the operation of the swj-dp please refer to the arm debug interface v5 architecture specification (arm ihi 0031a). for further power savings when not in deep sleep, the seria l controller1 peripheral can be individually disabled through the peripheral_disable register. disabling a peripheral saves power by stopping the clock feeding that peripheral. a peripheral should only be disabled through the peripheral_disable register when the peripheral is idle and disabled through the peripheral's own configuration registers, otherwise undefined behavior may occur. when a peripheral is disa bled through the peripher al_disable register, all registers associated with that peripheral ignore all subsequent writes, and subse quent reads return the value seen in the register at the moment the peripheral is disabled. 6.5.1. wake sources when in deep sleep the em346 can be returned to the running state in a number of ways, and the wake sources a r e split depending on deep sleep 1 or deep sleep 2. the following wake sources are available in both deep sleep 1 and 2. ?? wake on gpio activity: wake due to change of state on any gpio. ?? wake on serial controller 1: wake due to a change of state on gpio pin pb2. ?? wake on irqd: wake due to a change of state on irqd . since irqd can be conf igured to point to any gpio, this wake source is another means of waking on any gpio activity. ?? wake on setting of cdbgpwrupreq: wake due to setting the cdbgpwrupreq bit in the debug port in the swj. ?? wake on setting of csyspwrupreq: wake due to setting the csyspwrupreq bi t in the debug port in the swj. the following sources are only available in deep sleep 1 since the sleep timer is not active in deep sleep 2. ?? wake on sleep timer compare a. ?? wake on sleep timer compare b. ?? wake on sleep timer wrap. the following source is only available in deep sleep 0 sinc e the swj is required to write a memory mapped register to set this wake source and the swj only ha s access to some registers in deep sleep 0. ?? wake on write to the wake_core register bit. the wakeup recording module monitors all possible wakeup sources. more than one wakeup source may be r e corded because events are continually being recorded (not just in deep-sleep) and another event may happen between the first wake event and when the em346 wakes up.
em346 rev 1.0 45 6.5.2. basic sleep modes the power management state diagram in figure 6.3 shows the basic operation of the power management controller. figure 6.3. power management state diagram in normal operation an application may request one of two low power modes through program execution: ?? idle sleep is achieved by exec uting a wfi instru ction while the sleepdeep bit in the cortex system control register (scs_scr) is clear. this puts the cpu into an idle state where execution is suspended until an interrupt occurs. this is indicated by the state at the bottom of the diagram. power is maintained to the core logic of the em346 during the idle sleeping state. ?? deep sleep is achieved by exec uting a wfi instruction with the sl eepdeep bit in scs_scr set. this triggers the state transitions around the main loop of the diagram, resulting in powering down the em346's core logic, and leaving only the always-on domain powered. wake up is triggered when one of the pre- determined events occurs. if a deep sleep is requested the em346 first enters a pre-de e p sleep state. this state prevents any section of the chip from being powered off or reset until the swj goes idle (by clea ring csyspwrupreq). this pre-deep sleep state ensures debug operations are not interrupted. in the deep sleep state the em3 46 wait s for a wake up event which will return it to the running st ate. in powering up the core logic the arm ? cortex tm -m3 is put through a reset cycle and ember software restores the stack and application state to the point where deep sleep was invoked. deep sleep emulated deep sleep pre-deep sleep running idle sleep cdbgpwrupreq set cdbgpwrupreq cleared deep sleep requested (wfi instruction with sleep_deep=1) i n t e r r u p t c s y s p w r u p r e q & i n h i b i t c d b g p w r u p r e q = 0 & c s y s p w r u p r e q = 0 w a k e u p e v e n t o r c s y s p w r u p r e q s e t ( r e s e t s t h e p r o c e s s o r ) w a k e u p e v e n t ( r e s e t s t h e p r o c e s s o r ) c d b g p w r u p r e q = 1 & c s y s p w r u p r e q = 0 s l e e p r e q u e s t e d ( w f i i n s t r u c t i o n w i t h s l e e p _ d e e p = 0 )
em346 46 rev 1.0 6.5.3. further options for deep sleep by default the low-fr equency internal rc oscillato r (oscrc) is running during deep sleep (known as deep sleep 1). to conserver power, oscrc can be turned of during deep sl e e p. this mode is known as deep sleep 2. since the oscrc is disabled, the sleep timer and watchdog timer do not function and cannot wake the chip unless the low- frequency 32.768 khz crystal oscillator is used. no n-timer based wake sources contin ue to function. once a wake event does occur, oscrc is restarted and comes back up. 6.5.4. use of debugger with sleep modes the debugger communicates with the em346 using the swj. when the debugger is logically connected, the cdbgpwrupre q bit in th e debug port in the swj is set, and the em346 will only enter deep sleep 0 (the emulated deep sleep state). the cdbgpwrupreq bit indicates that a debug tool is logically connected to the chip and therefore debug state may be in the system debug components. to maintain the debug state in the system debug compo nents only deep sleep 0 may be used, since deep sleep 0 will not cause a power cycle or reset of the core domain . the csyspwrupreq bit in the debug port in the swj indicates that a debugger wants to access memory actively in the em346. therefore, whenever the csyspwrupreq bit is set while the em346 is awake, the em3 46 cannot enter deep sleep until this bit is cleared. this ensures the em346 does not disrupt debug communication into memory. clearing both csyspwrupreq and cdbgpwrupreq allows the em346 to achieve a true deep sleep state ( d eep sleep 1 or 2). both of these signals also operate as wake sources, so that when a debugger logically connects to the em346 and begins accessing the chip, th e em346 automatically comes out of deep sleep. when the debugger initiates access while the em346 is in deep sleep, the sw j intelligently holds off the debugger for a brief period of time until the em346 is properly powered and ready. note: the swj-dp signals csyspwrupreq an d cdbgpwrupreq are only reset by a power-on-reset or a debugger. physically connecting or disconnecting a debugger from the ch ip will not alter the state of these signals. a debugger must logically communicate with the swj-dp to set or clear these two signals. for more information regarding the swj and the intera ction of debuggers with deep sleep, contact customer support for application notes and arm ? coresight tm documentation.
em346 rev 1.0 47 6.5.5. registers address: 0x40004038 reset: 0x0 6.6. security accelerator the em346 contains a hard ware aes encryption engine accessible from the arm ? cortex tm -m3. nist-based ccm, ccm*, cbc-mac, and ctr modes are implemented in hardware. thes e modes are descr ibed in the ieee 802.15.4-2003 specification, with th e exception of ccm*, which is describ ed in the zigbee security services specification 1.0 . register 6.1. peripheral_disable bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 peridis_rsvd 0 0 0 peridis_sc1 0 bitname bitfield access description peridis_rsvd [5] rw reserved: this bit can change during n o rmal operation. when writing to peripheral_disable, the value of this bit must be preserved. peridis_sc1 [1] rw disable the clock to the sc1 peripheral.
em346 48 rev 1.0 7. gpio (general purpose input/output) the em346 has 16 gpio pins, which may be individually configured as follows: ?? general purpose output ?? general purpose open-drain output ?? alternate output controlled by a peripheral device ?? alternate open-drain output controlled by a peripheral device ?? analog ?? general purpose input ?? general purpose input with pu ll-up or pull-down resistor the basic structure of a sing le gpio is illustrated in gpio block diagram figure 7.1 . figure 7.1. gpio block diagram a schmitt trigger converts the gpio pin voltage to a digi tal input value. the digital input signal is then always routed to the gpio_pxin register; to the alternate inputs of associated peripheral devices; to wake detection logic if wake detection is enabled; and, for certain pins, to in terrupt generation logic. configuring a pin in analog mode disconnects the digital input from the pin and applies a high logic level to the input of the schmitt trigger. only one device at a time can control a gpio output. t he ou tput is controlled in normal output mode by the gpio_pxout register and in alternate output mode by a peripheral device. when in input mode or analog mode, digital output is disabled. gpio _pxin gpio _pxout gpio _pxset gpio _pxclr gpio _pxwake gpio _pxcfgh/l alternate output analog functions wake detection pin alternate input vdd_ pads gnd vdd_ pads gnd output control (push pull , open drain , or disabled ) schmitt trigger vdd_ pads gnd protection diode protection diode p-mos n- m os
em346 rev 1.0 49 7.1. gpio ports the 16 gpio pins are grouped into three ports: pa, pb, and pc. individual gpios within a port are numbered 0 to 7 according to their bit positions within the gpio registers. note: because gpio port registers? functions ar e identical, the notation px is used here to refer to pa, pb, or pc. for example, gpio_pxin refers to the registers gpio_pain, gpio_pbin, and gpio_pcin. each of the three gpio ports has the following registers whose low-order eight bits correspond to the port?s eight gpio pins: ?? gpio_pxin (input data register) returns the pin level (unless in analog mode). ?? gpio_pxout (output data register) controls the output level in normal output mode. ?? gpio_pxclr (clear output data register) clears bits in gpio_pxout. ?? gpio_pxset (set output data re gister) sets bits in gpio_pxout. ?? gpio_pxwake (wake monitor register) specifies the pins that can wake the em346. in addition to these registers, each por t has a p air of configuration regi sters, gpio_pxcfgh and gpio_pxcfgl. these registers specify the basic operating mode for the port?s pins. gpio_pxcfgl c onfigures the pins px[3:0] and gpio_pxcfgh configures the pins px [7:4]. for brevity, the notation gpio_pxcfgh/l refers to the pair of configuration registers. two gpio pins (pa7 and pc0) can sink and source hig h er current than standard gpio outputs. refer to table 2.5 digital i/o specifications in "2. electrical specifications" on page 7 for more information. 7.2. configuration each pin has a 4-bit configuration value in the gpio_pxc fgh/l register. the various gpio modes and their 4-bit configuration values are shown in table 7.1 . if a gpio has two peripherals that can be the source of alter nate output mode data, then other registers in addition to gpio_pxcfgh/l determine which peripheral controls the output. if a gpio does not have an associated peripheral in alternate output mode, its output is set to 0. for outputs assigned to the serial controllers, the serial inter f ace mode registers (scx_mode) determine how the gpio pins are used. the alternate outputs of pa4 and pa5 can either provide packet trace data (pti_en and pti_data) or synchronous cpu trace data (tracedata2 and tracedata3). the selection of packet trace or cpu trace is made through the ember software. table 7.1. gpio configuration modes gpio mode gpio_pxcfgh/l description analog 0x0 analog input or output. when in analog mode, the digital input (gpi - o_pxin) always reads 1. input (floating) 0x4 digital input without an internal pull up or pull down. output is disabled. input (pull-up or pull-down) 0x8 digital input with an internal pull up or pull down. a set bit in gpio_px - out selects pull up and a cleared bit selects pull down. output is dis - abled. output (push-pull) 0x1 push-pull output. gpio_pxout controls the output. output (open- dra i n) 0x5 open-drain output. gpio_pxout controls the output. if a pull up is requ ired, it must be external. alternate output ( push- pull) 0x9 push-pull output. an onboard peripheral controls the output. alternate output ( op en-drain) 0xd open-drain output. an onboard peripheral controls the output. if a pull up is required, it must be external.
em346 50 rev 1.0 7.3. forced functions for some gpios, the gpio_pxcfgh/l configuration will be overri dden. these functions are forced when the em346 is reset and remain forced until software overrides the forced functions. ta b l e 7.2 shows the gpios that have different functions forced on them regardless of the gpio_pxcfgh/l registers. pa7 is forced to be the regulator enable signal, reg_en. if an external regulator is used and controlled through reg_en, p a7?s forced functionality must not be overridden. if an external regulator is not used, reg_en may be disabled and pa7 may be reclaimed as a normal gp io. disabling reg_en is done by clearing the bit gpio_extregen in the gpio_dbgcfg register. pc0, pc2, pc3, and pc4 are forced to be the serial wire an d jtag (swj) interface. when the em346 resets, these four gpios are forced to operate in jtag mode. switching the debug interface between jtag mode and serial wire mode can only be accomplished by the exte rnal debug tool and cannot be affected by software executing on the em346. due to the fact that serial wire mode can only be invoked by an external debug tool and jtag mode is forced when the em346 resets, a designer must treat all four debug gpios as working in unison even though the serial wire interfac e only uses one of the gpio, pc4. note: an application must disable all debug swj debug functionality to reclaim any of the four gpios: pc0, pc2, pc3, and pc4. disabling swj debug functionality prevents external deb ug tools from operating, including flash programming and high-level debug tools. disabling the swj debugger interface is accomplished by setting the gpio_debugdis bit in the gpio_dbgcfg register. when this bit is set, all debugger-related pins (pc0, pc2, pc3, pc4) behave as standard gpios. if the swj debugger interface is already active, the bit gpio_debugdis cannot be se t. when gpio_debugdis is set, the swj debugger interface can be reclaimed by activa ting the swj while the em346 is held in reset. if the swj debugger interface is forced active in this manner, the bit gpio_forcedbg is set in the gpio_dbgstat register. the swj debugger interface is defined as active when the cdbgpwrupreq signal, a bit in the debug port?s crtl/stat register in the swj, is set high by an external debug tool. 7.4. reset a full chip reset is one due to po wer on (low or high voltage), the nreset pin, the wa tchdog, or the sysresetreq bit. a full chip reset affect s the gpio configuration as follows: ?? the gpio_pxcfgh/l configurations of all pins are configured as floating inputs. ?? the gpio_extregen bit is set in the gpio_dbgcfg re gister, which overrides the normal configuration for pa7. ?? the gpio_debugdis bit in the gpio_dbgcfg register is cleared, allowing serial wire/jtag access to override the normal configurati on of pc0, pc2, pc3, and pc4. table 7.2. gpio forced functions gpio forced mode forced signal pa7 open-drain output reg_en pc0 input with pull up jrst pc2 push-pull output jtdo pc3 input with pull up jdti pc4 * input with pull up jtms pc4 * bidirectional (push-pull output or floatin g input) controlled by debugger interface swdio *note: the choice of pc4?s forced signal is controlled by an external debug tool. jtms is forced when the swj is in jtag mode, and swdio is forced when the swj is in serial wire mode.
em346 rev 1.0 51 7.5. boot configuration nbootmode is a special altern ate function of pa5 that is active only during a pin reset (nreset) or a power-on- reset of the always-powered domain (por hv). if nbootmode is asserted (pulled or driven low) when coming out of reset, the processor starts executing an embedded serial-link-only monitor instead of its normal program. while in reset and during the subsequent power-on-reset st ar tup delay (512 oschf clo cks), pa5 is automatically configured as an input with a pull-up resistor. at the end of this time, the em346 samples nbootmode: a high level selects normal boot mode, and a low level selects the embedded monitor. figure 7.2 shows the timing parameters for invoking monitor mode from a pin (nrese t ) reset. because oschf is running uncalibrated during the reset sequence, the time for 512 oschf clocks may vary as indicated. figure 7.2. nbootmode and nreset timing timing for a power-on-res et is similar except that oschf doe s not begin oscillating until up to 70 sec after both core and hv supplies are valid. combined with the maximum 250 sec allowed for hv to ramp from 0.5 v to 1.7 v, a n additional 320 sec may be added to the 512 oschf clocks until nbootmode is sampled. if the monitor mode is selected (nbootmode is low after 512 clocks), the fib monitor software begins execution. in or der to filter out inad vertent jumps into the monitor, the fib moni tor re-samples the nbootmode signal after a 3 ms delay. if the signal is still low, then the device stays in monitor mode. if the signal is high, then monitor mode is exited and the normal program b egins execution. in summary, the nboot mode signal must be held low for 4 ms in order to properly invoke the fib monitor. after nbootmode has been sampled, pa5 is configured as a f l oating input like the other gpio configurations. the gpio_bootmode bit in the gpio_dbgstat register captures the stat e of nbootmode so that software may act on this signal if required. note: to avoid inadvertently asserting nbootmode, pa5?s capacitive load may not exceed 250 pf. 7.6. gpio modes 7.6.1. analog mode analog mode enables analog functions, and disconnects a pin from the digital input and output logic. only the following g pio pins have analog functions: ?? pc6 and pc7 can connect to an optional 32.768 khz crystal. note: when an external timing source is required, a 32.768 khz crystal is commonly connected to pc6 and pc7. alternatively, when pc7 is configured as a digital input, pc7 can accept a digital external clock input. when configured in analog mode: ?? the output drivers are disabled. ?? the internal pull-up and pull-down resistors are disabled. ?? the schmitt trigger input is connected to a high logic level. . . . nreset oschf . . . . . . nbootmode 26 sec min . . . . . . . . . 512 clocks; 26 sec min ? 85 sec max nbootmode sampled; fib monitor mode entered nbootmode sampled by fib monitor code
em346 52 rev 1.0 ?? reading gpio_pxin returns a constant 1. 7.6.2. input mode input mode is used both for general purpose input and fo r o n-chip peripheral inputs. input floating mode disables the internal pull-up and pull-down resistors, leaving the pin in a high-impedance state. input pull-up or pull-down mode enables either an internal pull-up or pull-down resi stor based on the gpio_pxout register. setting a bit to 0 in gpio_pxout enables the pull-down and setting a bit to 1 enables the pull up. when configured in input mode: ?? the output drivers are disabled. ?? an internal pull-up or pull-down resistor ma y be activated depending on gpio_pxcfgh/l and gpio_pxout. ?? the schmitt trigger input is connected to the pin. ?? reading gpio_pxin returns the input at the pin. ?? the input is also available to on-chip peripherals. 7.6.3. output mode output mode provides a general purpose outp ut under direct software control. regardless of whether an output is configured as push-pull or open-drain, the gpio?s bit in the gpio_pxout register controls the output. the gpio_pxset and gpio_pxclr registers can atomically set and clear bits within gpio_pxout register. these set and clear registers simplify software using the output port because they eliminate the need to disable interrupts to perform an atomic read-modify-write operation of gpio_pxout. when configured in output mode: ?? the output drivers are enabled and are controlled by the value written to gpio_pxout: ?? in open-drain mode: 0 activates the n-mo s current sink; 1 tri-states the pin. ?? in push-pull mode: 0 activates the n-mos current sink; 1 activates the p-mos current source. ?? the internal pull-up and pull-down resistors are disabled. ?? the schmitt trigger input is connected to the pin. ?? reading gpio_pxin returns the input at the pin. note: reading gpio_pxout returns the last value written to the register. ? depending on configuration and us age, gpio_pxou t and gpio_pxi n may not have the same value. 7.6.4. alternate output mode in this mode, the output is controlled by an on-chip pe ri pheral instead of gpio_pxout and may be configured as either push-pull or open-drain. most peripherals require a particular output type, but si nce using a peripheral does not by itself configure a pin, the gpio_pxcfgh/l registers must be configured properly for a peripheral?s particular needs. as described in "7.2. configuration" on page 49 , when more than one peripheral can be the source of output data, registers in addition to gpio_pxcfgh/l dete rmin e which to use. when configured in alternate output mode: ?? the output drivers are enabled and are controlled by the output of an on-chip peripheral: ?? in open-drain mode: 0 activates the n-mo s current sink; 1 tri-states the pin. ?? in push-pull mode: 0 activates the n-mos current sink; 1 activates the p-mos current source. ?? the internal pull-up and pull-down resistors are disabled. ?? the schmitt trigger input is connected to the pin. note: reading gpio_pxin return s the input to the pin. ? depending on configuration and us ag e, gpio_pxou t and gpio_pxi n may not have the same value. 7.7. wake monitoring the gpio_pxwake registers specify whic h gpios are monitored to wake the processor. if a gpio?s wake enable bit is set in gpio_pxwake, then a change in the logic valu e of that gpio causes the em346 to wake from deep sleep. the logic values of all gpio s are captured by hardware upon entering sleep. if any gpio?s logic value changes while in sleep and that gpio?s gpio_pxwake bit is set, then th e em346 wakes from deep sleep. (there is no mechanism for selecting a specific rising-edge, falling- edge, or level on a gpio: any change in logic value
em346 rev 1.0 53 triggers a wake event.) hardware records the fact that gpio activity caused a wake event, but not which specific gpio was responsible. instead, the ember software read s the state of the gpios on waking to determine this. the register gpio_wakefilt cont ains bits to enable digital filtering of the external wakeup event sources: the gpio pins, sc1 activity, and irqd. the digital filter oper ates by taking samples based on the (nominal) 10 khz rc oscillator. if three samples in a row all have the same logic value, and this samp led logic value is different from the logic value seen upon entering sleep, the filter outputs a wakeup event. in order to use gp io pins to wake the em346 fr om deep sleep, the gpio_wake bit in the wake_sel register must be set. waking up from gpio activity does not work with pins configured for analog mode since the digital logic input is always set to 1 when in analog mode. refer to "6. system modules" on page 33 for information on the em346?s power management and sleep modes. 7.8. external interrupts the em346 can use up to three external interrupt source s (irqa, irqc, and irqd), each with its own top-level nvic interrupt vector. since these external interrupt so urces connect to the standard gpio input path, an external interrupt pin may simultaneously be used by a peripheral device or even configured as an output. analog mode is the only gpio configuration that is not compatible with using a pin as an external interrupt. external interrupts have individual triggering and f ilter ing o ptions selected using the registers gpio_intcfga, gpio_intcfgb, gpio_intcfgc, and gpio_intcfgd. the bit field gpio_intmod of the gpio_intcfgx register enables irqx?s second-level interrupt and selects the triggering mode: 0 is disabled; 1 for rising edge; 2 for falling edge; 3 for both edges; 4 for active high level; 5 for active low level. the minimum width needed to latch an unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. with the digital filter enabled (the gpi o _intfilt bit in the gpio_intcfgx register is set), the minimum width needed is 450 ns. the register int_gpioflag is the second-level interrupt fl a g register that indicates pending external interrupts. writing 1 to a bit in the int_gpioflag register clears the flag while writing 0 has no effect. if the interrupt is level- triggered, the flag bit is set again immediately after being cleared if it s input is still in the active state. irqa has a fixed pin assignment. the other two external inter r upts, irqc and irqd, can use any gpio pin. the gpio_irqcsel and gpio_irqdsel registers specify the gpio pins assigned to irqc and irqd, respectively. ta b l e 7.3 shows how the gpio_irqcsel and gpio_irqdsel regi ster va lues select the gpio pin used for the external interrupt. in some cases, it may be useful to assign irqc or irqd to an input also in use by a peripheral, for example to generate an interrupt from the slave select signal (nssel) in an spi slave mode interface. refer to "9. interrupt system" on page 100 for further information regardi ng t h e em346 interrupt system. 7.9. debug control and status two gpio registers are largely concerned with de bugger functions. gpio_dbgcfg can disable debugger table 7.3. irqc/d gpio selection gpio_irqxsel gpio gpio_irqxsel gpio gpio_irqxsel gpio 4 pa4 8 pb0 16 pc0 5 pa5 9 pb1 17 pc1 7 pa7 10 pb2 18 pc2 11 pb3 19 pc3 12 pb4 20 pc4 21 pc5 22 pc6 23 pc7
em346 54 rev 1.0 operation, but has other miscellaneous control bits as well. gpio_dbgstat, a read-only register, returns status related to debugger activity (gpio_forcedbg and gpio _swen), as well a flag (gpio_bootmode) indicating whether nbootmode was asserted at the last power-on or nreset-based reset. 7.10. gpio signal assignment summary the gpio signal assignments are shown in table 7.4 . table 7.4. gpio signal assignments gpio analog alternate output input output current drive pa4 pti_en, tracedata2 standard pa5 pti_data, tracedata3 nbootmode 1 standard pa7 reg_en 2 high pb0 traceclk irqa standard pb1 sc1txd, sc1mosi, sc1miso, sc1sda sc1sda standard pb2 sc1sclk sc1miso, sc1mosi, sc1scl, sc1rx d s tandard pb3 sc1sclk sc1sclk, sc1ncts standard pb4 sc1nrts sc1nssel standard pc0 tracedata1 jrst 3 high pc1 tracedata0, swo standard pc2 jtdo 4 , swo standard pc3 jtdi 3 standard pc4 swdio 5 swdio 5 , jtms 5 standard pc5 tx_active standard pc6 osc32b ntx_active standard pc7 osc32a standard notes: 1. overrides during reset as an input with pull up. 2. ove rrides after reset as an open-drain output. 3. overrides in jtag mode as a input with pull up. 4. overrides in jtag mode as a push-pull output. 5. ove rrides in serial wire mode as either a push-pull output, or a floating input, controlled by the debugger.
em346 rev 1.0 55 7.11. registers note: substitute ?a?, ?b?, or ?c? for ?x? in the following detailed descriptions. gpio_pacfgl: address: 0x4000b000 reset: 0x4444 ? gpio_pbcfgl: address: 0x4000b400 reset: 0x4444 ? gpio_pccfgl: address: 0x4000b800 reset: 0x4444 register 7.1. gpio_pxcfgl ? gpio_pacfgl: port a configuration register (low) ? gpio_pbcfgl: port b conf igura t ion register (low) ? gpio_pccfgl: port c conf iguration register (low) bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name px3_cfg px2_cfg bit 7 6 5 4 3 2 1 0 name px1_cfg px0_cfg bitname bitfield access description px3_cfg [15:12] rw gpio configuration control. 0x0: analog, input or output ( g pio_pxin always reads 1). 0x1: output, push-pull (gpio_ pxout co ntro ls the output). 0x4: input, floating. 0x5: output, open-drain (gpio_ pxout controls the output). 0x8: input, pulled up or down (selected by gpio_pxout: 0 = pull-down, 1 = pull-up). 0x9: alternate output, push-pull (p er ipheral controls the output). 0xd: alternate output, open-drain (peripheral controls the output). px2_cfg [11:8] rw gpio configuration control: see px3_cfg above. px1_cfg [7:4] rw gpio configuration control: see px3_cfg above. px0_cfg [3:0] rw gpio configuration control: see px3_cfg above.
em346 56 rev 1.0 gpio_pacfgh: address: 0x40 00b004 reset: 0x4444 ? gpio_pbcfgh: address: 0x4000b404 reset: 0x4444 ? gpio_pccfgh: address: 0x4000b804 reset: 0x4444 register 7.2. gpio_pxcfgh ? gpio_pacfgh: port a confi gura t ion register (high) ? gpio_pbcfgh: port b configuration register (high) ? gpio_pccfgh: port c configuration register (high) bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name px7_cfg px6_cfg bit 7 6 5 4 3 2 1 0 name px5_cfg px4_cfg bitname bitfield access description px7_cfg [15:12] rw gpio configuration control. 0x0: analog, input or output (gpio_pxin always reads 1). 0x1: output, push-pull (gpio_pxout controls the output). 0x4: input, floating. 0x5: output, open-drain (gp io_pxout co ntro ls the output). 0x8: input, pulled up or down (selected by gpio_pxout: 0 = pull-down, 1 = pull-up). 0x9: alternate output, push-pull (peripheral controls the output). 0xd: alternate output, open-drain ( per ipheral controls the output). px6_cfg [11:8] rw gpio configuration control: see px7_cfg above. px5_cfg [7:4] rw gpio configuration control: see px7_cfg above. px4_cfg [3:0] rw gpio configuration control: see px7_cfg above.
em346 rev 1.0 57 gpio_pain: address: 0x4000b008 reset: 0x0 ? gpio_pbin: address: 0x4000b408 reset: 0x0 ? gpio_pcin: address: 0x 40 00b8 08 reset: 0x0 register 7.3. gpio_pxin ? gpio_pain: port a input data register ? gpio_pbin: port b input data register ? gpio_pcin: port c input data register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] rw input level at pin px7. px6 [6] rw input level at pin px6. px5 [5] rw input level at pin px5. px4 [4] rw input level at pin px4. px3 [3] rw input level at pin px3. px2 [2] rw input level at pin px2. px1 [1] rw input level at pin px1. px0 [0] rw input level at pin px0.
em346 58 rev 1.0 gpio_paout: address: 0x4000b00c reset: 0x0 ? gpio_pbout: address: 0x4000b40c reset: 0x0 ? gpio_pcout: address: 0x4000b80c reset: 0x0 register 7.4. gpio_pxout ? gpio_paout: port a output data register ? gpio_pbout: port b output data register ? gpio_pcout: port c output data register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] rw output data for px7. px6 [6] rw output data for px6. px5 [5] rw output data for px5. px4 [4] rw output data for px4. px3 [3] rw output data for px3. px2 [2] rw output data for px2. px1 [1] rw output data for px1. px0 [0] rw output data for px0.
em346 rev 1.0 59 gpio_paclr: address: 0x4000b014 reset: 0x0 ? gpio_pbclr: address: 0x4000b414 reset: 0x0 ? gpio_pcclr: address: 0x4000b814 reset: 0x0 register 7.5. gpio_pxclr ? gpio_paclr: port a output clear register ? gpio_pbclr: port b output clear register ? gpio_pcclr: port c output clear register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] w write 1 to clear the output data bit fo r px7 (writing 0 has no effect). px6 [6] w write 1 to clear the output data bit fo r px6 (writing 0 has no effect). px5 [5] w write 1 to clear the output data bit fo r px5 (writing 0 has no effect). px4 [4] w write 1 to clear the output data bit fo r px4 (writing 0 has no effect). px3 [3] w write 1 to clear the output data bit fo r px3 (writing 0 has no effect). px2 [2] w write 1 to clear the output data bit fo r px2 (writing 0 has no effect). px1 [1] w write 1 to clear the output data bit fo r px1 (writing 0 has no effect). px0 [0] w write 1 to clear the output data bit fo r px0 (writing 0 has no effect).
em346 60 rev 1.0 gpio_paset: address: 0x40 00b010 reset: 0x0 ? gpio_pbset: address: 0x40 00b 4 10 reset: 0x0 ? gpio_pcset: address: 0x 40 00b8 10 reset: 0x0 register 7.6. gpio_pxset ? gpio_paset: port a out put set register ? gpio_pbset: port b output set register ? gpio_pcset: port c output set register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name gpio_pxsetrsvd bit 7 6 5 4 3 2 1 0 name px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description gpio_pxsetrsvd [15:8] w reserved: these bits must be set to 0. px7 [7] w write 1 to set the output data bit for px7 (writing 0 has no effect). px6 [6] w write 1 to set the output data bit for px6 (writing 0 has no effect). px5 [5] w write 1 to set the output data bit for px5 (writing 0 has no effect). px4 [4] w write 1 to set the output data bit for px4 (writing 0 has no effect). px3 [3] w write 1 to set the output data bit for px3 (writing 0 has no effect). px2 [2] w write 1 to set the output data bit for px2 (writing 0 has no effect). px1 [1] w write 1 to set the output data bit for px1 (writing 0 has no effect). px0 [0] w write 1 to set the output data bit for px0 (writing 0 has no effect).
em346 rev 1.0 61 gpio_pawake: address: 0x 4000bc08 reset: 0x0 ? gpio_pbwake: address: 0x4000bc0c reset: 0x0 ? gpio_pcwake: address: 0x4000bc10 reset: 0x0 register 7.7. gpio_pxwake ? gpio_pawake: port a wakeup monitor register ? gpio_pbwake: port b wakeup monitor register ? gpio_pcwake: port c wakeup monitor register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name px7 px6 px5 px4 px3 px2 px1 px0 bitname bitfield access description px7 [7] rw write 1 to enable wakeup monitoring of px7. px6 [6] rw write 1 to enable wakeup monitoring of px6. px5 [5] rw write 1 to enable wakeup monitoring of px5. px4 [4] rw write 1 to enable wakeup monitoring of px4. px3 [3] rw write 1 to enable wakeup monitoring of px3. px2 [2] rw write 1 to enable wakeup monitoring of px2. px1 [1] rw write 1 to enable wakeup monitoring of px1. px0 [0] rw write 1 to enable wakeup monitoring of px0.
em346 62 rev 1.0 address: 0x4000bc1c reset: 0x0 register 7.8. gpio_wakefilt: gpio wakeup filtering register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 irqd_wake_ fi l ter 0 sc1_wake_ fil ter gpio_wake_ fil ter bitname bitfield access description irqd_wake_filter [3] rw enable filter on gpio wakeup source irqd. sc1_wake_filter [1] rw enable filter on gpio wakeup source sc1 (pb2). gpio_wake_filter [0] rw enable filter on gpio wakeup sour ces enabled by the gpio_pnwake regis - ters.
em346 rev 1.0 63 note: substitute ?c? or ?d? for ?x? in the following detailed description. gpio_irqcsel: address: 0x 4000bc14 reset: 0xf ? gpio_irqdsel: address: 0x 400 0bc18 reset: 0x10 register 7.9. gpio_irqxsel ? gpio_irqcsel: interrupt c select register ? gpio_irqdsel: interrupt d select register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 sel_gpio bitname bitfield access description sel_gpio [4:0] rw pin assigned to irqx. 0x04: pa4 0x05: pa5 0x07: pa7 0x08: pb0 0x09: pb1 0x0a: pb2 0x0b: pb3 0x0c: pb4 0x10: pc0 0x11: pc1 0x12: pc2 0x13: pc3 0x14: pc4 0x15: pc5 0x16: pc6 0x17: pc7 0x18?0x1f: reserved
em346 64 rev 1.0 note: substitute ?a?, ?b?, ?c?, or ?d? for ?x? in the following detailed description. gpio_intcfga: address: 0x4000a860 reset: 0x0 ? gpio_intcfgb: address: 0x4000a864 reset: 0x0 ? gpio_intcfgc: address: 0x4000a868 reset: 0x0 ? gpio_intcfgd: address: 0x 400 0a86 c reset: 0x0 register 7.10. gpio_intcfgx ? gpio_intcfga: gpio interrupt a conf iguration register ? gpio_intcfgb: gpio interrupt b conf iguration register ? gpio_intcfgc: gpio interrupt c conf iguration register ? gpio_intcfgd: gpio interrupt d configuration register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 gpio_intfilt bit 7 6 5 4 3 2 1 0 name gpio_intmod 0 0 0 0 0 bitname bitfield access description gpio_intfilt [8] rw set this bit to enable digit a l filtering on irqx. gpio_intmod [7:5] rw irqx triggering mode. 0x0: disabled. 0x1: rising edge triggered. 0x2: falling edg e triggered. 0x3: rising and fa lling edge triggered. 0x4: active high level triggered. 0x5: active low level triggered. 0x6, 0x7: reserved.
em346 rev 1.0 65 address: 0x4000a814 reset: 0x0 address: 0x4000bc00 reset: 0x10 register 7.11. int_gpioflag: gpio interrupt flag register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 int_irqdflag int_irqcflag 0 int_irqaflag bitname bitfield access description int_irqdflag [3] rw irqd interrupt pending. write 1 to clear irqd interrupt (writing 0 has no effect). int_irqcflag [2] rw irqc interrupt pending. write 1 to clear irqc interrupt (writing 0 has no effect). int_irqaflag [0] rw irqa interrupt pending. write 1 to clear ir qa interrupt (writing 0 ha s no effect). register 7.12. gpio_dbgcfg: gpio debug configuration register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 gpio_debugdis gpio_extregen gpio_dbgcfgrsvd 0 0 0 bitname bitfield access description gpio_debugdis [5] rw disable debug interface override of normal gpio configuration. 0: permit debug interface to be active. 1: disable debug interface (if it is not already active). gpio_extregen [4] rw enable reg_en override of pa7's normal gpio configuration. 0: disable override. 1: enable override. gpio_dbgcfgrsvd [3] rw reserved: this bit can change during normal operation. when writing to gpi - o_dbgcfg, the value of this bit must be preserved.
em346 66 rev 1.0 address: 0x4000bc04 reset: 0x0 register 7.13. gpio_dbgstat: gpio debug status register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 gpio_bootmode 0 gpio_forcedbg gpio_swen bitname bitfield access description gpio_bootmode [3] r the state of the nbootmode signal sampled at the end of reset. 0: nbootmode was not asserted (it read high). 1: nbootmode was asse rted (it read low). g pio_forcedbg [1] r status of debugger interface. 0: debugger interface not forced active. 1: debugger interface forced active by debugger cable. gpio_swen [0] r status of serial wire interface. 0: not enabled by swj-dp. 1: enabled by swj-dp.
em346 68 rev 1.0 8. serial controllers 8.1. overview the em346 has one serial controller, sc1, which prov ides several options for full-duplex synchronous and asynchronous serial communications. ?? spi (serial peripheral interface), slave only ?? uart (universal asynchrono us receiver/transmitter) ?? receive and transmit fifos and dma channels, spi and uart modes receive and transmit fifos allow faster data speeds usi ng b y te-at-a-time interrupts. for the highest spi and uart speeds, dedicated receive and transmit dma channe ls reduce cpu loading and extend the allowable time to service a serial controller interrup t. polled operation is also possible using direct access to the serial data registers. figure 8.1 shows the components of the serial controllers. figure 8.1. serial controller block diagram sc 1 _ uartstat sc1 _ spistat sc1 _ spicfg sc1 _ ratelin / exp sc 1 _ uartper / frac baud generator clock generator uart controller sc1 _ data uar t spi off sc1 _ mode 0 1 2 nrts ncts sclk mosi miso txd rxd rx - fifo tx- fifo sc1 _tx / rxbega /b sc1 _ rxcnta /b sc1 _ txcnt sc1 _ dmastat sc1 _ dmactrl sc1 _ rxerra /b dma controller int _ sc1flag int _ sc1cfg sc 1 _ uartcfg sc1 interrupt sc1 tx dma channel sc1 rx dma channel sc1 _tx / rxenda /b spi slave controller nssel sc1 _ rxcntsaved sc 1 only
em346 rev 1.0 69 8.2. configuration before using a serial controller, co nfigure and initialize it as follows: 1. set up the parameters specific to the opera ting mode (slave for spi, baud rate for uart, etc.). 2. configure the gpio pins used by t he seri al controller as shown in tables 8.1 . ? "7.2. configuration" on page 49 shows how to configure gpio pins. 3. if using dma, set up the dma and buffers. this is described fully in "8.5. dma channels" on page 86 . 4. if using interrupts, select e dge - or level-triggered interrupts with the scx_intmode register, enable the desired second-level interrupt sources in the int_sc xcfg register, and finally enable the top-level scx interrupt in the nvic. 5. write the serial interface operating mode (spi or uart) to the scx_mode register. table 8.1. sc1 gpio usage and configuration pb1 pb2 pb3 pb4 spi - slave sc1miso alternate output ( push-pull) sc1mosi input sc1sclk inpu t sc1nssel input uart txd alternate output ( push-pull) rxd input ncts inpu t 1 nrts alternate output (push-pull) * *note: used if rts/cts hardware fl ow control is enabled.
em346 70 rev 1.0 8.2.1. registers sc1_mode: address: 0x4000c854 reset: 0x0 register 8.1. sc1_mode: serial mode register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 0 0 sc_mode bitname bitfield access description sc_mode [1:0] rw serial controller mode. 0: disabled. 1: uart mode . 2: spi mode.
em346 rev 1.0 71 int_sc1flag: address: 0x 4000a808 reset: 0x0 register 8.2. int_sc1flag: serial controller 1 interrupt flag register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 int_ sc1parerr int _ sc1frmerr int_ sctxuldb int_ sctxulda int_ scrxuldb int_ scrxulda 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 int_ sctxund int_ scrx ovf int_ sctxidle int_ sctxfree int_scrxval bitname bitfield access description int_sc1parerr [14] rw parity error received (uart) interrupt pending. int_sc1frmerr [13] rw frame error received (uart) interrupt pending. int_sctxuldb [12] rw dma transmit buffer b unloaded interrupt pending. int_sctxulda [11] rw dma transmit buffer a unloaded interrupt pending. int_scrxuldb [10] rw dma receive buffer b unloaded interrupt pending. int_scrxulda [9] rw dma receive buffer a unloaded interrupt pending. int_sctxund [4] rw transmit buffer underrun interrupt pending. int_scrxovf [3] rw receive buffer overrun interrupt pending. int_sctxidle [2] rw transmitter idle in terr upt pending. int_sctxfree [1] rw transmit buffer free interrupt pending. int_scrxval [0] rw receive buffer has data interrupt pending.
em346 72 rev 1.0 int_sc1cfg: address: 0x4000a848 reset: 0x0 register 8.3. int_sc1cfg: serial controller 1 interrupt configuration register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 int_ sc1parerr in t_ sc1frmerr int_ sctxuldb int _ sctxulda int_ scrxuldb int _ scrxulda 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 int_ sctxund int_ scrxovf int_ sctxidle int_ sctxfree int _ scrxva l bitname bitfield access description int_sc1parerr [14] rw parity error received (uart) interrupt enable. int_sc1frmerr [13] rw frame error received (uart) interrupt enable. int_sctxuldb [12] rw dma transmit buffer b unloaded interrupt enable. int_sctxulda [11] rw dma transmit buffer a unloaded interrupt enable. int_scrxuldb [10] rw dma receive buffer b unloaded interrupt enable. int_scrxulda [9] rw dma receive buffer a unloaded interrupt enable. int_sctxund [4] rw transmit buffer underrun interrupt enable. int_scrxovf [3] rw receive buffer overrun interrupt enable. int_sctxidle [2] rw transmitter idle interrupt enable. int_sctxfree [1] rw transmit buffer free interrupt enable. int_scrxval [0] rw receive buffer has data interrupt enable.
em346 rev 1.0 73 sc1_intmode: address: 0x4000a854 reset: 0x0 register 8.4. sc1_intmode: serial controll er 1 interrupt mode register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 0 sc_txidlelevel sc_txfreelevel sc_rxvallevel bitname bitfield access description sc_txidlelevel [2] rw transmitter idle interrupt mode - 0: edge triggered, 1: level triggered. sc_txfreelevel [1] rw transmit buffer free interrupt mode - 0: e dge triggered, 1: level triggered. sc_rxvallevel [0] rw receive buffer has data interrupt mode - 0: edge triggered, 1: level triggered.
em346 74 rev 1.0 8.3. spislave mode the sc1 controller includes an spi slave controller wit h these features: ?? full duplex operation ?? up to 5 mbps data transfer rate ?? programmable clock polarity and clock phase ?? selectable data shift direction (either lsb or msb first) ?? slave select input 8.3.1. gpio usage the spi slave controller uses four signals: ?? mosi (master out, slave in) - inpu ts serial data from the master ?? miso (master in, slave out) - outputs serial data to the master ?? sclk (serial clock) - clocks data transfers on mosi and miso ?? nssel (slave select) - enables serial communication with the slave note: the spi slave controller does not tri-state the miso signal when slave select is deasserted. the gpio pins that can be assigned to these signals are shown in ta b l e 8.2 . table 8.2. spi slave gpio usage mosi miso sclk nssel direction input output input input gpio configuration input alternate output (p us h-pull) input input sc1 pin pb2 pb1 pb3 pb4
em346 rev 1.0 75 8.3.2. set up and configuration the serial controller, sc1, supports spi slave mode. spi sl ave mode is enabled by the following register settings: ?? the serial controller mode register, scx_mode, is 2 ?? the sc_spimst bit in the spi config uration register, scx_spicfg, is 0 the spi slave controller receives its clock from an ex tern al spi ma ster device and supports rates up to 5 mbps. the spi slave controller supports various frame format s d epending upon the clock polarity (sc_spipol), clock phase (sc_spipha), and direction of data (sc_spiord) (see ta b l e 8.3 ). the sc_spipol, sc_spip h a, and sc_spiord bits are defined within the scx_spicfg registers. table 8.3. spi slave formats scx_spicfg frame format sc_spixxx * mst ord pha pol 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 ? ? same as above except lsb first instead of msb first *note: the notation ?xxx? means that the corresponding column header below is inserted to form the field name. tx[7] rx[7] tx[6] rx[6] tx [5] rx[5] tx[4] rx[4] tx[3] rx[3] tx[2] rx[2] tx [1] rx[1] tx[0] rx[0] nssel sclk in mosi in miso out tx[7] rx[7] tx[6] rx[6] tx [5] rx[5] tx[4] rx[4] tx[3] rx[3] tx [2] rx[2] tx[1] rx[1] tx[0] rx[0] sclk in mosi in miso out tx[7] rx[7] tx[6] rx[6] tx [5] rx[5] tx[4] rx[4] tx[3] rx[3] tx [2] rx[2] tx[1] rx[1] tx[0] rx[0] nssel sclk in mosi in miso out tx[7] rx[7] tx[6] rx[6] tx [5] rx[5] tx[4] rx[4] tx[3] rx[3] tx [2] rx[2] tx[1] rx[1] tx[0] rx[0] nssel mosi in miso out sclk in
em346 76 rev 1.0 8.3.3. operation when the slave select (nssel) signal is asserted by the master, spi transmit data is driven to the output pin miso, and spi data is received from the input pin mosi. the nssel pin has to be asserted to enable the transmit serializer to drive data to the output signal miso. a falling edge on nssel resets the spi slave shift registers. note: the spi slave controller does not tri-state the miso signal when slave select is deasserted. characters transmitted and received by the spi slave cont roller are buffered in the transmit and receive fifos that are both four entries deep. when software writes a char acter to the scx_data register, it is pushed onto the transmit fifo. similarly, when softwa re reads from the scx_data register, the character returned is pulled from the receive fifo. if the transmit and receive dma channel s are used, the dma channels also write to and read from the transmit and receive fifos. characters received are stored in the receive fifo. receiving characters sets the sc_spirxval bit in the scx_spist a t register, to indicate that characters can be read from the receive fifo. characters received while the receive fifo is full are dropped, and the sc_spirxov f bit in the scx_spistat register is set. the receive fifo hardware generates the int_scrxov f interrupt, but the dma register w ill not indicate the error condition until the receive fifo is drained. once the dma marks a receive error, two co nditions will clear the error indication: setting the appropriate sc_tx/rxdmarst bit in the scx_dmactrl register, or loading the appropriate dma buffer after it has unloaded. receiving a character causes the seri al tra n smission of a character pulled from the transmit fifo. when the transmit fifo is empty, a transmit underrun is detected (no data in transmit fifo ) and the int_sctxund bit in the int_scxflag register is set. because no character is available for serialization, the spi serializer retransmits the last transmitted character or a busy token (0xff) , determined by the sc_spi rpt bit in the scx_spicfg register. refer to the register description of scx_ spicfg for more detailed information about sc_spirpt. when the transmit fifo and the serializer are both em pty , writing a character to the transmit fifo clears the sc_spitxidle bit in the scx_spistat register. this indi cates that not all characters have been transmitted. if characters are written to the transmit fifo until it is full, the sc_spitxfree bit in the scx_spistat register is cleared. shifting out a transmit character to the miso pin causes the sc_spitxfree bit in the scx_spistat register to get set. when the transmit fifo empties and the last character has been shifted out, the sc_spitxidle bit in the sc x_spistat register is set. the spi slave controller must guarantee that there is time to move ne w tran smit data fr om the transmit fifo into the hardware serializer. to provide sufficient time, the spi slave controller inserts a byte of padding at the start of every new string of transmit data defined by every time nssel is asserted. this byte is inserted as if this byte was placed there by software. the value of the byte of padding is always 0xff. 8.3.4. dma the dma channels "8.5. dma channels" on page 86 describes how to configure and use the serial receive and transmit dma channels. when using the receive dma channel and nssel transitions to the high (dea sserted) st ate, the active buffer's receive dma count register (scx_r xcnta/b) is saved in the scx_rx cntsaved register. scx_rxcntsaved is only written the first time nssel goes high after a buffer has been loaded. subs equent rising edges set a status bit but are otherwise ignored. the 3-bit field sc_rxssel in the scx_dmastat register records what, if anything, was saved to the scx_rxcntsaved r egister, and whether or not anothe r rising edge occurred on nssel.
em346 rev 1.0 77 8.3.5. interrupts spi slave controller second-level interrupts are generated on the following events: ?? transmit fifo empty and last character shifted out (depending on scx_intmode, either the 0 to 1 transition or the high level of sc_spitxidle) ?? transmit fifo changed from full to not full (depending on scx_intmode, either the 0 to 1 transition or the high level of sc_spitxfree) ?? receive fifo changed from empty to not empty (depen ding on scx_intmode, either the 0 to 1 transition or the high level of sc_spirxval) ?? transmit dma buffer a/b complete (1 to 0 transition of sc_txacta/b) ?? receive dma buffer a/b complete (1 to 0 transition of sc_rxacta/b) ?? received and lost characte r while receive fifo was full (receive overrun error) ?? transmitted character while transmit fifo was empty (transmit underrun error) to enable cpu interrupts, set desired interrupt bits in the second-level int_scxcfg register, and also enable the top-lev e l scx interrupt in the nvic by writin g the int_scx bit in the int_cfgset register.
em346 78 rev 1.0 8.4. uartuniversal asynchronous receiver/transmitter the sc1 uart is enabled by writing 1 to sc1_ mode. the uart supports the following features: ?? flexible baud rate clock (300 bps to 921.6 kbps) ?? data bits (7 or 8) ?? parity bits (none, odd, or even) ?? stop bits (1 or 2) ?? false start bit and noise filtering ?? receive and transmit fifos ?? optional rts/cts flow control ?? receive and transmit dma channels 8.4.1. gpio usage the uart uses two signals to transmit and receive serial data: ?? txd (transmitted data) - serial data sent by the em346 ?? rxd (received data) - serial data received by the em346 if rts/cts flow control is enabled, th ese two signals are also used: ?? nrts (request to send) - indicates the em346 is able to receive data ?? ncts (clear to send) - inhibits sending data from the em346 if not asserted the gpio pins assigned to these signals are shown in ta b l e 8.4 . table 8.4. uart gpio usage txd rxd ncts 1 nrts * direction output input input output gpio configuration alternate output (push- pull) input input alternate output (push-pull) sc1 pin pb1 pb2 pb3 pb4 *note: only used if rts/cts hardware flow control is enabled.
em346 rev 1.0 79 8.4.2. set up and configuration the uart baud rate clock is produced by a programmable baud generator starting from the 24 hz clock: the integer portion of the divisor, n, is written to the sc1_ uartper register and the fractional part, f, to the sc1_uartfrac register. table 8.5 shows the values used to generate some common baud rates and their associated clock frequency error. the uart requires an inte rn al clock that is at least eight times the baud rate clock, so the minimum allowabl e setting for sc1_uartper is 8. the uart can miss bytes when the inter-byte gap is long o r there is a baud rate mismatch between receiver and transmitter. the uart may de tect a parity and/or framing error on the corrupted byte, but th ere will not necessarily be any error detected. the uart is best operated in systems where the other si de of th e communication link also uses a crystal as its timing reference, and baud rates should be selected to mi nimize the baud rate mismatch to the crystal tolerance. additionally, uart protocols should contain some form of error checking (for example crc) at the packet level to detect, and retry in the event of errors. since the probability of corruption is low, there would only be a small effect on uart throughput due to retries. errors may occur when: table 8.5. uart baud rate divisors for common baud rates baud rate (bits/sec) sc1_uartper sc1_uartfrac baud rate error (%) 300 40000 0 0 2400 5000 0 0 4800 2500 0 0 9600 1250 0 0 19200 625 0 0 38400 312 1 0 57600 208 1 ? 0.08 115200 104 0 + 0.16 230400 52 0 + 0.16 460800 26 0 + 0.16 921600 13 0 + 0.16 baud 24 mhz 2n f + -------------------- = ? -------------------------------------- where: t gap = inter-byte gap in seconds baud = baud rate in bps ferror = relative frequency error in ppm ?
em346 80 rev 1.0 for example, if the baud rate toleranc e between receive and transmit is 200 ppm (reasonable if both sides are de rived from a crystal), and the baud rate is 115200 bps, then errors will not occur un til the inter-byte gap exceeds 43 ms. if the gap is excee ded then the chance of an er ror is essentially random, with a probability of approx imately p = baud / 24e6. at 115200 bps, the probability of corruption is 0.5%. t he uart character frame format is determined by four bits in the sc1_uartcfg register: ?? sc_uart8bit specifies the number of data bits in receiv ed and transmitted characters. if this bit is clear, characters have 7 data bits; if set, characters have 8 data bits. ?? sc_uart2stp selects the number of stop bits in tran smitted characters. (only one stop bit is required in received characters.) if this bit is clear, characters are transmitted with one stop bit; if set, characters are transmitted with two stop bits. ?? sc_uartpar controls whether or not received and transmitted characters include a parity bit. if sc_uartpar is clear, characters do not contain a parity bit, otherwise, characters do contain a parity bit. ?? sc_uartodd specifies whether transmitted and received pari ty bits contain odd or even parity. if this bit is clear, the parity bit is even, and if set, the parity bit is odd. even parity is the exclusive-or of all of the data bits, and odd parity is the inverse of the even parity value. sc_uartodd has no effect if sc_uartpar is clear. a uart character frame contains, in sequence: ?? the start bit ?? the least significant data bit ?? the remaining data bits ?? if parity is enabled, the parity bit ?? the stop bit, or bits, if 2 stop bits are selected. figure 8.2 shows the uart character frame format, with optional bit s indicated. depending on the options chosen for the character frame, the length of a character frame ranges from 9 to 12 bit times. note that asynchronous serial data may have arbitrarily lo ng idle periods between characters. when idle, serial data (txd or rxd) is held in the high state. serial data tr ansitions to the low state in the start bit at the beginning of a character frame. figure 8.2. uart character frame format idle time start bit data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 parity bit stop bit stop bit next start bit or idletime uart character frame format (optional sections are in italics) txd or rxd
em346 rev 1.0 81 8.4.3. fifos characters transmitted and received by the uart are buffe red in the transmit and receive fifos that are both 4 entries deep (see figure 8.3 ). when software writes a character to th e sc1_da ta register, it is pushed onto the transmit fifo. similarly, when software reads from the s c 1_data register, the character returned is pulled from the receive fifo. if the transmit and receive dma channel s are used, the dma channels also write to and read from the transmit and receive fifos. figure 8.3. uart fifos 8.4.4. rts/cts flow control rts/cts flow control, also called hardwa re flow co ntrol, uses two signals (n rts and ncts) in addition to received and transmitted data (see figure 8.4 ). flow control is used by a data re ce iver to prevent buffer overflow, by signaling an external device when it is and is not allowed to transmit. figure 8.4. rts/cts flow control connections the uart rts/cts flow control options are selected by the sc_uartflow and sc_uartauto bits in the sc1_uartcfg register (see table 8.6 ). whenever the sc_uartflow bit is set, the uart will not start transmitting a character unless ncts is low (asserted). if ncts tra n sitions to the high state (deasserts) while a character is being transmitted, transmission of that character continues until it is complete. if the sc_uartauto bit is set, nrts is controlled automa tically b y hardware: nrts is put into the low state (asserted) when the receive fifo has room for at leas t two characters, otherwise is it in the high state (unasserted). if sc_uartauto is clear, software controls the nrts output by setting or clearing the sc_uartrts bit in the sc1_uartcfg register. software cont rol of nrts is useful if the external serial device cannot stop transmitting characters promptly when nrts is set to the high state (deasserted). receive shift register sc1_data (read) transmit shift register sc1_data (write) rxd txd parity/frame errors sc1_uartstat receive fifo transmit fifo cpu and dma channel access other device uart receiver uart transmitter em346 uart transmitter uart receiver rxd txd nrts ncts txd rxd ncts nrts
em346 82 rev 1.0 8.4.5. dma "8.5. dma channels" on page 86 describes how to configure and use the serial receive and transmit dma channels. the receive dma channel has special provisions to record uar t receive errors. when the dma channel transfers a character from the receive fifo to a buffer in memory, it checks the stored parity and frame error status flags. when an error is flagged, the sc1_rxerra/b register is updated, marking the offset to the first received character with a parity or frame error. similarly if a receive overrun error occurs, the sc1_rxerra/b registers mark the error offset. the receive fifo hardware genera tes the int_scrxovf interrupt and dma status register indicates the error immediately, but in this case the error of fset is 4 characters ahead of the actual overflow at the input to the receive fifo. two condit ions will clear the error indication: se tting the appropriate sc_rxdmarst bit in the sc1_dmactrl register, or loading the appropriate dma buffer after it has unloaded. 8.4.6. interrupts uart interrupts are generated on the following events: ?? transmit fifo empty and last character shifted out (depending on scx_intmode, either the 0 to 1 transition or the high level of sc_uarttxidle) ?? transmit fifo changed from full to not full (depending on scx_intmode, either the 0 to 1 transition or the high level of sc_uarttxfree) ?? receive fifo changed from empty to not empty (depen ding on scx_intmode, either the 0 to 1 transition or the high level of sc_uartrxval) ?? transmit dma buffer a/b complete (1 to 0 transition of sc_txacta/b) ?? receive dma buffer a/b complete (1 to 0 transition of sc_rxacta/b) ?? character received with parity error ?? character received with frame error ?? character received and lost when receive fifo was full (receive overrun error) to enable cpu interrupts, set the desired interrupt bits in the second-level int_scxcfg register, and enable the top-lev e l scx interrupt in the nvic by writin g the int_scx bit in the int_cfgset register. table 8.6. uart rts/cts flow control configurations sc1_uartcfg pins used operating mode sc_uartxxx * flow auto rts 0 ? ? txd, rxd no rts/cts flow control 1 0 0/1 txd, rxd, ncts, nr ts flow co ntrol using rts/cts wit h sof tware control of nrts: ? nrts controlled by sc_uartrts bit in sc1_uartcfg register 1 1 ? txd, rxd, ncts, nr ts flow co ntrol using rts/cts wit h hardwar e control of nrts: ? nrts is asserted if room for at least 2 characters in receive fifo *note: the notation ?xxx? means that the corresponding column header below is inserted to form the field name.
em346 rev 1.0 83 8.4.7. registers refer to " " on page 73 (in ? ? ) for a description of the scx_data register. sc1_uartstat: address: 0x4000c848 reset: 0x40 register 8.9. sc1_uartstat: uart status register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 sc_ uar t txidle sc_ uart parerr sc_ uart frmerr sc_ uart rxovf sc_ uar ttxfree sc_ uart rxval sc_ uart cts bitname bitfield access description sc_uarttxidle [6] r this bit is set when both the transmit fi f o and the transmit serializer are empty. sc_uartparerr [5] r this bit is set when the byte in the data regi ster was recei v ed with a parity error. this bit is updated when the data register is read, and is cleared if the receive fifo is empty. sc_uartfrmerr [4] r this bit is set when the byte in the data regi ster was re ceived with a frame error. this bit is updated when the data register is read, and is cleared if the receive fifo is empty. sc_uartrxovf [3] r this bit is set when the receive fifo has been overrun. this occurs if a byte is re ce ived when the receive fifo is full. this bit is cleared by reading the data regis - ter. sc_uarttxfree [2] r this bit is set when the transmit fifo has space for at least one byte. sc_uartrxval [1] r this bit is set when the receive fifo contains at least one byte. sc_uartcts [0] r this bit shows the logical state (not voltage level) of the ncts input: 0: ncts is deasserted (pin is high, 'x off ' , rs232 negative voltage); the uart is inhibited from starting to transmit a byte. 1: ncts is asserted (pin is low, 'xon', rs232 positive voltage); the uart may transmit.
em346 84 rev 1.0 sc1_uartcfg: address: 0x4000c85c reset: 0x0 register 8.10. sc1_uartcfg: uart c onfig uration register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 sc_ uar t auto sc_ uart flow sc_ uart odd sc_ uart par sc_ uart 2stp sc_ uart 8bit sc_ ua rtrts bitname bitfield access description sc_uartauto [6] rw set this bit to enable automatic nrts control by hardware (sc_uartflow must a l so be set). when automatic control is enabled, nrts will be deasserted when the receive fifo has space for only one more byte (inhibits transmission from the other device) and will be asserted if it has space for more than one byte (enables trans - mission from the other device). the sc_uartrts bit i n this register has no effect if this bit is set. sc_uartflow [5] rw set this bit to enable using nrts/ncts flow control signals. clear this bit to disable the sig nals. whe n this bit is clear, the uart transmitter will not be inhibited by ncts. sc_uartodd [4] rw if parity is enabled, specifies the kind of parity. 0: even parity. 1: odd parity. sc_uartpar [3] rw specifies whether to use parity bits. 0: don't use parity. 1: use parity. sc_uart2stp [2] rw number of stop bits transmitted. 0: 1 stop bit. 1: 2 stop bits. sc_uart8bit [1] rw number of data bits. 0: 7 data bits. 1: 8 data bits. sc_uartrts [0] rw nrts is an output to control the flow of se ri al data sent to the em346 from another device. this bit directly controls the out put at the nrts pin (sc_uartflow must be set and sc_uartauto must be cleared). when this bit is set, nrts is asserted (pin is low, 'xon', rs232 positive voltage); the other device's transmission is enabled. when this bit is cleared, nrts is deasserted (pin is high, 'xoff', rs232 negative voltage), the other devi ce's transmission is inhibited.
em346 rev 1.0 85 sc1_uartper: address: 0x4000c868 reset: 0x0 sc1_uartfrac: address: 0x4000c86c reset: 0x0 register 8.11. sc1_uartper: uart baud rate period register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name sc_uartper bit 7 6 5 4 3 2 1 0 name sc_uartper bitname bitfield access description sc_uartper [15:0] rw the integer part of baud rate period (n) in the equation: register 8.12. sc1_uartfrac: uart baud rate frac tional period register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 0 0 0 sc_uartfrac bitname bitfield access description sc_uartfrac [0] rw the fractional part of the baud rate period (f) in the equation: rate 24 mhz 2n ? ?? f + ?? --------------------------------- = ? ?? f + ?? --------------------------------- =
em346 86 rev 1.0 8.5. dma channels the em346 serial dma channels enable efficient, high-s peed operation of the spi and uart controllers by reducing the load on the cpu as well as decreasing the freq uency of interrupts that it must service. the transmit and receive dma channels can transfer data between the transmit and receive fifos and the dma buffers in main memory as quickly as it can be transmitted or received. on ce software defines, configur es, and activates the dma, it only needs to handle an interrupt when a transmit buff er has been emptied or a rece ive buffer has been filled. the dma channels each support two memory buffers, la beled a and b, and can alternate ("ping-pong") between them automatically to allow co ntinuous communicat ion without critical interrupt timing. note: dma memory buffer terminology ?? load - make a buffer available for the dma channel to use ?? pending - a buffer loaded but not yet active ?? active - the buffer that will be used for the next dma transfer ?? unload - dma channel action when it has finished with a buffer ?? idle - a buffer that has not been loaded, or has been unloaded to use a dma channel, software should follow these steps: 1. reset the dma channel by setting the sc_txd marst (or sc _r xdmarst) bit in the scx_dmactrl register. 2. set up the dma buffers. the two dma buffers, a and b, are defined by writing the start address to scx_txbega/b (or scx_rxbega/b ) and the (inc lusive) end address to scx_txenda/b (or scx_rxenda/b). note that dma buffers must be in ram. 3. configure and initialize scx for the desired operating mode. 4. enable second-level interrupts triggered when dma buffers unload by setting the int_sctxulda/b (or int_scrxul da/b) bit s in the int_scxflag register. 5. enable top-level nvic inte rrupt s by setting the int_scx bi t in the int_cfgset register. 6. start the dma by loading the dma buffers by se tting the sc_txloda/ b (or sc _rxloda/b) bits in the scx_dmactrl register. a dma buffer's end address, scx_txen da/b (or sc x_rxenda/b), can be writ ten while the buffer is loaded or active. this is useful for receiving messages that contain an initial byte count, since it allows software to set the buffer end address at the last byte of the message. as the dma channel transfers data between the transmit or receive fifo and a memory buffer, the dma count regis t er contains the byte offset from the start of the buffer to the address of the next by te that will be written or read. a transmit dma channel has a single dma count register (scx_txcnt) that applies to whichever transmit buffer is active, but a receive dma channel has two dm a count registers (scx_rxcnt a/b), one for each receive buffer. the dma count register contents are preserved until the corresponding buffer, or either buffer in the case of the transmit dma count, is loaded, or until the dma is reset. the receive dma count register may be written while the corr espo ndin g buffer is loaded. if the buffer is not loaded, writing the dma count register also loads the buffer while preserving the count value written. this feature can simplify handling uart receive errors. the dma channel stops using a buffer and unloads it when the following is true: (dma buffer start address + dma buffer count) > dma buffer end address typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is unloaded after it is filled with dat a, but writing to the buff er end address or buffer count regist ers can also cause a buffer to unload early. serial controller dma channels include additional feat u r es specific to the spi and uart operation and are described in those sections.
em346 rev 1.0 87 8.5.1. registers sc1_dmactrl: address: 0x4000c830 reset: 0x0 register 8.13. sc1_dmactrl: serial dma control register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 sc_txdmarst sc_rxdmarst sc_txlodb sc_txloda sc_rxlodb sc_rxloda bitname bitfield access description sc_txdmarst [5] w setting this bit resets the transmit dma. the bit clears automatically. sc_rxdmarst [4] w setting this bit resets the receive dma. the bit clears automatically. sc_txlodb [3] rw setting this bit loads dma transmit buffer b addresses and allows the dma controller to st art processing transmit buffer b. if both buffer a and b are loaded simultane - ously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit return s dm a buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending. sc_txloda [2] rw setting this bit loads dma transmit buffer a addresses and allows the dma controller to st art processing transmit buffer a. if both buffer a and b are loaded simultane - ously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit return s d m a buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending. sc_rxlodb [1] rw setting this bit loads dma receive buffer b addresses and allows the dma controller to st art processing receive buffer b. if both buffer a and b are loaded simultaneously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit return s d m a buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending. sc_rxloda [0] rw setting this bit loads dma receive buffer a addresses and allows the dma controller to st art processing receive buffer a. if both buffer a and b are loaded simultaneously, buffer a will be used first. this bit is cleared when dma completes. writing a zero to this bit has no effect. reading this bit return s d m a buffer status: 0: dma processing is complete or idle. 1: dma processing is active or pending.
em346 88 rev 1.0 sc1_dmastat: address: 0x4000c82c reset: 0x0 register 8.14. sc1_dmastat: serial dma st atus register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 sc_rxssel sc_rxfrmb sc_rxfrma bit 7 6 5 4 3 2 1 0 name sc_rxparb sc_rxpara sc_rxovfb sc_rxovfa sc_txactb sc_txacta sc_rxactb sc_rxacta bitname bitfield access description sc_rxssel [12:10] r status of the receive count saved in sc x_rxcnts a ved (spi sl ave mode) when nssel deasserts. cleared when a receive buffer is loaded and when the receive dma is reset. 0: no count was saved becau se nssel did not deassert. 2: buf fer a's count was sa ved, nssel deasserted once. 3: buffer b's count was sa ved, nssel deasserted once. 6: buffer a's count was saved, nssel deasserted more than once. 7: buffer b's count was saved, nssel deasserted more than once. 1, 4, 5: reserved. sc_rxfrmb [9] r this bit is set when dma receive buffer b reads a byte with a frame error from the receive fifo . it is cleared the next time buffer b is l oaded or when the receive dma is reset. (sc1 in uart mode only) sc_rxfrma [8] r this bit is set when dma receive buffer a reads a byte with a frame error from the receive fif o . it is cleared the next time buffer a is l oaded or when the receive dma is reset. (sc1 in uart mode only) sc_rxparb [7] r this bit is set when dma receive buffer b reads a byte with a parity error from the receive fif o . it is cleared the next time buffer b is l oaded or when the receive dma is reset. (sc1 in uart mode only) sc_rxpara [6] r this bit is set when dma receive buffer a reads a byte with a parity error from the receive fif o . it is cleared the next time buffer a is l oaded or when the receive dma is reset. (sc1 in uart mode only) sc_rxovfb [5] r this bit is set when dma receive buffer b was passed an overrun error from the receive fif o . neither receive buffer was capable of accepting any more bytes (unloaded), and the fifo filled up. buffer b was the next buffer to load, and when it drained the fifo the over - run error was passed up to the dma and flagged with this bit. cleared the next time buffer b i s loaded and when the receive dma is reset. sc_rxovfa [4] r this bit is set when dma receive buffer a was passed an overrun error from the receive fif o . neither receive buffer was capable of accepting any more bytes (unloaded), and the fifo filled up. buffer a was the next buffer to load, and when it drained the fifo the over - run error was passed up to the dma and flagged with this bit. cleared the next time buffer a i s loaded and when the receive dma is reset. sc_txactb [3] r this bit is set when dma transmit buffer b is active. sc_txacta [2] r this bit is set when dma transmit buffer a is active.
em346 rev 1.0 89 sc1_txbega: address: 0x4000c810 reset: 0x20000000 sc_rxactb [1] r this bit is set when dma receive buffer b is active. sc_rxacta [0] r this bit is set when dma receive buffer a is active. register 8.15. sc1_txbega: transmit dma begin addre ss register a bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_txbega bit 7 6 5 4 3 2 1 0 name sc_txbega bitname bitfield access description sc_txbega [13:0] rw dma transmit buffer a start address.
em346 90 rev 1.0 sc1_txbegb: transmit dma begin address register b sc1_txenda: address: 0x4000c814 reset: 0x20000000 register 8.16. sc1_txbegb: transmit dma begin addre ss register b bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_txbegb bit 7 6 5 4 3 2 1 0 name sc_txbegb bitname bitfield access description sc_txbegb [13:0] rw dma transmit buffer b start address. register 8.17. sc1_txenda: transmit dma end address register a bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_txenda bit 7 6 5 4 3 2 1 0 name sc_txenda bitname bitfield access description sc_txenda [13:0] rw address of the last byte that will be read from the dma transmit buf fer a.
em346 rev 1.0 91 sc1_txendb: address: 0x4000c81c reset: 0x20000000 sc1_txcnt: address: 0x4000c828 reset: 0x0 register 8.18. sc1_txendb: transmit dma end address register b bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_txendb bit 7 6 5 4 3 2 1 0 name sc_txendb bitname bitfield access description sc_txendb [13:0] rw address of the last byte that will be read from the dma transmit buffer b. register 8.19. sc1_txcnt: transmit dma count register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_txcnt bit 7 6 5 4 3 2 1 0 name sc_txcnt bitname bitfield access description sc_txcnt [13:0] r the offset from the start of the active dma transmit buffer from which the next byte w ill be read. this regi ster is set to zero when the buffer is loaded and when the dma is reset.
em346 92 rev 1.0 sc1_rxbega: address: 0x4000 c800 reset: 0x20000000 sc1_rxbegb: address: 0x4000 c808 reset: 0x20000000 register 8.20. sc1_rxbega: receive dma be gin address regist er a bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxbega bit 7 6 5 4 3 2 1 0 name sc_rxbega bitname bitfield access description sc_rxbega [13:0] rw dma receive buffer a start address. register 8.21. sc1_rxbegb: receive dma be gin address regist er b bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxbegb bit 7 6 5 4 3 2 1 0 name sc_rxbegb
em346 rev 1.0 93 sc1_rxenda: address: 0x4000c804 reset: 0x20000000 bitname bitfield access description sc_rxbegb [13:0] rw dma receive buffer b start address. register 8.22. sc1_rxenda: receive dma end address register a bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxenda bit 7 6 5 4 3 2 1 0 name sc_rxenda bitname bitfield access description sc_rxenda [13:0] rw address of the last byte that will be w r itten in the dma receive buffer a.
em346 94 rev 1.0 sc1_rxendb: address: 0x4000c80c reset: 0x20000000 register 8.23. sc1_rxendb: receive dma end address register b bit 31 30 29 28 27 26 25 24 name 0 0 1 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxendb bit 7 6 5 4 3 2 1 0 name sc_rxendb bitname bitfield access description sc_rxendb [13:0] rw address of the last byte that will be written in the dm a receive buffer b.
em346 rev 1.0 95 sc1_rxcnta: address: 0x4000c820 reset: 0x0 register 8.24. sc1_rxcnta: receive dma count register a bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxcnta bit 7 6 5 4 3 2 1 0 name sc_rxcnta bitname bitfield access description sc_rxcnta [13:0] rw the offset from the start of dma receive buffer a at which the next byte will b e wr itten. this register is set to ze ro when the buffer is loaded and when the dma is reset. if this register is wr itten when the buffer is not loaded, the buffer is loaded.
em346 96 rev 1.0 sc1_rxcntb: address: 0x4000c824 reset: 0x0 register 8.25. sc1_rxcntb: receive dm a c ount register b bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxcntb bit 7 6 5 4 3 2 1 0 name sc_rxcntb bitname bitfield access description sc_rxcntb [13:0] rw the offset from the start of dma receiv e buf f er b at which the next byte will be written. this register is set to zero when the buffer is loaded and when the dma is reset. if this regi ster is written when the buffer is not loaded, the buf - fer is loaded.
em346 rev 1.0 97 sc1_rxcntsaved: address: 0x4000c870 reset: 0x0 register 8.26. sc1_rxcntsaved: saved r eceiv e dma count register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxcntsaved bit 7 6 5 4 3 2 1 0 name sc_rxcntsaved bitname bitfield acces s description sc_rxcntsaved [13:0] r receive dma count saved in spi slave mode when nssel deassert s . the count is only saved the first time nssel deasserts.
em346 98 rev 1.0 sc1_rxerra: dma first receive error register a register 8.27. sc1_rxerra: dma first receive error register a bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxerra bit 7 6 5 4 3 2 1 0 name sc_rxerra bitname bitfield access description sc_rxerra [13:0] r the offset from the start of dma receive buffer a of the first byte received with a p arity, frame, or overflow error. note that an overflow error occurs at the input to the receive fifo, so this offset is 4 bytes before the overflow position. if there is no error, it read s zero. this register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive dma is reset.
em346 rev 1.0 99 sc1_rxerrb: address: 0x4000c838 reset: 0x0 register 8.28. sc1_rxerrb: dma first receive error register b bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 sc_rxerrb bit 7 6 5 4 3 2 1 0 name sc_rxerrb bitname bitfield access description sc_rxerrb [13:0] r the offset from the start of dma receive buffer b of the first byte received with a p a rity, frame, or overflow error. note that an overflow error occurs at the input to the receive fifo, so this offset is 4 bytes before the overflow position. if there is no er ror, it reads zero. this register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive dma is reset.
em346 100 rev 1.0 9. interrupt system the em346's interrupt system is compos ed of two parts: a standard arm? cortex tm -m3 nested vectored interrupt controller (nvic) that provides top-level interrupts, and a proprietary event manager (em) that provides second- level interrupts. the nvic and em provide a simple hierarchy. all second-level interrupts from the em feed into top- level interrupts in the nvic. this two- level hierarchy allows for both fine granular control of interrupt sources and coarse granular control over entire peripherals, while a llowing peripherals to have their own interrupt vector. "9.1. nested vectored interrupt controller (nvic)" on page 100 provides a description of the nvic and an overview of the exception table (arm nomenclature refers to interrupts as exceptions). "9.2. event manager" on page 102 provides a more detailed description of the event manager includ ing a table of all top-level peripheral interrupts and their second-level interrupt sources. in practice, top-level peripheral interrupts are only used to enable or disable interrupts for an entire peripheral. seco nd- level interrupts originate from hardware sources, and therefore are the main focus of applications using interrupts. 9.1. nested vectored in terrupt controller (nvic) the arm ? cortex tm -m3 nested vectored inte rrupt controller (nvic) facilitates low-latency except ion and interrupt handling. the nvic and the processor core interface ar e closely coupled, which enables low-latency interrupt processing and efficient processing of late-arriving inte rrupts. the nvic also maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. the arm ? cortex tm -m3 nvic contains 10 standard interrupts t hat are related to chip and cpu operation and management. in addition to the 10 standard interrupts, it contains 17 individually vectored peripheral interrupts specific to the em346. the nvic defines a list of exceptions. the s e exceptions include not only traditional peripheral interrupts, but also more specialized events such as faults and cpu reset. in the arm ? cortex tm -m3 nvic, a cpu reset event is considered an exception of the highest priority, and the sta ck pointer is loaded from the first position in the nvic exception table. the nvic exception table defines all except ions and their position, including peripheral interrupts. the position of each exception is important since it directly tr anslates to the location of a 32-bit interrupt vector for each interrupt, and defines the hardware priority of exceptions. each exception in the table is a 32-bit address that is loaded into the program counter when that exception occurs. ta b l e 9.1 lists the entire exception table. exceptions 0 (stack pointer) through 15 (systick) are part of the standard arm ? cortex tm -m3 nvic, while exceptions 18 (management) through 32 (debug) are the peri pheral interrupts specific to the em346 peripherals. the peripheral interrupts are listed in greater detail in ta b l e 9.2 .
em346 rev 1.0 101 table 9.1. nvic exception table exception position description ? 0 stack top is loaded from first entry of vector table on reset. reset 1 invoked on power up and warm reset. on fi r s t instruction, drop s to lowest prior - ity (thread mode). asynchronous. nmi 2 cannot be stopped or preempted by any exception but reset. asynchronous. hard fault 3 all classes of fault, when the fault cannot activate because of priority or the con f igurable fault handler has been disabled. synchronous. memory fault 4 mpu mismatch, including access violation and no match. synchronous. bus fault 5 pre-fetch, memory access, and other ad dr ess/me mory-related faults. synchro - nous when precise and asynchronous when imprecise. usage fault 6 usage fault, such as ?undefined instruct ion e xecuted? or ?illegal state transition attempt?. synchronous. ? 7?10 reserved. svcall 11 system service call with svc ins tru ction. synchronous. debug monitor 12 debug monitor, when not halting. synchronous, but only active when enabled. it does not activate if lower prio rity than the current activation. ? 13 reserved. pendsv 14 pendable request for system service. asynchr o nous and only pended by soft - ware. systick 15 system tick timer has fired. asynchronous. ? 16 reserved. ? 17 reserved. management 18 management peripheral interrupt. baseband 19 baseband peripheral interrupt. sleep timer 20 sleep timer peripheral interrupt. serial controller 1 21 serial controller 1 peripheral interrupt. ? 22 reserved. security 23 security peripheral interrupt. mac timer 24 mac timer peripheral interrupt. mac transmit 25 mac transmit peripheral interrupt. mac receive 26 mac receive peripheral interrupt. ? 27 reserved. irqa 28 irqa periphera l interrupt. ? 29 reserved irqc 30 irqc periphera l interrupt. irqd 31 irqd periphera l interrupt. debug 32 debug peripheral interrupt.
em346 102 rev 1.0 the nvic also contains a software-configurable interrup t prioritization mechanism. the reset, nmi, and hard fault exceptions, in that order, are always the highest priority, and are not software-configurable. all other exceptions can be assigned a 5-bit priority number, with low values representing higher priority. if any exceptions have the same software-configurable priority, then the nvic uses the hardware-def ined priority. the hardware- defined priority number is the same as the position of the exception in the exception t able. for example, if irqa and irqc both fire at the same time and have the same software-defined priority, the nvic handles irqa, with priority number 28, first because it has a higher ha rdware priority than irqc with priority number 30. the top-level interrupts are controlled through five arm ? cortex tm -m3 nvic registers: int_cfgset, int_cfgclr, int_pendset, int_pendclr, and int_active . writing 0 into any bit in any of these five register is ineffective. ?? int_cfgset?writing 1 to a bit in int_cf gset enables that to p-level interrupt. ?? int_cfgclr?writing 1 to a bit in int_cfgc lr disables that top-level interrupt. ?? int_pendset?writing 1 to a bit in int_pends et triggers that top-level interrupt. ?? int_pendclr?writing 1 to a bit in int_pen dclr clears that top-level interrupt. ?? int_active cannot be written to and is used for in dicating which interrupts are currently active. int_pendset and int_pendclr set and clea r a simple latch; int_cfgset and int_cfgclr set and clear a mask on the output of the la tch. interrupts ma y be pended and cleared at any time, but any pended interrupt will not be taken unless the corresponding mask (int_cfgset) is set, which allows that interr upt to propagate. if an int_cfgset bit is set and the correspond ing int_pendset bit is set, then the interrupt will propagate and be taken. if int_cfgset is set after int_pendset is set, then the interrupt will also propagate and be taken. interrupt flags (signals) from the top- level interrupts ar e level-sensitive. the second-level interrupt registers, which provide control of the secon d-level event manager peripheral interrupts, are described in ?9.2. event manager? . for further information on the nvic and arm ? cortex tm -m3 exceptions, refer to the arm ? cortex tm -m3 technical reference manual and the arm armv7-m architecture reference manual. 9.2. event manager while the standard arm ? cortex tm -m3 nested vectored interrupt controller provides top-level interrupts into the cpu, the proprietary event manager provides second-level interrupts. the event manager takes a large variety of hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the nvic. effectively, all second-level interrupts from a peripheral are ?ord? together into a single interrupt in the nvic. in addition, the event manager provides missed indicators for the top-level peripheral in terrupts with the register int_miss. the description of each peripheral's in te rr upt configuration and flag registers can be found in the chapters of this datasheet describing each peripheral. figure 9.1 shows the peripheral interrupts block diagram.
em346 rev 1.0 103 figure 9.1. peripheral interrupts block diagram given a peripheral, ?periph?, the event manager regist ers (int_periphcfg and int_periphflag) follow the form: ?? int_periphcfg enables and disables second-level inte rrupts. writing 1 to a bit in the int_periphcfg register enables the second-level interrupt. writing 0 to a bit in the int_periphcfg register disables it. the int_periphcfg register behaves like a mask, and is responsible for allowing the int_periphflag bits to propagate into the top-level nvic interrupts. ?? int_periphflag indicates second-level interrupts that have occurred. writing 1 to a bit in a int_periphflag register clears the second-level inte rrupt. writing 0 to any bit in the int_periphflag register is ineffective. the int_peri phflag register is always active and may be set or cleared at any time, meaning if any second-level interrupt occurs, then the corresponding bit in the int_periphflag register is set regardless of the state of int_periphcfg. if a bit in the int_periphcfg register is set after the corr es po nding bit in the int_periphflag register is set then the second-level interrupt propagates into the top-level interrupts. the interrupt flags (signals) from the second- level interrupts into the top-level interrupts are level-sens itive. if a top-level nvic in terrupt is driven by a second- level em interrupt, then the to p-level nvic interrupt cannot be cleared until all second-level em interrupts are cleared. the int_periphflag register bits are designed to remain se t if the secon d-level interrupt event re-occurs at the same moment as the int_periphflag register bit is being cleared. this ensures the re-occurring second-level interrupt event is not missed. if another enabled second-level interrupt event of the same typ e occurs before the first interrupt event is cleared, the second interrupt event is lost because no counting or queuing is used. however, this condition is detected and stored in the top-level int_miss register to facilitate software detection of such problems. the int_miss register is ?acknowledged? in the same way as the int_periphflag register-by writing a 1 into the corresponding bit to be cleared. q latch s r read q latch s r write 1 read and write 1 q latch s r write 1 write 1 interrupts into nvic/cpu int_pendset int_pendclr int_cfgset int_cfgclr int_miss source interrupt events q latch s r write 1 read and or int_periphcfg int_periphflag read or write 1 peripheral interrupt instance interrupts from all peripherals and or
em346 104 rev 1.0 ta b l e 9.2 provides a map of all peripheral interrupts. this map lists the top-level nvic interrupt bits and, if there is one, the corresponding second-level em interrupt re gister bits that feed the top-level interrupts. 9.3. non-maskabl e interrupt (nmi) the non-maskable interrupt (nmi) is a special case. despite being one of the 10 standard arm ? cortextm-m3 nvic interrupts, it is sourced from the event manager like a peripheral interrupt. the nmi has two second-level sources; failure of the 24 mhz crystal and watchdog low water mark. 1. failure of the 24 mhz crystal: if the em346's main clo ck, sysclk, is operating from the 24 mhz crystal and the cryst al fails, the em346 de tects the failure and automaticall y switches to the internal 12 mhz rc clock. when t his failure detection and switch has occurred, the em346 triggers the clk24m_fail second- table 9.2. nvic and em peripheral interrupt map nvic interrupt (top-level) em interrupt (second-level) nvic interrupt (top-level) em interrupt (second-level) 16 int_debug 4 int_sleeptmr 15 int_irqd 3 int_bb 14 int_irqc 2 int_mgmt 13 reserved 1 reserved. 12 int_irqa 0 reserved 11 reserved 10 int_macrx 9 int_mactx 8 int_mactmr 7 int_sec 6 reserved 5 int_sc1 int_sc1flag register 14 int_sc1parerr 13 int_sc1frmerr 12 int_sctxuldb 11 int_sctxulda 10 int_scrxuldb 9 int_scrxulda 8 int_scnak 7 int_sccdmfin 6 int_sctxfin 5 int_scrxfin 4 int_sctxund 3 int_scrxovf 2 int_sctxidle 1 int_sctxfree 0 int_scrxval
em346 rev 1.0 105 level interrupt, which then triggers the nmi. 2. watchdog low water mark: if the em346's watchdog is active and the watchdog counter has not been reset for nominally 1.792 s, the watchdog triggers the watchdog_in t secon d -level interrupt, which then triggers the nmi. 9.4. faults four of the exceptions in the nvic are faults: hard fa ult, memory fault, bus fault, and usage fault. of these, three (hard fault, memory fault, and usage fault) are standard arm ? cortextm-m3 exceptions. the bus fault, though, is derived from em346-specific sources. the bus fault so urces are recorded in the scs_afsr register. note that it is possible for one a ccess to set multiple scs_afsr bits. also note that mpu configurations could prevent most of these bus fault access es from occurring, with the advantage that illegal writes are made precise faults. the four bus faults are: ?? wrongsize?generated by an 8-bit or 16-bit read or write of an apb pe ripheral register. this fault can also result from an unaligned 32-bit access. ?? protected?generated by a user mode (unprivileged) write to a system apb or ahb peripheral or protected ram (see "5.2.2.3. ram memory protection" on page 31 ). ?? reserved?generated by a read or write to an address within an apb peripheral's 4 kb block range, but the address is above the last physical register in that block range. also generated by a read or write to an address above the top of ram or flash. ?? missed?generated by a se cond scs_afsr fault. in practice, this bit is not seen since a second fault also generates a hard fault, and the hard fault preempts the bus fault.
em346 106 rev 1.0 9.5. registers address: 0xe000e100; reset: 0x0 register 9.1. int_cfgset: top-level set interrupts configuration register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 int_debug bit 15 14 13 12 11 10 9 8 name int_irqd int_irqc reserved int_irqa reserved int_macrx int_mactx int_mactmr bit 7 6 5 4 3 2 1 0 name int_sec reserved int_sc1 int_sleeptmr int_bb int_mgmt reserved reserved bit name bit field access description int_debug [16] rw write 1 to enable debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to enable irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to enable irqc interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to enable irqa interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to enable mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to enable mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to enable mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to enable security interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to enable serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to enable sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to enable baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to enable management interrupt. (writing 0 has no effect.)
em346 rev 1.0 107 address: 0xe000e180 reset: 0x0 register 9.2. int_cfgclr: top-level clear interrupts configuration register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 int_debug bit 15 14 13 12 11 10 9 8 name int_irqd int_irqc reserved int_irqa reserved int_macrx int_mactx int_mactmr bit 7 6 5 4 3 2 1 0 name int_sec reserved int_sc1 int_sleeptmr int_bb int_mgmt reserved reserved bitname bitfield access description int_debug [16] rw write 1 to disable debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to disable irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to disable irqc interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to disable irqa interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to disable mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to disable mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to disable mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to disable security interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to disable serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to disable sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to disable baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to disable management inte rrupt. (w riti ng 0 has no effect.)
em346 108 rev 1.0 address: 0xe000e200 reset: 0x0 register 9.3. int_pendset: top-level set int errupts pending register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 int_debug bit 15 14 13 12 11 10 9 8 name int_irqd int_irqc reserved int_irqa reserved int_macrx int_mactx int_mactmr bit 7 6 5 4 3 2 1 0 name int_sec reserved int_sc1 int_sleeptmr int_bb int_mgmt reserved reserved bitname bitfield access description int_debug [16] rw write 1 to pend debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to pend irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to pend irqc interrupt. (writing 0 has no effect.). int_irqa [12] rw write 1 to pend irqa interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to pend mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to pend mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to pend mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to pend security interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to pend serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to pend sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to pend baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to pend management interrupt. (writing 0 has no effect.)
em346 rev 1.0 109 address: 0xe000e280 reset: 0x0 register 9.4. int_pendclr: top-level clea r inte rrupts pending register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 int_debug bit 15 14 13 12 11 10 9 8 name int_irqd int_irqc reserved int_irqa reserved int_macrx int_mactx int_mactmr bit 7 6 5 4 3 2 1 0 name int_sec reserved int_sc1 int_sleeptmr int_bb int_mgmt reserved reserved bitname bitfield access description int_debug [16] rw write 1 to unpend debug interrupt. (writing 0 has no effect.) int_irqd [15] rw write 1 to unpend irqd interrupt. (writing 0 has no effect.) int_irqc [14] rw write 1 to unpend irqc interrupt. (writing 0 has no effect.) int_irqa [12] rw write 1 to unpend irqa interrupt. (writing 0 has no effect.) int_macrx [10] rw write 1 to unpend mac receive interrupt. (writing 0 has no effect.) int_mactx [9] rw write 1 to unpend mac transmit interrupt. (writing 0 has no effect.) int_mactmr [8] rw write 1 to unpend mac timer interrupt. (writing 0 has no effect.) int_sec [7] rw write 1 to unpend security interrupt. (writing 0 has no effect.) int_sc1 [5] rw write 1 to unpend serial controller 1 interrupt. (writing 0 has no effect.) int_sleeptmr [4] rw write 1 to unpend sleep timer interrupt. (writing 0 has no effect.) int_bb [3] rw write 1 to unpend baseband interrupt. (writing 0 has no effect.) int_mgmt [2] rw write 1 to unpend management interrupt. (writing 0 has no effect.)
em346 110 rev 1.0 address: 0xe000e300 reset: 0x0 register 9.5. int_active: top-level active interrupts register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 int_debug bit 15 14 13 12 11 10 9 8 name int_irqd int_irqc reserved int_irqa reserved int_macrx int_mactx int_mactmr bit 7 6 5 4 3 2 1 0 name int_sec reserved int_sc1 int_sleeptmr int_bb int_mgmt reserved reserved bitname bitfield access description int_debug [16] r debug interrupt active. int_irqd [15] r irqd interrupt active. int_irqc [14] r irqc interrupt active. int_irqa [12] r irqa interrupt active. int_macrx [10] r mac receive interrupt active. int_mactx [9] r mac transmit interrupt active. int_mactmr [8] r mac timer interrupt active. int_sec [7] r security interrupt active. int_sc1 [5] r serial controller 1 interrupt active. int_sleeptmr [4] r sleep timer interrupt active. int_bb [3] r baseband interrupt active. int_mgmt [2] r management interrupt active.
em346 rev 1.0 111 address: 0x4000a820 reset: 0x0 register 9.6. int_miss: top-level missed interrupts register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name int_ mis s irqd int_ missirqc reserved int_ missirqa reserved int_ missmacrx int_ missmactx int _ miss mactmr bit 7 6 5 4 3 2 1 0 name int_ missse c re served int_ misssc1 int_ mi sssleep int_ missbb int_ missmgmt 0 0 bitname bitfield access description int_missirqd [15] rw irqd interrupt missed. int_missirqc [14] rw irqc interrupt missed. int_missirqa [12] rw irqa interrupt missed. int_missmacrx [10] rw mac receive interrupt missed. int_missmactx [9] rw mac transmit interrupt missed. int_missmactmr [8] rw mac timer interrupt missed. int_misssec [7] rw security interrupt missed. int_misssc1 [5] rw serial controller 1 interrupt missed. int_misssleep [4] rw sleep timer interrupt missed. int_missbb [3] rw baseband interrupt missed. int_missmgmt [2] rw management interrupt missed.
em346 112 rev 1.0 address: 0xe000ed3c reset: 0x0 register 9.7. scs_afsr: auxiliary fault status register bit 31 30 29 28 27 26 25 24 name 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 name 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name 0 0 0 0 wrongsize protected reserved missed bitname bitfield access description wrongsize [3] rw a bus fault resulted from an 8-bit or 16-bit read or write of an apb peripheral register. this fault can also result from an unaligned 32-bit access. protected [2] rw a bus fault resulted from a user mode (unp rivile ged ) write to a system apb or ahb peripheral or protected ram. reserved [1] rw a bus fault resulted from a read or writ e to an ad dress within an apb peripheral's 4 kb bloc k range, but above the last physical regist er in that block. can also result from a read or write to an address ab ove the top of ram or flash. missed [0] rw a bus fault occurred when a bit was already set in this register.
em346 rev 1.0 113 10. trace port interface unit (tpiu) the em346 integrates the standard arm ? trace port interface unit (tpiu). the tpiu receives a data stream from the on-chip trace data generated by the standard arm ? instrument trace macrocell (itm), buffers the data in a fifo, formats the data, and serializes the data to be sent off-chip through alternate functions of the gpio. since the primary function of the tpiu is to provide a bridge between on-chip arm system debug components and external gpio, the tpiu itself does not generate data. figure 10.1 illustrates the three pr imary component s of the tpiu. figure 10.1. tpiu block diagram the tpiu is composed of: ?? asynchronous fifo: the asynchrono us fifo receives a data stream generated by the itm and enables the trace data to be sent off-chip at a speed that is not dependent on the speed of the data source. ?? formatter: the formatter inserts source id signals into the data packet stream so that trace data can be re- associated with its trace source. since the em346 has only one trace source, the itm, it is not necessary to use the formatter, and, therefore, the formatter only adds overhead into the data stream. since certain modes of the tpiu automatically en able the formatter, these modes should be avoided whenever possible. ?? trace out: the trace out block serializes the data and se nds it off-chip by the proper alternate output gpio functions. the six pins available to the tpiu are: ?? swo ?? traceclk ?? tracedata0 ?? tracedata1 ?? tracedata2 ?? tracedata3 since these pins are alternate outputs of gpio, refer to "17. pin definitions" on page 121 and "7. gpio (general purpose input/output)" on page 48 for complete pin descript ions an d co nfigurations. notes: 1. the swo alternate output is mirrored on gpio pc1 and pc2. 2. gpio pc1 sha r es both the swo and tracedata0 alternate outputs. this is possible because swo and tracedata0 are mutually exclusive, and only one may be selected at a time in the trace-out block. the ember software utilizes the tpiu to efficiently output debug data. altering the tpiu configuration may conflict with ember debug output. for further information on the tpiu, cont act s ilicon labs supp ort for the arm ? cortex tm -m3 technical reference manual, the arm ? coresight tm components technical reference manual, the arm ? v7-m architecture reference manual, and the arm ? v7-m architecture application level reference manual. asynchronous fifo formatter itm trace out (serializer) traceclk tracedata2 tracedata3 tracedata1 tracedata0 swo
em346 114 rev 1.0 11. instrumentation trace macrocell (itm) the em346 integrates the standard arm ? instrumentation trace macrocell (itm). the itm is an application-driven trace source that supports printf style debugging to trac e software events and emits diagnostic system information from the arm ? data watchpoint and trace (dwt). software us ing the itm generates software instrumentation trace (swit). in addition, the itm provides coarse-g rained timestamp functionality. the itm emits trace information as packets, and these pack ets are sent to the trace port inte rface unit (tpiu). three sources can generate packets. if multiple sources generate packets at the same time, the itm arbitrates the order in which the packets are output. the three sources, in decreasing order of priority, are: ?? software trace. software can write directly to itm stimulus registers, emitting packets. ?? hardware trace. the dwt genera tes packets that the itm emits. ?? time stamping. timestamps are emitted relative to packets, and the itm contains a 21-bit counter to generate the timestamps. the ember software utilizes the itm for efficiently ge nerating debug dat a. altering the itm configuration may conflict with ember debug output. for further info rmation on the itm, cont ac t s ilicon labs support for the arm ? cortextm-m3 technical reference manual, the arm ? coresight? components technical reference manual, the arm? v7-m architecture reference manual, and the arm? v7-m architecture application level reference manual.
em346 rev 1.0 115 12. data watchpoint and trace (dwt) the em346 integrates the standard arm ? data watchpoint and trace (dwt). the dwt provides hardware support for profiling and debugging functionalit y. the dwt offers the following features: ?? pc sampling ?? comparators to support: ?? watchpoints - enters debug state ?? data tracing ?? cycle count matched pc sampling ?? exception trace support ?? instruction cycle count calculation support apart from exception tracing, dwt f unction ality is co unter- or comparator-based. watchpoint and data trace support use a set of compare, mask, and function register s. dwt-generated events result in one of two actions: ?? generation of a hardware event packet. packets are generated and combined with software events and timestamp packets for transmission through the itm/tpiu. ?? a core halt - entry to debug state. when exception tracing is enabled, the dwt emits an e x ception trace packet under the following conditions: ?? exception entry (from thread mode or pre-emption of a thread or handler). ?? exception exit when exiting a handler. ?? exception return when reentering a preempted thread or handler code sequence. the dwt is designed for use with advanc ed profiling and debu g tools, available from mu ltiple vendors. altering dwt configuration may conflict with the opera tion of advanced prof iling and debug tools. for further information on the dwt , contact silicon labs support for the arm ? cortextm-m3 technical reference manual, the arm ? coresight? components technical reference manual, the arm ? v7-m architecture reference manual, and the arm ? v7-m architecture application level reference manual.
em346 116 rev 1.0 13. flash patch and breakpoint (fpb) the em346 integrates the standard arm ? flash patch and breakpoint (fpb). the fpb implements hardware breakpoints. the fpb also provides support for remapping of specific instruction or literal locations from flash memory to an address in ram memory. the fpb contains: ?? two literal comparators for matching against liter al loads from flash space and remapping to a corresponding ram space. ?? six instruction compar ators for matching against instruction fetches from flash space and remapping to a corresponding ram space. alternatively, the comparators can be individually configured to return a breakpoint instruction to the processor core on a match, implem enting hardware breakpoint capability. the fpb contains a global enable, but a l so individual enables for the eight comparators. if the comparison for an entry matches, the address is remapped to the address define d in the remap register plus and offset corresponding to the comparator that matched. alternately, the address is remapped to a breakpoint instruction. the comparison happens on the fly, but the result of the comparison occurs too late to stop the original instruction fetch or literal load taking place from the flash space. the processor ignor es this transaction, however, and only the remapped transaction is used. memory protection unit (mpu) lookups are performed fo r the original address, not the remapped address. unaligned literal accesses are not remapped. the orig inal access to the bus ta kes place in this case. the fpb is designed for use with advanced debug tools, available from multiple vendors. altering the fpb configuration may conflict with the operation of advanced debug tools. for further information on the fpb, co nt act silicon labs support for the arm ? cortextm-m3 technical reference manual, the arm ? coresight? components technical reference manual, the arm ? v7-m architecture reference manual, and the arm ? v7-m architecture application level reference manual.
em346 rev 1.0 117 14. integrated voltage regulator the em346 integrates two low dropo ut regulators to provide 1.8 v and 1.25 v power supplies as detailed in ta b l e 14.1 . the 1v8 regulator supplies the analog and memories, and the 1v25 regulator supplies the digital core. in deep sleep, the voltage regulators are disabled. when enabled, the 1v8 regulator steps down the pads supply voltage (vdd_pads) from a nominal 3.0 v to 1.8 v. t h e regulator output pin (vreg_out) must be decoupled externally with a suitable capacitor. vreg_out should be connected to the 1.8 v supply pins vdda, vdd_rf, vdd_vco, vdd_synth, vdd_if , and vdd_mem. the 1v 8 regulator can supply a maximum of 50 ma. when enabled, the 1v25 regulator steps down vdd_pads to 1.25 v. the regulator output pin (vdd_core, pin 1 7 ) must be decoupled externally with a suitable capacito r. it should connect to the other vdd_core pin (pin 44). the 1v25 regulator can supply a maximum of 10 ma. the regulators are controlled by the digital portion of the chip as described in "6. system modules" on page 33 . an example of decoupling capacitors and pcb layout can be fou nd in the application notes (see the various ember em35x reference design documentation). table 14.1. integrated voltage regulator specifications spec point min typ max units comments supply range for regulator 2.1 3.6 v vdd_pads 1v8 regulator output ?5% 1.8 +5% v regulator output after initialization 1v8 regulator output after reset ?5% 1.75 +5% regulator output after reset 1v25 regulator output ?5% 1.25 +5% v regulator output after initialization 1v25 regulator output after reset ?5% 1.45 +5% regulator output after reset 1v8 regulator capacitor 2.2 f low esr tantalum capacitor esr greater than 2 ? esr less than 10 ? de-coupling less than 100 nf ceramic 1v25 regulator capacitor 1.0 f ceramic capacitor (0603) 1v8 regulator output current 0 50 ma regulator output current 1v25 regulator output ? current 0 10 ma regulator output current no load current 600 a no load current (bandgap and regulators) 1v8 regulator current limit 200 ma short circuit current limit 1v25 regulato r current limit 25 ma shor t circuit current limit 1v8 regulator start-up time 50 s 0 v to por threshold 2.2 f capacitor 1v25 regulator start-up time 50 s 0 v to por threshold 1.0 f capacitor
em346 118 rev 1.0 an external 1.8 v regulator may replace both internal regulators. th e em346 ca n control external regulators during deep sleep using open-drain gpio pa7, as described in "7. gpio (general purpose input/output)" on page 48 . the em346 drives pa7 low during deep sleep to disable the exter nal r egulator, and an external pull-up is required to release this signal to indicate that supply volt age should be provided. current consumption increases approximately 2 ma when using an external regulator. when using an external regulator, the internal regulators sh ou ld be disabled through ember software. the always-on domain needs to be minimally powered at 2.1 v and can not be powered from the external 1.8 v regulator.
em346 rev 1.0 119 15. serial wire and jtag (swj) interface the em346 includes a standard serial wire and jtag (swj) interface. the swj is the primary debug and programming interface of the em346. the swj gives debug tools access to the internal buses of the em346 and allows for non-intrusive memory and register access as well as cpu halt-step style debugging. therefore, any design implementing the em346 should make the swj signals readily available. serial wire is an arm ? standard, bidirectional, two-wire protocol des igned to replace jtag and provides all the normal jtag debug and test functionality. jtag is a standard five-wire protocol providing debug and test functionality. in addition, the two serial wire signals (s wdio and swclk) are overlaid on two of the jtag signals (jtms and jtck). this keeps the design compact and allows debug tools to switch between serial wire and jtag as needed, without changing pin connections. while serial wire and jtag offer the same debug and te st functiona lity , silicon labs recommends serial wire. serial wire uses only two pins instead of five, and of fers a simple communication protocol, high performance data rates, low power, built-in error detection, and protection from glitches. the arm coresight? debug access port (dap) comprises t he serial wire and jtag interface (swj). as illustrated in figure 15.1 , the dap includes two primary components: a debug port (the swj-dp) and an access port (the ahb-ap). the swj-dp provides external debug a c cess while the ahb-ap provides internal bus access. an external debug tool connected to the em346's debug pins communicates with the swj-dp. the swj-dp then communicates with the ahb-ap. finally, the ahb-ap communicates on the internal bus. figure 15.1. swj block diagram serial wire and jtag share five pins: ?? jrst ?? jtdo ?? jtdi ?? swdio/jtms ?? swclk/jtck note: the swj pins are forced functions, and their corresponding gpio_pxcfgh/l configurations are overridden when the em346 resets. an application must disable all debug swj debug functionality to reclaim any of the four swj gpios: pc0, pc2, pc3, and pc4. since these pins can be repurposed, refer to "17. pin definitions" on page 121 and "7.3. forced functions" on page 50 for complete pin descript ions an d co nfigurations. for further information on the swj, contact customer support for application notes and arm ? coresight? documentation. swj-dp swj-dp select swj-dap sw interface jtag interface control and ap interface pins ahb-ap ahb
em346 120 rev 1.0 16. ordering information use the following part number to order the em346: ? the em300 series package is rohs-compliant. it conforms to the european court of justice decision regarding th e de ca-bde exemption of the rohs directive. it is pfos-compliant in accord ance with european directive 2006/122/ec*1 released in december 2006. the to eia specification 481. to order parts, contact silicon labs at 1+(877) 444-3032, or find a sales office or distributor on our website, www.silabs.com . part number part packaging material configuration EM346-RTR em346 2000 unit reel standard
em346 rev 1.0 121 17. pin definitions 17.1. pin definitions figure 17.1. em346 pin definitions refer to "7. gpio (general purpose input/output )" on page 48 for details about selecting gpio pin functions. vdd_24mhz vdd_vco rf_n rf_p vdd_rf rf_tx_alt_p rf_tx_alt_n vdd_if nc vdd_padsa pc5, tx_active pb0, vref, irqa, traceclk pc4, jtms, swdio pc3, jtdi pc2, jtdo, swo swclk, jtck pb2, sc1mosi, sc1rxd pb1, sc1miso, sc1txd nc vdd_pads pa5, pti_data, nbootmode, tracedata3 pa4, pti_en, tracedata2 nc vdd_pads pc1, swo, tracedata0 vdd_mem pc0, jrst, irqd, tracedata1 nc nc nc vdd_core vdd_pre vdd_synth oscb osca nc vdd_pads nc pb4, sc1nrts, sc1nssel pb3, sc1ncts, sc1sclk vdd_core vdd_pads vreg_out pc6, osc32b, ntx_active nc pc7, osc32a, osc32_ext pa7, reg_en 13 14 15 16 17 18 19 20 21 22 23 24 12 11 nreset 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 48 47 46 45 44 43 42 41 40 39 38 37 49 gnd em346
em346 122 rev 1.0 table 17.1. em346 pin descriptions pin # signal direction description 1 vdd_24mhz power 1.8 v high-frequency oscillator supply 2 vdd_vco power 1. 8 v vco supply 3 rf_p i/o differential (with rf_n) receiv er in put/transmitter output 4 rf_n i/o differential (with rf_p) receiv er inpu t/transmitter output 5 vdd_rf power 1.8 v rf supply (lna and pa) 6 rf_tx_alt_p o differential (with rf_tx_alt_n) tr an smitter output (optional) 7 rf_tx_alt_n o differential (with rf_tx_alt_p) tra n smitter output (optional) 8 vdd_if power 1.8 v if supply (mixers and filters) 9 nc do not connect 10 vdd_padsa power analog pad supply (1.8 v) 11 pc5 i/o digital i/o tx_active o logic-level control for external rx/tx switch. the em346 baseband con - trols tx_active and drives it high (vdd_pads) when in tx mode. select alternate output function with gpio_pccfgh[7:4] 12 nreset i active low chip reset (internal pull-up) 13 pc6 i/o digital i/o osc32b i/o 32.768 khz crystal oscillator select analog function with gpio_pccfgh[11:8] ntx_active o inverted tx_active signal (see pc5) select alternate output func tion with g pio_pccfgh[11:8] 14 pc7 i/o digital i/o osc32a i/o 32.768 khz crystal oscillator select analog function with gpio_pccfgh[15:12] osc32_ext i digital 32.768 khz clock input source 15 vreg_out power regulator output (1.8 v while awake, 0 v during deep sleep) 16 vdd_pads power pads supply (2.1?3.6 v) 17 vdd_core power 1.25 v digital core supply decoupling 18 pa7 i/o high current digital i/o disable reg_en with gpio_dbgcfg[4] reg_en o external regulator open drain output enabled after reset
em346 rev 1.0 123 19 pb3 i/o digital i/o sc1ncts i uart cts handshake of serial controller 1 enable with sc1_uartcfg[5] select uart with sc1_mode sc1sclk i spi slave clock of serial controller 1 enable slave with sc1_spicfg[4] select spi with sc1_mode 20 pb4 i/o digital i/o sc1nrts o uart rts handshake of serial controller 1 enable with sc1_uartcfg[5] select uart with sc1_mode select alternate output function with gpio_pbcfgh[3:0] sc1nssel i spi slave select of serial controller 1 enable slave with sc1_spicfg[4] select spi with sc1_mode 21 nc do not connect 22 nc do not connect 23 vdd_pads power pads supply (2.1?3.6 v) 24 nc do not connect 25 nc do not connect 26 pa4 i/o digital i/o pti_en o frame signal of packet trace interface (pti) disable trace interface in arm core enable pti in ember software select alternate output fu n c tion with gpio_pacfgh[3:0] tracedata2 o synchronous cpu trace data bit 2 select 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output fu n c tion with gpio_pacfgh[3:0] table 17.1. em346 pin descriptions (continued) pin # signal direction description
em346 124 rev 1.0 27 pa5 i/o digital i/o pti_data o data signal of packet trace interface (pti) disable trace interface in arm core enable pti in ember software select alternate output fu n c tion with gpio_pacfgh[7:4] nbootmode i activate fib monitor instead of main program or bootloader when coming out of reset. signal is active during and immediately after a reset on nreset. see "7.5. boot configuration" on page 51 . tracedata3 o synchronous cpu trace data bit 3 select 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output fu n c tion with gpio_pacfgh[7:4] 28 vdd_pads power pads supply (2.1?3.6 v) 29 nc do not connect 30 pb1 i/o digital i/o sc1miso o spi slave data out of serial controller 1 select spi with sc1_mode select slave with sc1_spicr select alternate output fu n c tion with gpio_pbcfgl[7:4] sc1txd o uart transmit data of serial controller 1 select uart with sc1_mode select alternate output fu n c tion with gpio_pbcfgl[7:4] 31 pb2 i/o digital i/o sc1mosi i spi slave data in of serial controller 1 select spi with sc1_mode select slave with sc1_spicr sc1rxd i uart receive data of serial controller 1 select uart with sc1_mode 32 swclk i/o serial wire clock input/output with debugger selected when in serial wire mode (see jtms description, pin 35) jtck i jtag clock input from debugger selected when in jtag mode (default mode, see jtms description, pin 35) internal pull-down is enabled table 17.1. em346 pin descriptions (continued) pin # signal direction description
em346 rev 1.0 125 33 pc2 i/o digital i/o enable with gpio_dbgcfg[5] jtdo o jtag data out to debugger selected when in jtag mode (default mode, see jtms description, pin 35) swo o serial wire output asynchronous trace output to debugger select asynchronous trace interface in arm core enable trace interface in arm core select alternate output func tion with gpio_pccfgl[11:8] enable serial wire mode (see jtms description, pin 35) internal pull-up is enabled 34 pc3 i/o digital i/o either enable with gpio_dbgcfg[5], ? or enable serial wire mode (see jtms description) jtdi i jtag data in from debugger selected when in jtag mode (default mode, see jtms description, pin 35) internal pull-up is enabled 35 pc4 i/o digital i/o enable with gpio_dbgcfg[5] jtms i jtag mode select from debugger selected when in jtag mode (default mode) jtag mode is enabled after pow er-up or by forcing nreset low sele ct serial wire mode using the arm-d efine d protocol through a debug - ger internal pull-up is enabled swdio i/o serial wire bidirectional data to/from debugger enable serial wire mode (see jtms description) select serial wire mode using the arm-d efine d protocol through a debug - ger internal pull-up is enabled 36 pb0 i/o digital i/o irqa i external interrupt source a traceclk o synchronous cpu trace clock enable trace interface in arm core select alternate output fu n c tion with gpio_pbcfgl[3:0] 37 vdd_pads power pads supply (2.1?3.6 v) table 17.1. em346 pin descriptions (continued) pin # signal direction description
em346 126 rev 1.0 38 pc1 i/o digital i/o swo (see also pin 33) o serial wire output asynchronous trace output to debugger select asynchronous trace interface in arm core enable trace interface in arm core select alternate output fu n c tion with gpio_pccfgl[7:4] tracedata0 o synchronous cpu trace data bit 0 select 1-, 2- or 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output fu n c tion with gpio_pccfgl[7:4] 39 vdd_mem power 1.8 v supply (flash, ram) 40 pc0 i/o high current digital i/o either enable with gpio_dbgcfg[5], ? or enable serial wire mode (see jtms description, pin 35) and disable traceda t a1 jrst i jtag reset input from debugger selected when in jtag mode (default mode, see jtms description) and traceda t a1 is disabled internal pull-up is enabled irqd i default external interrupt source d. irqc and irqd external interrupts can be ma pped to any digital i/o pin using the gpio_irqsel and gpio_irqdsel registers. tracedata1 o synchronous cpu trace data bit 1 select 2- or 4-wire synchronous trace interface in arm core enable trace interface in arm core select alternate output fu n c tion with gpio_pccfgl[3:0] 41 nc do not connect 42 nc do not connect 43 nc do not connect 44 vdd_core power 1.25 v digital core supply decoupling 45 vdd_pre power 1.8 v prescaler supply 46 vdd_synth power 1.8 v synthesizer supply 47 oscb i/o 24 mhz crystal oscillator or left open when using external clock input on osca table 17.1. em346 pin descriptions (continued) pin # signal direction description
em346 rev 1.0 127 48 osca i/o 24 mhz crystal oscillator or external clock input. ( an external clock input should only be u s ed for test and debug purposes. if used in this manner, the external clock input should be a 1.8 v, 50% duty cycle, square wave.) 49 gnd ground ground supply pad in the bottom cent er of the package forms pin 49. see the various ember em35x reference design documentation for pcb con - siderations. table 17.1. em346 pin descriptions (continued) pin # signal direction description
em346 128 rev 1.0 18. package the em346 package is a plastic 48-pin qfn that is 7 mm x 7 mm. figure 18.1 illustrates the package drawing. figure 18.1. package drawing
em346 rev 1.0 129 table 18.1. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0 0.035 0.05 a2 ? 0.65 0.67 a3 0.203 ref b 0.2 0.25 0.3 d 7 bsc e 7 bsc e 0.5 bsc j 5.2 5.3 5.4 k 5.2 5.3 5.4 l 0.35 0.40 0.45 aaa 0.10 bbb 0.1 ccc 0.08 ddd 0.1 eee 0.1 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vkkd-4. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
em346 130 rev 1.0 figure 18.2. solder mask dimensions table 18.2. pcb land pattern dimension min max c1 6.80 6.90 c2 6.80 6.90 e 0.50 bsc x1 0.20 0.30 x2 5.20 5.40 y1 0.75 0.85 y2 5.20 5.40 notes: general 1. all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60mm minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electr o-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 4x4 array of 1.1 mm square openings on 1.3 mm pitch can be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ ipc j-std-020c specification for small body components.
em346 rev 1.0 131 19. top marking figure 19.1 shows the part marking for the em346 series. the ci rcle in the top corner indicates pin 1. pins are numbered counter-clockwise from pin 1 with 12 pins per package edge. figure 19.1. part marking for em346 table 19.1. 48-pin qfn top marking explanation mark method: laser pin 1 marking: circle = 0.40 mm diameter (top-left justified) line 1 marking: logo and device part number right justified silicon labs logo . ? line 2 marking: tttttt = mfg code yy=year ww-work week manufacturing code from the assembly purchase for m . assigned by the assembly house. corre - sponds to the year and work week. right justified line 3 marking: circle = 1.3 mm diameter center justified country of origin iso abbreviation right justified ?e3? indicates sn solder finish. tw
em346 132 rev 1.0 a ppendix ar egister a ddress t able block cm_lv 40004000C40004038 cm_lv address name type reset description 40004038 peripheral_disable rw 0 peripheral disable register block interrupts 4000a000C4000afff interrupts address name type reset description 4000a808 int_sc1flag rw 0 serial controller 1 interrupt flag register 4000a814 int_gpioflag rw 0 gpio interrupt flag register 4000a820 int_miss rw 0 top-level missed interrupts register 4000a848 int_sc1cfg rw 0 serial controller 1 interrupt configuration register 4000a854 sc1_intmode rw 0 serial controller 1 interrupt mode register 4000a860 gpio_intcfga rw 0 gpio interrupt a co nfigur ation register 4000a864 gpio_intcfgb rw 0 gpio interrupt b co nfigur ation register 4000a868 gpio_intcfgc rw 0 gpio interrupt c configuration register 4000a86c gpio_intcfgd rw 0 gpio interrupt d configuration register
em346 rev 1.0 133 block gpio 4000b000C4000bfff general purpose io address name type reset description 4000b000 gpio_pacfgl rw 4444 port a configuration register (low) 4000b004 gpio_pacfgh rw 4444 port a configuration register (high) 4000b008 gpio_pain rw 0 port a input data register 4000b00c gpio_paout rw 0 port a output data register 4000b010 gpio_paset rw 0 port a output set register 4000b014 gpio_paclr rw 0 port a output clear register 4000b400 gpio_pbcfgl rw 4444 port b configuration register (low) 4000b404 gpio_pbcfgh rw 4444 port b configuration register (high) 4000b408 gpio_pbin rw 0 port b input data register 4000b40c gpio_pbout rw 0 port b output data register 4000b410 gpio_pbset rw 0 port b output set register 4000b414 gpio_pbclr rw 0 port b output clear register 4000b800 gpio_pccfgl rw 4444 port c configuration register (low) 4000b804 gpio_pccfgh rw 4444 port c configuration register (high) 4000b808 gpio_pcin rw 0 port c input data register 4000b80c gpio_pcout rw 0 port c output data register 4000b810 gpio_pcset rw 0 port c output set register 4000b814 gpio_pcclr rw 0 port c output clear register 4000bc00 gpio_dbgcfg rw 10 gpio debug configuration register 4000bc04 gpio_dbgstat r 0 gpio debug status register 4000bc08 gpio_pawake rw 0 port a wakeup monitor register 4000bc0c gpio_pbwake rw 0 port b wakeup monitor register 4000bc10 gpio_pcwake rw 0 port c wakeup monitor register 4000bc14 gpio_irqcsel rw f interrupt c select register 4000bc18 gpio_irqdsel rw 10 interrupt d select register 4000bc1c gpio_wakefilt rw 0 gpio wakeup filtering register
em346 134 rev 1.0 block serial 4000c000C4000cfff serial controllers address name type reset description 4000c800 sc1_rxbega rw 20000000 receive dma begin address register a 4000c804 sc1_rxenda rw 20000000 receive dma end address register a 4000c808 sc1_rxbegb rw 20000000 receive dma begin address register b 4000c80c sc1_rxendb rw 20000000 receive dma end address register b 4000c810 sc1_txbega rw 20000000 transmit dma begin address register a 4000c814 sc1_txenda rw 20000000 transmit dma end address register a 4000c818 sc1_txbegb rw 20000000 transmit dma begin address register b 4000c81c sc1_txendb rw 20000000 transmit dma end address register b 4000c820 sc1_rxcnta r 0 receive dma count register a 4000c824 sc1_rxcntb r 0 receive dma count register b 4000c828 sc1_txcnt r 0 transmit dma count register 4000c82c sc1_dmastat r 0 serial dma status register 4000c830 sc1_dmactrl rw 0 serial dma control register 4000c834 sc1_rxerra r 0 dma first receive error register a 4000c838 sc1_rxerrb r 0 dma first receive error register b 4000c83c sc1_data rw 0 serial data register 4000c840 sc1_spistat r 0 spi status register 4000c848 sc1_uartstat r 40 uart status register 4000c854 sc1_mode rw 0 serial mode register 4000c858 sc1_spicfg rw 0 spi configuration register 4000c85c sc1_uartcfg rw 0 uart configuration register 4000c860 sc1_ratelin rw 0 serial clock linear prescaler register 4000c864 sc1_rateexp rw 0 serial clock exponential prescaler register 4000c868 sc1_uartper rw 0 uart baud rate period register 4000c86c sc1_uartfrac rw 0 uart baud rate fractional period register 4000c870 sc1_rxcntsaved r 0 saved receive dma count register
em346 rev 1.0 135
em346 136 rev 1.0 block nvic e000e000 - e000efff nested vectored interrupt controller address name type reset description e000e100 int_cfgset rw 0 top-level set interrupts configuration register e000e180 int_cfgclr rw 0 top-level clear interrupts configuration register e000e200 int_pendset rw 0 top-level set interrupts pending register e000e280 int_pendclr rw 0 top-level clear interrupts pending register e000e300 int_active r 0 top-level active interrupts register e000ed3c scs_afsr rw 0 auxiliary fault status register
em346 rev 1.0 137 a ppendix ba bbreviations and a cronyms acronym/abbreviation meaning ack acknowledgment adc analog to digital converter aes advanced encryption standard agc automatic gain control ahb advanced high speed bus apb advanced peripheral bus cbc-mac cipher block chaining?message authentication code cca clear channel assessment ccm counter with cbc-mac mode for aes encryption ccm* improved counter with cbc-ma c mode for aes encryption cib customer information block clk1k 1 khz clock clk32k 32.768 khz crystal clock cpu central processing unit crc cyclic redundancy check csma-ca carrier sense multiple access-collision a v oidance ctr counter mode cts clear to send dnl differential non-linearity dma direct memory access dwt data watchpoint and trace eeprom electrically erasable programmable read only memory em event manager enob effective number of bits esd electro static discharge esr equivalent series resistance etr external trigger input fclk arm ? cortex tm -m3 cpu clock
em346 138 rev 1.0 fib fixed information block fifo first-in, first-out fpb flash patch and breakpoint gpio general purpose i/o (pins) hf high frequency i 2 c inter-integrated circuit ide integrated development environment if intermediate frequency ieee institute of electrical and electronics engineers inl integral non-linearity itm instrumentation trace macrocell jtag joint test action group lf low frequency lna low noise amplifier lqi link quality indicator lsb least significant bit mac medium access control mfb main flash block miso master in, slave out mos metal oxide semiconductor (p-channel or n-channel) mosi master out, slave in mpu memory protection unit msb most significant bit msl moisture sensitivity level nack negative acknowledge nist national institute of standards and technology nmi non-maskable interrupt nvic nested vectored interrupt controller opm one-pulse mode acronym/abbreviation meaning
em346 rev 1.0 139 o-qpsk offset-quadrature phase shift keying osc24m high frequency crystal oscillator osc32k low-frequency 32.768 khz oscillator oschf high-frequency internal rc oscillator oscrc low-frequency rc oscillator pa power amplifier pclk peripheral clock per packet error rate phy physical layer pll phase-locked loop por power-on-reset prng pseudo random number generator psd power spectral density pti packet trace interface pwm pulse width modulation qfn quad flat pack ram random access memory rc resistive/capacitive rf radio frequency rms root mean square rohs restriction of hazardous substances rssi receive signal strength indicator rts request to send rx receive sysclk system clock sdfr spurious free dynamic range sfd start frame delimiter sinad signal-to-noise and distortion ratio spi serial peripheral interface acronym/abbreviation meaning
em346 140 rev 1.0 swj serial wire and jtag interface thd total harmonic distortion trng true random number generator twi two wire serial interface tx transmit uart universal asynchronous receiver/transmitter uev update event vco voltage controlled oscillator abbreviation meaning db decibel dbc decibels relative to the carrier dbm decibels relative to 1 mw ghz gigaherz kb kilobyte kbps kilobits/second khz kiloherz k? kiloohm kv kilovolt ma milliampere mbps megabits per second mhz megaherz m ? megaohm msps megasamples per second a microampere sec microsecond nh nanohenry ns nanoseconds ? ohm pf picofarad ppm part per million v volt acronym/abbreviation meaning
em346 rev 1.0 141 a ppendix cr eferences ?? zigbee specification ( w ww. zigb ee. org ; zigbee document 053474) ?? zigbee-pro stack profile ( www.zigbee.org ; zigbee document 074855) ?? zigbee stack profile ( www.zigbee.org ; zigbee document 064321) ?? bluetooth core specification v2.1 ? ( http://www.bluetooth.org/docman/hand lers/downloaddoc.ashx?doc_id=241363 ) ?? ieee 802.15.4-2003 ( http://standards.ieee.org/getiee e802/download/802.15.4-2003.pdf ) ?? ieee 802.11g ( standards.ieee.org/getieee80 2/download/802.11g-2003.pdf ) ?? arm ? cortex ? -m3 reference manual ( http://infocenter.arm.c om/help/topic/com.arm.doc.subset.cortexm.m3/ index.html#cortexm3 )
em346 142 rev 1.0 d ocument c hange l ist revision 1.0 ? initial draft
em346 rev 1.0 143 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omer s d ifferentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are t r ademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered tr ademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.

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