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B41693 ULN20 BL081 MC14029B 06F5F SW525 74LS14 TS271M
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  8 bit microcontroller tlcs-870/c1 series TMP89FH46
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2007 toshiba corporation all rights reserved
revision history date revision 2007/10/27 1 first release 2007/11/3 2 contents revised

i table of contents TMP89FH46 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. cpu core 2.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 code area ............................................................................................................................... .................. 9 2.2.1.1 ram 2.2.1.2 bootrom 2.2.1.3 flash 2.2.2 data area ............................................................................................................................... ................. 12 2.2.2.1 sfr 2.2.2.2 ram 2.2.2.3 bootrom 2.2.2.4 flash 2.3 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 configuration ............................................................................................................................... ........... 15 2.3.2 control ............................................................................................................................... ..................... 15 2.3.3 functions ............................................................................................................................... ................. 17 2.3.3.1 clock generator 2.3.3.2 clock gear 2.3.3.3 timing generator 2.3.4 warm-up counter ............................................................................................................................... ..... 20 2.3.4.1 warm-up counter operation when the oscillation is enabled by the hardware 2.3.4.2 warm-up counter operation when the oscillation is enabled by the software 2.3.5 operation mode control circuit ................................................................................................................ 22 2.3.5.1 single-clock mode 2.3.5.2 dual-clock mode 2.3.5.3 stop mode 2.3.5.4 transition of operation modes 2.3.6 operation mode control ......................................................................................................................... 27 2.3.6.1 stop mode 2.3.6.2 idle1/2 and sleep1 modes 2.3.6.3 idle0 and sleep0 modes 2.3.6.4 slow mode 2.4 reset control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.1 configuration ............................................................................................................................... ........... 38 2.4.2 control ............................................................................................................................... ..................... 38 2.4.3 functions ............................................................................................................................... ................. 40 2.4.4 reset signal generating factors ............................................................................................................ 41 2.4.4.1 external reset input (reset pin input) 2.4.4.2 power-on reset 2.4.4.3 voltage detection reset 2.4.4.4 watchdog timer reset 2.4.4.5 system clock reset 2.4.4.6 trimming data reset 2.4.4.7 flash standby reset 2.4.4.8 internal factor reset detection status register 2.4.4.9 how to use the external reset input pin as a port
ii 3. interrupt control circuit 3.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 interrupt latches (il25 to il3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.1 interrupt master enable flag (imf) .......................................................................................................... 49 3.3.2 individual interrupt enable flags (ef25 to ef4) ...................................................................................... 49 3.4 maskable interrupt priority change function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5.1 initial setting ............................................................................................................................... ............ 54 3.5.2 interrupt acceptance processing ............................................................................................................. 54 3.5.3 saving/restoring general-purpose registers ............................................................................................ 55 3.5.3.1 using push and pop instructions 3.5.3.2 using data transfer instructions 3.5.3.3 using a register bank to save/restore genera l-purpose registers 3.5.4 interrupt return ............................................................................................................................... ......... 57 3.6 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.6.1 address error detection .......................................................................................................................... 58 3.6.2 debugging ............................................................................................................................... ............... 58 3.7 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4. external interrupt control circuit 4.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.1 low power consumption function ........................................................................................................... 63 4.3.2 external interrupt 0 ............................................................................................................................... .. 64 4.3.3 external interrupts 1/2/3 .......................................................................................................................... 64 4.3.3.1 interrupt request signal generating condition detection function 4.3.3.2 a noise canceller pass signal monitoring func tion when interrupt request signals are generated 4.3.3.3 noise cancel time selection function 4.3.4 external interrupt 4 ............................................................................................................................... .. 65 4.3.4.1 interrupt request signal generating condition detection function 4.3.4.2 a noise canceller pass signal monitoring func tion when interrupt request signals are generated 4.3.4.3 noise cancel time selection function 4.3.5 external interrupt 5 ............................................................................................................................... .. 67 5. watchdog timer (wdt) 5.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.1 setting of enabling/disabling the watchdog timer operation ................................................................... 71 5.3.2 setting the clear time of the 8-bit up counter .......................................................................................... 72 5.3.3 setting the overflow time of the 8-bit up counter .................................................................................... 72 5.3.4 setting an overflow detection signal of the 8-bit up counter ................................................................... 73 5.3.5 writing the watchdog timer control codes ............................................................................................... 73 5.3.6 reading the 8-bit up counter .................................................................................................................. 74 5.3.7 reading the watchdog timer status ........................................................................................................ 74 6. power-on reset circuit 6.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
iii 7. voltage detection circuit 7.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.1 enabling/disabling the voltage detection operation ................................................................................ 79 7.3.2 selecting the voltage detection operation mode ..................................................................................... 79 7.3.3 selecting the detection voltage level ...................................................................................................... 79 7.3.4 voltage detection flag and voltage detection status flag ......................................................................... 79 7.3.5 selecting the stop mode release signal ............................................................................................... 80 7.4 register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.1 setting procedure when the operation mode is set to generate voltage detection interrupt request signals 81 7.4.2 setting procedure when the operation mode is set to generate voltage detection reset signals ............ 81 8. i/o ports 8.1 i/o port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.2 list of i/o port settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.3 i/o port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.3.1 port p0 (p03 to p00) ............................................................................................................................... 88 8.3.2 port p1 (p13 to p10) ............................................................................................................................... 92 8.3.3 port p2 (p27 to p20) ............................................................................................................................... 95 8.3.4 port p4 (p47 to p40) ............................................................................................................................... 99 8.3.5 port p7 (p77 to p70) ............................................................................................................................. 1 02 8.3.6 port p8 (p83 to p80) ............................................................................................................................. 1 04 8.3.7 port p9 (p91 to p90) ............................................................................................................................. 1 06 8.3.8 port pb (pb7 to pb4) ........................................................................................................................... 109 8.4 serial interface selecting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9. special function registers 9.1 sfr1 (0x0000 to 0x003f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.2 sfr2 (0x0f00 to 0x0fff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.3 sfr3 (0x0e40 to 0x0eff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10. low power consumption f unction for peripherals 10.1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11. divider output (dvo) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.2.1 function ............................................................................................................................... ............... 125 12. time base timer (tbt) 12.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
iv 12.1.1 configuration ............................................................................................................................... ....... 127 12.1.2 control ............................................................................................................................... ................. 127 12.1.3 functions ............................................................................................................................... ............. 128 13. 16-bit timer counter (tca) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.3 low power consumption function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.4 timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.4.1 timer mode ............................................................................................................................... .......... 138 13.4.1.1 setting 13.4.1.2 operation 13.4.1.3 auto capture 13.4.1.4 register buffer configuration 13.4.2 external trigger timer mode ................................................................................................................ 142 13.4.2.1 setting 13.4.2.2 operation 13.4.2.3 auto capture 13.4.2.4 register buffer configuration 13.4.3 event counter mode ............................................................................................................................ 14 4 13.4.3.1 setting 13.4.3.2 operation 13.4.3.3 auto capture 13.4.3.4 register buffer configuration 13.4.4 window mode ............................................................................................................................... ...... 146 13.4.4.1 setting 13.4.4.2 operation 13.4.4.3 auto capture 13.4.4.4 register buffer configuration 13.4.5 pulse width measurement mode ........................................................................................................ 148 13.4.5.1 setting 13.4.5.2 operation 13.4.6 programmable pulse generate (ppg) mode ...................................................................................... 150 13.4.6.1 setting 13.4.6.2 operation 13.4.6.3 register buffer configuration 13.5 noise canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.5.1 setting ............................................................................................................................... .................. 153 14. 8-bit timer counter (tc0) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.2.1 timer counter 00 ............................................................................................................................... .. 157 14.2.2 timer counter 01 ............................................................................................................................... .. 159 14.2.3 common to timer counters 00 and 01 ................................................................................................ 161 14.2.4 operation modes and usable source clocks ....................................................................................... 163 14.3 low power consumption function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.4.1 8-bit timer mode ............................................................................................................................... ... 165 14.4.1.1 setting 14.4.1.2 operation 14.4.1.3 double buffer 14.4.2 8-bit event counter mode .................................................................................................................... 168 14.4.2.1 setting 14.4.2.2 operation 14.4.2.3 double buffer 14.4.3 8-bit pulse width modulation (pwm) output mode .............................................................................. 170 14.4.3.1 setting 14.4.3.2 operations 14.4.3.3 double buffer 14.4.4 8-bit programmable pulse generate (ppg) output mode .................................................................... 175 14.4.4.1 setting 14.4.4.2 operation
v 14.4.4.3 double buffer 14.4.5 16-bit timer mode ............................................................................................................................... . 178 14.4.5.1 setting 14.4.5.2 operations 14.4.5.3 double buffer 14.4.6 16-bit event counter mode .................................................................................................................. 182 14.4.6.1 setting 14.4.6.2 operations 14.4.6.3 double buffer 14.4.7 12-bit pulse width modulation (pwm) output mode ............................................................................ 184 14.4.7.1 setting 14.4.7.2 operations 14.4.7.3 double buffer 14.4.8 16-bit programmable pulse generate (ppg) output mode .................................................................. 190 14.4.8.1 setting 14.4.8.2 operations 14.4.8.3 double buffer 15. real time clock (rtc) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.3.1 low power consumption function ..................................................................................................... 194 15.3.2 enabling/disabling the real time clock operation ................................................................................. 194 15.3.3 selecting the interrupt generation interval .......................................................................................... 194 15.4 real time clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.4.1 enabling the real time clock operation ................................................................................................ 195 15.4.2 disabling the real time clock operation ............................................................................................... 195 16. asynchronous serial interface (uart) 16.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 16.3 low power consumption function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed 204 16.5 activation of stop, idle0 or sleep0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.5.1 transition of register status ................................................................................................................ 205 16.5.2 transition of txd pin status ............................................................................................................... 205 16.6 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7 infrared data format transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.8 transfer baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8.1 transfer baud rate calculation method ............................................................................................... 208 16.8.1.1 bit width adjustment using uart0cr2 16.8.1.2 calculation of set values of uart0cr2 and uart0dr 16.9 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.10 received data noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.11 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.11.1 data transmit operation .................................................................................................................... 214 16.11.2 data receive operation ...................................................................................................................... 214 16.12 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.12.1 parity error ............................................................................................................................... ......... 215 16.12.2 framing error ............................................................................................................................... ..... 216 16.12.3 overrun error ............................................................................................................................... ..... 217 16.12.4 receive data buffer full ................................................................................................................... 220 16.12.5 transmit busy flag ........................................................................................................................... 221 16.12.6 transmit buffer full .......................................................................................................................... 221 16.13 receiving process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
vi 16.14 ac properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 16.14.1 irda properties ............................................................................................................................... ... 224 17. synchronous serial interface (sio) 17.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 17.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.3 low power consumption function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.4 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 17.4.1 transfer format ............................................................................................................................... .... 231 17.4.2 serial clock ............................................................................................................................... .......... 231 17.4.3 transfer edge selection ...................................................................................................................... 231 17.5 transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.5.1 8-bit transmit mode ............................................................................................................................. 2 33 17.5.1.1 setting 17.5.1.2 starting the transmit operation 17.5.1.3 transmit buffer and shift operation 17.5.1.4 operation on completion of transmission 17.5.1.5 stopping the transmit operation 17.5.2 8-bit receive mode ............................................................................................................................. 2 38 17.5.2.1 setting 17.5.2.2 starting the receive operation 17.5.2.3 operation on completion of reception 17.5.2.4 stopping the receive operation 17.5.3 8-bit transmit/receive mode ................................................................................................................ 242 17.5.3.1 setting 17.5.3.2 starting the transmit/receive operation 17.5.3.3 transmit buffer and shift operation 17.5.3.4 operation on completion of transmission/reception 17.5.3.5 stopping the transmit/receive operation 17.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 18. serial bus interface (sbi) 18.1 communication format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 18.1.1 i2c bus ............................................................................................................................... ................ 249 18.1.2 free data format ............................................................................................................................... .. 250 18.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 18.4 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.4.1 low power consumption function ..................................................................................................... 255 18.4.2 selecting the slave address match detection and the general call detection ............................. 256 18.4.3 selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode ............................................................................................................................... ............................ 256 18.4.3.1 number of clocks for data transfer 18.4.3.2 output of an acknowledge signal 18.4.4 serial clock ............................................................................................................................... .......... 258 18.4.4.1 clock source 18.4.4.2 clock synchronization 18.4.5 master/slave selection ........................................................................................................................ 260 18.4.6 transmitter/receiver selection ............................................................................................................. 260 18.4.7 start/stop condition generation ........................................................................................................... 261 18.4.8 interrupt service request and release ................................................................................................. 262 18.4.9 setting of serial bus interface mode ................................................................................................... 262 18.4.10 software reset ............................................................................................................................... .... 262 18.4.11 arbitration lost detection monitor ...................................................................................................... 263 18.4.12 slave address match detection monitor ............................................................................................ 264 18.4.13 general call detection monitor .................................................................................................. 265 18.4.14 last received bit monitor ................................................................................................................... 265 18.4.15 slave address and address recognition mode specification ............................................................. 265 18.5 data transfer of i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
vii 18.5.1 device initialization ............................................................................................................................. 2 66 18.5.2 start condition and slave address generation ..................................................................................... 266 18.5.3 1-word data transfer ............................................................................................................................ 26 7 18.5.3.1 when sbi0sr2 is "1" (master mode) 18.5.3.2 when sbi0sr2 is "0" (slave mode) 18.5.4 stop condition generation ................................................................................................................... 271 18.5.5 restart ............................................................................................................................... ................. 271 18.6 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 19. key-on wakeup (kwu) 19.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 19.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 19.3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 20. 10-bit ad converter (adc) 20.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 20.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 20.3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 20.3.1 single mode ............................................................................................................................... ......... 284 20.3.2 repeat mode ............................................................................................................................... ....... 284 20.3.3 ad operation disable and forced stop of ad operation ....................................................................... 285 20.4 register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 20.5 starting stop/idle0/slow modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 20.6 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 287 20.7 precautions about the ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 20.7.1 analog input pin voltage range ........................................................................................................... 288 20.7.2 analog input pins used as input/output ports ...................................................................................... 288 20.7.3 noise countermeasure ........................................................................................................................ 288 21. flash memory 21.1 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 21.2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 21.2.1 flash memory command sequence executio n and toggle control (flscr1 ) ................... 293 21.2.2 flash memory area switching (flscr1) ............................................................................ 294 21.2.3 ram area switching (syscr3) .......................................................................................... 295 21.2.4 bootrom area switching (flscr1) ................................................................................ 295 21.2.5 flash memory standby control (flsstb) ............................................................................. 296 21.2.6 port input control register (spcr) ................................................................................ 297 21.3 command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 21.3.1 byte program ............................................................................................................................... ....... 298 21.3.2 sector erase (4-kbyte partial erase) ................................................................................................... 299 21.3.3 chip erase (all erase) ......................................................................................................................... 299 21.3.4 product id entry ............................................................................................................................... ... 299 21.3.5 product id exit ............................................................................................................................... ..... 300 21.3.6 security program ............................................................................................................................... . 300 21.4 toggle bit (d6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 21.5 access to the flash memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 21.5.1 flash memory control in serial prom mode ...................................................................................... 301 21.5.1.1 how to transfer and write a control program to the ram area in ram loader mode of the serial prom mode 21.5.2 flash memory control in mcu mode .................................................................................................. 304 21.5.2.1 how to write to the flash memory by transferring a control program to the ram area 21.5.2.2 how to write to the flash memory by us ing a support program (api) of bootrom
viii 22. serial prom mode 22.1 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 22.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 22.3 serial prom mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 22.3.1 serial prom mode control pins ......................................................................................................... 310 22.4 example connection for on-board writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 22.5 activating the serial prom mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 22.6 interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 22.6.1 sio communication ............................................................................................................................ 31 4 22.6.2 uart communication ......................................................................................................................... 314 22.7 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 22.8 operation commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 22.8.1 flash memory erase command (0xf0) ............................................................................................... 319 22.8.1.1 specifying the erase area 22.8.2 flash memory write command (operation command: 0x30) ............................................................... 322 22.8.3 flash memory read command (operation command: 0x40) ............................................................... 324 22.8.4 ram loader command (operation command: 0x60) ........................................................................... 326 22.8.5 flash memory sum output command (operation command: 0x90) ................................................... 328 22.8.6 product id code output command (operation command: 0xc0) ......................................................... 329 22.8.7 flash memory status output command (0xc3) ................................................................................... 331 22.8.7.1 flash memory status code 22.8.8 mask rom emulation setting command (0xd0) ................................................................................. 334 22.8.9 flash memory security setting command (0xfa) ................................................................................ 335 22.9 error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 22.10 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 22.10.1 calculation method ........................................................................................................................... 337 22.10.2 calculation data ............................................................................................................................... . 337 22.11 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 22.12 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 22.12.1 passwords ............................................................................................................................... ......... 339 22.12.1.1 how a password can be specified 22.12.1.2 password structure 22.12.1.3 password setting, cancellation and authentication 22.12.1.4 password values and setting range 22.12.2 security program .............................................................................................................................. 343 22.12.2.1 how the security program functions 22.12.2.2 enabling or disabling the security program 22.12.3 option codes ............................................................................................................................... ...... 344 22.12.4 recommended settings .................................................................................................................... 346 22.13 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 22.14 ac characteristics (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 22.14.1 reset timing ............................................................................................................................... ....... 349 22.14.2 flash memory erase command (0xf0) ............................................................................................. 349 22.14.3 flash memory write command (0x30) ............................................................................................... 350 22.14.4 flash memory read command (0x40) ............................................................................................... 350 22.14.5 ram loader command (0x60) ........................................................................................................... 351 22.14.6 flash memory sum output command (0x90) ................................................................................... 351 22.14.7 product id code output command (0xc0) ........................................................................................ 351 22.14.8 flash memory status output command (0xc3) ................................................................................. 352 22.14.9 mask rom emulation setting command (0xd0) ............................................................................... 352 22.14.10 flash memory security setting command (0xfa) ............................................................................ 352 23. on-chip debug function (ocd) 23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 23.2 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 23.3 how to connect the on-chip debug emulator to a target system . . . . . . . . . . 354
ix 23.4 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 24. input/output circuit 24.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 25. electrical characteristics 25.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 25.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 25.2.1 mcu mode (flash programming or erasing) ...................................................................................... 358 25.2.2 mcu mode (except flash programming or erasing) .......................................................................... 359 25.2.3 serial prom mode ............................................................................................................................. 3 60 25.3 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 25.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 25.5 power-on reset circuit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 25.6 voltage detecting circuit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 25.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 25.7.1 mcu mode (flash programming or erasing) ...................................................................................... 367 25.7.2 mcu mode (except flash programming or erasing) .......................................................................... 367 25.7.3 serial prom mode ............................................................................................................................. 3 68 25.8 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 25.8.1 write characteristics ........................................................................................................................... 368 25.9 recommended oscillating condition- 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 25.10 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 25.11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 26. package dimensions
x
page 1 TMP89FH46 cmos 8-bit microcontroller this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. ra000 ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improv e the quality and reliability of its products . nevertheless, semi conductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vu lnerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safe ty in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products coul d cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. al so, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended fo r usage in general electronics appl ications (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics , domestic appliances, etc.). t hese toshiba products are neithe r intended nor warranted for usage in equipment that requires extraordi narily high quality and/or reli ability or a malfunction or failure of which may cause loss of human life or b odily injury (?unintended usage?). unintended usage include atomic energy control instru ments, airplane or spaceship instruments, transpor tation instruments, traffic signal instrum ents, combustion control instruments, medi cal instru- ments, all types of safety devices, etc. unintended usage of to shiba products listed in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or em bedded to any downstream products of which manufacture, use and /or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our produc ts. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this doc ument are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers can be predi cted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/handling precautions. 030619_s TMP89FH46 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c1 series - instruction execution time : 100 ns (at 10 mhz) 122 s (at 32.768 khz) - 133 types & 732 basic instructions 2. 25 interrupt sources (external : 6 internal : 19 , except reset) 3. input / output ports (42 pins) large current output: 8 pins (typ. 20ma) 4. watchdog timer - interrupt or reset can be selected by the program. 5. power-on reset circuit 6. voltage detection circuit 7. divider output function 8. time base timer 9. 16-bit timer counter : 2 ch - timer, external trigger, event counter, window, pulse width measurement, ppg output modes the TMP89FH46 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of flash memory. it is pin-compatible with th e tmp89ch46 (mask rom version). the TMP89FH46 can re- alize operations equivalent to those of the tmp89ch46 by programming the on-chip flash memory. product no. rom (flash) ram package flash mcu emulation chip TMP89FH46dug 16384 bytes 2048 bytes lqfp48-p-0707-0.50d * tmp89ch46dug * tmp89c900xbg note : * ; under development note : two of above pins can not be used for the i/o port, beca use they should be connected with the high frequency osc input.
page 2 1.1 features TMP89FH46 ra000 10. 8-bit timer counter: 4 ch - timer, event counter, pwm, ppg output modes - usable as a 16-bit timer, 12-bit pwm output and 16-bit ppg output by the cascade connection of two channels. 11. real time clock 12. uart : 1ch 13. uart/sio : 1ch note : one sio cha nnel can be used at the same time. 14. i 2 c/sio : 1ch 15. key-on wake-up : 8 ch 16. 10-bit successive approximation type ad converter - analog input : 8ch 17. on-chip debug function - break/event - trace - ram monitor - flash memory writing 18. clock operation mode control circuit : 2 circuit single clock mode / dual clock mode 19. low power consumption operation (8 mode) - stop mode: oscillation stops. (battery/capacitor back-up.) - slow1 mode: low power consumption operation using low-fr equency clock.(high-frequency clock stop.) - slow2 mode: low power consumption operation using low-fre quency clock.(high-frequency clock oscillate.) - idle0 mode: cpu stops, and only the time-based-timer(tbt) on pe ripherals operate using high frequency clock. released when the reference time set to tbt has elapsed. - idle1 mode: the cpu stops, and peripherals operate using hi gh frequency clock. release by interruputs(cpu restarts). - idle2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruputs. (cpu restarts). - sleep0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using low frequency clock. released when the reference time set to tbt has elapsed. - sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interruput.(cpu restarts). 20. wide operation voltage: 4.3 v to 5.5 v at 10mhz /32.768 khz 2.7 v to 5.5 v at 4.2 mhz /32.768 khz 2.2 v to 5.5 v at 2mhz /32.768 khz
page 3 TMP89FH46 ra000 1.2 pin assignment figure 1-1 pin assignment vss (xout) p01 mode vdd (xtin) p02 (xtout) p03 ( reset ) p10 ( stop / int5 ) p11 ( int0 ) p12 (ocdck/so0/rxd0/txd0) p20 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 p42 (ain2/kwi2) p45 (ain5/kwi5) p47 (ain7/kwi7) p46 (ain6/kwi6) p75 (int2) p74 ( dvo ) p43 (ain3/kwi3) (int1) p13 (xin) p00 p25 (sclk0) p27 avss avdd p41 (ain1/kwi1) varef p26 p40 (ain0/kwi0) p91 (rxd1/txd1) p90 (txd1/rxd1) p77 (int4) p76 (int3) ( pwm02 / ppg02 /tc02) p80 ( pwm03 / ppg03 /tc03) p81 p82 p83 ( pwm00 / ppg00 /tc00) p70 ( pwm01 / ppg01 /tc01) p71 ( ppga0 /tca0) p72 ( ppga1 /tca1) p73 (so0/rxd0/txd0) pb4 (si0/txd0/rxd0) pb5 (sclk0) pb6 pb7 p24 (scl0/si0) p23 (sda0/so0) p22 (sclk0) p21 (rxd0/txd0/si0/ocdio) p44 (ain4/kwi4)
page 4 1.3 block diagram TMP89FH46 ra000 1.3 block diagram figure 1-2 block diagram
page 5 TMP89FH46 ra000 1.4 pin names and functions the TMP89FH46 has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin func- tions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/3) pin name input/output functions p03 xtout io o port03 low frequency osc output p02 xtin io i port02 low frequency osc input p01 xout io o port01 high frequency osc output p00 xin io i port00 high frequency osc input p13 int1 io i port13 external interrupt 1 input p12 int0 io i port12 external interrupt 0 input p11 int5 stop io i i port11 external interrupt 5 input stop mode release input p10 reset io i port10 reset signal input p27 io port27 p26 io port26 p25 sclk0 io io port25 serial clock input/output 0 p24 scl0 si0 io io i port24 i2c bus clock input/output 0 serial data input 0 p23 sda0 so0 io io o port23 i2c bus data input/output 0 serial data output 0 p22 sclk0 io io port22 serial clock input/output 0 p21 rxd0 txd0 si0 ocdio io i o i io port21 uart data input 0 uart data output 0 serial data input 0 ocd data input/output p20 txd0 rxd0 so0 ocdck io o i o i port20 uart data output 0 uart data input 0 serial data output 0 ocd clock input p47 ain7 kwi7 io i i port47 analog input 7 key-on wake-up input 7 p46 ain6 kwi6 io i i port46 analog input 6 key-on wake-up input 6
page 6 1.4 pin names and functions TMP89FH46 ra000 p45 ain5 kwi5 io i i port45 analog input 5 key-on wake-up input 5 p44 ain4 kwi4 io i i port44 analog input 4 key-on wake-up input 4 p43 ain3 kwi3 io i i port43 analog input 3 key-on wake-up input 3 p42 ain2 kwi2 io i i port42 analog input 2 key-on wake-up input 2 p41 ain1 kwi1 io i i port41 analog input 1 key-on wake-up input 1 p40 ain0 kwi0 io i i port40 analog input 0 key-on wake-up input 0 p77 int4 io i port77 external interrupt 4 input p76 int3 io i port76 external interrupt 3 input p75 int2 io i port75 external interrupt 2 input p74 dvo io o port74 divider output p73 tca1 ppga1 io i o port73 tca1 input ppga1 output p72 tca0 ppga0 io i o port72 tca0 input ppga0 output p71 tc01 ppg01 pwm01 io i o o port71 tc01 input ppg01 output pwm01 output p70 tc00 ppg00 pwm00 io i o o port70 tc00 input ppg00 output pwm00 output p83 io port83 p82 io port82 p81 tc03 ppg03 pwm03 io i o o port81 tc03 input ppg03 output pwm03 output p80 tc02 ppg02 pwm02 io i o o port80 tc02 input ppg02 output pwm02 output table 1-1 pin names and functions(2/3) pin name input/output functions
page 7 TMP89FH46 ra000 p91 rxd1 txd1 io i o port91 uart data input 1 uart data output 1 p90 txd1 rxd1 io o i port90 uart data output 1 uart data input 1 pb7 io portb7 pb6 sclk0 io io portb6 serial clock input/output 0 pb5 rxd0 txd0 si0 io i o i portb5 uart data input 0 uart data output 0 serial data input 0 pb4 txd0 rxd0 so0 io o i o portb4 uart data output 0 uart data input 0 serial data output 0 mode i test pin for out-going test (fix to low level). varef i analog reference voltage input pin for a/d conversion. avdd i analog power supply pin. avss i analog gnd pin vdd i vdd pin vss i gnd pin table 1-1 pin names and functions(3/3) pin name input/output functions
page 8 1.4 pin names and functions TMP89FH46 ra000
page 9 TMP89FH46 ra001 2. cpu core 2.1 configuration the cpu core consists of a cpu, a syst em clock controller and a reset circuit. this chapter describes the cpu core address space, the system clock controller and the reset circuit. 2.2 memory space the 870/c1 cpu memory space consists of a code area to be accessed as instruction operation codes and operands and a data area to be accessed as sources and destin ations of transfer and calculation instructions. both the code and data areas have independent 64-kbyte address spaces. 2.2.1 code area the code area stores operation codes, operands, vector ta bles for vector call instru ctions and interrupt vector tables. the ram, the bootrom and the flash are mapped in the code area. note: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. figure 2-1 memory m ap in the code area 0x0000 swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. 0x003f 0x0040 ram (2048 bytes) ram (2048 bytes) 0x083f swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. swi instruction (0xff) is fetched. 0x1000 bootrom (2048 bytes) bootrom (2048 bytes) 0x17ff 0x1800 0xbfff 0xc000 flash (16384 bytes) flash (16384 bytes) flash (16384 bytes) flash (16384 bytes) 0xffa0 vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) vector table for vec- tor call instructions (32 bytes) 0xffbf 0xffcc interrupt vector table (52 bytes) interrupt vector table (52 bytes) interrupt vector table (52 bytes) interrupt vector table (52 bytes) 0xffff immediately after re- set release when the ram is mapped in the code area when the bootrom is mapped in the code area when the ram and the bootrom are mapped in the code area
page 10 2. cpu core 2.2 memory space TMP89FH46 ra001 2.2.1.1 ram the ram is mapped in the data ar ea immediately after reset release. by setting syscr3 to "1" and writing 0xd4 to syscr4, ram can be mapped to 0x0040to 0x083f in the code area to execute the program. at this time, by setting syscr to "1" a nd writing 0xd4 to syscr4, vector table for vector call instructions and interrupt excep t reset can be mapped to ram. note 1: the value of syscr3 is invalid until 0xd4 is written into syscr4. note 2: to assign vector address areas to ram, set syscr3 to "1" and syscr3 to "1". note 3: do not set syscr3 to "0" by using the ram loader program. if an interrupt occurs with syscr3 set to "0", the bootrom area is referenced as a vector addre ss and, therefore, the program will not function properly. note 4: bits 7 to 3 of syscr3 are read as "0". note 1: syscr4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit opera- tion. note 2: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in normal mode when fcgck is fc/4 (cgcr=00). other wise, syscr3 may be enabled at unexpected tim- ing. note 3: after irstsr is modified, syscr4 should be wr itten 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. in the serial prom mode, the ram is mapped to 0x0040 to 0x083f in the code area, regardless of the value of syscr3. the program can be ex ecuted on the ram using the ram loader function. note 1: when the ram is not mapped in the code area, th e swi instruction is fetched from 0x0040 to 0x083f. note2: the contents of the ram become unstable when the power is turned on and immediately after a reset is released. to execute the program by using t he ram, transfer the program to be executed in the initialization routine. system control register 3 syscr3 (0x0fde) 76543210 bit symbol-----rvctrrarea(rstdis) read/write rrrrrr/wr/wr/w after reset00000000 rarea specifies mapping of the ram in the code area 0 : the ram is not mapped from 0x0040 to 0x083f in the code area. 1 : the ram is mapped from 0x0040 to 0x083f in the code area. rvctr specifies mapping of the vector table for vector call instructions and interrupts vector table for vector call instruc- tions vector table for interrupt 0 : 0xffa0 to 0xffbf in the code area 0xffc8 to 0xffff in the code area 1 : 0x01a0 to 0x01bf in the code ar ea 0x01c8 to 0x01fd in the code area system control register 4 syscr4 (0x0fdf) 76543210 bit symbol syscr4 read/write w after reset00000000 syscr4 writes the syscr3 data control code. 0xb2 : 0xd4 : 0x71 : enables the contents of syscr3. enables the contents of syscr3 and syscr3 . enables the contents of irstsr others : invalid
page 11 TMP89FH46 ra001 note: bits 7 to 3 of syssr4 are read as "0". 2.2.1.2 bootrom the bootrom is not mapped in the code area or the data area after reset release. note 1: when the bootrom is not mapped in the code area, an instruction is fetched from the flash or an swi instruction is fetched, depending on the capacity of the internal flash. note 2: only the first 2 kbytes of the bootrom are m apped in the memory map, except in the serial prom mode. note: the flash memory control register 1 has a double-buffer stru cture comprised of the register flscr1 and a shift register. writing "0xd5" to the register flscr2 allows a register setti ng to be reflected and take effect in the shift register. this means that a register setting value does not take effect until "0xd5" is written to the register flscr2. the value of the shift register can be checked by reading the register flscrm. system control status register 4 syssr4 (0x0fdf) 76543210 bit symbol-----rvctrsrareas(rstdis) read/writerrrrrrrr after reset00000000 rareas status of mapping of the ram in the code area 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". rvctrs status of mapping of the vector address in the area 0 : 1 : the enabled syscr3 data is "0". the enabled syscr3 data is "1". example: program transfer (transfer the program saved in the data area to the ram.) ld hl, transfer_start_address ; destination ram address ld de, program_start_address ; source rom address ld bc, byte_of_program ; number of bytes of the program to be executed -1 trans_ram: ld a, (de) ; reading the program to be transferred ld (hl), a ; writing the program to be transferred inc hl ; destination address increment inc de ; source address increment dec bc ; have all the programs been transferred? jrs f, trans_ram setting flsmd to "1" maps the bootrom to 0x1000 to 0x17ff in the code area and to 0x1000 to 0x17ff in the data area. the bootrom can be easily written into the flash by using the ap- plication program ming interface (api) integr ated in the bootrom. flash memory control register 1 flscr1 (0x0fd0) 76543210 bit symbol (flsmd) barea (farea) (romsel) read/write r/w r/w r/w r/w after reset01000000 barea specifies mapping of the bootrom in the code and data areas 0 : 1 : the bootrom is not mapped to 0x1000 to 0x17ff in the code area and to 0x1000 to 0x17ff in the data area. the bootrom is mapped to 0x1000 to 0x17ff in the code area and to 0x1000 to 0x17ff in the data area.
page 12 2. cpu core 2.2 memory space TMP89FH46 ra001 2.2.1.3 flash the flash is mapped to 0xc000 to 0xfff f in the code area after reset release. 2.2.2 data area the data area stores the data to be accessed as source s and destinations of transfer and calculation instruc- tions. the sfr, the ram, the bootrom and th e flash are mapped in the data area. note: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. figure 2-2 memory map in the data area flash memory control register 2 flscr2 76543210 (0x0fd1) bit symbol cr1en read/write w after reset******** cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved 0x0000 sfr1 (64 bytes) sfr1 (64 bytes) 0x003f 0x0040 ram (2048 bytes) ram (2048 bytes) 0x083f 0xff is read 0xff is read 0x0e40 sfr3 (192 bytes) sfr3 (192 bytes) 0x0eff 0x0f00 sfr2 (256 bytes) sfr2 (256 bytes) 0x0fff 0x1000 bootrom (2048 bytes) 0x17ff 0x1800 0xff is read 0xff is read 0xbfff 0xc000 flash (16384 bytes) flash (16384 bytes) 0xffff immediately after re- set release when the bootrom is mapped in the data area
page 13 TMP89FH46 ra001 2.2.2.1 sfr the sfr is mapped to 0x0000 to 0x003f (sfr1) , 0x0f00 to 0x0fff (sfr2) and 0x0e40 to 0x0eff (sfr3) in the data area after reset release. note: don't access the reserved sfr. 2.2.2.2 ram the ram is mapped to 0x0040 to 0x083f in the data area after reset release. note: the contents of the ram become unstable when the power is turned on and immediately after a reset is released. to execute the program by using the ram, transfer the program to be executed in the ini- tialization routine. 2.2.2.3 bootrom the bootrom is not mapped in the code area or the data area after reset release. note: the flash memory control register 1 has a double-buffer stru cture comprised of the register flscr1 and a shift register. writing "0xd5" to the register flscr2 allows a register setti ng to be reflected and take effect in the shift register. this means that a register setting value does not take effect until "0xd5" is written to the register flscr2. the value of the shift register can be checked by reading the register flscrm. example: ram initialization program ld hl, ram_top_address ; head of address of the ram to be initialized ld a, 0x00 ; initialization data ld bc, byte_of_clear_bytes ; number of bytes of ram to be initialized -1 clr_ram: ld (hl), a ; initialization of the ram inc hl ; initialization address increment dec bc ; have all the rams been initialized? jrs f, clr_ram setting flsmd to "1" maps the bootrom to 0x1000 to 0x17ff in the code area and to 0x1000 to 0x17ff in the data area. the bootrom can be easily written into the flash by using the ap- plication program ming interface (api) integr ated in the bootrom. note 1: when the bootrom is not mapped in the dat a area, 0xff is read from 0x1000 to 0x17ff. note2: only the first 2 kbytes of the bootrom are mapped in the memory map, except in the serial prom mode. flash memory control register 1 flscr1 (0x0fd0) 76543210 bit symbol (flsmd) barea (farea) (romsel) read/write r/w r/w r/w r/w after reset01000000 barea specifies mapping of the bootrom in the code and data areas 0 : 1 : the bootrom is not mapped to 0x1000 to 0x17ff in the code area and to 0x1000 to 0x17ff in the data area. the bootrom is mapped to 0x1000 to 0x17ff in the code area and to 0x1000 to 0x17ff in the data area. flash memory control register 2 flscr2 76543210 (0x0fd1) bit symbol cr1en read/write w after reset********
page 14 2. cpu core 2.2 memory space TMP89FH46 ra001 2.2.2.4 flash the flash is mapped to 0xc000 to 0xfff f in the data area after reset release. cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved
page 15 TMP89FH46 ra001 2.3 system clock controller 2.3.1 configuration the system clock controller consists of a clock ge nerator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. figure 2-3 system clock controller 2.3.2 control the system clock controller is contro lled by system control register 1 (s yscr1), system control register 2 (syscr2), the warm-up counter contro l register (wuccr), the warm-up c ounter data register (wucdr) and the clock gear control register (cgcr). note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: bits 2, 1 and 0 of syscr1 are read as "0". bit 3 is read as "1". system control register 1 syscr1 (0x0fdc) 76543210 bit symbol stop relm outen dv9ck - - - - read/writer/wr/wr/wr/wrrrr after reset00001000 stop activates the stop mode 0 : 1 : operate the cpu and the peripheral circuits stop the cpu and the peripheral circuits (activate the stop mode) relm selects the stop mode release method 0 : 1 : edge-sensitive release mode (release the stop mode at the rising edge of the stop mode release signal) level-sensitive release mode (release th e stop mode at the "h" level of the stop mode release signal) outen selects the port output state in the stop mode 0 : 1 : high impedance output hold dv9ck selects the input clock to stage 9 of the divider 0 : 1 : fcgck/2 9 fs/4 operation mode control circuit xtin xtout clock generator fs fc system clock intwuc interrupt system control register oscillation/stop control low-frequency clock oscillation circuit high-frequency clock oscillation circuit xin xout timing generator fcgck 1/4 syscr1 syscr2 tbtcr wuccr wucdr clock gear control register fcgcksel stop dv9ck xen/xten warm-up counter clock gear (x1/4,x1/2,x1)
page 16 2. cpu core 2.3 system clock controller TMP89FH46 ra001 note 3: if the stop mode is activated with syscr1 set at "0 ", the port internal input is fixed to "0". therefore, an exte r- nal interrupt may be set at the falling edge, dependi ng on the pin state when the stop mode is activated. note 4: the p11 pin is also used as the stop pin. when the st op mode is activated, the pin reverts to high impedance state and is put in input mode, regardless of the state of syscr1. note 5: writing of the second byte data will be executed improperly if the operation is switched to the stop state by an instruc - tion, such as ldw, which executes 2-byte data transfer at a time. note 6: don't set sysck1 to "1" before the oscillatio n of the low-frequency clock osci llation circuit becomes stable. note 7: in the slow1/2 or sleep1 mode, fs/4 is input to st age 9 of the divider, regardless of the state of syscr1< dv9ck >. note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: wdt: watchdog timer, tg: timing generator note 3: don't set both syscr2 and syscr2 to "1" simultaneously. note 4: writing of the second byte data will be executed improperly if the operation is switched to the idle state by an instruc tion, such as ldw, which executes 2-byte data transfer at a time. note 5: when the idle1/2 or sleep1 mode is releas ed, syscr2 is cleared to "0" automatically. note 6: when the idle0 or sleep0 mode is released , syscr2 is cleared to "0" automatically. note 7: bits 7, 1 and 0 of syscr2 are read as "0". note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: wuccr is cleared to "0" automatical ly, and need not be cleared to "0" after being set to "1". note 3: bits 7 to 4 of wuccr are read as "0". bit 0 is read as "1". note 4: before starting the warm-up counter operation, set t he source clock and the frequency division rate at wuccr and set the warm-up time at wucdr. system control register 2 syscr2 (0x0fdd) 76543210 bit symbol - xen xten sysck idle tghalt - - read/write r r/w r/w r/w r/w r/w r r after reset01000000 xen controls the high-frequency clock oscillation circuit 0 : 1 : stop oscillation continue or start oscillation xten controls the low-frequency clock oscillation circuit 0 : 1 : stop oscillation continue or start oscillation sysck selects a system clock 0 : 1 : gear clock (fcgck) (normal1/2 or idle1/2 mode) low-frequency clock (fs/4) (slow1/2 or sleep1 mode) idle cpu and wdt control (idle1/2 or sleep1 mode) 0 : 1 : operate the cpu and the wdt stop the cpu and the wdt (activate idle1/2 or sleep1 mode) tghalt tg control (idle0 or sleep0 mode) 0 : 1 : enable the clock supply from the tg to all the peripheral circuits disable the clock supply from the tg to the peripheral circuits except the tbt (activate idle0 or sleep0 mode) warm-up counter control register wuccr (0x0fcd) 76543210 bit symbol wucrst - - - wucdiv wucsel - read/write w r r r r/w r/w r after reset00001101 wucrst resets and stops the warm-up counter 0 : 1 : - clear and stop the counter wucdiv selects the frequency division of the warm-up counter source clock 00 : 01 : 10 : 11 : source clock source clock / 2 source clock / 2 2 source clock / 2 3 wucsel selects the warm-up counter source clock 0 : 1 : select the high-frequency clock (fc) select the low-frequency clock (fs)
page 17 TMP89FH46 ra001 note 1: don't start the warm-up counter operation with wucdr set at "0x00". note 1: fcgck: gear clock [h z], fc: high-frequency clock [hz] note 2: don't change cgcr in the slow mode. note 3: bits 7 to 2 of cgcr are read as "0". 2.3.3 functions 2.3.3.1 clock generator the clock generator generates the basic clock for the system clocks to be supplied to the cpu core and peripheral circuits. it contains two oscillation circuits: one for the high -frequency clock and the other for the low-frequency clock. the oscillation circuit pins are also used as ports p0 . for the setting to use them as ports, refer to the chapter of i/o ports. to use ports p00 and p01 as the high-frequency clock oscillation circuits (the xin and xout pins), set p0fc0 to "1" and then set syscr2 to "1". to use ports p02 and p03 as the low-frequency cloc k oscillation circuits (the xtin and xtout pins), set p0fc2 to "1" and then set syscr2 to "1". the high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an oscillator between the xin and xout pins and between the xtin and xtout pins respectively. clock input from an external oscillat or is also possible. in this case, external clocks are applied to the xin/xtin pins and the xout/xtout pins are kept open. enabling/disabling the oscillation of the high-frequ ency clock oscillation circuit and the low-frequency clock oscillation circuit and switching the pin functi on to ports are controlled by the software and hard- ware. the software control is executed by syscr2, syscr2 and the p0 port function con- trol register p0fc. warm-up counter data register wucdr (0x0fce) 76543210 bit symbol wucdr read/write r/w after reset01100110 wucdr warm-up time setting clock gear control register cgcr (0x0fcf) 76543210 bit symbol------ fcgcksel read/writerrrrrr r/w after reset00000000 fcgcksel clock gear setting 00 : 01 : 10 : 11 : fcgck = fc / 4 fcgck = fc / 2 fcgck = fc reserved
page 18 2. cpu core 2.3 system clock controller TMP89FH46 ra001 the hardware control is executed by reset release an d the operation mode control circuit when the oper- ation is switched to the stop mode as described in "2.3.5 operation mode control circuit". note: no hardware function is availabl e for external direct monitoring of the basic clock. t he oscillation fre- quency can be adjusted by programming the system to output pulses at a certain frequency to a port (for example, a clock output) with interrupts disabled and the watchdog ti mer disabled and monitoring the output. an adjustment program must be created in advance for a system that requires adjustment of the oscillation frequency. to prevent the dead lock of the cpu core due to th e software-controlled enabling/disabling of the oscil- lation, an internal factor reset is generated depending on the combination of values of the clock selected as the main system clock, syscr2, syscr2 and the p0 port function control register p0fc0. note: it takes a certain period of time after syscr2 is changed before the main system clock is switched. if the currently operating oscillation ci rcuit is stopped before the main system clock is switched, the internal condition bec omes as shown in table 2-1 and a system clock reset occurs. for details of clock switching, refer to "2.3.6 operation mode control". figure 2-4 examples of oscillator connection 2.3.3.2 clock gear the clock gear is a circuit that selects a gear cl ock (fcgck) obtained by dividing the high-frequency clock (fc) and inputs it to the timing generator. selects a divided cloc k at cgcr. two machine cycles are needed after cgcr is changed before the gear clock (fcgck) is changed. the gear clock (fcgck) may be longer than the set clock width, immediately after cgcr is changed. table 2-1 prohibited combi nations of oscillation en able register conditions p0fc0 syscr2 syscr2 syscr2 state don't care 0 0 don?t care all the oscillation circuits are stopped. don?t care don?t care 0 1 the low-frequency clock (fs) is selected as the main system clock, but the low-frequency clock oscillation circuit is stopped. don?t care 0 don?t care 0 the high-frequency clock (fc) is selected as the main system clock, but the high-frequency clock oscillation circuit is stopped. 0 1 don?t care don?t care the high-frequency clock oscillation circuit is allowed to oscillate, but the port is set as a general-purpose port. xin high-frequency clock xout (a) crystal or ceramic oscillator xin xout (b) external oscillator (open) xtin low-frequency clock xtout (c) crystal oscillator xtin xtout (d) external oscillator (open)
page 19 TMP89FH46 ra001 immediately after reset release, the gear clock (fcg ck) becomes the clock that is a quarter of the high- frequency clock (fc). note: don't change cgcr in the slow mode. this may stop the gear clock (fcgck) from being changed. 2.3.3.3 timing generator the timing generator is a circuit that generates system clocks to be supplied to the cpu core and the peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). the timing generator has the following functions: 1. generation of the main system clock (fm) 2. generation of clocks for the timer counter, the time base timer and other peripheral circuits figure 2-5 configurat ion of timing generator (1) configuration of timing generator the timing generator consists of a main system cl ock generator, a prescaler, a 21-stage divider and a machine cycle counter. 1. main system clock generator this circuit selects the gear cl ock (fcgck) or the clock that is a quarter of the low-frequency clock (fs) for the main system clock (fm) to operate the cpu core. clearing syscr2 to "0" selects the gear clock (fcgck ). setting it to "1" selects the clock that is a quarter of the low-frequency clock (fs). it takes a certain period of time after syscr2 is changed before the main sys- tem clock is switched. if the currently operating oscillation circuit is stopped before the main system clock is switched, the internal conditi on becomes as shown in table 2-1 and a system clock reset occurs. for details of clock switching, refer to "2.3.6 operation mode control". table 2-2 gear clock (fcgck) cgcr fcgck 00 fc / 4 01 fc / 2 10 fc 11 reserved main system clock generator machine cycle counter syscr2 syscr1 gear clock fcgck prescaler divider multiplexer a timer counter, time base timer and other peripheral circuits divider b s y main system clock fm a quarter of the basic clock for the low-frequency clock
page 20 2. cpu core 2.3 system clock controller TMP89FH46 ra001 2. prescaler and divider these circuits divide fcgck. the divided clocks are supplied to the timer counter, the time base timer and other peripheral circuits. when both syscr1 and syscr2 are "0", the input clock to stage 9 of the divider becomes the output of stage 8 of the divider. when syscr1 or syscr2 is "1", the input clock to stage 9 of the divider becomes fs/4. when sysc r2 is "1", the outputs of stages 1 to 8 of the divider and prescaler are stopped. the prescaler and divider are cl eared to "0" at a reset and at the end of the warm-up opera- tion that follows the release of stop mode. 3. machine cycle instruction execution is synchronized with the main system clock (fm). the minimum instruction execution unit is called a "machine cycle". one machine cycle corresponds to one main system clock. there are a total of 11 different types of inst ructions for the tlcs-870/c1 series: 10 types ranging from 1-cycle instructions, which re quire one machine cycl e for execution, to 10- cycle instructions, which require 10 machine cy cles for execution, and 13-cycle instructions, which require 13 machin e cycles for execution. 2.3.4 warm-up counter the warm-up counter is a ci rcuit that counts the high-frequency cloc k (fc) and the low-frequency clock (fs), and it consists of a source clock sel ection circuit, a 3-stage frequency division circuit and a 14-stage counter. the warm-up counter is used to secure the time after a power-on reset is released before the supply voltage becomes stable and secure the time af ter the stop mode is released or the operation mode is changed before the oscillation by the oscillat ion circuit becomes stable. figure 2-6 warm-up counter circuit s z d c b a s z a b clock for high-frequency clock oscillation circuit (fc) clock for low-frequency clock oscillation circuit (fs) com- parator wucdr syscr2 syscr1 wuccr enable/disable counting up xen xten stop intwuc interrupt enable cpu operation wucsel wucdiv wucrst warm-up counter controller 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 1 2 3
page 21 TMP89FH46 ra001 2.3.4.1 warm-up counter operation when t he oscillation is enabled by the hardware (1) when a power-on reset is released or a reset is released the warm-up counter serves to secure the time af ter a power-on reset is released before the supply voltage becomes stable and the time after a reset is released before the oscillation by the high-fre- quency clock oscillation circuit becomes stable. when the power is turned on and the supply voltage exceeds the power-on reset release voltage, the warm-up counter reset si gnal is released. at this time, the cpu and the peripheral circuits are held in the reset state. a reset signal initializes wuccr to "0" and wuccr to "11", which selects the high-frequency clock (fc) as the input clock to the warm-up counter. when a reset is released for the warm-up counter, the high-frequency clock (fc) is input to the warm-up counter, and the 14-stage counter st arts counting the high-frequency clock (fc). when the upper 8 bits of the warm-up counter become equal to wucdr, counting is stopped and a reset is released for the cpu and the peripheral circuits. wucdr is initialized to 0x66 after reset release, which makes the warm-up time 0x66 2 9 /fc[s]. note: the clock output from the oscillation circuit is used as the input clock to the warm-up counter. the warm-up time contains errors because the oscillat ion frequency is unstable unt il the oscillation cir- cuit becomes stable. (2) when the stop mode is released the warm-up counter serves to secure the time after the oscillation is enabled by the hardware before the oscillation becomes stable at the release of the stop mode. the high-frequency clock (fc) or the low-freque ncy clock (fs), which generates the main system clock when the stop mode is activated, is selected as the input clock for frequency division circuit, regardless of wuccr. before the stop mode is activat ed, select the division rate of the input clock to the warm-up counter at wuccr and se t the warm-up time at wucdr. when the stop mode is released , the 14-stage counter starts counting the input clock selected in the frequency division circuit. when the upper 8 bits of the warm-up counter become equal to wucdr, counting is stopped and the operation is restarted by an instruction th at follows the stop mode activation instruction. note 1: when the operation is switched to the stop mode duri ng the warm-up for the oscillation enabled by the software, the warm-up counter holds the value at the time, and restarts c ounting after the stop mode is released. in this case, the warm-up time at the release of the stop mode becomes insu fficient. don't switch the operation to the stop mode during the warm-up for the oscillati on enabled by the software. clock that generates the main system clock when the stop mode is acti- vated wuccr wuccr counter input clock warm-up time fc don?t care 00 fc 2 6 / fc to 255 x 2 6 / fc 01 fc / 2 2 7 / fc to 255 x 2 7 / fc 10 fc / 2 2 2 8 / fc to 255 x 2 8 / fc 11 fc / 2 3 2 9 / fc to 255 x 2 9 / fc fs don't care 00 fs 2 6 / fs to 255 x 2 6 / fs 01 fs / 2 2 7 / fs to 255 x 2 7 / fs 10 fs / 2 2 2 8 / fs to 255 x 2 8 / fs 11 fs / 2 3 2 9 / fs to 255 x 2 9 / fs
page 22 2. cpu core 2.3 system clock controller TMP89FH46 ra001 note 2: the clock output from the oscillati on circuit is used as the input clock to the warm-up counter. the warm-up time contai ns errors because the oscillation fr equency is unstable until the oscillation circui t becomes stable. set the sufficient time for the oscillation start property of the oscillator. 2.3.4.2 warm-up counter operation when t he oscillation is enabled by the software the warm-up counter serves to secure the time after the oscillation is enabled by the software before the oscillation becomes stable, at a mode change from normal1 to normal2 or from slow1 to slow2. select the input clock to the freque ncy division circui t at wuccr. select the input clock to the 14 -stage counter at wuccr. after the warm-up time is set at wucdr, setting syscr2 or syscr2 to "1" allows the stopped oscillation circuit to start oscillation an d the 14-stage counter to start counting the selected input clock. when the upper 8 bits of the count er become equal to wucdr, an intwuc interrupt occurs, counting is stopped and the counter is cleared. set wuccr to "1" to disc ontinue the warm-up operation. by setting it to "1", the count-up operation is stopped, the warm-up counter is cleared, and wuccr is cleared to "0". syscr2 and syscr2 hold the valu es when wuccr is set to "1". to restart the warm-up operation, syscr2 or syscr2 must be cleared to "0". note: the warm-up counter starts counting when syscr2 or syscr2 is changed from "0" to "1". the counter will not start counting by wr iting "1" to syscr2 or syscr2 when it is in the state of "1". note: the clock output from the osci llation circuit is used as the input clock to the warm-up counter. the warm-up time contains errors becau se the oscillation frequency is uns table until the oscillation circuit becomes stable. set the sufficient time for t he oscillation start property of the oscillator. 2.3.5 operation m ode control circuit the operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock (fm). there are three operating modes: th e single-clock mode, the dual-clock mode and the stop mode. these modes are controlled by the system co ntrol registers (syscr1 and syscr2). figure 2-7 shows the operating mode transition diagram. 2.3.5.1 single-clock mode only the gear clock (fcgck) is used fo r the operation in the single-clock mode. wuccr wuccr counter input clock warm-up time 0 00 fc 2 6 / fc to 255 x 2 6 / fc 01 fc / 2 2 7 / fc to 255 x 2 7 / fc 10 fc / 2 2 2 8 / fc to 255 x 2 8 / fc 11 fc / 2 3 2 9 / fc to 255 x 2 9 / fc 1 00 fs 2 6 / fs to 255 x 2 6 / fs 01 fs / 2 2 7 / fs to 255 x 2 7 / fs 10 fs / 2 2 2 8 / fs to 255 x 2 8 / fs 11 fs / 2 3 2 9 / fs to 255 x 2 9 / fs
page 23 TMP89FH46 ra001 the main system clock (fm) is generated from the g ear clock (fcgck). therefor e, the machine cycle time is 1/fcgck [s]. the gear clock (fcgck) is generated from the high-frequency clock (fc). in the single-clock mode, the low-frequency cloc k generation circuit pins p03 (xtin) and p04 (xtout) can be used as the i/o ports. (1) normal1 mode in this mode, the cpu core and the peripheral circuits operate using the gear clock (fcgck). the normal1 mode becomes active after reset release. (2) idle1 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck). the idle1 mode is activated by setting sy scr2 to "1" in the normal1 mode. when the idle1 mode is activated, the cpu and the watchdog timer stop. when the interrupt latch enabled by the interrup t enable register efr becomes "1", the idle1 mode is released to the normal1 mode. when the imf (interrupt master en able flag) is "1" (interrupts en abled), the operation returns nor- mal after the interrupt processing is completed. when the imf is "0" (interrupts di sabled), the operation is restarted by the instruction that follows the idle1 mode activation instruction. (3) idle0 mode in this mode, the cpu and the peripheral circuits stop, except the oscillat ion circuits and the time base timer. in the idle0 mode, the peripheral circuits stop in the states when the idle0 mode is activated or become the same as the states when a reset is releas ed. for operations of the pe ripheral circuits in the idle0 mode, refer to the secti on of each peripheral circuit. the idle0 mode is activated by setting syscr2 to "1" in the normal1 mode. when the idle0 mode is activat ed, the cpu stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. when the falling edge of the source clock selected at tbtcr is detected, the idle0 mode is released, the timing generator starts the clock supply to all the peripheral circuits and the normal1 mode is restored. note that the idle0 mode is activated an d restarted, regardless of the setting of tbtcr. when the idle0 mode is activated with tbtcr< tbten> set at "1", the inttbt interrupt latch is set after the normal mode is restored. when the imf is "1" and the ef5 (the individual in terrupt enable flag for the time base timer) is "1", the operation returns normal after the interrupt processing is completed. when the imf is "0" or when the imf is "1" and the ef5 (the individual interrupt enable flag for the time base timer) is "0", the operation is restarted by the instruction that follows the idle0 mode activation instruction.
page 24 2. cpu core 2.3 system clock controller TMP89FH46 ra001 2.3.5.2 dual-clock mode the gear clock (fcgck) and the low-frequency clock (fs) are used for the op eration in the dual-clock mode. the main system clock (fm) is generated from the gear clock (fcgck) in the normal2 or idle2 mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the slow1/2 or sleep0/1 mode. therefore, the mach ine cycle time is 1/fcgck [s] in the normal2 or idle2 mode and is 4/fs [s] in the slow1/2 or sleep0/1 mode. p03 (xtin) and p04 (xtout) are used as the low-frequency clock oscillation circuit pins. (these pins cannot be used as i/o ports in the dual-clock mode.) the operation of the tlcs-870/c1 se ries becomes the single-clock mode after reset release. to operate it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program. (1) normal2 mode in this mode, the cpu core operates using the gear clock (fcgck), and the pe ripheral circuits oper- ate using the gear clock (fcgck) or the clock th at is a quarter of the low-frequency clock (fs). (2) slow2 mode in this mode, the cpu core and th e peripheral circuits operate usin g the clock that is a quarter of the low-frequency clock (fs). in the slow mode, some peripheral circuits b ecome the same as the states when a reset is released. for operations of the peripheral circuits in the slow mode, refer to the section of each peripheral circuit. set syscr2 to switch the operation mode from normal2 to slow2 or from slow2 to normal2. in the slow2 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (3) slow1 mode in this mode, the high-frequency clock oscillation circuit stops operation and the cpu core and the peripheral circuits operate usin g the clock that is a quarter of the low-frequency clock (fs). this mode requires less power to operate the high-f requency clock oscillati on circuit than in the slow2 mode. in the slow mode, some peripheral circuits b ecome the same as the states when a reset is released. for operations of the peripheral circuits in the slow mode, refer to the section of each peripheral circuit. set syscr2 to switch the operation between the slow1 and slow2 modes. in the slow1 or sleep1 mode, outputs of the pres caler and stages 1 to 8 of the divider stop. (4) idle2 mode in this mode, the cpu and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). the idle2 mode can be activated and released in the same way as for the idle1 mode. the oper- ation returns to the normal2 mode after this mode is released.
page 25 TMP89FH46 ra001 (5) sleep1 mode in this mode, the high-frequency clock oscillatio n circuit stops operation, the cpu and the watch- dog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-fre- quency clock (fs). in the sleep1 mode, some peripheral circuits b ecome the same as the states when a reset is released. for operations of the peri pheral circuits in the sleep1 mode, refer to the section of each peripheral circuit. the sleep1 mode can be activated and released in the same way as for the idle1 mode. the operation returns to the slow1 mode after this mode is released. in the slow1 or sleep1 mode, outputs of the pres caler and stages 1 to 8 of the divider stop. (6) sleep0 mode in this mode, the high-frequency clock oscillation circuit stops operation, the time base timer oper- ates using the clock that is a quarter of the low- frequency clock (fs), and th e core and the peripheral circuits stop. in the sleep0 mode, the peripheral circuits stop in the states when the sleep0 mode is activated or become the same as the states when a reset is released. for operations of the peripheral circuits in the sleep0 mode, refer to the s ection of each peripheral circuit. the sleep0 mode can be activated and released in the same way as for the idle0 mode. the operation returns to the slow1 mode after this mode is released. in the sleep0 mode, the cpu stops and the timing generator stops the clock supply to the periph- eral circuits except the time base timer. 2.3.5.3 stop mode in this mode, all the operations in the system, incl uding the oscillation circuits, are stopped and the internal states in effect before the system was stopped are held with low power consumption. in the stop mode, the peripheral circuits stop in th e states when the stop m ode is activated or become the same as the states when a reset is released. for ope rations of the peripheral circuits in the stop mode, refer to the section of each peripheral circuit. the stop mode is activated by setting syscr1 to "1". the stop mode is released by the stop mode rel ease signals. after the warm-up time has elapsed, the operation returns to the mode that was active before the stop mode, and the oper ation is restarted by the instruction that follows the stop mode activation instruction.
page 26 2. cpu core 2.3 system clock controller TMP89FH46 ra001 2.3.5.4 transition of operation modes note 1: the normal1 and normal2 mode s are generically called t he normal mode; the slow1 and slow2 modes are called the slow mode; the idle0, idle1 and idle2 modes are called the idle mode; and the sleep0 and sleep1 are called the sleep mode. note 2: the mode is released by the falling edge of the source clock selected at tbtcr. figure 2-7 operation mode transition diagram idle0 mode reset warm-up that follows reset release normal1 mode stop normal2 mode slow2 mode slow1 mode idle0 mode idle2 mode sleep1 mode sleep0 mode (a) single-clock mode (b) dual-clock mode syscr2 = "1" syscr1 = "1" syscr2 = "1" syscr1 = "1" syscr2 = "1" syscr1 = "1" interrupt interrupt stop mode release signal stop mode release signal stop mode release signal interrupt syscr2 = "1" syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "1" reset release warm-up completed syscr2 = "1" (note 2) (note 2)
page 27 TMP89FH46 ra001 2.3.6 operation mode control 2.3.6.1 stop mode the stop mode is controlled by system control register 1 (syscr1) and the stop mode release sig- nals. (1) start the stop mode the stop mode is started by setting syscr1 to "1". in the stop mode, the following states are maintained: 1. both the high-frequency and low-frequency clock oscillation circuits stop oscillation and all internal operations are stopped. 2. the data memory, the registers and the program status word are all held in the states in effect before stop mode was started. the port output latch is determined by the value of syscr1. 3. the prescaler and the divider of th e timing generator are cleared to "0". 4. the program counter holds the address of the instruction 2 ahead of the instruction (e.g., [set (syscr1).7]) which started the stop mode. (2) release the stop mode the stop mode is released by the following stop mode release signals. it is also released by a reset by the reset pin, a power-on reset and a reset by the vol tage detection circuits. when a reset is released, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. 1. release by the stop pin table 2-3 operation modes and conditions operation mode oscillation circuit cpu core watchdog timer time base timer other periph- eral circuits machine cycle time high-fre- quency low-fre- quency single clock reset oscillation stop reset reset reset reset 1 / fcgck [s] normal1 operate operate operate operate idle1 stop stop idle0 stop stop stop stop ?| dual clock normal2 oscillation oscillation operate with the high fre- quency operate with the high/low frequency operate operate 1 / fcgck [s] idle2 stop stop slow2 operate with the low fre- quency operate with the low fre- quency 4/ fs [s] slow1 stop operate with the low fre- quency operate with the low fre- quency sleep1 stop stop sleep0 stop stop stop stop ?|
page 28 2. cpu core 2.3 system clock controller TMP89FH46 ra001 2. release by key-on wakeup 3. release by the volt age detection circuits note: during the stop period (from the start of the stop mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after the stop mode is released. before starting the stop mode, therefore, disable interrupts. also, before enabl ing interrupts after stop mode is released, clear unnecessary interrupt latches. 1. release by the stop pin release the stop mode by using the stop pin. to release the stop mode by using the stop pin, set vdcr2 to "00" or "10". (for details of vdcr2, refer to the s ection of voltage detection circuits.) the stop mode release by the stop pin includ es the level-sensitive release mode and the edge-sensitive release mode, either of which can be selected at syscr1. the stop pin is also used as the p11 port and the int5 (external interrupt input 5) pin. note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. - level-sensitive release mode the stop mode is released by setting the stop pin high. setting syscr1 to "1" selects the level-sensitive release mode. this mode is used for the capacitor backup when the main power supply is cut off and the long term battery backup. even if an instruction for starting the stop mode is executed while the stop pin in- put is high, the stop mode does not start. thus, to start the stop mode in the level- sensitive release mode, it is necessary fo r the program to firs t confirm that the stop pin input is low. this can be confirmed by testing the port by the software or using interrupts note: when the stop mode is released, the warm -up counter source cloc k automatically changes to the clock that generated the main system clock when the stop mode was started, regard- less of wuccr. example: starting the stop mode from the slow mode with an int5 interrupt (warm-up time at release of the stop mode is about 450ms at fs=32.768 khz.) pint5: test (p0prd).5 ; to reject noise, the stop mode does not start jrs f, sint5 ; if the stop pin input is high. ld (syscr1), 0x40 ; sets up the level-sensitive release mode ld (wuccr), 0x03 ; wuccr = 00 (no division) (note) ld (wucdr),0xe8 ; ; sets the warm-up time 450 ms/1.953 ms = 230.4 round up to 0xe8 di ; imf = 0 set (syscr1).7 ; starts the stop mode sint5: reti stop pin xout pin normal mode the stop mode is released by the hardware. normal mode v ih warm-up stop mode confirm by program that the stop pin input is low and start the stop mode. always released if the stop pin input is high.
page 29 TMP89FH46 ra001 even if the stop pin input returns to low after the warm-up starts, the stop mode is not restarted. figure 2-8 level-sensitive re lease mode (example when the hi gh-frequency clock oscillation circuit is selected) note: when the stop mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the stop mode was started, regardless of wuccr. note: if the rising edge is input to the stop pin within 1 machine cycle after syscr1 is set to "1", the stop mode will not be released. figure 2-9 edge-sensitive rel ease mode (example when the high-frequency clock oscillation circuit is selected) - edge-sensitive release mode in this mode, the stop mode is re leased at the rising edge of the stop pin input. setting syscr1 to "0" selects the edge-sensitive release mode. this is used in applications where a rela tively short program is executed repeatedly at periodic intervals. this periodic signal (f or example, a clock from a low-power con- sumption oscillator) is input to the stop pin. in the edge-sensitive release mode, the stop mode is started even when the stop pin input is high example: starting the stop mode from the normal mode (warm-up time at release of the stop mode is about 200ms at fc=10 mhz.) ld (wuccr),0x01 ; wuccr = 00 (no division) (note) ld (wucdr),0x20 ; ; sets the warm-up time 200ms / 6.4 s = 31.25 round up to 0x20 di ; imf = 0 ld (syscr1) , 0x80 ; starts the stop mode with the edge-sensitive release mode selected stop pin xout pin normal mode v ih warm-up stop mode stop mode the stop mode is started by the program. the stop mode is released by the hardware at the rising edge of the stop pin input. normal mode
page 30 2. cpu core 2.3 system clock controller TMP89FH46 ra001 2. release by the key-on wakeup the stop mode is released by inputting the prescribed level to the key-on wakeup pin. the level to release the stop mode can be selected from "h" and "l". for release by the key-on wakeup, refer to section "key-on wakeup". 3. release by the volt age detection circuits the stop mode is released by the supply voltage detection by the voltage detection cir- cuits. to release the stop mode by using the voltage detection circuits, set vdcr2 to "01" or "10". if the voltage detection operation mode of the voltage detection circuits is set to generate reset signals (when vdcr2 is 1 (x=1 to 2)), the stop mode is released and a reset is applied as soon as the supply voltage becomes lower than the detection voltage. when the supply voltage becomes equal to or higher than the detection voltage of the volt- age detection circuits, the reset is released a nd the warm-up starts. after the warm-up is com- pleted, the normal1 mode becomes active. if the voltage detection operation mode of the voltage detection circuits is set to generate interrupt request signals (when vdcr2 is 0 (x=1 to 2)), the stop mode is released when the supply voltage becomes equal to or higher than the detection voltage. for details, refer to the section of the voltage detection circuits. (3) stop mode release operation the stop mode is released in the following sequence: 1. oscillation starts. for the osci llation start operation in each m ode, refer to "table 2-4 oscil- lation start operation at re lease of the stop mode". 2. warm-up is executed to secure the time required to stabilize oscillation. the internal opera- tions remain stopped during warm-up. the wa rm-up time is set by the warm-up counter, depending on the oscillator characteristics. 3. after the warm-up time has elapsed, the norma l operation is restarted by the instruction that follows the stop mode start instruction. at th is time, the prescaler and the divider of the timing generator are cleared to "0". note: when the stop mode is released with a low hold voltage, the following cautions must be observed. the supply voltage must be at the operating voltage level before releasing the stop mode. the reset pin input must also be "h" level, rising together with the supply voltage. in this case, if an external time constant ci rcuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if the input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). note: if the key-on wakeup pin input becomes the opposite level to the release level after the warm-up starts, the stop mode is not restarted. note: if the supply voltage becomes equal to or higher than the detection voltage within 1 ma- chine cycle after syscr1 is set to "1", the stop mode will not be released.
page 31 TMP89FH46 ra001 note: when the operation returns to the normal2 mode, fc is i nput to the frequency division circuit of the warm-up counter. 2.3.6.2 idle1/2 and sleep1 modes the idle1/2 and sleep1 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following stat es are maintained during these modes. 1. the cpu and the watchdog timer stop their operations. the peripheral circuits continue to oper- ate. 2. the data memory, the registers, the program status word and th e port output latches are all held in the status in effect before id le1/2 or sleep1 mode was started. 3. the program counter holds the address of the inst ruction 2 ahead of the instruction which starts the idle1/2 or sleep1 mode. table 2-4 oscillation start operat ion at release of the stop mode operation mode before the stop mode is started high-frequency clock low-frequency clock oscillation start operation after release single-clock mode normal1 high-frequency clock oscillation circuit - the high-frequency clock oscillation circuit starts oscillation. the low-frequency clock oscillation circuit stops oscillation. dual-clock mode normal2 high-frequency clock oscillation circuit low-frequency clock oscillation cir- cuit the high-frequency clock oscillation circuit starts oscillation. the low-frequency clock oscillation circuit starts oscillation. slow1 - low-frequency clock oscillation cir- cuit the high-frequency clock oscillation circuit stops oscillation. the low-frequency clock oscillation circuit starts oscillation.
page 32 2. cpu core 2.3 system clock controller TMP89FH46 ra001 figure 2-10 idle1/ 2 and sleep 1 modes cpu and wdt stop interrupt processing reset yes no no no no imf = "1" reset input yes yes (interrupt release mode) (normal release mode) interrupt request starting idle1/2 mode or sleep1 mode by an instruction execution of the instruction which follows the idle1/2 mode or sleep1 mode start instruction
page 33 TMP89FH46 ra001 (1) start the idle1/2 and sleep1 modes after the interrupt master enable flag (imf) is se t to "0", set the individual interrupt enable flag (ef) to "1", which releases idle1/2 and sleep1 modes. to start the idle1/2 or sleep1 mode, set syscr2 to "1". if the release condition is satisfied when it is attempted to start the idle1/2 or sleep1 mode, syscr2 remains cleared and the idle1/ 2 or sleep1 mode will not be started. note 1: when a watchdog timer interrupt is generated immediately before the idle1/2 or sleep1 mode is started, the watchdog timer interrupt will be processed but the idle1/2 or sleep1 mode will not be started. note 2: before starting the idle1/2 or sleep1 m ode, enable the interrupt request signals to be gener- ated to release the idle1/2 or sleep1 mode and set the individual interrupt enable flag. (2) release the idle1/2 and sleep1 modes the idle1/2 and sleep1 modes include a normal re lease mode and an interrupt release mode. these modes are selected at the interrupt master enable flag (imf). af ter releasing idle1/2 or sleep1 mode, syscr2 is automatically clear ed to "0" and the operation mode is returned to the mode preceding the idle1/2 or sleep1 mode. the idle1/2 and sleep1 modes are also released by a reset by the reset pin, a power-on reset and a reset by the voltage detection circuits. after releasing the reset, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. ? normal release mode (imf = "0") the idle1/2 or sleep1 mode is released when the interrupt latch enabled by the individ- ual interrupt enable flag (ef) is "1". the operat ion is restarted by the instruction that follows the idle1/2 or sleep1 mode start instruction. normally, the interrupt latch (il) of the inter- rupt source used for releasing must be cleared to "0" by load instructions. ? interrupt release mode (imf = "1") the idle1/2 or sleep1 mode is released when the interrupt latch enabled by the individ- ual interrupt enable flag (ef) is "1". after the interrupt is processed, the operation is restarted by the instruction that follows the idle1 /2 or sleep1 mode start instruction. 2.3.6.3 idle0 and sleep0 modes the idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following states are maintained dur ing the idle0 and sleep0 modes: ? the timing generator stops the clock supply to the peripheral circuits except the time base timer. ? the data memory, the registers, the program status word and the port output latches are all held in the states in effect before the idle0 or sleep0 mode was started. ? the program counter holds the address of the instruction 2 ahead of the instruction which starts the idle0 or sleep0 mode.
page 34 2. cpu core 2.3 system clock controller TMP89FH46 ra001 figure 2-11 id le0 and sleep0 modes ? start the idle0 and sleep0 modes stop (disable) the peripherals such as a timer counter. to start the idle0 or sleep0 mode, set syscr2 to "1". ? release the idle0 and sleep0 modes the idle0 and sleep0 modes include a normal release mode and an interrupt release mode. these modes are selected at the interrupt master enable flag (imf), the individual inter- rupt enable flag (ef5) for the time base timer and tbtcr. after releasing the idle0 or sleep0 mode, syscr2 is automatically cleared to "0" and the opera- tion mode is returned to the mode preceding the idle0 or sleep0 mode. if tbtcr has been set at "1", the inttbt interrupt latch is set. the idle0 and sleep0 modes are also released by a reset by the reset pin, a power-on reset and a reset by the voltage detection circuits . when a reset is releas ed, the warm-up starts. after the warm-up is completed, the normal1 mode becomes active. reset yes no no "0" yes yes (interrupt release mode) (normal release mode) yes "1" no no stopping peripherals by instructions cpu and wdt stop interrupt processing reset input tbt source clock falling edge tbtcr tbt interrupt enabled imf = "1" starting idle0 or sleep0 mode by an instruction execution of the instruction which follows the idle0 or sleep0 mode start instruction
page 35 TMP89FH46 ra001 (1) normal release mode (imf , ef5, tbtcr = "0") the idle0 or sleep0 mode is released when the falling edge of the source clock selected at tbtcr is detected. after the idle0 or sleep0 mode is re leased, the operation is restarted by the instruction that follows the idle0 or s leep0 mode start instruction. when tbtcr is "1", the time base timer interrupt latch is set. (2) interrupt release mode (imf, ef5, tbtcr = "1") the idle0 or sleep0 mode is released when the falling edge of the source clock selected at tbtcr is detected. after the release, the inttbt interrupt processing is started. note 1: the idle0 or sleep0 mode is released to the normal1 or slow1 mode by the asynchro- nous internal clock selected at tbtcr. therefore, the period from the start to the release of the mode may be shorter than the time specified at tbtcr. note 2: when a watchdog timer interrupt is generat ed immediately before the idle0 or sleep0 mode is started, the watchdog timer interrupt will be processed but the idle0 or sleep0 mode will not be started. 2.3.6.4 slow mode the slow mode is controlled by system control register 2 (syscr2). (1) switching from the normal2 mode to the slow1 mode set syscr2 to "1". when a maximum of 2/fcgck + 10/fs [s] has elap sed since syscr2 is set to "1", the main system clock (fm) is switched to fs/4. after switching, wait for 2 machin e cycles or longer, and then cl ear syscr2 to "0" to turn off the high-frequency clock oscillator. if the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the warm-up counter before implementing the procedure described above. note 1: be sure to follow this procedure to sw itch the operation from the normal2 mode to the slow1 mode. note 2: it is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to return to normal2 mode. however, be sure to turn off the oscillation of the basic clock for the high-frequency clock when the stop mode is started from the slow mode. note 3: after switching syscr2, be sure to wa it for 2 machine cycles or longer before clear- ing syscr2 to "0". clearing it within 2 machine cycles causes a system clock reset. note 4: when the main system clock (fm) is switch ed, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. for the synchronization, fm is stopped for a period of 10/fs or shorter. figure 2-12 switch ing of the main system clock (fm) (switching from fcgck to fs/4) gear clock (fcgck) when the rising edge of fcgck is detected twice after syscr2 is changed from 0 to 1, f is stopped for synchronization. when the rising edge of fs/4 is detected twice after fm is stopped, fm is switched to fs. quarter of the low-frequency clock (fs/4) main system clock syscr2 10/fs (max.)
page 36 2. cpu core 2.3 system clock controller TMP89FH46 ra001 (2) switching from the slow1 mode to the normal1 mode set syscr2 to "1" to enable the high-freque ncy clock (fc) to oscillate. confirm at the warm-up counter that the oscillation of the basic clock for the high-frequen cy clock has stabilized, and then clear syscr2 to "0". when a maximum of 8/fs + 2.5/fcgck [s] has el apsed since syscr2 is cleared to "0", the main system clock (fm) is switched to fcgck. after switching, wait for 2 mach ine cycles or longer, and then clear syscr2 to "0" to turn off the low-frequency clock oscillator. the slow mode is also released by a reset by the reset pin, a power-on reset and a reset by the voltage detection circuits. when a reset is released, the warm-up starts. after the warm-up is com- pleted, the normal1 mode becomes active. note 1: be sure to follow this procedure to switch the operation from the slow1 mode to the normal1 mode. note 2: after switching syscr2, be sure to wa it for 2 machine cycles or longer before clear- ing syscr2 to "0". clearing it within 2 machine cycles causes a system clock reset. note 3: when the main system clock (fm) is switch ed, the gear clock (fcgck) is synchronized with the clock that is a quarter of the basic clock (fs) for the low-frequency clock. for the synchronization, fm is stopped for a period of 2.5/fcgck [s] or shorter. note 4: when p0fc0 is "0", setting syscr2 to "1" causes a system clock reset. note 5: when syscr2 is set at "1", writing "1" to syscr2 does not cause the warm-up counter to start counting the source clock. example 1: switching from the normal2 mode to the slow1 m ode (when fc is used as the basic clock for the high-fre- quency clock) set (syscr2).4 ; syscr2 = 1 ; (switches the main system clock to the basic clock for the low-frequen- cy clock for the slow2 mode) nop ; waits for 2 machine cycles nop clr (syscr2).6 ; syscr2 = 0 (turns off the high-frequency clock oscillation circuit) example 2: switching to the slow1 mode after the stable oscill ation of the low-frequency cloc k oscillation circuit is con- firmed at the warm-up counter (fs=32.768khz, warm-up time = about 100 ms) ; #### initialize routine #### set (p0fc).2 ; p0fc2 = 1 (uses p02/03 as oscillators) | | ld (wuccr), 0x02 ; wuccr = 00 (no division) wuccr = 1 (selects fs as the source clock) ld (wucdr), 0x33 ; sets the warm-up time (determines the time depending on the oscillator characteristics) 100 ms/1.95 ms = 51.2 round up to 0x33 set (eirl).4 ; enables intwuc interrupts set (syscr2).5 ; syscr2 = 1 (starts the low-frequency clock oscillation and starts the warm-up counter) | ; #### interrupt service routine of warm-up counter interrupts #### pintwuc: set (syscr2).4 ; syscr2 = 1 (switches the main system cl ock to the low-frequency clock) nop ; waits for 2 machine cycles nop clr (syscr2).6 ; syscr2 = 0 (turns off the high-frequency clock oscillation cir- cuit) reti | vintwuc: dw pintwuc ; intwuc vector table
page 37 TMP89FH46 ra001 figure 2-13 switching the ma in system clock (fm) (swit ching from fs/4 to fcgck) example : switching from the slow1 m ode to the normal1 mode after the stabili ty of the high-fre quency clock oscilla- tion circuit is confirmed at the warm-up c ounter (fc = 10 mhz, warm-up time = 4.0 ms) ; #### initialize routine #### set (p0fc).2 ; p0fc2 = 1 (uses p02/03 as oscillators) | | ld (wuccr), 0x09 ; wuccr = 10 (divided by 2) wuccr = 0 (selects fc as the source clock) ld (wucdr), 0x9d ; sets the warm-up time (determine the time depending on the frequency and the oscillator characteristics) 4ms / 25.6us = 156.25 round up to 0x9d set (eirl). 4 ; enables intwuc interrupts set (syscr2) .6 ; syscr2 = 1 (starts the oscillation of the high-frequency clock oscillation circuit) | ; #### interrupt service routine of warm-up counter interrupts #### pintwuc: clr (syscr2). 4 ; syscr2 = 0 (switches the main system clock to the gear clock) nop ; waits for 2 machine cycles nop clr (syscr2). 5 ; syscr2 = 0 (turns off the low-frequency clock oscillation circuit) reti | vintwuc: dw pintwuc ; intwuc vector table gear clock (fcgck) when the rising edge of fs/4 is detected twice after syscr2 is changed from 1 to 0, f is stopped for synchronization. when the rising edge of fcgck is detected twice after fm is stopped, fm is switched to fcgck. quarter of the low-frequency clock (fs/4) main system clock syscr2 2.5/fcgck(max.)
page 38 2. cpu core 2.4 reset control circuit TMP89FH46 ra001 2.4 reset control circuit the reset circuit controls the external and inte rnal factor resets and initializes the system. 2.4.1 configuration the reset control circuit consists of the following reset signal generation circuits: 1. external reset input (external factor) 2. power-on reset (internal factor) 3. voltage detection reset 1 (internal factor) 4. voltage detection reset 2 (internal factor) 5. watchdog timer reset (internal factor) 6. system clock rese t (internal factor) 7. trimming data reset (internal factor) 8. flash standby reset (internal factor) figure 2-14 reset control circuit 2.4.2 control the reset control circuit is controll ed by system control register 3 (s yscr3), system control register 4 (syscr4), system control status regi ster (syssr4) and the in ternal factor reset detection status register (irstsr). note 1: the enabled syscr3 is initialized by a power-on re set only, and cannot be initialized by an external reset input or internal factor reset. the value written in syscr3 is rese t by a power-on reset, external reset input or internal factor reset. note 2: the value of syscr3 is invalid until 0xb2 is written into syscr4. system control register 3 syscr3 (0x0fde) 76543210 bit symbol-----(rvctr)(rarea)rstdis read/writerrrrrr/wr/wr/w after reset00000000 rstdis external reset input enable register 0 : enables the external reset input. 1 : disables the external reset input. p10(reset) internal factor reset detection status register, voltage detection circuit reset signal external reset input enable reset signal warm-up counter reset signal system clock control circuit warm-up counter cpu/peripheral circuits reset signal flash standby reset signal trimming data reset signal system clock reset signal watchdog timer reset signal voltage detection reset 2 signal power-on reset signal p10 port voltage detection reset 1 signal
page 39 TMP89FH46 ra001 note 3: after syscr3 is modified, syscr4 shoul d be written 0xb2 (enable code for syscr3) in normal1 mode when fcgck is fc/4 (cgcr=00). otherwise, sys cr3 may be enabled at unex- pected timing. note 4: bits 7 to 3 of syscr3 are read as "0". note 1: syscr4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit opera- tion. note 2: after syscr3 is modified, syscr4 should be written 0xb2 (enable code for syscr3) in normal mode when fcgck is fc/4 (cgcr=00). other wise, syscr3 may be enabled at unexpected tim- ing. note 3: after irstsr is modified, syscr4 should be wr itten 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. note 1: the enabled syscr3 is initialized by a power- on reset only, and cannot be initialized by any other reset sig- nals. the value written in syscr3 is reset by a power-on reset and other reset signals. note 2: bits 7 to 3 of syscr4 are read as "0". system control register 4 syscr4 (0x0fdf) 76543210 bit symbol syscr4 read/write w after reset00000000 syscr4 writes the syscr3 data control code. 0xb2 : enables the contents of syscr3. 0xd4 : enables the contents of syscr3 and syscr3 . 0x71 : enables the contents of irstsr others : invalid system control status register 4 syssr4 (0x0fdf) 76543210 bit symbol-----(rvctrs)(rareas)rstdiss read/writerrrrrrrr after reset00000000 rstdiss external reset input enable status 0 : the enabled syscr3 data is "0". 1 : the enabled syscr3 data is "1". internal factor reset detection status register irstsr (0x0fcc) 76543210 bit symbol fclr flsrf trmds trmrf lvd2rf lvd1rf sysrf wdtrf read/writewrrrrrrr after reset00000000
page 40 2. cpu core 2.4 reset control circuit TMP89FH46 ra001 note 1: irstsr is initialized by an ex ternal reset input or power-on reset. note 2: care must be taken in system designing since the irstsr may not fulfill its functions due to disturbing noise and other effects. note 3: irstsr is initialized by a power-on reset, an external reset input or an internal reset factor. note 4: set irstsr to "1" and write 0x71 to syscr4. this enables irstsr and the internal factor reset detec- tion status register is clear to "0". irstsr is cleared to "0" automatically after initia lizing the internal factor rese t detection status register. note 5: after irstsr is modified, syscr4 should be wr itten 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. note 6: bit 7 of irstsr is read as "0". 2.4.3 functions the power-on reset, external reset input and internal f actor reset signals are input to the warm-up circuit of the clock generator. during reset, the warm-up counter circuit is reset, and the cpu and the peripheral circuits are reset. after reset is released, the warm-up counter starts co unting the high frequency clock (fc), and executes the warm-up operation that follows reset release. during the warm-up operation that foll ows reset release, the trimming data is loaded from the non-volatile exclusive use memory for ad justment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits. when the warm-up operation that foll ows reset release is finished, the cpu starts execution of the program from the reset vector address stor ed in addresses 0xfffe to 0xffff. when a reset signal is input during the warm-up opera tion that follows reset release, the warm-up counter circuit is reset. the reset operation is common to the power-on reset, ex ternal reset input and inte rnal factor resets, except for the initialization of some special function registers and the initialization of the voltage detection circuits. when a reset is applied, the peripheral circui ts become the states as shown in table 2-5. fclr flag initialization control 0 :- 1 : clears the internal factor reset flag to "0". flsrf flash standby reset detection flag 0 :- 1 : detects the flash standby reset. trmds trimming data status 0 :- 1 : detect state of abnormal trimming data trmrf trimming data reset detection flag 0 :- 1 : detects the trimming data reset. lvd2rf voltage detection reset 2 detection flag 0 :- 1 : detects the voltage detection 2 reset. lvd1rf voltage detection reset 1 detection flag 0 :- 1 : detects the voltage detection 1 reset. sysrf system clock re set detection flag 0 :- 1 : detects the system clock reset. wdtrf watchdog timer reset detection flag 0 :- 1 : detects the watchdog timer reset.
page 41 TMP89FH46 ra001 note: the voltage detection circuits are disabled by an external reset input or power-on reset only. 2.4.4 reset signal generating factors reset signals are generated by each factor as follows: 2.4.4.1 external reset input ( reset pin input) port p10 is also used as the reset pin, and it serves as the reset pin after the power is turned on. if the supply voltage is lower than the recommended operating voltage range, for example, when the power is turned on, the supply voltage is raised to the operating voltage range with the reset pin kept at the "l" level, and a reset is applied 5 s after the oscillation is stabilized. if the supply voltage is within the recommended operating voltage range, the reset pin is kept at the "l" level for 5 s with the stabilized oscillation, and then a reset is applied. in each case, after a reset is app lied, it is released by turning the reset pin to "h" and the warm-up operation that follows re set release gets started. table 2-5 initialization of built-in hardware by reset operation and its status after release built-in hardware during reset during the warm-up opera- tion that follows reset release immediately after the warm-up operation that fol- lows reset release program counter (pc) mcu mode: 0xfffe serial prom mode:0x01ff mcu mode: 0xfffe serial prom mode:0x01ff mcu mode: 0xfffe serial prom mode:0x01ff stack pointer (sp) 0x00ff 0x00ff 0x00ff ram indeterminate indeterminate indeterminate general-purpose registers (w, a, b, c, d, e, h, l, ix and iy) indeterminate indeterminate indeterminate register bank selector (rbs) 0 0 0 jump status flag (jf) indeterminate indeterminate indeterminate zero flag (zf) indeterminate indeterminate indeterminate carry flag (cf) indeterminate indeterminate indeterminate half carry flag (hf) indeterminate indeterminate indeterminate sign flag (sf) indeterminate indeterminate indeterminate overflow flag (vf) indeterminate indeterminate indeterminate interrupt master enable flag (imf) 0 0 0 individual interrupt enable flag (ef) 0 0 0 interrupt latch (il) 0 0 0 high-frequency clock oscillation circuit oscillation enabled oscillation enabled oscillation enabled low-frequency clock oscillation circuit oscillation disabled oscillation disabled oscillation disabled warm-up counter reset start stop timing generator prescaler and divider 0 0 0 watchdog timer disabled disabled enabled voltage detection circuit disabled or enabl ed disabled or enabled disabled or enabled i/o port pin status hiz hiz hiz special function register refer to the sfr map. refer to the sfr map. refer to the sfr map.
page 42 2. cpu core 2.4 reset control circuit TMP89FH46 ra001 note: when the supply voltage is equal to or lower than the detection voltage of the power-on reset circuit, the power-on reset remains active, even if the reset pin is turned to "h". figure 2-15 external reset input (when the power is turned on) figure 2-16 external reset input (when the power is stabilized) reset time warm-up operation during reset cpu and peripheral circuits start operation operating voltage reset pin cpu/peripheral circuits reset reset time warm-up operation during reset cpu and peripheral circuits start operation reset pin reset signal operating voltage
page 43 TMP89FH46 ra001 2.4.4.2 power-on reset the power-on reset is an internal factor rese t that occurs when the power is turned on. when power supply voltage goes on, if the supply vol tage is equal to or lower than the releasing voltage of the power-on reset circuit, a reset signal is generated and if it is higher than the releasing voltage of the power-on reset circuit, a reset signal is released. when power supply voltage goes down, if the supply voltage is equal to or lower than the detecting voltage of the power-on reset circuit, a reset signal is generated. refer to "power-on reset circuit". 2.4.4.3 voltage detection reset the voltage detection reset is an internal factor rese t that occurs when it is de tected that the supply volt- age has reached a predeter mined detection voltage. refer to "voltage detection circuit". 2.4.4.4 watchdog timer reset the watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer is detected. refer to "watchdog timer". 2.4.4.5 system clock reset the system clock reset is an internal factor reset that occurs when it is detected that the oscillation enable register is set to a combinat ion that puts the cpu into deadlock. refer to "clock control circuit". 2.4.4.6 trimming data reset the trimming data reset is an internal factor reset that occurs when the trimming data latched in the internal circuit is broken down during operation due to noise or other factors. the trimming data is a data bit provided for adjustment of the ladder resistor that generates the compar- ison voltage for the power-on reset and the voltage detection circuits. this bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows reset release (tpwup) and latched into the internal circuit. if the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation that follows reset release is abno rmal, irstsr is set to "1". when irstsr is read as "1" in the initialize routine imme diately after reset release, the trimming data need to be reloaded by generating an in ternal factor reset, such as a system clock reset, and activating the warm-u p operation again. if irstsr is still set to "1" after repeated reading, the detection voltage of the voltage detec- tion circuit and power-on reset circuit does not satisfy the characteristic specified in the electric character- istics. design the system so that the sy stem will not be damaged in such a case. 2.4.4.7 flash standby reset the flash standby reset is an internal factor reset generated by the reading or writing of data of the flash memory while it is on standby. refer to "flash memory".
page 44 2. cpu core 2.4 reset control circuit TMP89FH46 ra001 2.4.4.8 internal factor reset detection status register by reading the internal factor reset detection status register irstsr af ter the release of an internal fac- tor reset, except the power-on reset, the f actor which causes a reset can be detected. the internal factor reset detection status register is initialized by an external reset input or power-on reset. set irstsr to "1" and write 0x71 to sys cr4. this enables irstsr and the internal factor reset detection status register is clear to "0". irstsr is cleared to "0" automatically after initializing the internal factor reset detection status register. note 1: care must be taken in system designing since the irstsr may not fulfill its functions due to disturb- ing noise and other effects. note 2: after irstsr is modified, syscr4 should be written 0x71 (enable code for irstsr in normal mode when fcgck is fc/4 (cgcr=00). otherwise, irstsr may be enabled at unexpected timing. 2.4.4.9 how to use the external reset input pin as a port to use the external reset input pin as a port, keep the external reset input pin at the "h" level until the power is turned on and the warm-up operation that follows reset release is finished. after the warm-up operation that follows reset release is finished, set p1pu0 to "1" and p1cr0 to "0", and connect a pull-up resistor for a port. then set syscr3 to "1" and write 0xb2 to syscr4. this disables the external reset function and makes th e external reset input pin usable as a normal port. to use the pin as an external reset pin when it is used as a port, set p1pu0 to "1" and p1cr0 to "0" and connect the pull-up resistor to put the pin to the input mode. then clear sy scr3 to "0" and write 0xb2 to syscr4. this enables the external reset function and ma kes the pin usable as the external reset input pin. note 1: if you switch the external reset input pin to a por t or switch the pin used as a port to the external reset input pin, do it when the pin is stabilized at the "h " level. switching the pin function when the "l" level is input may cause a reset. note 2: if the external reset input is used as a por t, the statement which clears syscr3 to "0" is not written in a program. by the abnormal execution of program, the external reset input set as a port may be changed as the external reset input at unexpected timing. note 3: after syscr3 is modified, sy scr4 should be written 0xb2 (enable code for syscr3) in normal1 mode when fcgck is fc/4 (cgcr=00). otherwise, syscr3 may be enabled at unexpected timing.
page 45 TMP89FH46 ra003 3. interrupt control circuit the TMP89FH46 has a total of 25 interrupt sources excluding reset. interrupts can be nested with priorities. three of the internal interrupt sources are n on-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and have independent vec- tor addresses. when a request for an inte rrupt is generated, its interrupt latch is set to "1", which requests the cpu to accept the interrupt. acceptance of inte rrupts is enabled or disabled by soft ware using the interrupt master enable flag (imf) and individual enab le flag (ef) for each interrupt source. if multiple maskable interrupts are generated simultaneously, the interrupts are accepted in order of descending priority. the pr iorities are determ ined by the inter- rupt priority change control register (ilprs1-ilprs6) as levels and determined by the hardware as the basic prior- ities. however, there are no prioritized interr upt sources among non-maskable interrupts. note 1: to use the watchdog timer interrupt (intwdt), clear wdct r to "0" (it is set for the "reset request" after reset is released). for details, see "watchdog timer". note 2: 0xfffa and 0xfffb function not as interrupt vectors but as option codes in the serial prom mode. for details, see "serial prom mode". note 3: vector address areas can be changed by the syscr3 setting. to assign vector address areas to ram, set syscr3 to "1" and syscr3 to "1". interrupt sources enable condition interrupt latch vector address (mcu mode) basic prior- ity rvctr=0 enabled rvctr=1 enabled internal/ external (reset) non-maskable - 0xfffe - 1 internal intswi non-maskable - 0xfffc 0x01fc 2 internal intundef non-maskable - 0xfffc 0x01fc 2 internal intwdt non-maskable ill 0xfff8 0x01f8 2 internal intwuc imf and eirl = 1 ill 0xfff6 0x01f6 5 internal inttbt imf and eirl = 1 ill 0xfff4 0x01f4 6 internal intrxd0 / intsio0 imf and eirl = 1 ill 0xfff2 0x01f2 7 internal inttxd0 imf and eirl = 1 ill 0xfff0 0x01f0 8 external int5 imf and eirh = 1 ilh 0xffee 0x01ee 9 internal intvltd imf and eirh = 1 ilh 0xffec 0x01ec 10 internal intadc imf and eirh = 1 ilh 0xffea 0x01ea 11 internal intrtc imf and eirh = 1 ilh 0xffe8 0x01e8 12 internal inttc00 imf and eirh = 1 ilh 0xffe6 0x01e6 13 internal inttc01 imf and eirh = 1 ilh 0xffe4 0x01e4 14 internal inttca0 imf and eirh = 1 ilh 0xffe2 0x01e2 15 internal intsbi0/intsio0 imf and eirh = 1 ilh 0xffe0 0x01e0 16 external int0 imf and eire = 1 ile 0xffde 0x01de 17 external int1 imf and eire = 1 ile 0xffdc 0x01dc 18 external int2 imf and eire = 1 ile 0xffda 0x01da 19 external int3 imf and eire = 1 ile 0xffd8 0x01d8 20 external int4 imf and eire = 1 ile 0xffd6 0x01d6 21 internal inttca1 imf and eire = 1 ile 0xffd4 0x01d4 22 internal intrxd1 imf and eire = 1 ile 0xffd2 0x01d2 23 internal inttxd1 imf and eire = 1 ile 0xffd0 0x01d0 24 internal inttc02 imf and eird = 1 ild 0xffce 0x01ce 25 internal inttc03 imf and eird = 1 ild 0xffcc 0x01cc 26 -- - - - - - -- - - - - -
page 46 3. interrupt control circuit TMP89FH46 ra003 note 4: do not set syscr3 to "0" in the serial prom mode. if an interrupt is generated with syscr3 ="0", the software refers to the vector area in the bootrom and the user cannot use it.
page 47 TMP89FH46 ra003 3.1 configuration figure 3-1 interrupt control circuit s a3 2 1 0 4 b q il 4 il 4 il 5 il 6 il 7 il 8 il 9 il 10 il 11 il 12 il 13 il 14 il 15 il 16 il 17 il 18 il 19 il 20 il 21 r s q imf r internal factor reset en intswi intundef intwdt interrupt source 4 interrupt source 5 interrupt source 6 interrupt source 7 interrupt source 8 interrupt source 9 interrupt source 10 interrupt source 11 interrupt source 12 interrupt source 13 interrupt source 14 interrupt source 15 interrupt source 16 interrupt source 17 interrupt source 18 interrupt source 19 interrupt source 20 decoder vector address generation priority encoder di instruction interrupt accept idle1/2,sleep1/2 mode clear request interrupt request imf (interrupt master enable flag) internal factor reset instruction to write ?0? to imf non-maskable interrupts maskable interrupts maskable interrupt priority change circuit ilprs1 ilprs2 ilprs3 ilprs4 s q il 3 r 5 4 3 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 data bus address bus il 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 [retn] instruction [ret1]1 instruction (only when the imf is set to ?1? before interrupt acceptance) (only when the imf is set to ?1? before interrupt acceptance) [ei] instruction instruction to write ?1? to imf il3 vector read signal il4 clear signal il4 vector read signal reading ilprs6 25 ef 25 to ef 4 il 25 interrupt source25 il 25 to il 4
page 48 3. interrupt control circuit 3.2 interrupt latches (il25 to il3) TMP89FH46 ra003 3.2 interrupt latches (il25 to il3) an interrupt latch is provided for each interrupt source, except for a software interrup t and an unde fined instruc- tion execution interrupt. when an interrupt request is generate d, the latch is set to "1", and the cpu is requested to accept the interrupt if its acceptance is en abled. the interrupt latch is cleared to "0" immediately af ter the interrupt is accepted. all interrupt latches are initialized to "0" during reset. the interrupt latches are located at addresses 0x0fe0, 0x0fe1, 0x0fe2, 0x0fe3 in sfr area. each latch can be cleared to "0" individual ly by an instruction. however, il2 and il3 interrupt latches cannot be cleared by instruc- tions. do not use any read-modify-wr ite instruction, such as a bit manipulatio n or operation instruction, because it may clear interrupt requests generated while the instruction is executed. interrupt latches cannot be set to "1" by using an instructi on. writing "1" to an interrupt latch is equivalent to deny- ing clearing of the interrupt latch, and not setting the interrupt latch. since interrupt latches can be read by instructions, the st atus of interrupt requests can be monitored by software. note: in the main program, before manipulating an interrupt latch (il), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1 " as required after operating the il (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0 " automatically and need not be cleared to "0" normally. how- ever, if using multiple interrupt in the interrupt servic e routine, manipulate the il before setting the imf to "1". example 1: clears interrupt latches di ; imf 0 ld (ill), 0y00111111 ; il7 to il6 0 ld (ilh), 0y11101000 ; il12, il10 to il8 0 ei ; imf 1 example 2: reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3: tests interrupt latches test (ill). 7 ; if il7=1 then jump jr f, sset ;
page 49 TMP89FH46 ra003 3.3 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction inte rrupt and watchdog interrupt). non-maskable interrupts are accepted regardless of the contents of the eir. the eir consists of the interrupt mast er enable flag (imf) and the individu al interrupt enable flags (ef). these registers are located at addresses 0x003a, 0x003b, 0x003c, 0x003d in the sfr area, and they can be read and writ- ten by instructions (including read-modify-write instruct ions such as bit manipulation or operation instructions). 3.3.1 interrupt ma ster enable flag (imf) the interrupt master enable flag (i mf) enables and disables the acceptance of all maskable interrupts. clear- ing the imf to "0" disables the acceptance of all maskab le interrupts. set ting the imf to "1" enables the accep- tance of the interrupts that are specified by the indivi dual interrupt enable flags. when an interrupt is accepted, the imf is stacked and then cleared to "0 ", which temporarily disables the subsequent maskable interrupts. after the interrupt serv ice routine is executed, the stacked data, which was the status before interrupt acceptance, reloaded on th e imf by return interrupt instruction [reti]/[retn]. the imf is located on bit 0 in eirl (address: 0x03a in sfr), and can be read an d written by instructions. the imf is normally set and cleared by [e i] and [di] instructions respectively. during reset, the imf is initial- ized to "0". 3.3.2 individual interrupt enable flags (ef25 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its in terrupt, and setting th e bit to "0" dis- ables acceptance. during reset, all the individual interrupt enable flags are initialized to "0" and no maskable interrupts are accepted until the flags are set to "1". note:in the main program, before manipulating the interrupt enable flag (ef), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the ef (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0 " automatically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt se rvice routine, manipulate the ef before setting the imf to "1". example: enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 0y1110100010100000 ; ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1
page 50 3. interrupt control circuit 3.3 interrupt enable register (eir) TMP89FH46 ra003 note 1: il3 is a read-only register. writing the register does not affect interrupt latch. note 2: in the main program, before manipulating an interrupt latch (il), be sure to clear the interrupt master enable flag (imf ) to "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the il (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0" autom atically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate the il before setting the imf to "1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 4: when a read instruction is executed on ill, bits 0 to 2 are read as "0". other unused bits are read as "0". interrupt latch (ill) ill 76543210 (0x0fe0) bit symbol il7 il6 il5 il4 il3 - - - read/writer/wr/wr/wr/wrrrr after reset00000000 function inttxd0 intrxd0 / intsio0 inttbt intwuc intwdt interrupt latch (ilh) ilh 76543210 (0x0fe1) bit symbol il15 il14 il13 il12 il11 il10 il9 il8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function intsbi0/ intsio0 inttca0 inttc01 inttc00 intrtc intadc intvltd int5 interrupt latch (ile) ile 76543210 (0x0fe2) bit symbol il23 il22 il21 il20 il19 il18 il17 il16 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function inttxd1 intrxd1 inttca1 int4 int3 int2 int1 int0 interrupt latch (ild) ild 76543210 (0x0fe3)bit symbol------il25il24 read/writerrrrrrr/wr/w after reset00000000 function inttc03 inttc02 il25 to il4 interrupt latch read write 0: 1: no interrupt request interrupt request clears the interrupt request (notes 2 and 3) does not clear the interrupt request (interrupt is not set by writing "1".) il3 0: 1: no interrupt request interrupt request -
page 51 TMP89FH46 ra003 note 1: do not set the imf and the interrupt enable flag (ef15 to ef4) to "1" at the same time. note 2: in the main program, before manipulating the interrupt enable flag (ef), be sure to clear the master enable flag (imf) t o "0" (disable interrupt by di instruction). then set the imf to "1" as required after operating the ef (enable interrupt by ei instruction) in the interrupt service routine, the imf becomes "0" autom atically and need not be cleared to "0" normally. however, if using multiple interrupt in the interrupt service routine, manipulate the ef before setting the imf to "1". note 3: when a read instruction is executed on eirl, bits 3 to 1 are read as "0". other unused bits are read as "0". interrupt enable register (eirl) eirl 76543210 (0x003a) bit symbol ef7 ef6 ef5 ef4 - - - imf read/write r/w r/w r/w r/w r r r r/w after reset00000000 function inttxd0 intrxd0 / intsio0 inttbt intwuc interrupt master en- able flag interrupt enable register (eirh) eirh 76543210 (0x003b) bit symbol ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function intsbi0/ intsio0 inttca0 inttc01 inttc00 intrtc intadc intvltd int5 interrupt enable register (eire) eire 76543210 (0x003c) bit symbol ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function inttxd1 intrxd1 inttca1 int4 int3 int2 int1 int0 interrupt enable register (eird) eird 76543210 (0x003d) bit symbol ------ef25ef24 read/writerrrrr/wr/wr/wr/w after reset00000000 function inttc03 inttc02 ef25 to ef4 individual interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts. enables the acceptance of all maskable interrupts.
page 52 3. interrupt control circuit 3.4 maskable interrupt priority change function TMP89FH46 ra003 3.4 maskable interrupt priority change function the priority of maskable interrupts (il4 to il25) can be changed to four levels, levels 0 to 3, regardless of the basic priorities 5 to 26. interrupt priorities can be changed by the interrupt priority cha nge control register (ilprs1 to ilprs6). to raise the interrupt priority, set the level to a larger number. to lower the interrupt priority, set the level to a smaller number. when different maskable interrupts are generate d simultaneously at the same level, the interrupt with higher basic priority is processed preferentially. fo r example, when the ilprs1 register is set to 0xc0 and interrupts il4 and il7 ar e generated at the same time, il7 is prefer entially processed (provided that ef4 and ef7 have been enabled). after reset is released, all maskable interrupts are set to priority level 0 (the lowest priority). note: in the main program, before manipulating the interrupt pr iority change control register (ilprs1 to 6), be sure to clear the master enable flag (imf) to "0" (disable interrupt by di instruction). set the imf to "1" as required after operating ilpr s1 to 6 (enable interrupt by ei instruction). in the interrupt service routine, the imf becomes "0 " automatically and need not be cleared to "0" normally. how- ever, if using multiple interrupt in the interrupt service r outine, manipulate ilprs1 to 6 before setting the imf to "1". interrupt priority cha nge control register 1 ilprs1 76543210 (0x0ff0) bit symbol il07p il06p il05p il04p read/write r/w r/w r/w r/w after reset00000000 il07p sets the interrupt priority of il7. 00: level 0 (lower priority) il06p sets the interrupt priority of il6. 01: level 1 il05p sets the interrupt priority of il5. 10: level 2 il04p sets the interrupt priority of il4. 11: level 3 (higher priority) interrupt priority cha nge control register 2 ilprs2 76543210 (0x0ff1) bit symbol il11p il10p il09p il08p read/write r/w r/w r/w r/w after reset00000000 il11p sets the interrupt priority of il11. 00: level 0 (lower priority) il10p sets the interrupt priority of il10. 01: level 1 il09p sets the interrupt priority of il9. 10: level 2 il08p sets the interrupt priority of il8. 11: level 3 (higher priority) interrupt priority cha nge control register 3 ilprs3 76543210 (0x0ff2) bit symbol il15p il14p il13p il12p read/write r/w r/w r/w r/w after reset00000000 il15p sets the interrupt priority of il15. 00: level 0 (lower priority) il14p sets the interrupt priority of il14. 01: level 1 il13p sets the interrupt priority of il13. 10: level 2 il12p sets the interrupt priority of il12. 11: level 3 (higher priority)
page 53 TMP89FH46 ra003 interrupt priority cha nge control register 4 ilprs4 76543210 (0x0ff3) bit symbol il19p il18p il17p il16p read/write r/w r/w r/w r/w after reset00000000 il19p sets the interrupt priority of il19. 00: level 0 (lower priority) il18p sets the interrupt priority of il18. 01: level 1 il17p sets the interrupt priority of il17. 10: level 2 il16p sets the interrupt priority of il16. 11: level 3 (higher priority) interrupt priority cha nge control register 5 ilprs5 76543210 (0x0ff4) bit symbol il23p il22p il21p il20p read/write r/w r/w r/w r/w after reset00000000 il23p sets the interrupt priority of il23. 00: level 0 (lower priority) il22p sets the interrupt priority of il22. 01: level 1 il21p sets the interrupt priority of il21. 10: level 2 il20p sets the interrupt priority of il20. 11: level 3 (higher priority) interrupt priority cha nge control register 6 ilprs6 76543210 (0x0ff5) bit symbol - - il25p il24p read/write r/w r/w r/w r/w after reset00000000 - - 00: level 0 (lower priority) - - 01: level 1 il25p sets the interrupt priority of il25. 10: level 2 il24p sets the interrupt priority of il24. 11: level 3 (higher priority)
page 54 3. interrupt control circuit 3.5 interrupt sequence TMP89FH46 ra003 3.5 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruction. in terrupt acceptance sequence requires 8-mach ine cycles after the completion of the current instruction. the interrupt service task terminat es upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [r etn] (for non-maskable interrupts). 3.5.1 initial setting using an interrupt requires specifying an sp (stack pointer) for it in advance. the sp is a 16-bit register pointing at the start address of a stack. the sp is post-decremented when a subroutine call or a push instruction is executed or when an interrupt request is accepted. it is pre-incremented when a return or pop instruction is executed. therefore, the stack become s deeper toward lower stack location addresses. be sure to reserve a stack area having an appropriate size based on the sp setting. the sp is initialized to 00ffh after a reset. if you need to change the sp, do so right after a reset or when the interrupt master enab le flag (imf) is ? 0 ? . 3.5.2 interrupt acceptance processing interrupt acceptance processing is packaged as follows. 1. the interrupt master enable flag (imf) is cleared to ? 0 ? in order to disable the acceptance of any fol- lowing interrupt. 2. the interrupt latch (il) for the in terrupt source accepted is cleared to ? 0 ? . 3. the contents of the program counter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer ( sp) is decremented by 3. 4. the entry address (interrupt v ector) of the corresponding interr upt service program, loaded on the vector table, is transfer red to the program counter. 5. the instruction stored at the entry address of the interrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of register bank and imf are also saved. example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program figure 3-2 vector tabl e address and entry address example :sp setting ld sp, 023fh ; sp = 023fh ld sp, sp+04h ; sp = sp + 04h add sp, 0010h ; sp = sp + 0010h 0x03 0xfff4 0xfff5 vector table address 0xd2 0x0f 0xd203 0xd204 vector table address 0x06
page 55 TMP89FH46 ra003 a maskable interrupt is not accepted until the imf is set to ? 1 ? even if the maskable interrupt is requested in the interrupt service routine. in order to utilize nested interrupt service, the imf must be set to ? 1 ? in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the in dividual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ? 1 ? . as for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests. 3.5.3 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automatically save d on the stack, but the general purpose registers are not. these registers must be saved by software if necessary. when multiple in terrupt services are nested, it is also necessary to avoid using the same data memory area for saving register s. the following methods are used to save/restore the general-purpose registers. 3.5.3.1 using push and pop instructions to save only a specific register, push and pop instructions are available. figure 3-3 saving/restor ing general-purpose registers example :using push and pop instructions pintxx push wa ; save wa register interrupt processing pop wa ; restore wa register reti ; return at acceptance of an interrupt psw sp pc l pc h address (example) b-4 b-3 b-2 b-1 b psw sp pc l pc h at execution of push instruction at execution of pop instruction sp at execution of an reti instruction psw w a sp pc l pc h
page 56 3. interrupt control circuit 3.5 interrupt sequence TMP89FH46 ra003 3.5.3.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.5.3.3 using a register bank to sa ve/restore general-purpose registers in non-multiple interrupt handling, the register bank function can be used to save/restore the general- purpose registers at a time. the register bank functi on saves (switches) the general-purpose registers by executing a register bank manipulation instruction (suc h as ld rbs,1) at the beginning of an interrupt service task. it is unnecessary to re-execute the regi ster bank manipulation instruction at the end of the interrupt service task because execu ting the reti instruction makes a re turn automatically to the register bank that was being used by the main ta sk according to the content of the psw. note: two register banks (bank0 and bank1) are avail able. each bank consists of 8-bit general-purpose registers (w, a, b, c, d, e, h, and l) and 16-bit general-purpose registers (ix and iy). example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register interrupt processing ld a, (gsava) ; restore a register reti ; return example :saving/restoring registers, using an instruction for transfer with data memory (with the main task using the regis- ter bank bank0) pintxx: ld rbs, 1 ; switches to the register bank bank1 interrupt processing reti ; return (makes a return automatically to bank0 that was being used by the main task when the psw is restored) main task interrupt acceptance interrupt service task saving registers restoring registers interrupt return
page 57 TMP89FH46 ra003 figure 3-5 saving/restoring general-purpose r egisters under interrupt processing 3.5.4 interrupt return interrupt return instructions [reti]/[retn] perform as follows. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (register bank) are restored from tha stack. 2. stack pointer (sp) is incremented by 3. main task interrupt service task interrupt acceptance interrupt return switching occurs to the register bank bank1. a return is made automatically to the register bank bank0. ld (rbs),1 the register bank bank0 is in use.
page 58 3. interrupt control circuit 3.6 software interrupt (intsw) TMP89FH46 ra003 3.6 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is the top-priority interrupt). use the swi instruction only for address error detection or for debugging described below. 3.6.1 address error detection 0xff is read if for some cause such as noise the cp u attempts to fetch an instruction from a non-existent memory address. code 0xff is an sw i instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be furthe r expanded by writing 0xff to unused areas in the pro- gram memory. 3.6.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.7 undefined instruct ion interrupt (intundef) when the cpu tries to fetch and execute an instruction that is not defined, intundef is generated and starts the interrupt processing. intundef is accepte d even if another non-maskable interrupt is in process. the current pro- cess is discontinued and the intundef interrupt process starts soon after it is requested. note: the undefined instruction interrupt (intundef) forces the cpu to jump into the interrupt vector address, as soft- ware interrupt (swi) does.
page 59 TMP89FH46 ra000 4. external interrupt control circuit external interrupts detects the change of the input signal and generates an interrupt request. noise can be removed by the built-in digital noise canceller. 4.1 configuration the external interrupt control circuit co nsists of a noise canceller, an edge de tection circuit, a level detection cir- cuit and an interrupt signal generation circuit. externally input signals are in put to the rising edge or fa lling edge or level detection ci rcuit for each external inter- rupt, after noise is removed by the noise canceller. figure 4-1 external interrupts 0/5 figure 4-2 external interrupts 1/2/3 figure 4-3 external interrupt 4 noise canceller intj pin fs/4 fcgck intj inter r request j=0,5 falling edge detection circuit interrupt request signal generation circuit noise canceller 3 4 2 1 fcgck fs/4 inti pin intilvl inties inti interrupt request i=1 to 3 abcd s z rising edge detection circuit interrupt request signal generation circuit falling edge detection circuit eintcri noise canceller 3 4 2 1 fcgck int4 pin int4lvl int4es int4 interrupt request abcd s z rising edge detection circuit interrupt request signal generation circuit level detection circuit falling edge detection circuit eintcr4 fs
page 60 4. external interr upt control circuit 4.2 control TMP89FH46 ra000 4.2 control external interrupts are contro lled by the following registers: note 1: clearing intxen(x=0 to 5) to "0" stops the clock supply to the external interrupts. this invalidates the data written in the control register for each external interrupt. when using the external interrupts, set intxen to "1" and then write data into the control register for each external interrupt. note 2: interrupt request signals may be generated when intx en is changed. before changing intxen, clear the corre- sponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/ 2 or idle1/2, wait 2/fcgck+3/fspl [s] after th e operation mode is changed and clear the interrupt latch. note 3: bits 7 and 6 of poffset3 are read as "0". note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to di sable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1 , wait 12/fs [s] after the operation mode is changed and low power consumption register 3 poffcr3 76543210 (0x0f77) bit symbol - - int5en int4en int3en int2en int1en int0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 int5en int5 control 0 1 disable enable int4en int4 control 0 1 disable enable int3en int3 control 0 1 disable enable int2en int2 control 0 1 disable enable int1en int1 control 0 1 disable enable int0en int0 control 0 1 disable enable external interrupt control register 1 eintcr1 (0x0fd8) 76543210 bit symbol - - - int1lvl int1es int1nc read/writerrrr r/w r/w after reset0000 0 0 ini1lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 1 0 : 1 : initial state or signal level "l" signal level "h" int1es selects the interrupt request gener- ating condition for external interrupt 1 00 : 01 : 10 : 11 : an interrupt request is generated at the rising edge of the noise canceller pass signal an interrupt request is generated at the falling edge of the noise canceller pass signal an interrupt request is generated at both edges of the noise canceller pass signal reserved int1nc sets the noise canceller sampling interval for external interrupt 1 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz]
page 61 TMP89FH46 ra000 clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr1 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generatio n of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr1 are read as "0". note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to di sable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1 , wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr2 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generatio n of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr2 are read as "0". external interrupt control register 2 eintcr1 (0x0fd9) 76543210 bit symbol - - - int2lvl int2es int2nc read/writerrrr r/w r/w after reset0000 0 0 ini2lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 2 0 : 1 : initial state or signal level "l" signal level "h" int2es selects the interrupt request gener- ating condition for external interrupt 2 00 : 01 : 10 : 11 : an interrupt request is generated at the rising edge of the noise canceller pass signal an interrupt request is generated at the falling edge of the noise canceller pass signal an interrupt request is generated at both edges of the noise canceller pass signal reserved int2nc sets the noise canceller sampling interval for external interrupt 2 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] external interrupt control register 3 eintcr3 (0x0fda) 76543210 bit symbol - - - int3lvl int3es int3nc read/writerrrr r/w r/w after reset0000 0 0
page 62 4. external interr upt control circuit 4.2 control TMP89FH46 ra000 note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to di sable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1 , wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr3 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generatio n of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 4: bits 7 to 5 of eintcr3 are read as "0". note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: interrupt requests may be generated during transition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to di sable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1 , wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. note 3: interrupt requests may be generated when eintcr4 is changed. before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generatio n of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the inter- rupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. ini3lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 3 0 : 1 : initial state or signal level "l" signal level "h" int3es selects the interrupt request gener- ating condition for external interrupt 3 00 : 01 : 10 : 11 : an interrupt request is generated at the rising edge of the noise canceller pass signal an interrupt request is generated at the falling edge of the noise canceller pass signal an interrupt request is generated at both edges of the noise canceller pass signal reserved int3nc sets the noise canceller sampling interval for external interrupt 3 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz] external interrupt control register 4 eintcr4 (0x0fdb) 76543210 bit symbol - - - int4lvl int4es int4nc read/writerrrr r/w r/w after reset0000 0 0 ini4lvl noise canceller pass signal level when the interrupt request signal is generated for external interrupt 4 0 : 1 : initial state or signal level "l" signal level "h" int4es selects the interrupt request gener- ating condition for external interrupt 4 00 : 01 : 10 : 11 : an interrupt request is generated at the rising edge of the noise canceller pass signal an interrupt request is generated at the falling edge of the noise canceller pass signal an interrupt request is generated at both edges of the noise canceller pass signal an interrupt request is generated at "h" of the noise canceller pass signal int4nc sets the noise canceller sampling interval for external interrupt 4 normal1/2, idle1/2 slow1/2, sleep1 00 : 01 : 10 : 11 : fcgck [hz] fcgck / 2 2 [hz] fcgck / 2 3 [hz] fcgck / 2 4 [hz] 00 : 01 : 10 : 11 : fs/4 [hz] fs/4 [hz] fs/4 [hz] fs/4 [hz]
page 63 TMP89FH46 ra000 note 4: the contents of eintcrx are updat ed each time an interrupt request signal is generated. note 5: bits 7 to 5 of eintcr4 are read as "0". 4.3 function the condition for generating interrupt request signals and the noise cancel time can be set for external interrupts 1 to 4. the condition for generating interrupt request signals and the noise cancel time are fixed for external interrupts 0 and 5. note 1: fcgck, gear clock [hz]; fs, low frequen cy clock [hz]; fspl, sampling interval [hz] 4.3.1 low power c onsumption function external interrupts have a function that saves power by using the low power consumption register (poffcr3) when th ey are not used. setting poffcr3 to "0" stops (disables) the basic clock for external interrupts and helps save power. note that this makes external interrupts una vailable. setting poffcr3 to "1" supplies (enables) the basic clock for external interrup ts and makes external interrupts available. after reset, poffcr3 is initialized to "0 " and external interrupts become unavailable. when using the external interrupt function for the first time, be sure to set poffcr3 to "1" in the initial setting of software (before operating the external interrupt control registers). note:interrupt request signals may be generated when intx en is changed. before changing intxen, clear the cor- responding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed from normal1/2 or idle1/2 to slow1/2 or sl eep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the oper ation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/fcgck+3/fspl [s] af ter the operation mode is changed and clear the interrupt latch. table 4-1 external interrupts source pin enable conditions interrupt request signal generated at external interrupt pin input signal width and noise removal normal1/2, idle1/2 slow1/2, sleep1 int0 int0 imf and ef16 = 1 falling edge less than 1/fcgck: noise more than 1/fcgck and less than 2/ fcgck: indeterminate more than 2/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int1 int1 imf and ef17 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int2 int2 imf and ef18 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int3 int3 imf and ef19 = 1 falling edge rising edge both edges less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int4 int4 imf and ef20 = 1 falling edge rising edge both edges "h" level less than 2/fspl: noise more than 2/fspl and less than 3/fspl+1/ fcgck: indeterminate more than 3/fspl+1/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal int5 int5 imf and ef8 = 1 falling edge less than 1/fcgck: noise more than 1/fcgck and less than 2/ fcgck: indeterminate more than 2/fcgck: signal less than 4/fs: noise more than 4/fs and less than 8/fs: inde- terminate more than 8/fs: signal
page 64 4. external interr upt control circuit 4.3 function TMP89FH46 ra000 4.3.2 external interrupt 0 external interrupt 0 detects the falling edge of the int0 pin and generates interrupt request signals. in normal1/2 or idle1/2 mode, pulses of less than 1/ fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. in slow/sleep mode, pulses of less than 4/fs are remo ved as noise and pulses of 8/fs or more are recog- nized as signals. 4.3.3 external interrupts 1/2/3 external interrupts 1/2/3 detect the falling edge, the rising edge or both edges of the int1, int2 and int3 pins and generate interrupt request signals. 4.3.3.1 interrupt request signal gener ating condition detection function select interrupt request signal generating conditions at eintcrx for external interrupts 1/2/ 3. note: x=1 to 3 4.3.3.2 a noise canceller pass signal monito ring function when interrupt request signals are generated the level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using eintcrx. when both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading eintcrx. table 4-2 selection of interrupt request generation edge eintcrx detected at 00 rising edge 01 falling edge 10 both edges 11 reserved signal that has passed through the noise canceller inti pin interrupt request signal (detected at the falling edge) interrupt request signal (detected at the rising edge) interrupt request signal (detected at both edges) int lvl int lvl int lvl
page 65 TMP89FH46 ra000 note: the contents of eintcrx are updated each time an interrupt request signal is generated. figure 4-4 interrupt request ge neration and eintcrx 4.3.3.3 noise cancel time selection function in normal1/2 or idle1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at eint crx. if the same level is det ected three consecuti ve times, the signal is recognized as a signal. if not, the signal is removed as noise. figure 4-5 noise cancel operation in slow1/2 or sleep1 mode, a signal is sampled by the low frequency clock divided by 4. if the same level is detected twice consecutively, the signal is recognized as a signal. in idle0, sleep0 or stop mode, the noise cance ller sampling operation is stopped and an external interrupts are unavailable. when operation returns to normal1/2, idle1/2, slow1/2 or sleep1 mode, sampling operation restarts. note 1: if noise is input consecutivel y during sampling of external interr upt pins, the noise cancel function does not work properly. set eintcrx accord ing to the cycle of externally input noise. note 2: if an external interrupt pin is used as an output por t, the input signal to the port is fixed to "l" when the mode is switched to the output mode, and thus an in terrupt request occurs. to use the pin as an out- put port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. note 3: interrupt requests may be generated during tr ansition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed fr om normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.4 external interrupt 4 external interrupt 4 detects the falling edge, the rising edge, both edges or "h" level of the int4 pin and gen- erates interrupt request signals. 4.3.4.1 interrupt request signal gener ating condition detection function select an interrupt request signal generating cond ition at eintcr4 for external interrupt 4. table 4-3 noise canceller sampling lock eintcrx sampling interval 00 fcgck 01 fcgck/2 2 10 fcgck/2 3 11 fcgck/2 4 inti pin signal after noise removal i=1 to 3 noise signal
page 66 4. external interr upt control circuit 4.3 function TMP89FH46 ra000 4.3.4.2 a noise canceller pass signal monito ring function when interrupt request signals are generated the level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using eintcr4. when both edges are selected as detection edges, the edge where an interrupt is generated can be detected by reading eintcr4. figure 4-6 interrupt request generation and eintcr4 4.3.4.3 noise cancel time selection function in normal1/2 or idle1/2 mode, a signal that has been sampled by fcgck is sampled at the sampling interval selected at eint crx. if the same level is det ected three consecuti ve times, the signal is recognized as a signal. if not, the signal is removed as noise. table 4-4 selection of interrupt request generation edge eintcr4 detected at 00 rising edge 01 falling edge 10 both edges 11 "h" level interrupt int4 pin interrupt request signal (detected at the falling edge) interrupt request signal (detected at the rising edge) interrupt request signal (detected at both edges) int4lvl int4lvl int4lvl int4lvl interrupt request signal (level detection) signal that has passed through the noise canceller
page 67 TMP89FH46 ra000 figure 4-7 noise cancel operation in slow1/2 or sleep1 mode, a signal is sampled by the low frequency clock divided by 4. if the same level is detected twice consecutively, the signal is recognized as a signal. in idle0, sleep0 or stop mode, the noise cance ller sampling operation is stopped and an external interrupts are unavailable. when operation returns to normal1/2, idle1/2, slow1/2 or sleep1 mode, sampling operation restarts. note 1: when noise is input consecut ively during sampling exte rnal interrupt pins, the noise cancel function does not work properly. set eintcrx accord ing to the cycle of externally input noise. note 2: when an external interrupt pin is used as an out put port, the input signal to the port is fixed to "l" when the mode is switched to the output mode, and thus an interrupt request occurs. to use the pin as an output port, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. note 3: interrupt requests may be generated during tr ansition of the operation mode. before changing the operation mode, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. when the operation mode is changed fr om normal1/2 or idle1/2 to slow1/2 or sleep1, wait 12/fs [s] after the operation mode is changed and clear the interrupt latch. and when the operation mode is changed from slow1/2 or sleep1 to normal1/2 or idle1/2, wait 2/ fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch. 4.3.5 external interrupt 5 external interrupt 5 detects the falling edge of the int5 pin and generates interrupt request signals. in normal1/2 or idle1/2 mode, pulses of less than 1/ fcgck are removed as noise and pulses of 2/fcgck or more are recognized as signals. in slow/sleep mode, pulses of less than 4/fs are remo ved as noise and pulses of 8/fs or more are recog- nized as signals. table 4-5 noise canceller sampling lock eintcr4 sampling interval 00 fcgck 01 fcgck/2 2 10 fcgck/2 3 11 fcgck/2 4 int4 pin signal after noise removal noise signal
page 68 4. external interr upt control circuit 4.3 function TMP89FH46 ra000
page 69 TMP89FH46 ra000 5. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signals used for detecting malfunctio ns can be programmed as watchdog interrupt request sig- nals or watchdog timer reset signals. note: care must be taken in system designing since the watchdog timer may not fulfill its func tions due to disturbing noise and other effects. 5.1 configuration figure 5-1 watchdog timer configuration 5.2 control the watchdog timer is controlled by the watchdog timer control register (wdctr), the watchdog timer control code register (wdcdr), the watchdog timer counter m onitor (wdcnt) and the watchdog timer status (wdst). the watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished. watchdog timer control register wdctr (0x0fd4) 76543210 bit symbol - - wdten wdtw wdtt wdtout read/write r r r/w r/w r/w r/w after reset10100110 source clock watchdog timer interrupt requestl cpu/peripheral circuits reset fcgck/2 10 or fs/2 3 fcgck/2 12 or fs/2 5 fcgck/2 14 or fs/2 7 fcgck/2 16 or fs/2 9 watchdog timer reset signal 2 8 wdctr wdcdr wdcnt wdst overflow clear 2 3 4 6 7 8 5 control code decoder disable control circuit disable code (0xb1) clear code (0x4e) n e t d w w t d w t t d w t u o t d w t s t d w 1 t s t n i w 2 t s t n i w clear time control circuit 8-bit up counter interrupt request/reset signal control circuit r o t c e l e s
page 70 5. watchdog timer (wdt) 5.2 control TMP89FH46 ra000 note 1: fcgck, gear clock [h z]; fs, low frequency clock [hz] note 2: wdctr, wdctr and wdctr cannot be changed when wdctr is "1". if wdctr is "1", clear wdctr to "0" and write the disable c ode (0xb1) into wdcdr to disable the watchdog timer operation. note that wdctr, wdctr and wdctr can be changed at the same time as setting wdctr to "1". note 3: bit 7 and bit 6 of wdctr are read as "1" and "0" respectively. note: wdcdr is a write-only register and must not be accessed by us ing a read-modify-write instruction, such as a bit operation. wdten enables/disables the watchdog timer operation. 0 : 1 : disable enable wdtw sets the clear time of the 8-bit up counter. 00 : 01 : 10 : 11 : the 8-bit up counter is cleared by wr iting the clear code at any point within the overflow time of the 8-bit up counter. a watchdog timer interrupt request is generated by writing the clear code at a point within the first quarter of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code after the first quarter of the overflow time has elapsed. a watchdog timer interrupt request is generated by writing the clear code at a point within the first half of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writ ing the clear code after the first half of the overflow time has elapsed. a watchdog timer interrupt request is generated by writing the clear code at a point within the first three quarters of the overflow time of the 8-bit up counter. the 8-bit up counter is cleared by writing the clear code after the first three quarters of the overflow time have elapsed. wdtt sets the overflow time of the 8-bit up counter. normal mode slow mode dv9ck=0 dv9ck=1 00 : 2 18 /fcgck 2 11 /fs 2 11 /fs 01: 2 20/ fcgck 2 13 /fs 2 13 /fs 10: 2 22 /fcgck 2 15 /fs 2 15 /fs 11: 2 24 /fcgck 2 17 /fs 2 17 /fs wdtout selects an overflow detection signal of the 8-bit up counter. 0 : 1 : watchdog timer interrupt request signal watchdog timer reset request signal watchdog timer control code register wdcdr (0x0fd5) 76543210 bit symbol wdtcr2 read/write w after reset00000000 wdtcr2 writes watchdog timer control codes. 0x4e : 0xb1 : others : clears the watchdog timer. (clear code) disables the watchdog timer operation and clears the 8-bit up counter when wdctr is "0". (disable code) invalid 8-bit up counter monitor wdcnt (0x0fd6) 76543210 bit symbol wdcnt read/write r after reset00000000 wdcnt monitors the count value of the 8-bit up counter the count value of the 8-bit up counter is read.
page 71 TMP89FH46 ra000 note 1: wdst and wdst are cleared to "0" by reading wdst. note 2: values after reset are read from bits 7 to 3 of wdst. 5.3 functions the watchdog timer can detect the cpu malfunctions and deadlock by detecting the overflow of the 8-bit up counter and detecting releasing of the 8-bit up counter outside the clear time. the watchdog timer stoppage and other abnormalities can be detected by reading the count value of the 8-bit up counter at random times and comparing the value to the last read value. 5.3.1 setting of enabling/disabl ing the watchdog timer operation setting wdctr to "1" enables the watchdog timer operation, and the 8-bit up counter starts counting the source clock. wdctr is initialized to "1" after the warm-up operation that follows reset is released. this means that the watchdog timer is enabled. to disable the watchdog timer operation, clear wdctr to "0" and write 0xb1 into wdcdr. disabling the watchdog timer operation clears the 8-bit up counter to "0". note:if the overflow of the 8-bit up counter occurs at t he same time as 0xb1 (disable code) is written into wdcdr with wdctr set at "1", the watchdog timer operation is disabled prefer entially and the overflow detection is not executed. to re-enable the watchdog timer operation, set wdctr< wdten> to "1". there is no need to write a con- trol code into wdcdr. figure 5-2 wdctr se t timing and overflow time watchdog timer status wdst (0x0fd7) 76543210 bit symbol-----wintst2wintst1wdtst read/writerrrrrrrr after reset01011001 wintst2 watchdog timer interrupt request signal factor status 2 0 : 1 : no watchdog timer interrupt request signal has occurred. a watchdog timer interrupt request signal has occurred due to the over- flow of the 8-bit up counter. wintst1 watchdog timer interrupt request signal factor status 1 0 : 1 : no watchdog timer interrupt request signal has occurred. a watchdog timer interrupt request signal has occurred due to releasing of the 8-bit up counter outside the clear time. wdtst watchdog timer operating state sta- tus 0 : 1 : operation disabled operation enabled 8-bit up counter value watchdog timer source clock wdctr 00h 01h ffh wdctr interrupt request signal 00h overflow time overflow time 1 clock (max.)
page 72 5. watchdog timer (wdt) 5.3 functions TMP89FH46 ra000 note:the 8-bit up counter source clock operates out of synchronization with wdctr. therefore, the first overflow time of the 8-bit up counter after wdctr is set to "1" may get shorter by a maximum of 1 source clock. the 8-bit up counter must be cleared within the period of the overflow time minus 1 source clock cycle. 5.3.2 setting the clear time of the 8-bit up counter wdctr sets the clear time of the 8-bit up counter. when wdctr is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the 8-bit up counter can be cleared at any time. when wdctr is not "00", the clear time is fixed to only a certain period within the overflow time of the 8-bit up counter. if the operation for releas ing the 8-bit up counter is attempted outside the clear time, a watchdog timer interrupt request signal occurs. at this time, the watchdog timer is not cleared but continues counting. if the 8-bit up counter is not cleared within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs due to the overflow, depending on the wdctr setting. figure 5-3 wdctr and t he 8-bit up counter clear time 5.3.3 setting the ov erflow time of t he 8-bit up counter wdctr sets the overflow time of the 8-bit up counter. when the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs, depending on the wdctr setting. if the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog counter continues counting, even after the overflow has occurred. the watchdog timer temporarily stops counting up in the stop mode (including warm-up) or in the idle/ sleep mode, and restarts counting up after the stop/idl e/sleep mode is released. to prevent the 8-bit up counter from overflowing immediately after the stop/i dle/sleep mode is released, it is recommended to clear the 8-bit up counter before the operation mode is changed. table 5-1 watchdog timer overflow time (fcgck=10.0 mhz; fs=32.768 khz) wdtt watchdog timer overflow time [s] normal mode slow mode dv9ck = 0 dv9ck = 1 00 26.21 m 62.50 m 62.50 m 01 104.86 m 250.00 m 250.00 m 10 419.43 m 1.000 1.000 11 1.678 4.000 4.000 when wdctr is 00 8-bit up counter value when wdctr is 01 when wdctr is 10 when wdctr is 11 00h 01h 3fh 40h 7fh 80h bfh c0h ffh 00h ffh clear time clear time outside the clear time clear time outside the clear time clear time outside the clear time
page 73 TMP89FH46 ra000 note:the 8-bit up counter source clock operates out of synchronization with wdctr. therefore, the first overflow time of the 8-bit up counter after wdctr is set to "1" may get shorter by a maximum of 1 source clock. the 8-bit up counter mu st be cleared within a period of the ov erflow time minus 1 source clock cycle. 5.3.4 setting an overflow detecti on signal of the 8-bit up counter wdctr selects a signal to be generated when the overflow of the 8-bit up counter is detected. 1. when the watchdog timer interrupt request sign al is selected (when wdctr is "0") releasing wdctr to "0" causes a watchdog timer interrupt request signal to occur when the 8-bit up counter overflows. a watchdog timer interrupt is a non-maskable interrupt, and it s request is always accepted, regard- less of the interrupt master enable flag (imf) setting. note: when a watchdog timer interrupt is generated while another interrupt, including a watchdog timer interrupt, is already accepted, the new watchdog timer interrupt is processed imm ediately and the preceding interrupt is put on hold. therefore, if watchdog timer interrupts are generated cont inuously without execution of the retn instruction, too many levels of nest- ing may cause a malfunction of the microcontroller. 2. when the watchdog timer reset request signal is selected (when wdctr is "1") setting wdctr to "1" causes a watchdog timer reset request signal to occur when the 8-bit up counter overflows. this watchdog timer reset request signal resets the TMP89FH46 and starts the warm-up operation. 5.3.5 writing the watchdog timer control codes the watchdog timer control codes are written into wdcdr. by writing 0x4e (clear code) into wdcdr, the 8-bit up counter is cleared to "0" and continues counting the source clock. when wdctr is "0", writing 0xb1 (disable code) into wdcdr disables the watchdog timer operation. to prevent the 8-bit up count er from overflowing, clear the 8-bit up counter in a period shorter than the over- flow time of the 8-bit up counter and within the clear time. by designing the program so that no overflow will occur, the program malfunctions and deadlock can be detected through interrupts generated by watchdog timer interrupt request signals. by applying a reset to the microcomputer using wa tchdog timer reset request signals, the cpu can be restored from malfunctions and deadlock. note:if the overflow of the 8-bit up counter and writing of 0x4e (clear code) into wdcdr occur simultaneously, the 8-bit up counter is cleared preferentially and the overfl ow detection is not executed. example: when wdctr is "0", set t he watchdog timer detection time to 2 20 /fcgck [s], set the counter clear time to half of the overflow time, and allow a watchdog ti mer reset request signal to occur if a malfunction is detected. ld (wdctr), 0y00110011 ; wdtw 10, wdtt 01, wdtout 1 clear the 8-bit up counter at a point after half of its overflow time and within a peri- od of the overflow time minus 1 source clock cycle. ld (wdcdr), 0x4e ; clear the 8-bit up counter clear the 8-bit up counter at a point after half of its overflow time and within a peri- od of the overflow time minus 1 source clock cycle. ld (wdcdr), 0x4e ; clear the 8-bit up counter
page 74 5. watchdog timer (wdt) 5.3 functions TMP89FH46 ra000 5.3.6 reading t he 8-bit up counter the counter value of the 8-bit up coun ter can be read by reading wdcnt. the stoppage of the 8-bit up counter can be detected by reading wdcnt at random times and comparing the value to the last read value. 5.3.7 reading the watchdog timer status the watchdog timer status can be read at wdst. wdst is set to "1" when the watchdog timer op eration is enabled, and it is cleared to "0" when the watchdog timer operation is disabled. wdst is set to "1" when a watchdog timer in terrupt request signal occurs due to the overflow of the 8-bit up counter. wdst is set to "1" when a watchdog timer interrupt request signal occurs due to the operation for releasing the 8-bit up co unter outside the clear time. you can know which factor has caused a watchdog timer interrupt request signal by reading wdst and wdst in the watchdog timer interrupt service routine. wdst and wdst are cleared to "0" when wdst is read. if wdst is read at the same time as the condition for turning wdst or wdst to "1" is satisfied, wdst or wdst is set to "1", rather than being cleared. figure 5-4 changes in the watchdog timer status 8-bit up counter value when wdctr is 10 writing of 4eh (clear code) wdst watchdog timer interrupt request signal interrupt request signal generated by clearing the 8-bit up counter outside the clear time interrupt request signal generated by the overflow of the 8-bit up counter 00h 01h 3fh 40h 01h 7fh 80h bfh c0h ffh 00h ffh clear time outside the clear time reading of wdst wdst
page 75 TMP89FH46 ra000 6. power-on reset circuit the power-on reset circuit generates a reset when the power is turned on. when the supply voltage is lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated. 6.1 configuration the power-on reset circuit consists of a refere nce voltage generation circuit and a comparator. the supply voltage divided by ladder resistor is compared with the voltage generated by the reference voltage gen- eration circuit by the comparator. figure 6-1 power- on reset circuit 6.2 function when power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the power-on reset circuit, a power-on reset signal is generated and if it is higher than the releasing voltage of the power- on reset circuit, a power-on reset signal is released. when power supply voltage goes down, if the supply voltage is equal to or lower than the detecting voltage of the power-on reset circuit, a power-on reset signal is generated. until the power-on reset signal is generate d, a warm-up circuit and a cpu is reset. when the power-on reset signal is rel eased, the warm-up circuit is activated . the reset of the cpu and peripheral circuits is released after the warm-up tim e that follows reset release has elapsed. increase the supply voltage into the operating range during the period from detection of the power-on reset release voltage until the end of the warm-up time that follows re set release. if the supply volta ge has not reached the operat- ing range by the end of the warm-up time that follows reset release, the TMP89FH46 cannot operate properly. vdd power-on reset signal comparator reference voltage generation circuit
page 76 6. power-on reset circuit 6.2 function TMP89FH46 ra000 note 1: the power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (vdd). refer to the electrical characteri stics and take them into consideration when designing equipment. note 2: for the ac timing, refer to the electrical characteristics. figure 6-2 oper ation timing of power-on reset supply voltage (vdd) vproff operating voltage vpron vdd ppw pron warm-up counter start pwup proff power-on reset signal warm-up counter clock cpu/peripheral circuits reset signal
page 77 TMP89FH46 ra002 7. voltage detection circuit the voltage detection circuit detects any decrease in the supply voltage and generates voltage detection interrupt request signals and voltage detection reset signals. note: the voltage detection circuit may operate improperly, depen ding on fluctuations in the supply voltage (vdd). refer to the electrical characterist ics and take them into consideration when designing equipment. 7.1 configuration the voltage detection circuit consists of a reference volta ge generation circuit, a detection voltage level selection circuit, a comparator and control registers. the supply voltage (vdd) is divided by the ladder resistor and input to the detection voltage selection circuit. a voltage is selected in the detection voltage selection circuit, depending on the detection voltage (vdxlvl), and compared to the reference voltage in the comparator. when the supply voltag e (vdd) becomes lower than the detec- tion voltage (vdxlvl), a voltage detection interrupt request signal or a voltage detection reset signal is generated. either the voltage detection interrupt request signal or th e voltage detection reset signal can be selected by pro- gramming the software. figure 7-1 voltage detection circuit 7.2 control the voltage detection circuit is controlled by voltage detection control registers 1,2 and 3. voltage detection control register 1 vdcr1 (0x0fc6) 76543210 bit symbol vd2f vd2sf vd2lvl vd1f vd1sf vd1lvl read/write r/w read only r/w r/w read only r/w after reset00000000 vdd n e 1 d v d o m 1 d v n e 2 d v d o m 2 d v l v l 2 d v l v l 1 d v f s 1 d v f 1 d v f s 2 d v f 2 d v vdcr2 vdcr1 f/f voltage detection reset signal 1 voltage detection reset signal 2 voltage detection interrupt request signal f/f voltage detection stop mode release signal 1 e g a t l o v n o i t c e t e d t i u c r i c n o i t c e l e s l e v e l 2 e g a t l o v n o i t c e t e d t i u c r i c n o i t c e l e s l e v e l reference voltage generation circuit interrupt request signal generation circuit
page 78 7. voltage detection circuit 7.3 function TMP89FH46 ra002 note 1: vdcr1 is initialized by a power -on reset or an external reset input. note 2: when vd2f or vd1f is cleared by the software and is se t due to voltage detection at the same time, the setting due to voltage detection is given priority. note 3: vd2f and vd1f cannot be programmed to "1" by the software. note 1: vdcr2 is initialized by a power -on reset or an external reset input. note 2: bits 7 and 6 of vdcr2 are read as "0". 7.3 function two detection voltages (vdxlvl, x=1-2) can be set in th e voltage detection circuit. for each voltage, enabling/ disabling the voltage detection and the operation to be executed when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl) can be programmed. vd2f voltage detection 2 flag (retains the state when vdd page 79 TMP89FH46 ra002 7.3.1 enabling/disabling th e voltage detection operation setting vdcr2 to "1" enables the voltage detection operation. setting it to "0" disables the oper- ation. vdcr2 is cleared to "0" immedi ately after a power-on reset or a reset by an external reset input is released. note:when the supply voltage (vdd) is lower than the detection voltage (vdxlvl), setting vdcr2 to "1" generates a voltage detection interrupt request signal or a voltage detection reset signal at the time. 7.3.2 selecting the voltage detection operation mode if the voltage detection operation mode is set to generate voltage detection interrupt request signals (vdcr1="0") and vdcr2 is set to "1", a voltage detection interrupt request signal is generated when the supply voltage (vdd) become s lower than the detection voltage (vdxlvl). if the voltage detection operation mode is set to ge nerate voltage detection reset signals (vdcr1="1") and vdcr2 is set to "1", a voltage detection reset signal is generated when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl). vdcr1 and vdcr2 are initialized by a power-on reset or an external reset input only. therefore, the volt- age detection reset signals are generated continuously, as long as the supply voltage (vdd) is lower than the detection voltage (vdxlvl). note:if the voltage detection mode is set to generate voltage detection interrupt request signals and the supply volt- age (vdd) becomes lower than the detection voltage (vdxlvl) in the stop, idle0 or sleep0 mode, a volt- age detection interrupt request signal is generated afte r the operation mode is released and returned to normal or slow mode. figure 7-2 voltage detection interrupt req uest signal and voltage detection reset signal 7.3.3 selecting the de tection voltage level select a detection voltage at vdcr1. 7.3.4 voltage detection flag an d voltage detection status flag the magnitude relation between the supply voltage (vdd) and the detection voltage (vdxlvl) can be checked by reading vdcr1 and vdcr1. if vdcr2 is set at "1", when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl), vdcr1 is set to "1" and is held in this state. vdcr1 is not cleared to "0" when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl). when vdcr2 is cleared to "0" after vdcr1 is set to "1", the previous state is still held. to clear vdcr1, "0" must be written to it. detection voltage level vdd level voltage detection interrupt request signal vdcr2 voltage detection reset signal
page 80 7. voltage detection circuit 7.3 function TMP89FH46 ra002 if vdcr2 is set at "1", when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl), vdcr1 is set to "1". when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl), vdcr1 is cleared to "0". unlike vdcr1, vdcr1 does not hold the set state. note 1: when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl) in the stop, idle0 or sleep0 mode, the voltage detection flag and the voltage detection status flag are changed after the opera- tion mode is returned to normal or slow mode. note 2: depending on the voltage detection timing, the vo ltage detection status flag (vdxsf) may be changed ear- lier than the voltage detection flag (v dxf) by a maximum of 2/fcgck[s]. figure 7-3 changes in the voltage detection flag and t he voltage detect ion status flag 7.3.5 selecting the stop mode release signal by setting vdcr2 to select the voltage det ection stop mode release signal as the stop mode release signal, stop mode can be released when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl). to use this function, set vdcr2 to "0" and set the operation mode to generate voltage detec- tion interrupt request signals. in addition, before the operation is switched to stop mode, clear syscr1 to "0" and select the edge release mode. if the level release mode is selected and the supply vol tage (vdd) is equal to or higher than the detection voltage (vdxlvl), stop mode cannot be activated. setting vdcr2 to "00" allows stop mode to be released depending on the state of the stop pin. setting it to "01" allows stop mode to be releas ed when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl). setting it to "10" allows stop mode to be released depending on the state of the stop pin or when the sup- ply voltage (vdd) becomes equal to or hi gher than the detection voltage (vdxlvl). refer to section 2 "cpu" for settings to activate or release stop mode. note 1: after stop mode is released by a voltage dete ction stop mode release signal, the interrupt latch becomes "1". if it is undesirable to accept an inte rrupt after stop mode is released, disable interrupts before stop mode is activated. in addition, clear t he interrupt latch before enabling interrupts after stop mode is released. note 2: if the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl) within 1 machine cycle after syscr1 is set to "1" an d stop mode is activated, stop mode is not released. note 3: when the voltage detection interrupt request signal of the voltage detection circ uit is used as the stop mode release signal, take into account sudden fluct uations in the supply voltage (vdd) and changes near the detection voltage (vdxlvl) in setting the detection voltage (vdxlvl) and the warm-up time. detection voltage level vdd level vdcr1 vdcr2 write 0 to vdcr1 the flag is not set because vdcr2 is 0 . vdcr1
page 81 TMP89FH46 ra002 figure 7-4 stop mode release by vdcr1 7.4 register settings 7.4.1 setting procedure when the operation mode is set to gener ate voltage detection interrupt request signals when the operation mode is set to generate voltage detection interrupt request signal, make the following setting: in this case, setting vdcr2 allows stop mo de to be released when the supply voltage (vdd) becomes equal to or higher than the detection voltage (vdxlvl). 1. clear the voltage detection circu it interrupt enable flag to "0". 2. set the detection voltage at vdcr1(x=1 to 2). 3. clear vdcr2 to "0" to set the operation mode to generate voltage detection interrupt request signals. 4. set vdcr2 to "1" to enable the voltage detection operation. 5. wait for 5 [us] or more until the voltage detection circuit becomes stable. 6. make sure that vdcr1 is "0". 7. clear the voltage detection circuit interrupt latch to "0" and set the interrupt enable flag to "1" to enable interrupts. note:if the set value of detection voltage (vdxlvl) is close to the supply voltage (vdd), voltage detection request signals may be generated frequently. at the return from the voltage detection interrupt processing, execute appropriate wait processing depending on fluctuations in the system power supply and clear the interrupt latch. 7.4.2 setting procedure when the operation mode is set to gener ate voltage detection reset signals when the operation mode is set to generate voltage detection reset signals, make the following setting: 1. clear the voltage detection circu it interrupt enable flag to "0". 2. set the detection voltage at vdcr1(x=1 to 2). 3. clear vdcr2 to "0" to set the operation mode to generate voltage detection interrupt request signals. 4. set vdcr2 to "1" to enable the voltage detection operation. 5. wait for 5 [us] or more until the voltage detection circuit becomes stable. 6. make sure that vdcr1 is "0". 7. set vdcr2 to "1" to set the operation mode to generate voltage detection reset signals. note 1: vdcr1 and vdcr2 are initialized by a power-on rese t or an external reset input only. if the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl) in the period from release of the voltage detec- tion reset until clearing of vdcr2 to "0", a voltage detection reset signal is generated immedi- ately. detection voltage level voltage detection interrupt request signal stop mode is released at the falling edge of vdcr1 vdd level vdcr1 stop mode is released at the falling edge of vdcr1 normal mode normal mode stop mode stop mode is activated by programming. stop mode is activated by programming. stop mode warm-up normal mode warm-up
page 82 7. voltage detection circuit 7.4 register settings TMP89FH46 ra002 note 2: the voltage detection reset signals are generated c ontinuously as long as the supply voltage (vdd) is lower than the detection voltage (vdxlvl).
page 83 TMP89FH46 ra005 8. i/o ports note: p00 and p01 pins can not be used for the i/o port, bec ause they should be connected with the high frequency osc input. each output port contains a latch, which holds the output data. no input port has a latch, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. figure 8-1 shows input/output timing examples. external data is read from an i/o po rt in the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transi ent input such as chattering must be processed by the program. data is out- put to an i/o port in the next cycle of the write cycle during execution of the wr ite instruction. figure 8-1 input/output timing (example) note: the positions of the read and write c ycles may vary, depending on the instruction. table 8-1 list of i/o ports port name pin name number of pins input/output secondary functions port p0 p03 to p00 (note) 4 (note) input/output also used as the high-frequency oscillator connection pin and the low-frequency oscillator connection pin port p1 p13 to p10 4 input/output also used as the external reset input, the external interrupt input and the stop mode release signal input port p2 p27 to p20 8 input/output also used as the uart input/output, the serial interface input/output and the serial bus interface input/output port p4 p47 to p40 8 input/output also used as the analog input and the key-on wakeup input port p7 p77 to p70 8 input/output also used as the timer counter input/output, the divider output and the external interrupt input port p8 p83 to p80 4 input/output also used as the timer counter input/output port p9 p91 to p90 2 input/output also used as the uart input/output port pb pb7 to pb4 4 input/output also used as the uart input/output and the serial interface input/out- put instruction execution cycle system clock internal read signal data input example: ld a, (x) fetch cycle fetch cycle read cycle instruction execution cycle internal write signal data input example: ld (x), a fetch cycle fetch cycle (a) input timing write cycle (b) input timing system clock
page 84 8. i/o ports 8.1 i/o port control registers TMP89FH46 ra005 8.1 i/o port control registers the following control registers are used for i/o ports. (the port number is indicated in place of x.) registers that can be set vary depending on the port. for deta ils, refer to the description of each port. ?pxdr register this is the register for setting output data. when a po rt is set to the "output m ode", the value specified at pxdr is output from the port. ?pxprd register this is the register for reading input data. when a por t is set to the "input mode", the current port input status can be read by reading pxprd. ? pxcr register this register switches a port be tween input and output. a port ca n be switched between the "input mode" and the "output mode". ?pxfc register this register enables the secondary function output of each port. the secondary function output of each port can be enabled or disabled. ? pxoutcr register this register switches the port output between the c-mos output and the open drain output. ?pxpu register this register determines whether or not the built-in pull-up resistor is connected when a port is used in the input mode or as the open drain output.
page 85 TMP89FH46 ra005 8.2 list of i/o port settings for the setting methods for individual i/o ports, refer to the following table. table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc other required settings port p0 p03 to p00 port input 0 without register 0 port output 1 0 p03 xtout * without register p02 xtin * 1 p01 xout * without register p00 xin * 1 port p1 p13 to p11 port input 0 without register without register port output 1 p10 port input 0 note 1 p10 port output 1 note 1 p13 int1 input 0 p12 int0 input 0 p11 int5 input 0 p11 stop input 0 p10 reset input * note 1 port p2 p27 to p20 port input 0 * * port output 1 * 0 p25 sclk0 input 0 * * sersel="01" sclk0 output 1 * 1 sersel="01" p24 scl0 input/output 1 without register 1 sersel="*0" si input 0 * sersel="01" p23 sda0 input/output 1 without register 1 sersel="*0" so output 1 1 sersel="01" p22 sclk0 input 0 * * sersel="10" sersel="0" sclk0 output 1 * 1 sersel="10" sersel="0" p21 rxd0 input 0 * * sersel="0*" sersel="0" uatcng="0" txd0 output 1 * 1 sersel="0*" sersel="0" uatcng="1" si0 input 0 * * sersel="10" sersel="0"
page 86 8. i/o ports 8.2 list of i/o port settings TMP89FH46 ra005 p20 txd0 output 1 * 1 sersel="0*" sersel="0" uatcng="0" rxd0 input 0 * * sersel="0*" sersel="0" uatcng="1" so0 output 1 * 1 sersel="10" sersel="0" port p4 p47 to p40 port input 0 without register * port output 1 0 ain7 to ain0 0 1 kwi7 to kwi4 * * kwucr1 kwi3 to kwi0 * * kwucr0 port p7 p77 to p70 port input 0 without register * port output 1 0 p77 int4 input 0 without register p76 int3 input 0 without register p75 int2 input 0 without register p74 dvo output 1 1 p73 tca1 input 0 * ppga1 output 1 1 p72 tca0 input 0 * sersel="00" ppga0 output 1 1 p71 tc01 input 0 * ppg01 / pwm01 output 1 1 p70 tc00 input 0 * ppg00 / pwm00 output 1 1 table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc other required settings
page 87 TMP89FH46 ra005 note 1: after the power is turned on, pin p10 serves as an exte rnal reset input. to use pin p10 as a port, refer to "how to use the external reset input pin as a port". note 2: about sersel, please refer to "8.4 serial interface selecting function". note 3: the symbol and numeric characters in the table have the following meanings: port p8 p83 to p80 port input 0 without register * port output 1 0 p81 tc03 input 0 * ppg03 / pwm03 output 1 1 p80 tc02 input 0 * ppg02 / pwm02 output 1 1 port p9 p92 to p90 port input 0 * * port output 1 * 0 p91 rxd1 input 0 * 0 uatcng="0" txd1 output 1 * 1 uatcng="1" p90 txd1 output 1 * 1 uatcng="0" rxd1 input 0 * 0 uatcng="1" port pb pb7 to pb4 port input 0 * * port output 1 * 0 pb6 sclk0 input 0 * * sersel="10" sersel="1" sclk0 output 1 * 1 sersel="10" sersel="1" pb5 rxd0 input 0 * * sersel="0*" sersel="1" uatcng="0" txd0 output 1 * 1 sersel="0*" sersel="1" uatcng="1" si0 input 0 * * sersel="10" sersel="1" pb4 txd0 output 1 * 1 sersel="0*" sersel="1" uatcng="0" rxd0 input 0 * * sersel="0*" sersel="1" uatcng="1" so0 output 1 * 1 sersel="10" sersel="1" symbol and numeric charac- ters meaning 0 set "0". 1 set "1". * don?t care (operation is the same whether "1" or "0" is selected.) without register there is no register that corresponds to the bit. table 8-2 list of i/o port settings port name pin name function register set value pxcr pxoutcr pxfc other required settings
page 88 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 8.3 i/o port registers 8.3.1 port p0 (p03 to p00) port p0 is a 4-bit input/output port th at can be set to input or output fo r each bit individually, and it is also used as the high-frequency oscillation connection pi n and the low-frequency oscillation connection pin. port p0 contains a programmable pull-up resistor on the vdd side. this pull-up resistor can be used when the port is used in the input mode. figure 8-2 port p0 (p00, p01) table 8-3 port p0 ----p03p02p01p00 secondary function ----xtoutxtinxoutxin output latch (for each bit) p0dr0 write p00 (xin) r note1 : r = 100 ? (typ.) note2 : rf = 1.2m ? (typ.) note3 : ro = 0.5k ? (typ.) note4 : r in3 = 50k ? (typ.) p0prd0 read function control (for each bit) input/output control (for each bit) p0fc0 write p0cr0 write vdd vdd pull-up control (for each bit) p0pu0 write syscr2 p0dr1 write p01 (xout) r r in3 r in3 rf ro p0prd1 read system clock reset (internal factor reset) p0cr1 write programmable pull-up resistor programmable pull-up resistor vdd vdd p0pu1 write syscr1 syscr1 reset signal pull-up control (for each bit) input/output control (for each bit) output latch (for each bit) internal data bus
page 89 TMP89FH46 ra005 figure 8-3 port p0 (p02, p03) internal data bus output latch (for each bit) p0dr2 write p02 (xtin) r rf p0prd2 read function control (for each bit) input/output control (for each bit) p0fc2 write p0cr2 write vdd vdd pull-up control (for each bit) p0pu2 write syscr2 output latch (for each bit) p0dr3 write p03 (xtout) r r in3 r in3 p0prd3 read input/output control (for each bit) p0cr3 write programmable pull-up resistor programmable pull-up resistor vdd vdd pull-up control (for each bit) p0pu3 write syscr1 syscr1 reset signal note1 : r = 100 ? (typ.) note2 : rf = 6m ? (typ.) note3 : ro = 220k ? (typ.) note4 : r in3 = 50k ? (typ.) ro
page 90 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 note: p0cr1 and p0cr0 must be clear to "0". note 1: when syscr2 is "1", setting p0fc0 to "0" generates a system clock (internal factor) reset. normally, ports p00 or p01 are not used as ports, so p0fc0 must be set to "1". note 2: symbol "i" means secondary function input port p0 output latch p0dr (0x0000) 76543210 bit symbol----p03p02p01p00 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port p0 input/output control p0cr (0x0f1a) 76543210 bit symbol----p0cr3p0cr2p0cr1p0cr0 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: input mode (port input) 1: output mode (port output) port p0 function control p0fc (0x0f34) 76543210 bit symbol-----p0fc2-p0fc0 read/writerrrrrr/wrr/w after reset00000001 function 0: port func- tion port func- tion 1: xtin (i) xin (i) port p0 built-in pull-up resistor control p0pu (0x0f27) 76543210 bit symbol----p0pu2p0pu2p0pu1p0pu0 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: the built-in pull-up resistor is not connected. 1: the built-in pull-up resistor is connected. (the resistor is connected in the input mode only. under any other con- ditions, setting to "1" does not make the resistor con- nected.) port p0 input data p0prd (0x000d) 76543210 bit symbol----p0prd3p0prd2p0prd1p0prd0 read/writerrrrrrrr after reset0000 **** function if the port is in the input mode, the contents of the port are read. if not, "0" is read.
page 91 TMP89FH46 ra005 note 1: * : don?t care note 2: i = 0, 1 note 1: * : don?t care note 2: j = 2, 3 table 8-4 p0prd read value (p00 to p01) set condition p0prdi read value p0fc0 p0cri *1 "0" 1* "0" 0 0 contents of port table 8-5 p0prd read value (p02 to p03) set condition p0prdj read value p0fc2 p0crj *1 "0" 1* "0" 0 0 contents of port
page 92 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 8.3.2 port p1 (p13 to p10) port p1 is a 4-bit input/output port th at can be set to input or output for each bit individually, and is also used as the external interrupt input, the stop mode release signal input and the external reset input. port p1 contains a programmable pull-up resistor on the vdd side. this pull-up resistor can be used when the port is used in the input mode. after reset, pin p10 serves as the external reset input. to use pin p10 as a port, refer to "how to use external reset input pin as a port". table 8-6 port p1 ----p13p12p11p10 secondary function ----int1 int0 int5 stop reset
page 93 TMP89FH46 ra005 figure 8-4 port p1 internal data bus output latch (for each bit) en p1dr write p10 r in2 r in3 r in3 r note1 : r = 100 ? (typ.) note2 : r in2 = 220k ? (typ.) note3 : r in3 = 50k ? (typ.) p1prd read input/output control (for each bit) p1cr write programmable pull-up resistor reset pull-up resistor vdd vdd vdd pull-up control (for each bit) p1pu write internal data bus output latch (for each bit) p1dr write syscr1 syscr3 syscr4 b2h write syscr1 reset signal reset signal p1i r note1 : r = 100 ? (typ.) note2 : r in3 = 50k ? (typ.) note3 : i = 1 ~ 3 int0, int1, int5, stop p1prd read in case of p11 in case of p12 and p13 input/output control (for each bit) p1cr write programmable pull-up resistor vdd vdd pull-up control (for each bit) p1pu write interrupt stop control peripheral functions low-voltage detection reset 1 signal low-voltage detection reset 2 signal watchdog timer reset signal system clock reset signal trimming data reset signal flash standby reset signal power-on reset signal reset 1 reset 2
page 94 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 note: symbol "i" means secondary function input note 1: * : don?t care note 2: i = 0 to 3 port p1 output latch p1dr (0x0001) 76543210 bit symbol----p13p12p11p10 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port p1 input/output control p1cr (0x0f1b) 76543210 bit symbol----p1cr3p1cr2p1cr1p1cr0 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: input mode (port input) int1 (i) int0 (i) int5 (i) stop (i) - 1: output mode (port output) port p1 built-in pull-up resistor control p1pu (0x0f28) 76543210 bit symbol----p1pu4p1pu2p1pu1p1pu0 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: the built-in pull-up resistor is not connected. 1: the built-in pull-up resistor is connected. (the resistor is connected only when the port is used in the input mode or as the open drain output. under any other conditions, setting to "1" does not make the resistor connected.) port p1 input data p1prd (0x000e) 76543210 bit symbol----p1prd3p1prd2p1prd1p1prd0 read/writerrrrrrrr after reset0000 **** function if the port is in the input mode, the contents of the port are read. if not, "0" is read. table 8-7 p1prd read value set condi- tion p1prdi read value p1cri 0 contents of port 1"0"
page 95 TMP89FH46 ra005 8.3.3 port p2 (p27 to p20) port p2 is an 8-bit in put/output port that can be se t to input or output for each bit individually, and it is also used as the serial bus interface i nput/output, the serial interface input/o utput, the uart input/output and the on-chip debug function. the output circuit has the p-channel output control function and either the sink open drain output or the c- mos output can be selected. port p2 contains a progr ammable pull-up resistor on the vdd side. this pull-up resistor can be used when the port is used in the input mode or as a sink open drain output. when this port is used as the serial bus interface, th e serial interface or the uart , setting for serial interface selecting function is also needed. for details, re fer to "8.4 serial interface selecting function". for the on-chip debug function, refer to the chapter of "on-chip debug function (ocd)". table 8-8 port p2 p27p26p25p24p23p22p21p20 secondary function --sclk0si0 scl0 so0 sda0 sclk0 si0 rxd0 txd0 ocdio so0 txd0 rxd0 ocdck
page 96 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 figure 8-5 port p2 internal data bus 0 1 s output latch (for each bit) p2dr write p2i r r in3 note1 : r = 100 ? (typ.) note2 : r in3 = 50k ? (typ.) sclk0, so0, txd0 sclk0, si0, rxd0 sio0 uart0 peripheral functions sio0 i2c0 peripheral functions p2prd read function control (for each bit) input/output control (for each bit) p2fc write p2cr write output control (for each bit) p2outcr write programmable pull-up resistor vdd vdd pull-up control (for each bit) p2pu write internal data bus 0 1 s output latch (for each bit) p2dr write p2j r note1 : r = 100 ? (typ.) note2 : j = 3, 4 scl0, sda0, so0 scl0, sda0, si0 p2prd read function control (for each bit) input/output control (for each bit) p2fc write p2cr write syscr1 syscr1 reset signal syscr1 syscr1 reset signal note3 : i = 0 to 2, 5 to 7 functions enclosed by the dotted line are for p20, p21,p22 and p25 only.
page 97 TMP89FH46 ra005 note: symbol "i" means secondary function input. symbol "o" means se condary function output. symbol "i/o" means secondary function input/output port p2 output latch p2dr (0x0002) 76543210 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. (serve s as hi-z or pull-up depending on settings of p2outcr and p2pu.) port p2 input/output control p2cr (0x0f1c) 76543210 bit symbol p2cr7 p2cr6 p2cr5 p2cr4 p2cr3 p2cr2 p2cr1 p2cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: input mode (port input) - - sclk0 (i) si0 (i) - sclk0 (i) rxd0 (i) si0 (i) rxd0 (i) 1: output mode (port output) - - sclk0 (o) scl0 (i/o) sda0 (i/o) so (o) sclk0 (o) txd0(o) txd0 (o) so0 (o) port p2 function control p2fc (0x0f36) 76543210 bit symbol - - p2fc5 p2fc4 p2fc3 p2fc2 p2fc1 p2fc0 read/write r r r/w r/w r/w r/w r/w r/w after reset00000000 function 0: port function 1: sclk0 (o) scl0 (i/o) sda0 (i/o) so0 (o) sclk0 (o) txd0 (o) txd0 (o) so0 (o) port p2 output control p2outcr (0x0f43) 76543210 bit symbol p2out7 p2out6 p2 out5 - - p2out2 p2out1 p2out0 read/write r/w r/w r/w r r r/w r/w r/w after reset00000000 function 0: c-mos output c-mos output 1: open drain output open drain output
page 98 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 note: * : don?t care note: i = 0 to 2, 5 to 7 port p2 built-in pull-up resistor control p2pu (0x0f29) 76543210 bit symbol p2pu7 p2pu6 p2pu5 - - p2pu2 p2pu1 p2pu0 read/write r/w r/w r/w r r r/w r/w r/w after reset00000000 function 0: the built-in pull-up resistor is not con- nected. the built-in pull-up resistor is not con- nected. 1: the built-in pull-up resistor is connected. (the resistor is connected only when the port is used in the input mode or as the open drain output. under any other con- ditions, setting to "1" does not make the resistor connected.) the built-in pull-up resistor is connected. (the resistor is connected only when the port is used in the input mode or as the open drain output. under any other con- ditions, setting to "1" does not make the resistor connected.) port p2 input data p2prd (0x000f) 76543210 bit symbol p2prd7 p2prd6 p2prd5 p2 prd4 p2prd3 p2prd2 p2prd1 p2prd0 read/writerrrrrrrr after reset******** function if the port is used in the input mode or as the open drain output, the contents of the port are read. if not, "0" is read. the contents of the port are read without condition. if the port is used in the input mode or as the open drain output, the contents of the port are read. if not, "0" is read. table 8-9 p2prd read value (p20 to p22, p25 to p27) set condition p2prdi read value p2cri p2outcri 0 * contents of port 10 "0" 1 1 contents of port
page 99 TMP89FH46 ra005 8.3.4 port p4 (p47 to p40) port p4 is an 8-bit in put/output port that can be se t to input or output for each bit individually, and it is also used as the analog input and the key-on wakeup input. port p4 contains a programmable pull-up resistor on the vdd side. this pull-up resistor can be used when the port is used in the input mode. figure 8-6 port p4 table 8-10 port p4 p47p46p45p44p43p42p41p40 secondary function ain7 kwi7 ain6 kwi6 ain5 kwi5 ain4 kwi4 ain3 kwi3 ain2 kwi2 ain1 kwi1 ain0 kwi0 internal data bus output latch (for each bit) p4dr write p4i r r in3 note1 : r = 100 ? (typ.) note2 : r in3 = 50k ? (typ.) note3 : i = 0 to 7 kwii key-on wakeup ad peripheral functions p4prd read aini enable signal kwii enable signal adccr1 function control (for each bit) input/output control (for each bit) p4fc write p4cr write programmable pull-up resistor vdd vdd pull-up control (for each bit) p4pu write reset signal aini syscr1 syscr1
page 100 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 note 1: symbol "i" means secondary function input. note 2: when the key-on wakeup input (kwii) is enabled (kwucrm="1"), there is no need to set p4cri. (i=7 to 0, m=1 to 0, n=3 to 0) note 1: when the key-on wakeup input (kwii) is enabled, there is no need to set p4fci. port p4 output latch p4dr (0x0004) 76543210 bit symbol p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port p4 input/output control p4cr (0x0f1e) 76543210 bit symbol p4cr7 p4cr6 p4cr5 p4cr4 p4cr3 p4cr2 p4cr1 p4cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: input mode (port input) ain7 (i)ain6 (i)ain5 (i)ain4 (i)ain3 (i)ain2 (i)ain1 (i)ain0 (i) 1: output mode (port output) port p4 function control p4fc (0x0f38) 76543210 bit symbol p4fc7 p4fc6 p4fc5 p4fc4 p4fc3 p4fc2 p4fc1 p4fc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: port function 1:ain7 (i)ain6 (i)ain5 (i)ain4 (i)ain3 (i)ain2 (i)ain1 (i)ain0 (i) port p4 built-in pull-up resistor control p4pu (0x0f2b) 76543210 bit symbol p4pu7 p4pu6 p4pu5 p4pu4 p4pu3 p4pu2 p4pu1 p4pu0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: the built-in pull-up resistor is not connected. 1: the built-in pull-up resistor is connected. (the resistor is connected only when the key-on wakeup input (kwii) is enabl ed or the port is used in the input mode (p4fci="0" and p4cri="0"). under any other conditions, setting to "1" does not make the resistor con- nected.) port p4 input data p4prd (0x0011) 76543210 bit symbol p4prd7 p4prd6 p4prd5 p4 prd4 p4prd3 p4prd2 p4prd1 p4prd0 read/writerrrrrrrr after reset******** function if the port is in the input mode, the contents of the port are read. if not, "0" is read.
page 101 TMP89FH46 ra005 note 1: * : don?t care note 2: i = 0 to 7 table 8-11 p4prd read value set condition p4prdi read value p4cri p4fci 0 0 contents of port *1 "0" 1* "0"
page 102 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 8.3.5 port p7 (p77 to p70) port p7 is an 8-bit in put/output port that can be se t to input or output for each bit individually, and it is also used as the external interrupt input, the divider output and the timer counter input/output. figure 8-7 port p7 table 8-12 port p7 p77p76p75p74p73p72p71p70 secondary function int4 int3 int2 dvo ppga1 tca1 ppga0 tca0 ppg01 pwm01 tc01 ppg00 pwm00 tc00 internal data bus 0 1 s output latch (for each bit) p7dr write p7i r note1 : r = 100 ? (typ.) note2 : i = 0 to 7 dvo, ppga1, ppga0, ppg01, ppg00, pwm01, pwm00 int4, int3, int2, tca1, tca0, tc01, tc00 p7prd read function control (for each bit) input/output control (for each bit) p7fc write p7cr write vdd functions enclosed by the dotted line are for p74 to p70 only. divider output external interrupt tca0 tca1 tc00 tc01 peripheral functions syscr1 syscr1 reset signal note3 : nch large current (only p70 to p73) (note3)
page 103 TMP89FH46 ra005 note: symbol "i" means secondary function inpu t. symbol "o" means secondary function output. note 1: * : don?t care note 2: i = 0 to 7 port p7 output latch p7dr (0x0007) 76543210 bit symbol p77 p76 p75 p74 p73 p72 p71 p70 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: outputs l level when the output mode is selected 1: outputs h level when the output mode is selected port p7 input/output control p7cr (0x0f21) 76543210 bit symbol p7cr7 p7cr6 p7cr5 p7cr4 p7cr3 p7cr2 p7cr1 p7cr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 function 0: input mode (port input) int4 (i) int3 (i) int2 (i) - tca1 (i) tca0 (i) tc01 (i) tc00 (i) 1: output mode (port output) --- dvo (o) ppga1 (o) ppga0 (o) ppg01 (o) pwm01 (o) ppg00 (o) pwm00 (o) port p7 function control p7fc (0x0f3b) 76543210 bit symbol - - - p7fc3 p7fc3 p7fc2 p7fc1 p7fc0 read/write r r r r/w r/w r/w r/w r/w after reset00000000 function 0: port function 1: dvo (o) ppga1 (o) ppga0 (o) ppg01 (o) pwm01 (o) ppg00 (o) pwm00 (o) port p7 input data p7prd (0x0014) 76543210 bit symbol p7prd7 p7prd6 p7prd5 p7 prd4 p7prd3 p7prd2 p7prd1 p7prd0 read/writerrrrrrrr after reset******** function if the port is used in the input mode, the contents of the port are read. if not, "0" is read. table 8-13 p7prd read value set condition p7prdi read value p7cri 0 contents of port 1"0"
page 104 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 8.3.6 port p8 (p83 to p80) figure 8-8 port p8 port p8 is a 4-bit input/outpu t port that can be set to input or output for each bit indi vidually, and it is also used as the timer counter input/output. table 8-14 port p8 p83 p82 p81 p80 secondary function ------ ppg03 pwm03 tc03 ppg02 pwm02 tc02 internal data bus 0 1 s output latch (for each bit) p8dr write p8i r note1 : r = 100 ? (typ.) ppg03, ppg02, pwm03, pwm02 tc03, tc02 p8prd read function control (for each bit) input/output control (for each bit) p8fc write p8cr write vdd functions enclosed by the dotted line are for p81 and p80 only. tc03 tc02 peripheral functions syscr1 syscr1 reset signal note2 : i = 0 to 3
page 105 TMP89FH46 ra005 note: symbol "i" means secondary function inpu t. symbol "o" means secondary function output. port p8 output latch p8dr (0x0008) 76543210 bit symbol----p83p82p81p80 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port p8 input/output control p8cr (0x0f22) 76543210 bit symbol----p8cr3p8cr2p8cr1p8cr0 read/writerrrrr/wr/wr/wr/w after reset00000000 function 0: input mode (port input) - - tc03 (i) tc02 (i) 1: output mode (port output) -- ppg03 (o) pwm03 (o) ppg02 (o) pwm02 (o) port p8 function control p8fc (0x0f3c) 76543210 bit symbol------p8fc1p8fc0 read/writerrrrrrr/wr/w after reset00000000 function 0: port function 1: ppg03 (o) pwm03 (o) ppg02 (o) pwm02 (o) port p8 input data p8prd (0x0015) 76543210 bit symbol----p8prd3p8prd2p8prd1p8prd0 read/writerrrrrrrr after reset0000 **** function if the port is used in the input mode, the contents of the port are read. if not, "0" is read. table 8-15 p8prd read value set condition p8prdi read value p8cri 0 contents of port 1"0" note 1: * : don?t care note 2: i = 0 to 3
page 106 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 8.3.7 port p9 (p91 to p90) port p9 is a 2-bit input/output port th at can be set to input or output fo r each bit individually, and it is also used as the uart. the output circuit has the p-channel output control function and either the sink open drain output or the c- mos output can be selected. port p9 contains a progr ammable pull-up resistor on the vdd side. this pull-up resistor can be used when the port is used in the input mode or as a sink open drain output. when this port is used as the uart, setting for the se rial interface selecting func tion is also needed. for details, refer to "8.4 serial interface selecting function". figure 8-9 port p9 table 8-16 port p9 p91 p90 secondary function ------rxd1 txd1 txd1 rxd1 internal data bus 0 1 s output latch (for each bit) p9dr write p9i r r in3 note1 : r = 100 ? (typ.) note2 : r in3 = 50k ? (typ.) note3 : i = 0 to 1 txd1 rxd1 p9prd read function control (for each bit) input/output control (for each bit) p9fc write p9cr write output control (for each bit) p9outcr write programmable pull-up resistor vdd vdd pull-up control (for each bit) p9pu write uart1 peripheral functions syscr1 syscr1 reset signal
page 107 TMP89FH46 ra005 note: symbol "i" means secondary function inpu t. symbol "o" means secondary function output. note 1: the built-in pull-up resistor is c onnected. (the resistor is connected only w hen the port is used in the input mode or a s the open drain output. under any other conditions, setting to "1" does not make the resistor connected.) port p9 output latch p9dr (0x0009) 76543210 bit symbol------p91p90 read/writerrrrrrr/wr/w after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. (serves as hi-z or pull-up depending on settings of p9outcr and p9pu.) port p9 input/output control p9cr (0x0f23) 76543210 bit symbol------p9cr1p9cr0 read/writerrrrrrr/wr/w after reset00000000 function 0: input mode (port input) rxd1 (i) rxd1 (i) 1: output mode (port output) txd1 (o) txd1 (o) port p9 function control p9fc (0x0f3d) 76543210 bit symbol------p9fc1p9fc0 read/writerrrrrrr/wr/w after reset00000000 function 0: port function 1: txd1 (o) txd1 (o) port p9 output control p9outcr (0x0f4a) 76543210 bit symbol------p9out1p9out0 read/writerrrrrrr/wr/w after reset00000000 function 0: c-mos output 1: open drain output port p9 built-in pull-up resistor control p9pu (0x0f30) 76543210 bit symbol------p9pu1p9pu0 read/writerrrrrrr/wr/w after reset00000000 function 0: the built-in pull-up resistor is not connected. 1: note 1
page 108 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 note 1: * : don?t care note 2: i = 0 to 1 port p9 input data p9prd (0x0016) 76543210 bit symbol------p9prd1p9prd0 read/writerrrrrrrr after reset000000* * function if the port is used in the input mode or as the sink open drain output, the contents of the port are read. if not, "0" is read. table 8-17 p9prd read value set condition p9prdi read value p9cri p9outcri 0 * contents of port 10 "0" 1 1 contents of port
page 109 TMP89FH46 ra005 8.3.8 port pb (pb7 to pb4) port pb is an 4-bit input/out put port that can be set to input or outpu t for each bit individually, and it is also used as the serial interface input /output and the uart input/output. the output circuit has the p-channel output control function and either the sink open drain output or the c- mos output can be selected. when this port is used as the serial interface or th e uart, setting for serial interface selecting function is also needed. for details, refer to "8 .4 serial interface selecting function". figure 8-10 port pb table 8-18 port pb pb7 pb6 pb5 pb4 - - - - secondary function - sclk0 si0 rxd0 txd0 so0 txd0 rxd0 ---- internal data bus 0 1 s output latch (for each bit) pbdr write pbi r note1 : r = 100 ? (typ.) note2 : nch large current peripheral functions pbprd read function control (for each bit) input/output control (for each bit) pbfc write pbcr write output control (for each bit) pboutcr write (note2) syscr1 syscr1 reset signal note3 : i = 4 to 7 sio0 uart0 sclk0, si0, rxd0 sclk0, so0, txd0 functions enclosed by the dotted line are for pb6 to pb4 only.
page 110 8. i/o ports 8.3 i/o port registers TMP89FH46 ra005 port pb output latch pbdr (0x000b) 76543210 bit symbol pb7 pb6 pb5 pb4 - - - - read/writer/wr/wr/wr/wrrrr after reset00000000 function 0: outputs l level when the output mode is selected. 1: outputs h level when the output mode is selected. port pb input/output control pbcr (0x0f25) 76543210 bit symbol pbcr7 pbcr6 pbcr5 pbcr4 - - - - read/writer/wr/wr/wr/wrrrr after reset00000000 function 0: input mode (port input) 1: output mode (port output) port pb function control pbfc (0x0f3f) 76543210 bit symbol - pbfc6 pbfc5 pbfc4 - - - - read/writerr/wr/wr/wrrrr after reset00000000 function 0: port function 1: sclk0 (o) txd0 (o) txd0 (o) so0 (o) port pb output control pboutcr (0x0f4c) 76543210 bit symbol pbout7 pbout6 pbout5 pbout4 - - - - read/writer/wr/wr/wr/wrrrr after reset00000000 function 0: c-mos output 1: open drain output port pb input data pbprd (0x0018) 76543210 bit symbol pbprd7 pbprd6 pbprd5 pbprd4 read/writerrrrrrrr after reset******** function if the port is used in the input mode or as the open drain output, the contents of the port are read. if not, "0" is read.
page 111 TMP89FH46 ra005 note 1: * : don?t care note 2: i = 4 to 7 table 8-19 pbprd read value set condition pbprdi read value pbcri pboutcri 0 * contents of port 10 "0" 1 1 contents of port
page 112 8. i/o ports 8.4 serial interface selecting function TMP89FH46 ra005 8.4 serial interface selecting function on the TMP89FH46 , the built-in serial interface (sio, uart and i 2 c) communication pins and interrupt source assignment can be changed. two out of three functions, sio0, uart0 and i 2 c0, can be used at the same time by using this selecting function. the input pins of the 16-bit timer counter a0 input (tca 0 input) can be changed by using this selecting function. figure 8-11 serial inte rface select ing function note 1: the operation for changing sersel must be executed whil e the applicable serial interf ace and timer counter operations are stopped. if sersel is switched during operation of these peripheral functions, each peri pheral function may receive (transmit) unexpected data and operate improperly. serial interface selection control register sersel (0x0fcb) 76543210 bit symbol tca0sel srsel2 srsel0 read/write r/w r/w r r/w r r r/w r/w after reset00000000 tca0sel 16-bit timer counter a0 input switch- ing 00: 01: 10: 11: p72 input (tca0) p21 input (also used as rxd0) p91 input (also used as rxd1) reserved srsel2 select uart0/sio0 input/output port 0: 1: select p20, p21, p22 select pb4, pb5, pb6 srsel0 serial interface selection 0 00: 01: 10: 11: select uart0, i2c0 select uart0, sio0 select sio0, i2c0 reserved uart1 p90 (txd1) p91 (rxd1) uart0 sio0 i2c0 tca0 p20 (txd0 / so0) p21 (rxd0 / si0) p22 (sclk0) sersel sersel 0* 10 selector selector s p23 (sda0 / so0) p24 (scl0 / si0) p25 (sclk0) p72 (tca0) p21 (rxd0) p91 (rxd1) 01 *0 selector s 00 01 10 selector s port port port pb4 (txd0 / so0) pb5 (rxd0 / si0) pb6 (sclk0) sersel s 1 0 port port
page 113 TMP89FH46 ra005 note 2: it is recommended to clear the interrupt latch for the applicable serial interface imm ediately after changing sersel. in ter- rupt latches are common to intrxd and intsio and to intsbi and intsio. therefore, if an interrupt occurs before or after sersel is switched, it is difficult to tell which function has caused the interrupt. note 1: the operation for changing uatcng must be executed while the applicable serial interface operations are stopped. note 1: can be used as a port. (set the function register (pxfc) to "0".) uart input/output change control register uatcng (0x0f57) 76543210 bit symbol------uat1iouat0io read/writerrrrrrr/wr/w after reset00000000 rxd pin txd pin uat1io select uart1 input/ output port 0: 1: p91 p90 p90 p91 uat0io select uart0 input/ output port sersel ="0" sersel ="1" sersel ="0" sersel ="1" 0: 1: p21 p20 pb5 pb4 p20 p21 pb4 pb5 table 8-20 select input/output port and interrupt sersel sersel uatcng port interrupt uart0/sio0 i2c0/sio0 pb4 pb5 pb6 p20 p21 p22 p23 p24 p25 il7 il6 il15 00: 0: 0: note 1 note 1 note 1 txd0 rxd0 note 1 sda0 scl0 note 1 inttxd0 intrxd0 intsbi0 1: rxd0 txd0 1: 0: txd0 rxd0 note 1 note 1 note 1 note 1 1: rxd0 txd0 01: 0: 0: note 1 note 1 note 1 txd0 rxd0 note 1 so0 si0 sclk 0 inttxd0 intrxd0 intsio0 1: rxd0 txd0 1: 0: txd0 rxd0 note 1 note 1 note 1 note 1 1: rxd0 txd0 10: 0: 0 or 1: note 1 note 1 note 1 so0 si0 sclk 0 sda0 scl0 note 1 - intsio0 intsbi0 1: 0 or 1: so0 si0 sclk 0 note 1 note 1 note 1 11: 0 or 1: 0 or 1: reserved
page 114 8. i/o ports 8.5 revision history TMP89FH46 ra005 8.5 revision history rev description ra005 "figure 8-4 port p1" revised reset control signal.
page 115 TMP89FH46 ra001 9. special function registers the TMP89FH46 adopts the memory mapp ed i/o system, and all peripheral hardware data control and transfer operations are performed through the special function regi sters (sfr). sfr1 is mapped on addresses 0x0000 to 0x003f, sfr2 is mapped on addresses 0x0f00 to 0x0fff , and sfr3 is mapped on addresses 0x0e40 to 0x0ebf. 9.1 sfr1 (0x0000 to 0x003f) note 1: do not access reserved addresses by the program. table 9-1 sfr1 (0x0000 to 0x003f) address register name address register name 0x0000 p0dr 0x0020 sio0sr 0x0001 p1dr 0x0021 sio0buf 0x0002 p2dr 0x0022 sbi0cr1 0x0003 reserved 0x0023 sbi0cr2/sbi0sr2 0x0004 p4dr 0x0024 i2c0ar 0x0005 reserved 0x0025 sbi0dbr 0x0006 reserved 0x0026 t00reg 0x0007 p7dr 0x0027 t01reg 0x0008 p8dr 0x0028 t00pwm 0x0009 p9dr 0x0029 t01pwm 0x000a reserved 0x002a t00mod 0x000b pbdr 0x002b t01mod 0x000c reserved 0x002c t001cr 0x000d p0prd 0x002d ta0dral 0x000e p1prd 0x002e ta0drah 0x000f p2prd 0x002f ta0drbl 0x0010 reserved 0x0030 ta0drbh 0x0011 p4prd 0x0031 ta0mod 0x0012 reserved 0x0032 ta0cr 0x0013 reserved 0x0033 ta0sr 0x0014 p7prd 0x0034 adccr1 0x0015 p8prd 0x0035 adccr2 0x0016 p9prd 0x0036 adcdrl 0x0017 reserved 0x0037 adcdrh 0x0018 pbprd 0x0038 dvocr 0x0019 reserved 0x0039 tbtcr 0x001a uart0cr1 0x003a eirl 0x001b uart0cr2 0x003b eirh 0x001c uart0dr 0x003c eire 0x001d uart0sr 0x003d eird 0x001e td0buf/rd0buf 0x003e reserved 0x001f sio0cr 0x003f psw
page 116 9. special function registers 9.2 sfr2 (0x0f00 to 0x0fff) TMP89FH46 ra001 9.2 sfr2 (0x0f00 to 0x0fff) note 1: do not access reserved addresses by the program. table 9-2 sfr2 (0x0f00 to 0x0f7f) address register name address register name address register name address register name 0x0f00 reserved 0x0f20 reserved 0x0f40 reserved 0x0f60 reserved 0x0f01 reserved 0x0f21 p7cr 0x 0f41 reserved 0x0f61 reserved 0x0f02 reserved 0x0f22 p8cr 0x 0f42 reserved 0x0f62 reserved 0x0f03 reserved 0x0f23 p9cr 0x0f43 p2outcr 0x0f63 reserved 0x0f04 reserved 0x0f24 reserved 0x0f44 reserved 0x0f64 reserved 0x0f05 reserved 0x0f25 pbcr 0x 0f45 reserved 0x0f65 reserved 0x0f06 reserved 0x0f26 reserved 0x0f46 reserved 0x0f66 reserved 0x0f07 reserved 0x0f27 p0pu 0x 0f47 reserved 0x0f67 reserved 0x0f08 reserved 0x0f28 p1pu 0x 0f48 reserved 0x0f68 reserved 0x0f09 reserved 0x0f29 p2pu 0x 0f49 reserved 0x0f69 reserved 0x0f0a reserved 0x0f2a reserved 0x0f4a p9outcr 0x0f6a reserved 0x0f0b reserved 0x0f2b p4pu 0x 0f4b reserved 0x0f6b reserved 0x0f0c reserved 0x0f2c reserved 0x0f4c pboutcr 0x0f6c reserved 0x0f0d reserved 0x0f2d reserved 0x0f4d reserved 0x0f6d reserved 0x0f0e reserved 0x0f2e reserved 0x0f4e reserved 0x0f6e reserved 0x0f0f reserved 0x0f2f reserved 0x0f4f reserved 0x0f6f reserved 0x0f10 reserved 0x0f30 p9pu 0x 0f50 reserved 0x0f70 reserved 0x0f11 reserved 0x0f31 reserved 0x0f51 reserved 0x0f71 reserved 0x0f12 reserved 0x0f32 reserved 0x0f52 reserved 0x0f72 reserved 0x0f13 reserved 0x0f33 reserved 0x0f53 reserved 0x0f73 reserved 0x0f14 reserved 0x0f34 p0fc 0x0f54 uart1cr1 0x0f74 poffcr0 0x0f15 reserved 0x0f35 reserved 0x0f55 uart1cr2 0x0f75 poffcr1 0x0f16 reserved 0x0f36 p2fc 0x0f56 uart1dr 0x0f76 poffcr2 0x0f17 reserved 0x0f37 reserved 0x0f57 uart1sr 0x0f77 poffcr3 0x0f18 reserved 0x0f38 p4fc 0x0f58 td1buf/rd1buf 0x0f78 reserved 0x0f19 reserved 0x0f39 reserved 0x0f59 reserved 0x0f79 reserved 0x0f1a p0cr 0x0f3a reserved 0x 0f5a reserved 0x0f7a reserved 0x0f1b p1cr 0x0f3b p7fc 0x0f 5b reserved 0x0f7b reserved 0x0f1c p2cr 0x0f3c p8fc 0x0f 5c reserved 0x0f7c reserved 0x0f1d reserved 0x0f3d p9fc 0x 0f5d reserved 0x0f7d reserved 0x0f1e p4cr 0x0f3e reserved 0x 0f5e reserved 0x0f7e reserved 0x0f1f reserved 0x0f3f pbfc 0x0f5f reserved 0x0f7f reserved
page 117 TMP89FH46 ra001 note 1: do not access reserved addresses by the program. table 9-3 sfr2 (0x0f80 to 0x0fff) address register name address register name address register name address register name 0x0f80 reserved 0x0fa0 reserv ed 0x0fc0 reserved 0x0fe0 ill 0x0f81 reserved 0x0fa1 reserv ed 0x0fc1 reserved 0x0fe1 ilh 0x0f82 reserved 0x0fa2 reserv ed 0x0fc2 reserved 0x0fe2 ile 0x0f83 reserved 0x0fa3 reserv ed 0x0fc3 reserved 0x0fe3 ild 0x0f84 reserved 0x0fa4 reserv ed 0x0fc4 kwucr0 0x0fe4 reserved 0x0f85 reserved 0x0fa5 reserv ed 0x0fc5 kwucr1 0x0fe5 reserved 0x0f86 reserved 0x0fa6 reserv ed 0x0fc6 vdcr1 0x0fe6 reserved 0x0f87 reserved 0x0fa7 reserv ed 0x0fc7 vdcr2 0x0fe7 reserved 0x0f88 t02reg 0x0fa8 ta1dral 0 x0fc8 rtccr 0x0fe8 reserved 0x0f89 t03reg 0x0fa9 ta1drah 0x0fc9 reserved 0x0fe9 reserved 0x0f8a t02pwm 0x0faa ta1drbl 0x0fca reserved 0x0fea reserved 0x0f8b t03pwm 0x0fab ta1drbh 0x0fcb sersel 0x0feb reserved 0x0f8c t02mod 0x0fac ta1mod 0x 0fcc irstsr 0x0fec reserved 0x0f8d t03mod 0x0fad ta1cr 0x0fcd wuccr 0x0fed reserved 0x0f8e t023cr 0x0fae ta1sr 0x0fce wucdr 0x0fee reserved 0x0f8f reserved 0x0faf reserv ed 0x0fcf cgcr 0x0fef reserved 0x0f90 reserved 0x0fb0 reserv ed 0x0fd0 flscr1 0x0ff0 ilprs1 0x0f91 reserved 0x0fb1 reserved 0x 0fd1 flscr2/flscrm 0x0ff1 ilprs2 0x0f92 reserved 0x0fb2 reserv ed 0x0fd2 flsstb 0x0ff2 ilprs3 0x0f93 reserved 0x0fb3 reserv ed 0x0fd3 spcr 0x0ff3 ilprs4 0x0f94 reserved 0x0fb4 reserv ed 0x0fd4 wdctr 0x0ff4 ilprs5 0x0f95 reserved 0x0fb5 reserv ed 0x0fd5 wdcdr 0x0ff5 ilprs6 0x0f96 reserved 0x0fb6 reserv ed 0x0fd6 wdcnt 0x0ff6 reserved 0x0f97 reserved 0x0fb7 reserv ed 0x0fd7 wdst 0x0ff7 reserved 0x0f98 reserved 0x0fb8 reserved 0x0fd8 eintcr1 0x0ff8 reserved 0x0f99 reserved 0x0fb9 reserved 0x0fd9 eintcr2 0x0ff9 reserved 0x0f9a reserved 0x0fba reserved 0x0fda eintcr3 0x0ffa reserved 0x0f9b reserved 0x0fbb reserved 0x0fdb eintcr4 0x0ffb reserved 0x0f9c reserved 0x0fbc reserved 0x0fdc syscr1 0x0ffc reserved 0x0f9d reserved 0x0fbd reserved 0x0fdd syscr2 0x0ffd reserved 0x0f9e reserved 0x0fbe reserved 0x0fde syscr3 0x0ffe reserved 0x0f9f reserved 0x0fbf reserved 0x0fdf syscr4/syssr4 0x0fff reserved
page 118 9. special function registers 9.3 sfr3 (0x0e40 to 0x0eff) TMP89FH46 ra001 9.3 sfr3 (0x0e40 to 0x0eff) note 1: do not access reserved addresses by the program. table 9-4 sfr3 (0x0e40 to 0x0ebf) address register name address register name address register name address register name 0x0e40 reserved 0x0e60 reserved 0x0e80 reserved 0x0ea0 reserved 0x0e41 reserved 0x0e61 reserved 0x0e81 reserved 0x0ea1 reserved 0x0e42 reserved 0x0e62 reserved 0x0e82 reserved 0x0ea2 reserved 0x0e43 reserved 0x0e63 reserved 0x0e83 reserved 0x0ea3 reserved 0x0e44 reserved 0x0e64 reserved 0x0e84 reserved 0x0ea4 reserved 0x0e45 reserved 0x0e65 reserved 0x0e85 reserved 0x0ea5 reserved 0x0e46 reserved 0x0e66 reserved 0x0e86 reserved 0x0ea6 reserved 0x0e47 reserved 0x0e67 reserved 0x0e87 reserved 0x0ea7 reserved 0x0e48 reserved 0x0e68 reserved 0x0e88 reserved 0x0ea8 reserved 0x0e49 reserved 0x0e69 reserved 0x0e89 reserved 0x0ea9 reserved 0x0e4a reserved 0x0e6a reserved 0x0e8a reserved 0x0eaa reserved 0x0e4b reserved 0x0e6b reserved 0x0e8b reserved 0x0eab reserved 0x0e4c reserved 0x0e6c reserved 0x0e8c reserved 0x0eac reserved 0x0e4d reserved 0x0e6d reserved 0x0e8d reserved 0x0ead reserved 0x0e4e reserved 0x0e6e reserved 0x0e8e reserved 0x0eae reserved 0x0e4f reserved 0x0e6f reserved 0x0e8f reserved 0x0eaf reserved 0x0e50 reserved 0x0e70 reserved 0x0e90 reserved 0x0eb0 reserved 0x0e51 reserved 0x0e71 reserved 0x0e91 reserved 0x0eb1 reserved 0x0e52 reserved 0x0e72 reserved 0x0e92 reserved 0x0eb2 reserved 0x0e53 reserved 0x0e73 reserved 0x0e93 reserved 0x0eb3 reserved 0x0e54 reserved 0x0e74 reserved 0x0e94 reserved 0x0eb4 reserved 0x0e55 reserved 0x0e75 reserved 0x0e95 reserved 0x0eb5 reserved 0x0e56 reserved 0x0e76 reserved 0x0e96 reserved 0x0eb6 reserved 0x0e57 uatcng 0x0e77 reserved 0x 0e97 reserved 0x0eb7 reserved 0x0e58 reserved 0x0e78 reserved 0x0e98 reserved 0x0eb8 reserved 0x0e59 reserved 0x0e79 reserved 0x0e99 reserved 0x0eb9 reserved 0x0e5a reserved 0x0e7a reserved 0x0e9a reserved 0x0eba reserved 0x0e5b reserved 0x0e7b reserved 0x0e9b reserved 0x0ebb reserved 0x0e5c reserved 0x0e7c reserved 0x0e9c reserved 0x0ebc reserved 0x0e5d reserved 0x0e7d reserved 0x0e9d reserved 0x0ebd reserved 0x0e5e reserved 0x0e7e reserved 0x0e9e reserved 0x0ebe reserved 0x0e5f reserved 0x0e7f reserved 0x0e9f reserved 0x0ebf reserved
page 119 TMP89FH46 ra001 note 1: do not access reserved addresses by the program. table 9-5 sfr3 (0x0ec0 to 0x0eff) address register name address register name address register name address register name 0x0ec0 reserved 0x0ed0 reserved 0x0ee0 reserved 0x0ef0 reserved 0x0ec1 reserved 0x0ed1 reserved 0x0ee1 reserved 0x0ef1 reserved 0x0ec2 reserved 0x0ed2 reserved 0x0ee2 reserved 0x0ef2 reserved 0x0ec3 reserved 0x0ed3 reserved 0x0ee3 reserved 0x0ef3 reserved 0x0ec4 reserved 0x0ed4 reserved 0x0ee4 reserved 0x0ef4 reserved 0x0ec5 reserved 0x0ed5 reserved 0x0ee5 reserved 0x0ef5 reserved 0x0ec6 reserved 0x0ed6 reserved 0x0ee6 reserved 0x0ef6 reserved 0x0ec7 reserved 0x0ed7 reserved 0x0ee7 reserved 0x0ef7 reserved 0x0ec8 reserved 0x0ed8 reserved 0x0ee8 reserved 0x0ef8 reserved 0x0ec9 reserved 0x0ed9 reserved 0x0ee9 reserved 0x0ef9 reserved 0x0eca reserved 0x0eda reserved 0x0eea reserved 0x0efa reserved 0x0ecb reserved 0x0edb reserved 0x0eeb reserved 0x0efb reserved 0x0ecc reserved 0x0edc reserved 0x0eec reserved 0x0efc reserved 0x0ecd reserved 0x0edd reserved 0x0eed reserved 0x0efd reserved 0x0ece reserved 0x0ede reserved 0x0eee reserved 0x0efe reserved 0x0ecf reserved 0x0edf reserved 0x0eef reserved 0x0eff reserved
page 120 9. special function registers 9.3 sfr3 (0x0e40 to 0x0eff) TMP89FH46 ra001
page 121 TMP89FH46 ra001 10. low power consumption function for peripherals the TMP89FH46 has low power consumption registers (p offcrn) that save power when specific peripheral functions are unused. each bit of the low power consumption registers can be set to enable or disable each peripheral function. (n = 0, 1, 2, 3) the basic clock supply to each periphe ral function is disabled for power sa ving, by setting the corresponding bit of the low power consumption registers (p offcrn) to "0". (the disabled peri pheral functions become unavailable.) the basic clock supply to each peripher al function is enabled and the function becomes available by setting the cor- responding bit of the low power consumption registers (poffcrn) to "1". after reset, the low power consumption registers (poffcrn) are initialized to "0", and thus the peripheral func- tions are unavailable. when each periphera l function is used for the first time, be sure to set the corresponding bit of the low power consumption registers (poffcrn) to "1" in the initial settings of the program (before operating the control register for the peripheral function). when a peripheral function is operating, the corr esponding bit of the low power consumption registers (poffcrn) must not be changed to "0". if it is ch anged, the peripheral function may operate unexpectedly.
page 122 10. low power consumption function for peripherals TMP89FH46 ra001 10.1 control the low power consumption function is controlled by the lo w power consumption registers (poffcrn). (n = 0, 1, 2, 3) low power consumption register 0 poffcr0 76543210 (0x0f74) bit symbol - - tc023en tc001en - - tca1en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tca1en tca1 control 0 1 disable enable tca0en tca0 control 0 1 disable enable low power consumption register 1 poffcr1 76543210 (0x0f75) bit symbol - - - sbi0en - - uart1en uart0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 sbi0en i2c0 control 0 1 disable enable uart1en uart1 control 0 1 disable enable uart0en uart0 control 0 1 disable enable low power consumption register 2 poffcr2 76543210 (0x0f76) bit symbol - - rtcen - - - - sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 rtcen rtc control 0 1 disable enable sio0en sio0 control 0 1 disable enable low power consumption register 3 poffcr3 76543210 (0x0f77) bit symbol - - int5en int4en int3en int2en int1en int0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000
page 123 TMP89FH46 ra001 int5en int5 control 0 1 disable enable int4en int4 control 0 1 disable enable int3en int3 control 0 1 disable enable int2en int2 control 0 1 disable enable int1en int1 control 0 1 disable enable int0en int0 control 0 1 disable enable
page 124 10. low power consumption function for peripherals TMP89FH46 ra001
page 125 TMP89FH46 ra001 11. divider output ( dvo ) this function outputs approximately 50% duty pulses that can be used to drive the piezoelectri c buzzer or other device. 11.1 configuration figure 11-1 divider output 11.2 control the divider output is controlled by the divider output control register (dvocr). note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: dvocr is cleared to "0" when the operation is switched to stop or idle0/sleep0 mode. dvocr holds the value. note 3: when syscr1 is "1" in the normal 1/2 or idle 1/2 mode, the dvo frequency is subject to some fluctuations to synchronize fs and fcgck. note 4: bits 7 to 3 of dvocr are read as "0". 11.2.1 function select the divider output frequency at dvocr. divider output control register dvocr (0x0038) 76543210 bit symbol-----dv0en dvock read/writerrrrrr/w r/w after reset00000000 dvoen enables/disables the divider output 0: disable the divider output 1: enable the divider output dvock selects the divider output frequency unit: [hz] normal 1/2, idle 1/2 mode slow1/2 sleep1 mode dv9ck=0 dv9ck=1 00 fcgck/2 12 fs/2 5 fs/2 5 01 fcgck/2 11 fs/2 4 fs/2 4 10 fcgck/2 10 fs/2 3 fs/2 3 11 fcgck/2 9 reserved reserved dvocr selector dvoen dvo pin dvock 2 a b c y d s fcgck/2 12 or fs/2 5 fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 9
page 126 11. divider output (dvo) 11.2 control TMP89FH46 ra001 the divider output is enabled by setting dvocr to "1". then, the rectangular waves selected by dvocr is output from dvo pin. it is disabled by clearing dvovr to "0". and dvo pin keeps "h" level. when the operation is changed to stop or idle0 /sleep0 mode, dvocr is cleared to "0" and the dvo pin outputs the "h" level. the divider output source clock operates, regardless of the value of dvocr. therefore, the frequency of the first divider output af ter dvocr is set to "1" is not the frequency set at dvocr. when the operation is changed to the software, stop or idle0/sleep0 mo de is activated and dvocr is cleared to "0", the frequency of the divider output is not the frequency set at dvocr. figure 11-2 divider output timing when the operation is changed from normal mode to slow mode or from slow mode to normal mode, the divider output frequency do es not reach the expected value due to synchronization of the gear clock (fcgck) and the low-frequency clock (fs). example: 2.441 khz pulse output (fcgck = 10.0 mhz) ld (dvocr), 00000100b ; dvock "00", dvoen "1" table 11-1 divider output frequency (exa mple: fcgck = 10.0 mhz, fs = 32.768 khz) dvock divider output frequency [hz] normal 1/2, idle 1/2 mode slow1/2, sleep1 mode dv9ck = 0 dv9ck = 1 00 2.441 k 1.024 k 1.024 k 01 4.883 k 2.048 k 2.048 k 10 9.766 k 4.096 k 4.096 k 11 19.531 k reserved reserved tbtcr divider output timing chart dvo output
page 127 TMP89FH46 ra001 12. time base timer (tbt) the time base timer generates the time base for key scan ning, dynamic display and other processes. it also pro- vides a time base timer interrupt (inttbt) in a certain cycle. 12.1 time base timer 12.1.1 configuration figure 12-1 time base timer configuration 12.1.2 control the time base timer is controlled by the time base timer control register (tbtcr). note 1: fcgck : gear clock [hz ], fs : low-frequency clock [hz] note 2: when the operation is changed to the stop mode, tbt cr is cleared to "0" and tbtcr maintains the value. time base timer control register tbtcr (0x0039) 76543210 bit symbol----tbten tbtck read/writerrrrr/w r/w after reset00000000 tbten enables/disables the time base timer interrupt requests 0: disables generation of interrupt request signals 1: enables generation of interrupt request signals tbtck selects the time base timer interrupt frequency unit: [hz] tbtck normal 1/2, idle 1/2 mode slow1/2, sleep1 mode dv9ck = 0 dv9ck = 1 000 fcgck/2 22 fs/2 15 fs/2 15 001 fcgck/2 20 fs/2 13 fs/2 13 010 fcgck/2 15 fs/2 8 reserved 011 fcgck/2 13 fs/2 6 reserved 100 fcgck/2 12 fs/2 5 reserved 101 fcgck/2 11 fs/2 4 reserved 110 fcgck/2 10 fs/2 3 reserved 111 fcgck/2 8 reserved reserved falling edge detector tbtcr source clock tbten tbtck 3 inttbt interrupt request selector idle0, sleep0 release request fcgck/2 22 or fs/2 15 fcgck/2 20 or fs/2 13 fcgck/2 15 or fs/2 8 fcgck/2 13 or fs/2 6 fcgck/2 12 or fs/2 5 fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8
page 128 12. time base timer (tbt) 12.1 time base timer TMP89FH46 ra001 note 3: tbtcr should be set when tbtcr is "0". note 4: when syscr1 is "1" in the normal 1/2 or idle1/2 mode, the interrupt request is subject to some fluctuations to synchronize fs and fcgck. note 5: bits 7 to 4 of tbtcr are read as "0". 12.1.3 functions select the source clock frequency for the time base timer by tbtcr. tbtcr should be changed when tbtcr is "0". otherwise, the inttbt interrupt request is generated at unex- pected timing. setting tbtcr to "1" causes interrupt request signals to occur at the falling edge of the source clock. when tbtcr is cleared to "0 ", no interrupt request signal will occur. when the operation is changed to the stop mode, tbtcr is cleared to "0". the source clock of the time base timer oper ates regardless of the tbtcr value. a time base timer interrupt is generated at the first fa lling edge of the source cloc k after a time base timer interrupt request is enabled. therefor e, the period from when the time tbtcr is set to "1" to the time when the first interrupt request occurs is shor ter than the frequency period set at tbtcr. figure 12-2 time ba se timer interrupt when the operation is changed from normal mode to slow mode or from slow mode to normal mode, the interrupt request will not o ccur at the expected tim ing due to synchronization of the gear clock (fcgck) and the low-freque ncy clock (fs). it is recommened that the operation mode is changed when tbtcr is "0". table 12-1 time base timer interrupt frequency (example: wh en fcgck = 10.0 mhz and fs = 32.768 khz) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1 mode dv9ck = 0 dv9ck = 1 000 2.38 1 1 001 9.54 4 4 010 305.18 128 reserved 011 1220.70 512 reserved 100 2441.41 1024 reserved 101 4882.81 2048 reserved 110 9765.63 4096 reserved 111 39062.5 reserved reserved example: set the time base timer interrupt frequency to fcgck/2 15 [hz] and enable interrupts. source clock time base timer enable interrupt period tbtcr inttbt interrupt request
page 129 TMP89FH46 ra001 di ; imf 0 set (eirl). 5 ; set the interrupt enable register ei ; imf 1 ld (tbtcr), 0y00000010 ; set the interrupt frequency ld (tbtcr), 0y00001010 ; enable generation of interrupt request signals
page 130 12. time base timer (tbt) 12.1 time base timer TMP89FH46 ra001
page 131 TMP89FH46 ra001 13. 16-bit timer counter (tca) the TMP89FH46 contains 2 channels of high- performance 16-bit timer counters (tca). this chapter describes the 16-bit timer counter a0. for the 16-bit timer counter a1, replace the sfr addresses and pin names, as shown in table 13-1 and table 13-2. table 13-1 sfr address assignment taxdral (address) taxdrah (address) taxdrbl (address) taxdrbh (address) taxmod (address) taxcr (address) taxsr (address) low power consump- tion register timer counter a0 ta0dral (0x002d) ta0drah (0x002e) ta0drbl (0x002f) ta0drbh (0x0030) ta0mod (0x0031) ta0cr (0x0032) ta0sr (0x0033) poffcr0 timer counter a1 ta1dral (0x0fa8) ta1drah (0x0fa9) ta1drbl (0x0faa) ta1drbh (0x0fab) ta1mod (0x0fac) ta1cr (0x0fad) ta1sr (0x0fae) poffcr0 table 13-2 pin names timer input pin ppg output pin timer counter a0 tca0 pin ppga0 pin timer counter a1 tca1 pin ppga1 pin
page 132 13. 16-bit timer counter (tca) 13.1 configuration TMP89FH46 ra001 13.1 configuration figure 13-1 timer counter a0 ta0drah selector selector selector selector overflow match detection pulse width measurement mode ppg mode reading and writing of ta0drah reading and writing of ta0dral ta0dral temporary buffer double buffer (16 bits) 16-bit up counter internal bus internal bus 01 0 0 0 1 1 1 comparator intta0 interrupt request match detection count up count clear clear ta0s ta0drbh ta0mod ta0cr ta0sr decorder ta0dbe ta0ove ppga0 output timer f/f ta0ted edge detection 2 edge detection 1 edge detection 2 edge detection 1 edge detection 1 edge detection 2 edge detection 2 rising falling edge detection 1 falling rising ta0ted 0 1 edge detection 1 edge detection 2 tamcap en ta0cap ta0nc fcgck/2 10 or fs/2 3 fcgck/2 6 fcgck/2 2 fcgck/2 e a b c d 0 1 2 ta0ck ta0m ta0dbe ta0ted ta0mett ta0nc ta0ove ta0cap ta0mppg ta0cpfb ta0cpfa ta0ovf ta0s ta0tff y y s0 s1 s selector selector selector window mode event counter mode ppg mode tca0 pin input selector reading and writing of ta0drbh reading and writing of ta0drbl ta0drbl temporary buffer double buffer (16 bits) 01 0 0 0 1 1 1 external trigger input selection auto capture control capture control timer start control external trigger timer mode pulse width measurement mode capture control noise canceller 2 3 comparator
page 133 TMP89FH46 ra001 13.2 control timer counter a0 is controlled by the low power consumption register (poffcr0), the timer counter a0 mode register (ta0mod), the timer counter a0 control register (ta0cr) and two 16-bit timer a0 registers (ta0dra and ta0drb). low power consumption register 0 poffcr0 76543210 (0x0f74) bit symbol - - tc023en tc001en - - tca1en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tca1en tca1 control 0 1 disable enable tca0en tca0 control 0 1 disable enable
page 134 13. 16-bit timer counter (tca) 13.2 control TMP89FH46 ra001 note 1: fcgck, gear clock [h z]; fs, low-frequency clock [hz] note 2: set ta0mod in the stopped state (ta0cr="0" ). writing to ta0mod is invalid during the operation (ta0cr="1"). timer counter a0 mode register ta0mod 76543210 (0x0031) bit symbol ta0dbe ta0ted ta0mcap ta0mett ta0ck ta0m read/write r/w r/w r/w r/w r/w after reset10000000 ta0dbe double buffer control 0 1 disable the double buffer enable the double buffer ta0ted external trigger input selection 0 1 rising edge/h level falling edge/l level ta0mcap pulse width measurement mode control 0 1 double edge capture single edge capture ta0mett external trigger timer mode control 0 1 trigger start trigger start & stop ta0ck timer counter 1 source clock selection normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode syscr1 ="0" syscr1 ="1" 00 fcgck/2 10 fs/2 3 fs/2 3 01 fcgck/2 6 fcgck/2 6 - 10 fcgck/2 2 fcgck/2 2 - 11 fcgck/2 fcgck/2 - ta0m timer counter 1 operation mode selection 000 timer mode 001 timer mode 010 event counter mode 011 ppg output mode (software start) 100 external trigger timer mode 101 window mode 110 pulse width measurement mode 111 reserved
page 135 TMP89FH46 ra001 note 1: the auto capture can be used only in the timer, event counter, external trigger timer and window modes. note 2: set ta0tff, ta0ove and ta0nc in the stopped state (ta0s="0"). writing is invalid during the operation (ta0s="1"). note 3: when the stop mode is started, the start control (ta0s) is automatically cleared to "0 " and the timer stops. set ta0s again to use the timer counter afte r the release of the stop mode. note 4: when a read instruction is executed on ta0cr, bits 3 and 2 are read as "0". note 5: do not set ta0nc to "01" or "10" when the slow 1/2 or sleep 1 mode is used. setting ta0nc to "01" or "10" stops the noise canceller and no signal is input to the timer. timer counter a0 control register ta0cr 76543210 (0x0032) bit symbol ta0ove ta0tff ta0nc - - ta0cap ta0mppg ta0s read/write r/w r/w r/w r r r/w r/w after reset01000000 ta0ove overflow interrupt control 0 1 generate no intta0 interrupt request when the counter overflow occurs. generate an intta0 interrupt request when the counter overflow occurs. ta0tff timer f/f control 0 1 clear set ta0nc noise canceller sampling interval setting normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode 00 no noise canceller no noise canceller 01 fcgck/2 - 10 fcgck/2 2 - 11 fcgck/2 8 fs/2 ta0acap auto capture function 0 1 disable the auto capture enable the auto capture ta0mppg ppg output control 0 1 continuous one-shot ta0s timer counter a start control 0 1 stop & counter clear start
page 136 13. 16-bit timer counter (tca) 13.2 control TMP89FH46 ra001 note 1: ta0ovf, ta0cpfa and ta0cpfb are cleared to "0" automat ically after ta0sr is read. writing to ta0sr is invalid. note 2: when a read instruction is executed on ta0sr, bits 6 to 2 are read as "0". note 1: when a write instruction is executed on ta0dral (t a0drbl), the set value does not become effective immedi- ately, but is temporarily stored in the temporary buffer . subsequently, when a write instruction is executed on the higher-level register, ta0drah (ta0drbh), the 16-bit set va lues are collectively stored in the double buffer or ta0dral/h. when setting data to the timer counter a0 regist er, be sure to write the data into the lower level reg- ister and the higher level in this order. note 2: the timer counter a0 register is not writable in the pulse width measurement mode. timer counter a0 status register ta0sr 76543210 (0x0033)bit symbolta0ovf-----ta0cpfata0cpfb read/writerrrrrrrr after reset00000000 ta0ovf overflow flag 0 1 no overflow has occurred. at least an overflow has occurred. ta0cpfa capture completion flag a 0 1 no capture operation has been executed. at least a pulse width capture has been executed in the double-edge capture. ta0cpfb capture completion flag b 0 1 no capture operation has been executed. at least a capture operation has been executed in the single-edge cap- ture. at least a pulse duty width capture has been executed in the double- edge capture. timer counter a0 register ah ta0drah 151413121110 9 8 (0x002e) bit symbol ta0drah read/write r/w after reset11111111 timer counter a0 register al ta0dral 76543210 (0x002d) bit symbol ta0dral read/write r/w after reset11111111 timer counter a0 register bh ta0drbh 151413121110 9 8 (0x0030) bit symbol ta0drbh read/write r/w after reset11111111 timer counter a0 register bl ta0drbl 76543210 (0x002f) bit symbol ta0drbl read/write r/w after reset11111111
page 137 TMP89FH46 ra001 13.3 low power consumption function timer counter a0 has the low power consumption regist er (poffcr0) that saves power consumption when the timer is not used. setting poffcr0 to "0" disables the basic clock supply to timer counter a0 to save power. note that this makes the timer unusable. setting poffcr0 to "1" enables the basic clock supply to timer counter a0 and allows the timer to operate. after reset, poffcr0 is initialized to "0", an d this makes the timer unusable. when using the timer for the first time, be sure to set poffcr0 to "1 " in the initial setting of the program (before the timer control register is operated). do not change poffcr0 to "0" during the ti mer operation. otherwise timer counter a0 may operate unexpectedly.
page 138 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 13.4 timer function timer counter a0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse width measurement and programmable pulse generate (ppg) output modes. 13.4.1 timer mode in the timer mode, the up-counter counts up using the in ternal clock, and interrupts can be generated regu- larly at specified times. 13.4.1.1 setting setting the operation mode selection ta0mod to "000" or "001" activates the timer mode. select the source clock at ta0mod. setting ta0cr to "1" starts the timer operatio n. after the timer is started, writing to ta0mod and ta0cr becomes invalid. be sure to comp lete the required mode settings before starting the timer. 13.4.1.2 operation setting ta0cr to "1" allows the 16-bit up co unter to increment based on the selected internal source clock. when a match between the up-counte r value and the value set to timer register a (ta0dra) is detected, an intta0 interrupt reque st is generated and the up counter is cleared to "0000h". after being cleared, the up counter continues counting. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0000h". 13.4.1.3 auto capture the latest contents of the up counter can be taken into timer register b (ta0drb) by setting ta0cr to "1" (auto capture function). when ta0cr is "1", the current con- tents of the up counter can be read by reading ta0drbl. ta0drbh is loaded at the same time as ta0drbl is read. therefore, wh en reading the captured value, be sure to read ta0drbl and ta0drbh in this order. (the capture time is the tim ing when ta0drbl is read.) the auto capture func- tion can be used whether the timer is operating or stopped. when the timer is stopped, ta0drbl is read as "00h". ta0drbh keeps the captu red value after the timer stops, but it is cleared to "00h" when ta0drbl is read while the timer is stopped. if the timer is started with ta0cr written to "1", the auto capture is enabled immediately after the timer is started. note 1: the value set to ta0cr cannot be changed at the same time as ta0cr is rewritten from "1" to "0". (this setting is invalid.) table 13-3 timer mode resolution and maximum time setting ta0mod source clock [hz] resoluti on maximum time setting normal 1/2 or idle 1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 00 fcgck/2 10 fs/2 3 fs/2 3 102.4 s 244.1us 6.7s 16s 01 fcgck/2 6 fcgck/2 6 -6.4 s - 419.4ms - 10 fcgck/2 2 fcgck/2 2 - 400ns - 26.2ms - 11 fcgck/2 fcgck/2 - 200ns - 13.1ms -
page 139 TMP89FH46 ra001 13.4.1.4 register buffer configuration (1) temporary buffer the TMP89FH46 contains an 8-bit temporary bu ffer. when a write instruction is executed on ta0dral, the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. subsequently, when a write instruction is executed on ta0drah, the set value is stored into the double buffer or ta0drah. at the same time, the set value in the temporary buffer is stored into the double buffer or ta0dral. (this structure is designed to enable the set values of the lower- level and higher-level registers simultaneously.) ther efore, when setting data to ta0dra, be sure to write the data into ta0dral and ta0drah in this order. see figure 13-1 for the tempor ary buffer configuration. (2) double buffer in the TMP89FH46, the double buffer can be used by setting ta0cr. setting ta0cr to "0" disables the double buffer. setting ta0cr to "1" enables the double buffer. see figure 13-1 for the double buffer configuration. - when the double buffer is enabled when a write instruction is executed on ta0drah during the timer operation, the set value is first stored into the double buffer, and ta0drah/l are not updated immediately. ta0drah/l compare the up counter value to the last set values. if the values are matched, an inttca0 interrupt request is generated and the double buffer set value is stored in ta0drah/l. subsequently, the match detection is executed using a new set value. when a read instruction is executed on ta0dr ah/l, the double buffer value (the last set value) is read, rather than the ta0drah/l values (the current effective values). when a write instruction is executed on ta0drah/l while the timer is stopped, the set value is immediately stored into both the double buffer and ta0drah/l. - when the double buffer is disabled when a write instruction is executed on ta0drah during the timer operation, the set value is immediately stored into ta0drah/l. subsequently, the match detection is exe- cuted using a new set value. if the values set to ta0drah/l are smaller than the up counter value, the match detection is executed using a new set value after the up counter overflows. therefore, the interrupt request interval may be longer than the selected time. if that is a problem, enable the double buffer. when a write instruction is executed on ta0drah/l while the timer is stopped, the set value is immediately stored into ta0drah/l.
page 140 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 figure 13-2 timer mode timing chart source clock counter timer start 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah reflected by an interrupt reflected at the same time as data is written into ta0drah while the timer is stopped counter clear inttca interrupt request 234 mn-1 mn 01 rs 01 220 3 ta0drah ta0cr s r timer stop match detection counter clear rs-1 ta0mod when the double buffer is disabled (ta0mod=?0?) source clock counter timer start 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r counter clear inttca interrupt request 234 mn-1 mn 01 mn 01 23 ta0drah ta0cr s r n temporary buffer (8 bits) s n temporary buffer (8 bits) s mn double buffer (16 bits) rs match detection match detection counter clear 01 mn-1 rs rs-1 ta0mod when the double buffer is enabled (ta0mod=?1?)
page 141 TMP89FH46 ra001 figure 13-3 timer mode ti ming chart (auto capture) source clock counter timer start ta0drbh is updated when ta0drbl is read read ta0drbl read ta0drbh read value 00h read value 00h ta0drbl ta0drbh ta0cr timer stop 18fd 0000 0001 0002 18fe 18ff 1900 1901 1902 1903 1904 1905 1906 0000 fd 00 01 00 18 02 fe ff 00 01 02 03 04 05 06 00 00 ta0mod read value feh read value 18h read value 00h read value 00h read value 18h
page 142 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 13.4.2 external trigger timer mode in the external trigger timer mode, the up counter starts counting when it is triggered by the input to the tca0 pin. 13.4.2.1 setting setting the operation mode selection ta0mod to "100" activates the external trigger timer mode. select the source clock at ta0mod. select the trigger edge at the trigger edge input selection ta0mod. setting ta0mod to "0" selects the rising edge, an d setting it to "1" selects the falling edge. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode beforehand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before starting the timer. 13.4.2.2 operation after the timer is started, when the selected trigger edge is input to the tca0 pin, the up counter incre- ments according to the selected sour ce clock. when a match between th e up counter value and the value set to timer register a (ta0dra) is detected, an in tta0 interrupt request is generated and the up counter is cleared to "0000h". after being cl eared, the up counter continues counting. when ta0mod is "1" and the edge opposite to the selected trigger edge is detected, the up counter stops counting and is cleared to "0000h". subsequently, when the selected trigger edge is detected, the up counter rest arts counting. in this mode, an interrupt request can be generated by detecting that the input pulse exceeds a certa in pulse width. if ta0mod is "0", the detection of the selected edge and the opposite edge is ignored during the period from the detectio n of the specified trigger edge and the start of counting through until the match detection. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0000h". 13.4.2.3 auto capture refer to "13.4.1.3 auto capture". 13.4.2.4 register buffer configuration refer to "13.4.1.4 register buffer configuration".
page 143 TMP89FH46 ra001 figure 13-4 external tr igger timer timing chart source clock counter timer start counting start edge is invalid during counting counting start 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah counter clear inttca interrupt request 23 mn-1 mn 01 rs 01 220 3 ta0drah ta0cr s r timer stop match detection counter clear rs-1 ta0mod ta0 pin input when the trigger is started (ta0mod=?0?) timer start counting start counting start counting start counting stop 1 0 n m ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah counter clear counter clear inttca interrupt request 23 mn-1 mn 01 rs 01 1 20 0 ta0drah ta0cr s r timer stop match detection counter clear rs-1 ta0mod when the trigger is started and stopped (ta0mod=?1?) edge is invalid during counting source clock counter write to ta0dral write to ta0drah ta0 pin input
page 144 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 13.4.3 event counter mode in the event counter mode, the up counter counts up at the edge of the input to the tca0 pin. 13.4.3.1 setting setting the operation mode selection ta0mod to "010" activates the event counter mode. set the trigger edge at the external trigger input selection ta0mod. setting ta0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge for count- ing up. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode beforehand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before starting the timer. 13.4.3.2 operation after the event counter mode is started, when the sel ected trigger edge is input to the tca0 pin, the up counter increments. when a match between the up counter value and the va lue set to timer register a (ta0dra) is detected, an intta0 interrupt request is generated and the up counter is cleared to "0000h". after being cleared, the up counter continues counting and counts up at ea ch edge of the input to the tca0 pin. setting ta0cr to "0" during the operation causes the up counter to stop counting and be cleared to "0000h". the maximum frequency to be supplied is fcgck/2 [hz] (in the normal 1/2 or idle 1/2 mode) or fs/ 2 [hz] (in the slow 1/2 or sleep 1 mode), and a puls e width of two machine cycl es or more is required at both the "h" and "l" levels. 13.4.3.3 auto capture refer to "13.4.1.3 auto capture". 13.4.3.4 register buffer configuration refer to "13.4.1.4 register buffer configuration".
page 145 TMP89FH46 ra001 figure 13-5 event coun t mode timing chart ta0 pin input counter timer start when the rising edge is selected (ta0mod=?0?) 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write s write m write r reflected by writing to ta0drah reflected by writing to ta0drah counter clear inttca interrupt request 23 4 mn-1 mn 01 rs 01 220 3 ta0drah ta0cr s r timer stop match detection counter clear rs-1
page 146 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 13.4.4 window mode in the window mode, the up counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tca0 pin (window pulse) and the internal clock. 13.4.4.1 setting setting the operation mode selection ta0mod to "101" activates the window mode. select the source clock at ta0mod. select the window pulse level at the trigger edge input selection ta0mod. setting ta0mod to "0" enables counting up as long as the window pulse is at the "h" level. setting ta0mod to "1" enables counting up as long as the window pulse is at the "l" level. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode beforehand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before starting the timer. 13.4.4.2 operation after the operation is started, when the level selected at ta0mod is input to the tca0 pin, the up counter increments according to the source cl ock selected at ta0mod. when a match between the up counter value and the value set to timer register a (ta0dra) is detected, an intta0 interrupt request is generated and the up counter is cleared to "0000h". after being cleared, the up counter restarts counting. the maximum frequency to be supplied must be slow enough for the program to analyze the count value. define a frequency pulse that is sufficiently lower than the programmed internal source clock. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0000h". 13.4.4.3 auto capture refer to "13.4.1.3 auto capture". 13.4.4.4 register buffer configuration refer to "13.4.1.4 register buffer configuration".
page 147 TMP89FH46 ra001 figure 13-6 window mode timing chart source clock counter timer start count in the period of h level count in the period of h level 1 0 n m write to ta0dral write to ta0drah ta0dral match detection write n write m reflected by writing to ta0drah counter clear inttca interrupt request 25 46 456 3 mn-1 mn 1 02 0 3 ta0drah ta0cr timer stop ta0mod ta0 pin input during the h-level counting (ta0mod=?0?)
page 148 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 13.4.5 pulse width measurement mode in the pulse width measurement mode, the up counter starts counting at the rising/falling edge(s) of the input to the tca0 pin and measures the input pulse width based on the internal clock. 13.4.5.1 setting setting the operation mode selection ta0mod to "110" activates the pulse width measure- ment mode. select the source clock at ta0mod. select the trigger edge at the trigger edge input selection ta0mod. setting ta0mod to "0" selects the rising edge, and setting it to "1" selects the falling edge as a trig- ger to start the capture. the operation after capturing is determined by the pulse width meas urement mode control ta0mod. setting ta0mod to "0" selects the double-edge capture. setting ta0mod to "1" sel ects the single-edge capture. the operation to be executed in case of an overflow of th e up counter can be selected at the overflow interrupt control ta0cr. setting ta0ove to "1" makes an intta0 interrupt request occur in case of an overflow. setting ta0ove to "0" make s no intta0 interrupt request occur in case of an overflow. note that this mode uses the ta0 input pin, and the tca0 pin must be set to the input mode beforehand in port settings. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before starting the timer. 13.4.5.2 operation after the timer is started, when the selected trigger edge (start edge) is input to the tca0 pin, the up counter increments according to the selected source cl ock. subsequently, when the edge opposite to the selected edge is detected, the up counter value is captured into ta0drb, an intta0 interrupt request is generated, and ta0sr is set to "1". depending on the ta0mod setting, the operation differs as follows: ? double-edge capture (when ta0mod is "0") the up counter continues counting up after the edge opposite to the selected edge is detected. subsequently, when the selected trigger edge is input, the up counter value is captured into ta0dra, an intta0 interrupt request is generated, and ta0sr is set to "1". at this time, the up counter is cleared to "0000h". ? single-edge capture (when ta0mod is "1") the up counter stops counting up and is cleared to "0000h" when the edge opposite to the selected edge is detected. subsequently, when the start edge is input, the up counter restarts increment. when the up counter overfl ows during capturing, the overflow flag ta0sr is set to "1". at this time, an intta0 interrupt request occurs if the overflow interrupt control ta0cr is set to "1". the capture completion flags (ta0sr and the overflow flag (ta0sr) are cleared to "0" automatically when ta0sr is read.
page 149 TMP89FH46 ra001 the captured value must be read from ta0drb (and also from ta0dra for the double-edge capture) before the next trigger edge is detected. if the captured value is not read, it becomes undefined. ta0dra and ta0drb must be read by us ing a 16-bit access instruction. setting ta0cr to "0" during the timer operation causes the up counter to stop counting and be cleared to "0000h". note 1: after the timer is started, if the edge opposite to the selected trigger edge is detected first, no capture is executed and no intta0 interrupt request occurs. in this case, the capture starts when the selected trigger edge is detected next. figure 13-7 pulse width me asurement mode timing chart source clock counter counter clear counter clear counter clear counter clear timer start count start count start after the timer is started, if the falling edge is detected first, no interrupt occurs. 1 0 ta0drbh, l inttca interrupt request 0 24 3 3 mn-1 mn 1 0 mn 20 ta0cr timer stop ta0mod ta0 pin input single-edge capture (ta0mod=?0?) source clock counter timer start after the timer is started, if the falling edge is detected first, no interrupt occurs. 1 0 ta0drbh, l inttca interrupt request 0 24 3 mn-1 mn mn+1 st-1 st mn 0 012 0 ta0drah, l st ta0cr timer stop ta0mod ta0 pin input double-edge capture (ta0mod=?1?)
page 150 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 13.4.6 programmable pu lse generate (ppg) mode in the ppg output mode, an arbitrary duty pulse is output by two timer registers. 13.4.6.1 setting setting the operation mode selection ta0mod to "011" activates the ppg output mode. select the source clock at ta0mod. sel ect continuous or one-shot ppg output at ta0cr. set the ppg output cycle at ta0dra and set the time until the output is reversed first at ta0drb. be sure to set register values so that ta0dra is larger than ta0drb. note that this mode uses the ppga0 pin. the ppga0 pin must be set to the output mode beforehand in port settings. set the initial state of the ppga0 pin at the timer flip-flop ta0cr. setting ta0cr to "1" selects the "h" level as the initial state of the ppga0 pin. setting ta0cr to "0" selects the "l" level as the initial state of the ppga0 pin. the operation is started by setting ta0cr to "1". after the timer is started, writing to ta0mod and ta0cr is disabled. be sure to complete the required mode settings before starting the timer. 13.4.6.2 operation after the timer is started, the up counter increments . when a match between the up counter value and the valu e set to timer register b (ta0drb) is detected, the ppga0 pin is changed to the "h" level if ta0cr is "0", or the ppga0 pin is changed to the "l" level if ta0cr is "1". subsequently, the up counter continues counting. when a match between the up counter value and the value set to timer register a (ta0dra) is detected, the ppga0 pin is changed to the "l" level if ta0cr is "0", or the ppga0 pin is changed to the "h" level if ta0cr is "1". at this time, an intta0 interrupt request occurs. if the ppg output control ta0cr is set to "1" (one-shot), ta0cr is automatically cleared to "0" and the timer stops. if ta0cr is set to "0" (continuous), the up counter is cleared to "0000h" and continues counting and ppg output. when ta0cr is set to "0" (including the auto stop by the one-shot operation) during the ppg output, the ppga0 pin returns to the level set in ta0cr. ta0cr can be changed during the operation. changing ta0cr from "1" to "0" during the operation cancels the one-shot operation and enables the continuous operation. changing ta0cr from "0" to "1 " during the operation clears ta0c r to "0" and stops the timer automatically after the cu rrent pulse output is completed. timer registers a and b can be set to the double buffer. setting ta0cr to "1" enables the double buffer. when the values set to ta0dra and ta0drb are changed during the ppg output with the double buffer enabled, the writing to ta0dra and ta0drb will not immediately become effective but will become effective when a match between ta0dra and the up counter is detected. if the double buffer is disabled, the writing to ta0dra and ta0drb will become effective immediately. if the written value is smaller than the up counter value, the up counter overflows. after a cycle, the counter match process is executed to reverse the output.
page 151 TMP89FH46 ra001 13.4.6.3 register buffer configuration (1) temporary buffer the TMP89FH46 contains an 8-bit temporary bu ffer. when a write instruction is executed on ta0dral (ta0drbl), the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. subsequently, when a write instruction is executed on ta0drah (ta0drbh), the set value is stored into the double buffer or ta0drah (ta0drbh). at the same time, the set value in the temporary buffer is stored into the double buffer or ta0dral (ta0drbl). (this structure is desi gned to enable the set values of the lower-level register and the higher-level register simultaneously.) therefore, when setting data to ta0dra (ta0drb), be sure to write the data into ta0dral and ta0drah (ta0drbl and ta0drbh) in this order. see figure 13-1 for the tempor ary buffer configuration. (2) double buffer in the TMP89FH46, the double buffer can be used by setting ta0cr. setting ta0cr to "0" disables the double buffer. setting ta0cr to "1" enables the double buffer. see figure 13-1 for the double buffer configuration. - when the double buffer is enabled when a write instruction is executed on ta0drah (ta0drbh) during the timer opera- tion, the set value is first stored into the double buffer, and ta0drah/l are not updated immediately. ta0drah/l (ta0drbh/l) compare the last set values to the counter value. if a match is detected, an inttca0 interrupt request is generated and the double buffer set value is stored into ta0drah/l (ta0drbh/l). subsequently, the match detection is exe- cuted using a new set value. when a read instruction is executed on ta0drah/l (ta0drbh/l), the double buffer value (the last set value) is read, not the ta0drah/l (ta0drbh/l) values (the current effective values). when a write instruction is executed on ta0drah/l (ta0drbh/l) while the timer is stopped, the set value is immediately stored into both the double buffer and ta0drah/l (ta0drbh/l). - when the double buffer is disabled when a write instruction is executed on ta0drah (ta0drbh) during the timer opera- tion, the set value is immediately stored in ta0drah/l (ta0drbh/l). subsequently, the match detection is executed using a new set value. if the values set to ta0drah/l (ta0drbh/l) are smaller than the up counter value, the up counter overflows and the match detection is executed using a new set value. as a result, the output pulse width may be longer than the set time. if that is a problem, enable the double buffer. when a write instruction is executed on ta0drah/l (ta0drbh/l) while the timer is stopped, the set value is immediately stored into ta0drah/l (ta0drbh/l).
page 152 13. 16-bit timer counter (tca) 13.4 timer function TMP89FH46 ra001 figure 13-8 ppg mode timing chart source clock counter timer start 1 0 n m m (duty pulse) m (duty pulse) n (1 cycle) r (duty pulse) s (1 cycle) s r write to ta0dral, h write to ta0drbl, h ta0dral, h match detection match detection write n write s write m write r becomes the level set at ta0tff when the timer is stopped reflected by an interrupt request returns to the level set at ta0tff counter clear inttca interrupt request 2m 1 m+1 n 00 ta0drbl, h ta0cr timer stop match detection match detection counter clear 2r 1 r+1 r r+1 s 0 match detection ta0mod ppg0 pin output continuous (ta0cr=?0?) double buffer (ta0mod=?1?) r (duty pulse) source clock counter timer start 1 0 n m n (1 cycle) write to ta0dral, h write to ta0drbl, h ta0dral, h match detection match detection write n write m becomes the level set at ta0tff when the timer is stopped returns to the level set at ta0tff counter clear inttca interrupt request 2m m+1 n 0 ta0drbl, h ta0cr timer stops automatically ta0mod ppg0 pin output one-shot (ta0cr=?1?)
page 153 TMP89FH46 ra001 13.5 noise canceller the digital noise canceller can be used in the operation modes that use the tca0 pin. 13.5.1 setting when the digital noise canceller is used, the input level is sampled at the sampling intervals set at ta0cr. when the same level is detected thr ee times consecutively, the level of the input to the timer is changed. setting ta0cr to any values than "00" allows the noise canceller to start operation, regardless of the ta0cr value. when the noise canceller is used, allow the timer to start after a period of time that is equal to four times the sampling interval after ta0cr is set ha s elapsed. this stabilizes the input signal. set ta0cr while the timer is stopped (ta0cr = "0"). when ta0cr is "1", writing is ignored. in the slow 1/2 or sleep 1 mode, setting ta0cr to "11" selects fs/2 as the source clock for the operation. setting ta0cr to "00" disables the noise canceller. setting ta0cr to "01" or "10" disables the tca0 pin input. table 13-4 noise cancel time ( fcgck = 10 [mhz] ) ta0nc sampling interval time removed as noise time regarded as signal 00 none - - 01 200 ns (2/fcgck) 600 ns or less 800 ns or more 10 400 ns (4/fcgck) 1.2 s or less 1.6 s or more 11 25.6 s (256/fcgck) 76.8 s or less 102.4 s or more
page 154 13. 16-bit timer counter (tca) 13.5 noise canceller TMP89FH46 ra001
page 155 TMP89FH46 ra002 14. 8-bit timer counter (tc0) the TMP89FH46 contains 4 channels of high-performance 8-bit timer counters (tc0). each timer can be used for time measurement and pulse output with a prescribed width. two 8-bit timer counters are cascadable to form a 16-bit timer. this chapter describes 2 channels of 8-bit timer counters 00 a nd 01. for 8-bit timer counters 02 and 03, replace the sfr addresses and pin names as shown in table 14-1 and table 14-2. table 14-1 sfr address assignment 16-bit mode t0xreg (address) t0xpwm (address) t0xmod (address) t0xxcr (address) low power consumption register timer counter 00 lower t00reg (0x0026) t00pwm (0x0028) t00mod (0x002a) t001cr (0x002c) poffcr0 timer counter 01 higher t01reg (0x0027) t01pwm (0x0029) t01mod (0x002b) timer counter 02 lower t02reg (0x0f88) t02pwm (0x0f8a) t02mod (0x0f8c) t023cr (0x0f8e) poffcr0 timer counter 03 higher t03reg (0x0f89) t03pwm (0x0f8b) t03mod (0x0f8d) table 14-2 pin names timer input pin pwm output pin ppg output pin timer counter 00 tc00 pin pwm0 pin ppg0 pin timer counter 01 tc01 pin pwm1 pin ppg1 pin timer counter 02 tc02 pin pwm2 pin ppg2 pin timer counter 03 tc03 pin pwm3 pin ppg3 pin
page 156 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.1 configuration figure 14-1 8-bit time r counters 00 and 01 t01reg selector selector selector selector reading and writing of t01reg reading and writing of t01pwm t01pwm internal bus 01 0 0 0 1 1 1 comparator comparator 8-bit up counter 8-bit up counter comparator comparator t00reg dbe1 fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8 fcgck/2 6 fcgck/2 4 fcgck/2 2 fcgck/2 fc or fs/2 2 i a b c d e f g h y s0 s1 1 0 y s 0 1 y s 1 0 y s selector selector selector selector overflow clear count up count up clear overflow timer/event count modes 8/16-bit ppg mode reading and writing of t00reg reading and writing of t00pwm t00pwm double buffer double buffer double buffer double buffer 01 0 0 0 1 1 1 intt01 interrupt request ppg1 pwm1 pin output tff1 internal bus t01mod t001cr 2 tck1 ein1 tff0 tcm0 dbe0 dbe1 tcm1 tff1 outand tcas tc00run tc01run t00mod tck0 ein0 2 2 2 tc00 pin input fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8 fcgck/2 6 fcgck/2 4 fcgck/2 2 fcgck/2 fc or fs/2 2 i a b c d e f g h y s0 s1 tc01 pin input 8-bit pwm mode counter f/f 12-bit pwm mode 8-bit pwm mode counter 12-bit pwm mode timer/event count modes 8-bit ppg mode tcas tcas tcas intt00 interrupt request 16-bit ppg mode ppg0 pwm0 pin output f/f 1 0 y s outand tff0
page 157 TMP89FH46 ra002 14.2 control 14.2.1 timer counter 00 the timer counter 00 is controlled by the timer counter 00 mode regist er (t00mod) and two 8-bit timer reg- isters (t00reg and t00pwm). note 1: for the configuration of t00pwm in the 8-bit and 12-bit pwm modes, refer to "14.4.3 8-bit pulse width modulation (pwm) output mode" and "14.4.7 12-bit pulse width modulation (pwm) output mode". timer register 00 t00reg 15 14 13 12 11 10 9 8 (0x0026) bit symbol t00reg read/write r/w after reset11111111 timer register 00 t00pwm 76543210 (0x0028) bit symbol t00pwm read/write r/w after reset11111111
page 158 14. 8-bit timer counter (tc0) TMP89FH46 ra002 note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: set t00mod while the timer is stopped. writing da ta into t00mod is invalid during the timer operation. note 3: in the 8-bit timer/event modes, the tff0 setting is invalid. in this mode, when the pwm0 and ppg0 pins are set as the function output pins in the port setting, the pins always output the "h" level. note 4: when ein0 is set to "1" and the external clock input is selected as the source clock, the tck0 setting is ignored. note 5: when the t001cr bit is "1", timer 00 operates in the 16-bit mode. the t00mod setting is invalid and timer 00 cannot be used independently in this mode. when the pwm0 and ppg0 pins are set to the function output pins in the port setting, the pins always output the "h" level. note 6: when the 16-bit mode is selected at t001cr, the ti mer start is controlled at t001cr. timer 00 is not started by writing data into t001cr. timer counter 00 mode register t00mod 76543210 (0x002a) bit symbol tff0 dbe0 tck0 ein0 tcm0 read/write r/w r/w r/w r/w r/w after reset11000000 tff0 timer f/f0 control 0 1 clear set dbe0 double buffer control 0 1 disable the double buffer enable the double buffer tck0 operation clock selection normal1/2 or idle1/2 mode slow1/2 or sleep1 mode syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 001 fcgck/2 10 fs/2 3 fs/2 3 010 fcgck/2 8 fcgck/2 8 - 011 fcgck/2 6 fcgck/2 6 - 100 fcgck/2 4 fcgck/2 4 - 101 fcgck/2 2 fcgck/2 2 - 110 fcgck/2 fcgck/2 - 111 fcgck fcgck fs/2 2 ein0 selection for using external source clock 0 1 select the internal clock as the source clock. select an external clock as the source clock. (the falling edge of the tc00 pin) tcm0 operation mode selection 00 8-bit timer/event counter modes 01 8-bit timer/event counter modes 10 8-bit pulse width modulation output (pwm) mode 11 8-bit programmable pulse generate (ppg) mode
page 159 TMP89FH46 ra002 14.2.2 timer counter 01 timer counter 01 is controlled by timer counter 01 mode register (t01mod) and two 8-bit timer registers (t01reg and t01pwm). note 1: for the configuration of t00pwm in the 8-bit and 12-bit pwm modes, refer to "14.4.3 8-bit pulse width modulation (pwm) output mode" and "14.4.7 12-bit pulse width modulation (pwm) output mode". timer register 01 t01reg 15 14 13 12 11 10 9 8 (0x0027) bit symbol t01reg read/write r/w after reset11111111 timer register 01 t01pwm 76543210 (0x0029) bit symbol t01pwm read/write r/w after reset11111111
page 160 14. 8-bit timer counter (tc0) TMP89FH46 ra002 note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: set t01mod while the timer is stopped. writing da ta into t01mod is invalid during the timer operation. note 3: in the 8-bit timer/event modes, the tff1 setting is invalid. in this mode, when the pwm1 and ppg1 pins are set as the function output pins in the port setting, the pins always output the "h" level. note 4: when ein1 is set to "1" and the external clock input is selected as the source clock, the tck1 setting is ignored. timer counter 01 mode register t01mod 76543210 (0x002b) bit symbol tff1 dbe1 tck1 ein1 tcm1 read/write r/w r/w r/w r/w r/w after reset11000000 tff1 timer f/f1 control 0 1 clear set dbe1 double buffer control 0 1 disable the double buffer enable the double buffer tck1 operation clock selection normal1/2 or idle1/2 mode slow1/2 or sleep1 mode syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 001 fcgck/2 10 fs/2 3 fs/2 3 010 fcgck/2 8 fcgck/2 8 - 011 fcgck/2 6 fcgck/2 6 - 100 fcgck/2 4 fcgck/2 4 - 101 fcgck/2 2 fcgck/2 2 - 110 fcgck/2 fcgck/2 - 111 fcgck fcgck fs/2 2 ein1 selection for using external source clock 0 1 select the internal clock as the source clock. select an external clock as the source clock. (the falling edge of the tc01 pin) tcm1 operation mode selection t001cr="0" (8-bit mode) t001cr="1" (16-bit mode) 00 8-bit timer/event counter modes 16-bit timer/event counter modes 01 8-bit timer/event counter modes 16-bit timer/event counter modes 10 8-bit pulse width modulation out- put (pwm) mode 12-bit pulse width modulation out- put (pwm) mode 11 8-bit programmable pulse gener- ate (ppg) mode 16-bit programmable pulse gener- ate (ppg) mode
page 161 TMP89FH46 ra002 14.2.3 common to ti mer counters 00 and 01 timer counters 00 and 01 have the low power consumption register (poffcr0) and timer 00 and 01 control registers in common. low power consumption register 0 poffcr0 76543210 (0x0f74) bit symbol - - tc023en tc001en - - tca1en tca0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 tc023en tc02,03 control 0 1 disable enable tc001en tc00,01 control 0 1 disable enable tca1en tca1 control 0 1 disable enable tca0en tca0 control 0 1 disable enable
page 162 14. 8-bit timer counter (tc0) TMP89FH46 ra002 note 1: when stop mode is started, t00run and t01run are cl eared to "0" and the timers stop. set t001cr again to use tim- ers 00 and 01 after stop mode is released. note 2: when a read instruction is executed on t001cr, bits 7 to 4 are read as "0". note 3: when outand is "1", output is obtained from the pwm1 and ppg1 pins only. there is no timer output to the pwm0 and ppg0 pins. if the pwm0 and ppg0 pins are set as the function output pins in the port setting, the pins always output "h". note 4: outand and tcas can be changed only when both tc01run and tc00run are "0". when either tc01run or tc00run is "1" or both are "1", the register values rema in unchanged by executing write instructions on outand and tcas. outand and tcas can be changed at the same time as tc01run and tc00run are changed from "0" to "1". timer counter 01 control register t001cr 76543210 (0x002c) bit symbol ----outandtcast01runt00run read/writerrrrr/wr/wr/wr/w after reset00000000 outand timers 00 and 01 output control 0 1 output the timer 00 output from the pwm0 and ppg0 pins and the timer 01 output from the pwm1 and ppg1 pins. output a pulse that is a logical anded product of the outputs of timers 00 and 01 from the pwm1 and ppg1 pins. tcas timers 00 and 01 cascade control 0 1 use timers 00 and 01 independently (8-bit mode). cascade timers 00 and 01 (16-bit mode). t01run timer 01 control timers 00/01 control (16-bit mode) 0 1 stop and clear the counter start t00run timer 00 control 0 1 stop and clear the counter start
page 163 TMP89FH46 ra002 14.2.4 operation modes and usable source clocks the operations modes of the 8-bit timers an d the usable source clocks are listed below. note 1: : usable, -: unusable note 2: set the source clock in the 16-bit modes on the tc01 side (tck1). note 3: when the low-frequency clock, fs, is not oscillating, it must not be selected as the source clock. if fs is selected whe n it is not oscillating, no source clock is supplie d to the timer, and the timer remains stopped. note 4: i=0, 1 (i=0 only in the 16-bit modes) note 5: the operation modes of the 8-bit timers and the usable source cl ocks are listed below. note 1: : usable, -: unusable note 2: set the source clock in the 16-bit modes on the tc01 side (tck1). note 3: i=0, 1 (i=0 only in the 16-bit modes) table 14-3 operation modes and usable source clocks (normal1/2 and idle1/2 modes) tck0 000 001 010 011 100 101 110 111 tc0i pin input operation mode fcgck/2 11 or fs/2 4 fcgck/2 10 or fs/2 3 fcgck/2 8 fcgck/2 6 fcgck/2 4 fcgck/2 2 fcgck/2 fcgck 8-bit timer modes 8-bit timer ??????? - 8-bit event counter - - - - - - - - 8-bit pwm ??????? - 8-bit ppg ??????? - 16-bit timer modes 16-bit timer ??????? - 16-bit event counter -------- 12-bit pwm ???????? 16-bit ppg ???????? table 14-4 operatio n modes and usable source clocks (slow1 /2 and sleep1 modes) tck0 000 001 010 011 100 101 110 111 tc0i pin input operation mode fs/2 4 fs/2 3 ----- fs/2 2 8-bit timer modes 8-bit timer ? ----- - 8-bit event counter - - - - - - - - 8-bit pwm ? ----- - 8-bit ppg ? ----- - 16-bit timer modes 16-bit timer ? ----- - 16-bit event counter -------- 12-bit pwm ? ----- ? 16-bit ppg ? ----- ?
page 164 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.3 low power consumption function timer counters 00 and 01 have the low power consumpti on registers (poffcr0) that save power when the timers are not used. setting poffcr0 to "0" disables the basic clock supply to timer counters 00 and 01 to save power. note that this renders the timers unusable. setting po ffcr0 to "1" enable s the basic clock supply to timer counters 00 and 01 and allows the timers to operate. after reset, poffcr0 are initialized to "0", and this makes the timers unu sable. when using the tim- ers for the first time, be sure to set poffcr0 to "1" in the initial setting of the program (before the timer control registers are operated). do not change poffcr0 to "0" during the timer operation. otherwise timer counters 00 and 01 may operate unexpectedly.
page 165 TMP89FH46 ra002 14.4 functions timer counters tc00 and tc01 have 8-bit modes in which they are used independently and 16-bit modes in which they are cascaded. the 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, the 8-bit pulse width modulation output (pwm) mode and the 8-bit programmable pulse generated output (ppg) mode. the 16-bit modes include four operation modes; the 16-bit timer mode, the 16-bit event counter mode, the 12-bit pwm mode and the 16-bit ppg mode. 14.4.1 8-bit timer mode in the 8-bit timer mode, the up-counter counts up using the internal clock, and interrupts can be generated regularly at specified times. the operation of tc00 is described below, and the same applies to the operation of tc01. (replace tc00- by tc01-). 14.4.1.1 setting tc00 is put into the 8-bit timer mode by se tting t00mod to "00" or "01", t001cr to "0" and t00mod to "0". select the so urce clock at t00mod. set the count value to be used for the match detection as an 8- bit value at the timer register t00reg. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod becomes invalid. be sure to complete the required mode settings before starting the timer. 14.4.1.2 operation setting t001cr to "1" allows the 8-bit up counter to increment based on the selected inter- nal source clock. when a match between the up coun ter value and the t00reg set value is detected, an intt00 interrupt request is generated and the up counte r is cleared to "0x00". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x00". 14.4.1.3 double buffer the double buffer can be used for t00reg by setting t00mod. the double buffer is disabled by setting t00mod to "0" or enabled by setting t00mod to "1". ? when the double buffer is enabled when a write instruction is executed on t00reg during the timer operation, the set value is initially stored in the double buffer, and t00reg is not immediately updated. t00reg com- pares the previous set value with the up counte r value. when the values match, an intt00 interrupt request is generated and the double buffer set value is stored in t00reg. subse- quently, the match detection is executed using a new set value. when a write instruction is ex ecuted on t00reg while the timer is stopped, the set value is immediately stored in both the double buffer and t00reg. ? when the double buffer is disabled when a write instruction is executed on t00reg during the timer operation, the set value is immediately stored in t00reg. subsequently, the match detection is executed using a new set value.
page 166 14. 8-bit timer counter (tc0) TMP89FH46 ra002 if the value set to t00reg is smaller than the up counter value, the match detection is exe- cuted using a new set value after the up counter overflows. therefore, the interrupt request interval may be longer than the selected time. if the value set to t00reg is equal to the up counter value, the match detection is executed immediately after data is written into t00reg. therefore, the interrupt request interval may no t be an integral multiple of the source clock (figure 14-3). if these are pr oblems, enable the double buffer. when a write instruction is ex ecuted on t00reg while the timer is stopped, the set value is immediately stored in t00reg. when a read instruction is executed on t00reg, the la st value written into t00reg is read out, regard- less of the t00mod setting. table 14-5 8-bit timer mode resolution and maximum time setting t00mod source clock [hz] resoluti on maximum time setting normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8 s488.2 s 52.2ms 124.5ms 001 fcgck/2 10 fs/2 3 fs/2 3 102.4 s244.1 s 26.1ms 62.3ms 010 fcgck/2 8 fcgck/2 8 -25.6 s - 6.5ms - 011 fcgck/2 6 fcgck/2 6 -6.4 s - 1.6ms - 100 fcgck/2 4 fcgck/2 4 -1.6 s - 408 s- 101 fcgck/2 2 fcgck/2 2 - 400ns - 102 s- 110 fcgck/2 fcgck/2 - 200ns - 51 s- 111 fcgck fcgck fs/2 2 100ns 122.1 s25.5 s31.1ms (example) operate tc00 in the 8-bit timer mode with the operation clock of fcgck/2 2 [hz] and generate interrupts at 64 s intervals (fcgck = 10 mhz) ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xe8 ; selects the 8-bit timer mode and fcgck/2 2 ld (t00reg),0xa0 ; sets the timer register (64 s / (2 2 /fcgck) = 0xa0) set (t001cr).0 ; starts tc00
page 167 TMP89FH46 ra002 figure 14-2 timer mode timing chart figure 14-3 operation when t00reg and the up coun ter have the same value source clock counter timer start 1 0 m write to t00reg match detection write m write n reflected by writing to t00reg reflected by writing to t00reg reflected by an interrupt reflected at the same time as data is written into t00reg while the timer is stopped counter clear intt00 interrupt request 234 m-1 m 01 n 01 220 3 t00reg t001cr n timer stop match detection counter clear n-1 t00mod when the double buffer is disabled (t00mod=?0?) source clock counter timer start 1 0 m write to t00reg match detection write m write n counter clear intt00 interrupt request 234 m-1 m 01 m 01 23 t00reg t001cr n m double buffer n match detection match detection counter clear 01 m-1 n n-1 t00mod when the double buffer is enabled (t00mod=?1?) source clock counter n-4 n-5 n-2 n write to t00reg write n-2 intt00 interrupt request n-3 n-2 0 1 2 t00reg match detection counter clear t00mod
page 168 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.2 8-bit event counter mode in the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the tc00 or tc01 pin. the operation of tc00 is described below, and the same applies to the operation of tc01. 14.4.2.1 setting tc00 is put into the 8-bit event counter mode by setting t00mod to "00", t001cr to "0" and t00mod to "1". set the count value to be used for the match detection as an 8-bit value at the timer register t00reg. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod becomes invalid. be sure to complete the required mode settings before starting the timer. 14.4.2.2 operation setting t001cr to "1" allows the 8-bit up counter to increment at the falling edge of the tc00 pin. when a match between the up-counter valu e and the t00reg set value is detected, an intt00 interrupt request is generated and the up counter is cleared to "0x00". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x00". the maximum frequency to be supplied is fcgck/2 2 [hz] (in normal1/2 or idle1/2 mode) or fs/24 [hz] (in slow1/2 or sleep1 mode), and a pulse widt h of two machine cycles or more is required at both the "h" and "l" levels. 14.4.2.3 double buffer refer to "14.4.1.3 double buffer". (example) operate tc00 in the 8-bit event counter mode and generate an interrupt each time 16 falling edges are detected at the tc00 pin. ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xc4 ; selects to the 8-bit event counter mode ld (t00reg),0x10 ; sets the timer register set (t001cr).0 ; starts tc00
page 169 TMP89FH46 ra002 figure 14-4 event count er mode timing chart tc00 pin input counter timer start when the double buffer is disabled (t00mod=?0?) 1 0 m write to t00reg match detection write m write n reflected by writing to t00reg reflected by writing to t00reg counter clear intt00 interrupt request 23 4 m-1 m 01 n 01 220 3 t00reg t001cr n timer stop match detection counter clear n-1
page 170 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.3 8-bit pulse width modulation (pwm) output mode the pulse-width modulated pulses with a resolution of 7 bits are output in the 8-bit pwm mode. an addi- tional pulse can be added to the 2 n-th duty pulse. this enables pwm output with a resolution nearly equiva- lent to 8 bits. (n=1, 2, 3...) the operation of tc00 is described below, and the same applies to the operation of tc01. 14.4.3.1 setting tc00 is put into the 8-bit pwm mode by setti ng t00mod to "10" and t001cr to "0". set t00mod to "0" and select the clock at t00mod. set the count value to be used for the match detection and the additional pulse value at the pwm register t00pwm. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod becomes invalid. be sure to complete the required mode settings before starting the timer. in the 8-bit pwm mode, the t00pwm re gister is confi gured as follows: pwmduty is a 7-bit register used to set the duty pulse width value (the time before the first output change) in a cycle (128 co unts of the source clock). pwmad is a register used to set the additional pu lse. when pwmad is "1", an additional pulse that corresponds to 1 count of the source clock is added to the 2 n-th duty pulse (n=1, 2, 3...). in other words, the 2 n-th duty pulse has the output of pwmduty+1. the additional pulse is not added when pwmad is "0". timer register 00 t00pwm 76543210 (0x0028) bit symbol pwmduty pwmad read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset11111111 timer register 01 t01pwm 76543210 (0x0029) bit symbol pwmduty pwmad read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset11111111
page 171 TMP89FH46 ra002 figure 14-5 pwm0 pulse output set the initial state of the pwm0 pin at t00mod. setting t00mod to "0" selects the "l" level as the initial state of the pwm0 pin. setting t00mod to "1" selects the "h" level as the initial state of the pwm0 pin. if the pwm0 pin is set as the function output pin in the port setting while the timer is stopped, the value of t 00mod is output to the pwm0 pin. table 14-6 shows the list of output levels of the pwm0 pin. and by setting "1" to t001cr bit, a logical product (and) pulse of tc00 and tc01?s out- put can be output to pwm0 pin. by using this function, the remote-control waveform can be created eaily. 14.4.3.2 operations setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the lower 7 bits of the up counter value and the value set to t00pwm is detected, the output of the pwm0 pin is reversed. when t00mod is "0", the pwm0 pin changes from the "l" to "h" leve l. when t00mod is "1", the pwm0 pin changes from the "h " to "l" level. if t00pwm is "1", an additional pulse th at corresponds to 1 count of the source clock is added at the 2 n-th match detection (n=1, 2, 3...). in other words, the pwm0 pin output is reversed at the timing of t00pwm+1. when t00mod is "0", the period of the "l" level becomes longer than the value set to t00 by 1 source clock. when t00mod is "1", the period of the "h" level becomes longer th an the value set to t00p wm by 1 source clock. this function allows two cycles of output puls es to be handled with a resolution nearly equivalent to 8 bits. no additional pulse is inserted when t00pwm is "0". table 14-6 list of output levels of pwm0 pin tff0 pwm0 pin output level before the start of operation (initial state) t00pwm matched (after the addi- tional pulse) overflow operation stopped (initial state) 0lhll 1hlhh t00pwm timer start additional pulse (duty pulse width) 128 counts (cycle width) 128 counts (cycle width) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 pwm0 pin output (tff0=?1?) t00pwm (duty pulse width) additional pulse additional pulse pwm0 pin output (tff0=?0?) intt00 interrupt request
page 172 14. 8-bit timer counter (tc0) TMP89FH46 ra002 subsequently, the up counter continues counting up. when the up counter value reaches 128, an over- flow occurs and the up counte r is cleared to "0x00". at the same time, the output of the pwm0 pin is reversed. when t00mod is "0", the pwm0 pin changes from the "h" to "l" level. when t00mod is "1", the pwm0 pin changes from the "l" to "h" level. if the 2 n-th overflow occurs at this time, an intt00 interrupt request is genera ted. (no interrupt request is generated at the 2 n-th -1 overflow.) subsequently, the up counter continues counting up. when t001cr is set to "0" during the timer operation, the up counter is stopped and cleared to "0x00". the pwm0 pin returns to the level selected at t00mod. figure 14-6 8-bit pw m mode timing chart (example) operate tc00 in the 8-bit pwm mode with the operation clock of fcgck/2 and output a duty pulse nearly equivalent to 11.6 s (fcgck = 10 mhz) (actually, output a total duty pulse of 23.2 s in 2 cycles (102.4 s)) set (p7fc).0 ; sets p7fc0 to "1" set (p7cr).0 ; sets p7cr0 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xf2 ; selects the 8-bit pwm mode and fcgck/2 ld (t00pwm),0x73 ; sets the timer register (duty pulse) ; (11.6 s 2) / (2/fcgck) = 0x73 set (t001cr).0 ; starts tc00 source clock counter timer start 1 0 m m m (duty pulse) 128 counts (cycle 1) 128 counts (cycle 2) 128 counts (cycle 3) 128 counts (cycle 4) rs rs write to t00pwm double buffer write m write r write s becomes the level selected at tff0 while the timer is stopped reflected by an interrupt request interrupt request reflected by an interrupt request returns to the level selected at tff0 intt00 interrupt request 1 m+1 m0 t00pwm t00pwm t001cr no interrupt request is generated no interrupt request is generated 128 timer stop match detection m+1 m 1 0 128 r+1 r 1 0 128 r+1 r 1 00 128 match detection match detection counter clear overflow overflow overflow counter clear counter clear counter clear t00mod pwm0 pin output when the double buffer is enabled (t00mod=1) m (duty pulse) r (duty pulse) r+1 (duty pulse) additional pulse match detection
page 173 TMP89FH46 ra002 14.4.3.3 double buffer the double buffer can be used for t00pwm by setting t00mod. the double buffer is dis- abled by setting t00mod to "0" or enabled by setting t00mod to "1". ? when the double buffer is enabled when a write instruction is ex ecuted on t00pwm during the timer operation, the set value is first stored in the double buffer, and t00pwm is not updated immediately. t00pwm compares the previous set value with th e up counter value. when the 2 n-th overflow occurs, an intt00 interrupt request is generated and the double buffer set value is stored in t00pwm. subsequently, the match detection is executed using a new set value. when a read instruction is executed on t00pwm, the value in the double buffer (the last set value) is read out, not the t00pwm value (the currently effective value). when a write instruction is ex ecuted on t00pwm while the timer is stopped, the set value is immediately stored in both the double buffer and t00pwm. ? when the double buffer is disabled when a write instruction is ex ecuted on t00pwm during the timer operation, the set value is immediately stored in t00pwm. subsequently, the match detection is executed using a new set value. if the value set to t00pwm is smaller than the up counter value, the pwm0 pin is not reversed until the up counter overflows and a match detection is executed using a new set value. if the value set to t00pwm is equal to the up counter value, the match detection is exe- cuted immediately after data is written into t00pwm. therefore, the timing of changing the pwm0 pin may not be an integral multiple of th e source clock (figure 14-7). similarly, if t00pwm is set during the additional pulse output, the timing of changing the pwm0 pin may not be an integral multiple of the source clock. if these are problems, enable the double buffer. when a write instruction is ex ecuted on t00pwm while the timer is stopped, the set value is immediately stored in t00pwm. figure 14-7 operation w hen t00pwm and the up count er have the same value source clock counter n-4 n-5 n-2 n write to t00pwm write n-2 pwm0 pin output n-3 n-2 n-1 n t00pwm match detection t00mod
page 174 14. 8-bit timer counter (tc0) TMP89FH46 ra002 table 14-7 resolutions and cycles in the 8-bit pwm mode t00mod source clock [hz] resolution 7-bit cycle (period 2) normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8 s488.2 s 26.2ms (52.4ms) 62.5ms (125ms) 001 fcgck/2 10 fs/2 3 fs/2 3 102.4 s244.1 s 13.1ms (26.2ms) 31.3ms (62.5ms) 010 fcgck/2 8 fcgck/2 8 -25.6 s- 3.3ms (6.6ms) - 011 fcgck/2 6 fcgck/2 6 -6.4 s- 819.2 s (1638.4 s) - 100 fcgck/2 4 fcgck/2 4 -1.6 s- 204.8 s (409.6 s) - 101 fcgck/2 2 fcgck/2 2 - 400ns - 51.2 s (102.4 s) - 110 fcgck/2 fcgck/2 - 200ns - 25.6 s (51.2 s) - 111 fcgck fcgck fs/2 2 100ns 122.1 s 12.8 s (25.6 s) 15.6ms (31.3ms)
page 175 TMP89FH46 ra002 14.4.4 8-bit programmable pul se generate (ppg) output mode in the 8-bit ppg mode, the pulses with arbitrary du ty and cycle are output by using the t00reg and t00pwm registers. by setting the t001cr register, a pulse that is a logical anded product of the tc00 and tc01 outputs can be output to the tc01 pin. this function f acilitates the generation of remote-controlled waveforms, for example. the operation of tc00 is described below, and the same applies to the operation of tc01. 14.4.4.1 setting tc00 is put into the 8-bit ppg mode by se tting t00mod to "10" and t001cr to "0". set t00mod to "0" and select the clock at t00mod. set the duty pulse width at t00pwm and the cycle width at t00reg. set t00mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t00mod becomes invalid. be sure to complete the required mode settings before starting the timer. figure 14-8 ppg0 pulse output set the initial state of the ppg0 pin at t00mod. setting t00mod to "0" selects the "l" level as the initial state of the ppg0 pin. setting t00mod to "1" selects the "h" level as the initial state of the ppg0 pin. if the ppg0 pin is set as the function output pin in the port setting while the timer is stopped, the value of t00mod is output to the ppg0 pin. table 14-8 shows the list of out- put levels of the ppg0 pin. setting the t001cr bit to "1" allows the ppg0 pin to output a pulse that is a logical anded product of the tc00 and tc01 outputs. table 14-8 list of output levels of ppg0 pin tff0 ppg0 pin output level before the start of operation (initial state) t00pwm matched t00reg matched operation stopped (initial state) 0lhll 1hlhh t00pwm timer start (duty pulse) (duty pulse) (1 cycle) (1 cycle) t00reg ppg0 pin output (tff0=?0?) ppg0 pin output (tff0=?1?) timer stop t00pwm t00reg
page 176 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.4.2 operation setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the internal up counter value and the value set to t00pwm is detected, the output of the ppg0 pin is reversed. when t00mod is "0", the ppg0 pin changes from the "l" to "h" level. when t00mod is "1", the ppg0 pin changes from the "h" to "l" level. subsequently, the up counter continues counting up. when a match between the up counter value and t00reg is detected, the output of the ppg0 pin is reversed again. when t00mod is "0", the ppg0 pin changes from the "h" to "l" le vel. when t00mod is "1", the ppg0 pin changes from the "l" to "h" level. at this time, an intt00 interrupt request is generated. when t001cr is set to "0" during the operation, the up counter is stopped and cleared to "0x00". the ppg0 pin returns to the level selected at t00mod. 14.4.4.3 double buffer the double buffer can be used for t00pwm and t00reg by setting t00mod. the double buffer is disabled by setting t00mod to "0" or enabled by setting t00mod to "1". ? when the double buffer is enabled when a write instruction is executed on t00p wm (t00reg) during the timer operation, the set value is first stored in the double buffer, and t00pwm (t00reg) is not updated immedi- ately. t00pwm (t00reg) compar es the previous set value with the up counter value. when an intt00 interrupt request is generated, the double buffer set value is stored in t00pwm (t00reg). subsequently, the match detection is executed using a new set value. when a read instruction is executed on t00p wm (t00reg), the value in the double buffer (the last set value) is read out, not the t00pwm (t00reg) value (the currently effective value). when a write instruction is executed on t00p wm (t00reg) while the timer is stopped, the set value is immediately stored in both the double buffer and t00pwm (t00reg). ? when the double buffer is disabled when a write instruction is executed on t00p wm (t00reg) during the timer operation, the set value is immediately stored in t00pwm (t00reg). subsequently, the match detection is executed using a new set value. if the value se t to t00pwm (t00reg) is smaller than the up counter value, the ppg0 pin is not reversed until the up counter overflows and a match detection is executed using a new set value. if the value set to t00pwm (t00reg) is equal to the up counter value, the match detection is executed immediately after data is written into t00pwm (t00reg). therefore, the timing of changing the ppg0 pin may not be an integral multiple of the source clock (figure 14-10). if these are problems, enable the double buffer. when a write instruction is executed on t00p wm (t00reg) while the timer is stopped, the set value is immediately stored in t00pwm (t00reg). (example) operate tc00 in the 8-bit ppg mode with the operation clock of fcgck/2 and output the 8 s duty pulse in 32 s cycles (fcgck = 10 mhz) set (p7fc).0 ; sets p7fc0 to "1" set (p7cr).0 ; sets p7cr0 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xf3 ; selects the 8-bit ppg mode and fcgck/2 ld (t00reg),0xa0 ; sets the timer register (cycle) ; 32 s / (2/fcgck) = 0xa0
page 177 TMP89FH46 ra002 figure 14-9 8-bit ppg mode timing chart figure 14-10 operation w hen t00pwm (t00reg) and the up counter have the same value ld (t00pwm),0x28 ; sets the timer register (duty pulse) ; 8 s / (2/fcgck) = 0x28 set (t001cr).0 ; starts tc00 source clock counter timer start 1 0 m m m (duty pulse) p (1 cycle) s (1 cycle) s (1 cycle) w (1 cycle) rt rs write to t00pwm double buffer match detection write m write r write t becomes the level selected at tff0 while the timer is stopped returns to the level selected at tff0 intt00 interrupt request 1 m+1 m0 t00pwm t001cr ps w write to t00reg double buffer write p write s write w p timer stop match detection r+1 r 1 0 s r+1 r 1 0 s t+1 t 1 00 w match detection match detection counter clear counter clear counter clear counter clear t00mod ppg0 pin output when the double buffer is enabled (t00mod=?1?) r (duty pulse) r (duty pulse) t (duty pulse) ps w t00reg match detection match detection match detection source clock counter n-4 n-5 n-2 n write to t00pwm (t00reg) write n-2 ppg0 pin output n-3 n-2 n-1 n t00pwm (t00reg) match detection t00mod
page 178 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.5 16-bit timer mode in the 16-bit timer mode, tc00 and tc 01 are cascaded to form a 16-bit tim er counter, which can measure a longer period than an 8-bit timer. 14.4.5.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit mode. all the set- tings of tc00 are ignored and those of tc01 are effective in the 16-bit mode. the 16-bit timer mode is activated by setting t01mod to "00" or "01" and t01mod to "0". select the source clock at t01mod. set the count value to be used for the match detect ion as a 16-bit value at the timer registers t00reg and t01reg. set the lower 8 bits of the 16-bit value at t00reg and the higher 8 bits at t01reg. (here- inafter, the 16-bit value specified by the combined setting of t01r eg and t00reg is indicated as t01+00reg.) the timer register settings are reflect ed on the double buffer or t01+00reg when a write instruction is executed on t01reg. be sure to execu te the write instructions on t00reg and t01reg in this order. (when data is written to the high-order register, the set values of the low-order and high-order registers become effect ive at the same time.) set t01mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t01mod becomes invalid. be sure to complete the required mode settings before starting the timer. (make settings when t001cr and are "0".) 14.4.5.2 operations setting t001cr to "1" allows the 16-bit up counter to increment based on the selected internal source clock. when a match between th e up counter value and the t00+01reg set value is detected, an intt01 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x0000". 14.4.5.3 double buffer the double buffer can be used for t01+00reg by setting t01mod. the double buffer is dis- abled by setting t01mod to "0" or enabled by setting t01mod to "1". ? when the double buffer is enabled when write instructions are executed on t00reg and t01reg in this order during the timer operation, the set value is first stored in the double buffer, and t01+00reg is not updated immediately. t01+00reg compares the previous set value with the up counter value. when the values are matched, an intt01 interrupt re quest is generated and the double buffer set value is stored in t01+00reg. subsequently, the match detection is executed using a new set value. when write instructions are executed on t00reg and t01reg in this order while the timer is stopped, the set value is immediately stored in both the double buffer and t01+00reg. ? when the double buffer is disabled when write instructions are executed on t00reg and t01reg in this order during the timer operation, the set value is im mediately stored in t01+00reg. subsequently, the match detec- tion is executed using a new set value.
page 179 TMP89FH46 ra002 if the value set to t01+00reg is smaller than the up counter value, the match detection is executed using a new set value after the up counte r overflows. therefore, the interrupt request interval may be longer than the selected time. if the value set to t01+00reg is equal to the up counter value, the match detection is execu ted immediately after data is written into t01+00reg. therefore, the interrupt request inte rval may not be an integral multiple of the source clock. if these are problems, enable the double buffer. when write instructions are executed on t00reg and t01reg in this order while the timer is stopped, the set value is immediately stored in t01+00reg. when a read instruction is executed on t01+00reg, th e last value written into t01+00reg is read out, regardless of the t00mod setting. (example) operate tc00 and tc01 in the 16-bit timer mode with the operation clock of fcgck/2 [hz] and generate interrupts at 96 s intervals (fcgck = 10 mhz) ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t01mod),0xf0 ; selects the 16-bit timer mode and fcgck/2 ld (t00reg),0xe0 ; sets the timer register (96 s / (2/fcgck) = 0x1e0) ld (t01reg),0x01 ; sets the timer register ld (t001cr),0x06 ; starts tc00 and tc001 (16-bit mode)
page 180 14. 8-bit timer counter (tc0) TMP89FH46 ra002 figure 14-11 16-bit timer counter timing chart source clock counter timer start 1 0 write to t00reg write m write r reflected by writing to t01reg reflected by writing to t01reg reflected by an interrupt reflected simultaneously by writing to t01reg while the timer is stopped counter clear intt01 interrupt request 234 km-1 km 01 sr 01 220 3 t001cr timer stop counter clear km write to t01reg match detection write k write s write to t01reg write k write s t01+00reg sr sr-1 t01mod when the double buffer is disabled (t01mod=?0?) source clock counter timer start 1 0 km write to t00reg match detection write m write r counter clear intt01 interrupt request 234 km-1 km 01 km 01 23 t01+00reg t001cr sr km double buffer sr match detection match detection counter clear 01 km-1 sr sr-1 t01mod when the double buffer is enabled (t01mod=?1?) reflected by writing to t01reg match detection
page 181 TMP89FH46 ra002 table 14-9 16-bit timer mode resolution and maximum time setting t01mod source clock [hz] resoluti on maximum time setting normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8 s488.2 s 13.4s 32s 001 fcgck/2 10 fs/2 3 fs/2 3 102.4 s244.1 s6.7s 16s 010 fcgck/2 8 fcgck/2 8 -25.6 s - 1.7s - 011 fcgck/2 6 fcgck/2 6 -6.4 s - 419.4ms - 100 fcgck/2 4 fcgck/2 4 -1.6 s - 104.9ms - 101 fcgck/2 2 fcgck/2 2 - 400ns - 26.2ms - 110 fcgck/2 fcgck/2 - 200ns - 13.1ms - 111 fcgck fcgck fs/2 2 100ns 122.1 s6.6ms 8s
page 182 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.6 16-bit event counter mode in the 16-bit event counter mode, the up counter counts up at the falling edge of the input to the tc00 pin. tc00 and tc01 are cascaded to form a 16-bit timer counter, which can measure a longer period than an 8-bit timer. 14.4.6.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit timer mode. all the settings of tc00 are ignored and those of tc 01 are effective in th e 16-bit timer mode. the 16-bit timer mode is activated by setting t01mod to "00" or "01" and t01mod to "1". set the count value to be used for the match detect ion as a 16-bit value at the timer registers t00reg and t01reg. set the lower 8 bits of the 16-bit value at t00reg and set the higher 8 bits at t01reg. (hereinafter, the 16-bit value specified by the combin ed setting of t01reg an d t00reg is indicated as t01+00reg.) the timer register settings are reflect ed on the double buffer or t01+00reg when a write instruction is executed on t01reg. be sure to execu te the write instructions on t00reg and t01reg in this order. (when data is written to the high-order register, the set values of the low-order and high-order registers become effect ive at the same time.) set t01mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t01mod becomes invalid. be sure to complete the required mode settings before starting the timer. (make settings when t001cr and are "0".) 14.4.6.2 operations setting t001cr to "1" allows the 16-bit up co unter to increment at th e falling edge of the tc00 pin. when a match between the up counter value and the t00+01reg set value is detected, an intt01 interrupt request is generated and the up counter is cleared to "0x0000". after being cleared, the up counter restarts counting. setting t001cr to "0" during the timer operation makes the up counter stop counting and be cleared to "0x0000". the maximum frequency to be supplied is fcgck/2 [hz] (in normal1/2 or idle1/2 mode) or fs/2 4 [hz] (in slow1/2 or sleep1 mode), and a pulse widt h of two machine cycles or more is required at both the "h" and "l" levels. 14.4.6.3 double buffer refer to 14.4.5.3. (example) operate tc00 and tc01 in the 16-bit event counter mode and generate an interrupt each time the 384th falling edge is detected at the tc00 pin ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t00mod),0xc4 ; selects the 16-bit event counter mode ld (t00reg),0x80 ; sets the timer register ld (t01reg),0x10 ; sets the timer register ld (t001cr),0x06 ; starts tc00 and tc001 (16-bit mode)
page 183 TMP89FH46 ra002 figure 14-12 16-bit event counter mode timing chart tc00 pin input counter timer start when the double buffer is disabled (t01mod=?0?) 1 0 km write to t00reg match detection write m write s reflected by writing to t01reg reflected by writing to t01reg counter clear write to t01reg write k write r intt00 interrupt request 23 4 km-1 km 01 rs 01 220 3 t01+00reg t001cr rs timer stop match detection counter clear counter clear rs-1 tc00 pin input counter timer start when the double buffer is enabled (t01mod=?1?) 1 0 km write to t00reg match detection write m write s reflected by writing to t01reg reflected by writing to t01reg counter clear write to t01reg write k write r intt00 interrupt request 23 4 km-1 km 01 km 01 21 3 t01+00reg t001cr rs km double buffer rs m a t c h d e t e c t i o n counter clear counter clear km-1 rs 0 rs-1 m a t c h d e t e c t i o n reflected by an interrupt
page 184 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.7 12-bit pulse width modulation (pwm ) output mode in the 12-bit pwm output mode, tc00 and tc01 are cascaded to output the pulse-width modulated pulses with a resolution of 8 bits. an additional pulse of 4 bits can be inserted, which enables pwm output with a res- olution nearly equivalent to 12 bits. 14.4.7.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit timer mode. all the settings of tc00 are ignored and those of tc 01 are effective in th e 16-bit timer mode. the 12-bit pwm mode is selected by setting t01mod to "10". to use the internal clock as the source clock, set t01mod to "0" and select the clock at t01mod. to use an external clock as the source clock, set t01mod to "1". set t01mod to "1" to use the double buffer. setting t001cr to "1" starts the operation. after the timer is started, writing to t01mod becomes invalid. be sure to complete the required mode settings before starting the timer. (make settings when t001cr and are "0".) set the count value to be used for the match detecti on and the additional pulse value as a 12-bit value at the timer registers t00pwm and t01pwm. set bits 11 to 8 of the 12-bit value at the lower 4 bits of t01pwm and set bits 7 to 0 at t00pwm. refer to the following table for the register configuration. here- inafter, the 12-bit value specified by the combined setting of t00pwm and t01pwm is indicated as t01+00pwm. the timer register setti ngs are reflected on the double buf fer or t01+00pwm when a write instruction is executed on t01pwm. be sure to ex ecute the write instructi ons on t00pwm and t01pwm in this order. (when data is written to the high-or der register, the set values of the low-order and high- order registers become eff ective at the same time.) bits 7 to 4 of t01pwm are not used in the 12-bit pwm mode. however, data can be written to these bits of t01pwm and the written values are read out as they are when th e bits are read. normally, set these bits to "0". pwmdutyh and pwmdutyl are 4-bit registers. they are combined to set an 8-bit value of duty pulse width (time before the first change in the outp ut) for one cycle (256 coun ts of the source clock). hereinafter, an 8-bit value specifi ed by the combined setting of pwmdutyh and pwmdutyl is indi- cated as pwmduty. pwmad3 to 0 are the additional pulse setting regist er. additional pulses can be inserted in specific cycles of the duty pulse by setting each bit to "1". the additional pulses are inserted in th e positions listed in table 14-10. pwmad 3 to 0 can be combined to specify the number of times of inserting the additional pulses in 16 cycles to any number from 1 to 16. examples of inserting additional pulses are shown in fig- ure 14-13. timer register 00 t00pwm 76543210 (0x0028) bit symbol pwmdutyl pwmad3 pwmad2 pwmad1 pwmad0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset11111111 timer register 01 t01pwm 76543210 (0x0029) bit symbol pwmdutyh read/write r/w r/w r/w r/w after reset11111111
page 185 TMP89FH46 ra002 set the initial state of the pwm1 pin at t01mod. setting t01mod to "0" selects the "l" level as the initial state of the pwm1 pin. setting t01mod to "1" selects the "h" level as the initial state of the pwm1 pin. if the pwm1 pin is set as the function output pin in the port setting while the timer is stopped, the value of t01mod is output to the pwm1 pin. table 14-11 shows the list of output levels of the pwm1 pin. table 14-10 cycles in which additional pulses are inserted cycles in which additional pulses are inserted among cycles 1 to 16 pwmad0="1" 9 pwmad1="1" 5, 13 pwmad2="1" 3, 7, 11, 15 pwmad3="1" 2, 4, 6, 8, 10, 12, 14, 16 table 14-11 list of output levels of pwm1 pin tff1 pwm1 pin output level before the start of operation (initial state) pwmduty matched (after the addi- tional pulse) overflow operation stopped (initial state) 0lhll 1hlhh
page 186 14. 8-bit timer counter (tc0) TMP89FH46 ra002 figure 14-13 examples of inserting additional pulses 14.4.7.2 operations setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the lower 8 bits of the up counter value and the value set to pwmduty is detected, the output of the pwm1 pin is reversed. when t01mod is "0", the pwm1 pin changes from the "l" to "h" level. when t01mod is "1", the pwm1 pin changes from the "h" to "l" level. if any of pwmad3 to 0 is "1", an additional puls e that corresponds to 1 count of the source clock is inserted in specific cycles of th e duty pulse. in other words, the pwm1 pin output is reversed at the timing of pwmduty+1. when t00mod is "0", the pe riod of the "l" level becomes longer than the value set to pwmduty by 1 source clock. when t0 0mod is "1", the period of the "h" level becomes longer than the value set to pwmduty by 1 source clock. this func tion allows 16 cycles of output pulses to be handled with a resolution nearly equivalent to 12 bits. no additional pulse is inserted when pwmad3 to 0 are all "0". subsequently, the up counter continues counting up. when the up counter value reaches 256, an over- flow occurs and the up counte r is cleared to "0x00". at the same time, the output of the pwm1 pin is reversed. when t01mod is "0", the pwm1 pin changes from the "h" to "l" level. when t01mod is "1", the pwm1 pin changes from the "l" to "h" level. at this time, an intt00 inter- timer start additional pulse 1234567891011121314151617 pwm1 pin output (tff1=?1?) timer stop timer stop pwm1 pin output (tff1=?0?) intt00 interrupt request intt01 interrupt request cycle when pwmad1=?1? additional pulse timer start 1234567891011121314151617 pwm1 pin output (tff1=?1?) pwm1 pin output (tff1=?0?) intt00 interrupt request intt01 interrupt request cycle when pwmad0 = ?1? and pwmad2 = ?1? additional pulse additional pulse additional pulse additional pulse additional pulse
page 187 TMP89FH46 ra002 rupt request is generated (an intt00 interrupt requ est is generated each time an overflow occurs.) an intt01 interrupt request is generated at the 16 n-th overflow (n=1, 2, 3...). subsequently, the up counter continues counting up. when t001cr is set to "0" during the timer operation, the up counter is stopped and cleared to "0x00". the pwm1 pin returns to the level selected at t01mod. when an external source clock is selected, input the clock at the tc00 pin. the maximum frequency to be supplied is fcgck/2 [hz] (in normal1/2 or idle1/2 mode) or fs/2 4 [hz] (in slow1/2 or sleep1 mode), and a pulse width of two m achine cycles or more is required at both the "h" and "l" levels. figure 14-14 pwm1 pin output 14.4.7.3 double buffer the double buffer can be used for t01+00pwm by setting t01mod. the double buffer is dis- abled by setting t01mod to "0" or enabled by setting t01mod to "1". ? when the double buffer is enabled when write instructions are executed on t0 0pwm and t01pwm in this order during the timer operation, the set value is first stored in the double buffer, and t01+00pwm is not updated immediately. t01+00pwm compares the previous set value with the up counter value. when the 16 n-th overflow occurs, an intt01 interrupt request is generated and the double buffer set value is stored in t01+00pwm. subs equently, the match detection is executed using a new set value. when a read instruction is executed on t01+00pwm (t00reg), the value in the double buffer (the last set value) is read out, not th e t01+00pwm value (the cu rrently effective value). when write instructions are executed on t00pwm and t01pwm in this order while the timer is stopped, the set value is immediately stored in both the double buffer and t01+00pwm. ? when the double buffer is disabled when write instructions are executed on t0 0pwm and t01pwm in this order during the timer operation, the set value is immediately stored in t01+00pwm. subsequently, the match detection is executed using a new set value. if the value set to t01+00pwm is smaller than the up counter value, the pwm1 pin is not reversed until the up counter overflows and a match detection is executed using a new set value. if the value set to t01+00pwm is equal to the up counter value, the match detection is execu ted immediately after data is written into t01+00pwm. therefore, the timing of changing the pwm1 pin may not be an integral multiple of the source clock. similarly, if t01+00pwm is set during the additional pulse output, the tim- ing of changing the pwm1 pin may not be an integral multiple of the source clock. if these are problems, enable the double buffer. pwmduty timer start additional pulse (1 source clock) (duty pulse width) 256 counts (cycle width) 256 counts (cycle width) pwm1 pin output (tff0=?1?) pwmduty (duty pulse width) pwm1 pin output (tff0=?0?)
page 188 14. 8-bit timer counter (tc0) TMP89FH46 ra002 when write instructions are executed on t00pwm and t01pwm in this order while the timer is stopped, the set value is immediately stored in t01+00pwm. figure 14-15 12-bit pwm mode timing chart (example) operate tc00 and tc01 in the 12-bit pwm mode with the operation clock of fcgck/2 and output a duty pulse nearly equiva- lent to 14.0625 s in 51.2 s cycles (fcgck = 10 mhz) (actually, output a duty pulse of 225 s in total in 16 cycles (819.2 s)) set (p7fc).1 ; sets p7fc1 to "1" set (p7cr).1 ; sets p7cr1 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t01mod),0xf2 ; selects the 16-bit pwm mode and fcgck/2 ld (t00pwm),0x65 ; sets the timer register (duty pulse) ; (14.0625 s 16) / (2/fcgck) = 0x465 ld (t00pwm),0x04 ; sets the timer register (duty pulse) ld (t001cr),0x06 ; starts tc00 and tc01 source clock counter timer start 1 0 km (0001) km km (duty pulse) 256 counts (cycle 1) 256 counts (cycle 2) 256 counts (cycle 9) 256 counts (cycle 16) (cycle 17) rs (0011) rs write to t00pwm double buffer match detection write m (0001) write s (0011) becomes the level selected at tff0 while the timer is stopped interrupt request interrupt reque s interrupt request write to t01pwm write k write r intt00 interrupt request intt00 interrupt request 1 km +1 km km +1 km km +1 km km +1 km 0 0001 0011 pwmduty pwmad3 ~ 0 t001cr 256 match detection 1 0 256 1 0 256 rs 1 0 256 match detection match detection counter clear overflow overflow overflow counter clear counter clear counter clear t00mod pwm0 pin output when the double buffer is enabled (t01mod=?1?) km (duty pulse) km (duty pulse) km+1 (duty pulse) rs (duty pulse) additional pulse interrupt request
page 189 TMP89FH46 ra002 table 14-12 resolutions and cycles in the 12-bit pwm mode t01mod source clock [hz] resolution 8-bit cycle (period 16) normal1/2 or idle1/2 mode slow1/2 or sleep1 mode fcgck=10mhz fs=32.768khz fcgck=10mhz fs=32.768khz syscr1 = "0" syscr1 = "1" 000 fcgck/2 11 fs/2 4 fs/2 4 204.8 s488.2 s 52.4ms (838.9ms) 125ms (2000ms) 001 fcgck/2 10 fs/2 3 fs/2 3 102.4 s244.1 s 26.2ms (419.4ms) 62.5ms (1000ms) 010 fcgck/2 8 fcgck/2 8 -25.6 s- 6.6ms (104.9ms) - 011 fcgck/2 6 fcgck/2 6 -6.4 s- 1.6ms (26.2ms) - 100 fcgck/2 4 fcgck/2 4 -1.6 s- 409.6 s (6.6ms) - 101 fcgck/2 2 fcgck/2 2 - 400ns - 102.4 s (1.6ms) - 110 fcgck/2 fcgck/2 - 200ns - 51.2 s (819.2 s) - 111 fcgck fcgck fs/2 2 100ns 122.1 s 25.6 s (409.6 s) 31.3ms (500ms)
page 190 14. 8-bit timer counter (tc0) TMP89FH46 ra002 14.4.8 16-bit programmable pul se generate (ppg) output mode in the 16-bit ppg mode, tc00 and tc01 are cascaded to output the pulses that have a resolution of 16 bits and arbitrary pulse width and duty. two 16-bit register s, t01+00reg and t01+00pwm, are used to output the pulses. this enables output of longer pulses than an 8-bit timer. 14.4.8.1 setting setting t001cr to "1" connects tc00 and tc01 and activates the 16-bit mode. all the set- tings of tc00 are ignored and those of tc01 are effective in the 16-bit mode. the 16-bit ppg mode is selected by setting t01mod to "11". to use the internal clock as the source clock, set t01mod to "0" and select the clock at t01mod. to use an external clock as the source clock, set t01mod to "1". set t01mod to "1" to use the double buffer. set the count value that corresponds to a cycle as a 16-bit value at the timer registers t01reg and t00reg. set the count value that co rresponds to a duty pulse as a 16-bit value at t01pwm and t00pwm (hereinafter, the 16-bit value specified by the combin ed setting of t01reg and t00reg is indicated as t01+00reg, and the 16-bit value specified by the co mbined setting of t01pwm and t00pwm is indi- cated as t01+00pwm). the timer re gister settings are reflected on the double buffer or t01+00pwm and t01+00reg when a write instruction is executed on t01pwm. be sure to execute the wr ite instructions on t00reg, t01reg and t00pwm before executing a write instruction on t01pwm. (when data is written to t01pwm, the set values of the four tim er registers become effective at the same time.) set the initial state of the ppg1 pin at t01mod. setting t01mod to "0" selects the "l" level as the initial state of the ppg1 pin. setting t01mod to "1" selects the "h" level as the initial state of the ppg1 pin. if the ppg1 pin is set as the function output pin in the port setting while the timer is stopped, the value of t 01mod is output to the ppg1 pin. table 14-13 shows the list of output levels of the ppg1 pin. 14.4.8.2 operations setting t001cr to "1" allows the up counter to increment based on the selected source clock. when a match between the up counter value an d the value set to t01+00pwm is detected, the out- put of the ppg1 pin is reversed. when t01mod is "0", the ppg1 pin changes from the "l" to "h" level. when t01mod is "1", the ppg1 pin changes from the "h" to "l" level. at this time, an intt00 interrupt request is generated. the up counter continues counting up. when a match between the up counter value and the value set to t01+00reg is detected, the output of the ppg1 pin is reversed again. wh en t01mod is "0", the ppg1 pin changes from the "h" to "l" le vel. when t01mod is "1", the ppg1 pin changes from the "l" to "h" level. at this time, an intt01 interrupt request is generated and the up counter is cleared to "0x0000". when t001cr is set to "0" during the timer operation, the up counter is stopped and cleared to "0x0000". the ppg1 pin returns to the level selected at t01mod. table 14-13 list of output levels of ppg1 pin tff1 ppg1 pin output level before the start of operation (initial state) t01+00pwm matched t01+00reg matched operation stopped (initial state) 0lhll 1hlhh
page 191 TMP89FH46 ra002 when an external source clock is selected, input the clock at the tc00 pin. the maximum frequency to be supplied is fcgck/2 [hz] (in normal1/2 or idle1/2 mode) or fs/2 4 [hz] (in slow1/2 or sleep1 mode), and a pulse width of two m achine cycles or more is required at both the "h" and "l" levels. 14.4.8.3 double buffer the double buffer can be used for t01+00pwm and t01+00reg by setting t01mod. the double buffer is enabled by setting t01mod to "0" or disabled by setting t01mod to "1". ? when the double buffer is enabled when a write instruction is executed on t01pwm after writ e instructions are executed on t00reg, t01reg and t00pwm duri ng the timer operation, the set values are first stored in the double buffer, and t01+00pwm and t01+00reg are not updated immediately. t01+00pwm and t01+00reg compare the previo us set values with the up counter value. when a match between the up counter value and the t01+00reg set value is detected, an intt01 interrupt request is generated and the double buffer set values are stored in t01+00pwm and t01+00reg. subsequently, the match detection is executed using new set values. when a write instruction is executed on t01pwm after writ e instructions are executed on t00reg, t01reg and t00pwm while the timer is stopped, the set values are immediately stored in both the double buffer and t01+00pwm and t01+00reg. ? when the double buffer is disabled when a write instruction is executed on t01pwm after writ e instructions are executed on t00reg, t01reg and t00pwm during the timer operation, the set values are immediately stored in t01+00pwm and t01+00reg. subsequently, the match detection is executed using new set values. if the value set to t01+00pwm or t01+00reg is smaller than the up counter value, the ppg1 pin is not reversed until the up counter overflows and a match detection is executed using a new set value. if the value set to t01+00 pwm or t01+00reg is equal to the up counter value, the match detection is executed immediat ely after data is written into t01+00pwm and t01+00reg. therefore, th e timing of changing the ppg1 pin may not be an integral multiple of the source clock. if these are problems, enable the double buffer. when a write instruction is executed on t01pwm after writ e instructions are executed on t00reg, t01reg and t00pwm while the timer is stopped, the set values are immediately stored in t01+00pwm and t01+00reg. when read instructions are ex ecuted on t01+00pwm and t01+00reg, the last value written into t01+00reg is read out, regardless of the t00mod setting. (example) operate tc00 and tc01 in the 16-bit ppg mode with the operation clock of fcgck/2 and output the 68 s duty pulse in 96 s cycles (fcgck = 10 mhz) set (p7fc).1 ; sets p7fc0 to "1" set (p7cr).1 ; sets p7cr0 to "1" ld (poffcr0),0x10 ; sets tc001en to "1" di ; sets the interrupt master enable flag to "disable" set (eirh).4 ; sets the inttc00 interrupt enable register to "1" ei ; sets the interrupt master enable flag to "enable" ld (t01mod),0xf3 ; selects the 8-bit ppg mode and fcgck/2 ld (t00reg),0xe0 ; sets the timer register (cycle) ld (t01reg),0x01 ; sets the timer register (cycle) ; 96 s / (2/fcgck) = 0x01e0 ld (t00pwm),0x54 ; sets the timer register (duty pulse) ld (t01pwm),0x01 ; sets the timer register (duty pulse) ; 68 s / (2/fcgck) = 0x0154
page 192 14. 8-bit timer counter (tc0) TMP89FH46 ra002 figure 14-16 16-bit ppg output mode timing chart ld (t001cr),0x06 ; starts tc00 and tc01 source clock counter timer start 1 0 gh gh gh (duty pulse) ab (cycle 1) cd (cycle 1) cd (cycle 1) ef (cycle 1) km qr km qr write to t00pwm double buffer match detection write h write m write r becomes the level selected at tff1 while the timer is stopped returns to the level selected at tff1 write to t01pwm write g write k write q intt00 interrupt request intt00 interrupt request 1 gh +1 km +1 gh 0 t01+00pwm t001cr ab cd ef write to t01reg double buffer write a write c write e write to t00reg write b write d write f ab timer stop match detection km km +1 km qr +1 qr 1 0 cd 1 0 cd 1 00 ef match detection counter clear counter clear counter clear counter clear t01mod ppg1 pin output when the double buffer is enabled (t01mod=?1?) km (duty pulse) km (duty pulse) qr (duty pulse) ab cd ef t01+00reg match detection match detection match detection match detection match detection
page 193 TMP89FH46 ra000 15. real time clock (rtc) the real time clock is a function that generates interr upt requests at certain intervals using the low-frequency clock. the number of interrupts is counted by the software to realize the clock function. the real time clock can be used only in the operation modes where the low- frequency clock oscillates, except for sleep0. 15.1 configuration figure 15-1 real time clock 15.2 control the real time clock is cont rolled by following resisters. low power consumption register 2 poffcr2 76543210 (0x0f76) bit symbol - - rtcen - - - - sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 rtcen rtc control 0 1 disable enable sio0en sio0 control 0 1 disable enable real time clock control register rtccr (0x0fc8) 76543210 bit symbol---- rtcsel rtcrun read/writerrrr r/w r/w after reset00000000 rtcsel rtcrun intrtc interrupt request fs (32.768 khz) rtccr selector binary counter 2 15 /fs 2 14 /fs 2 13 /fs 2 12 /fs 2 11 /fs 2 10 /fs 2 9 /fs 2 8 /fs
page 194 15. real time clock (rtc) 15.3 function TMP89FH46 ra000 note 1: fs: low-frequency clock [hz] note 2: rtccr can be rewritten only when rtccr< rtcrun> is "0". if data is written into rtccr when rtccr is "1", the existing data re mains effective. rtccr can be rewritten at the same time as enabling the real time clock, but it cannot be rewritten at the same time as disabling the real time clock. note 3: if the real time clock is enabled and when 1) syscr 2 is cleared to "0" to stop the low-frequency clock oscillation circuit or 2) the ope ration is changed to the stop mode or the sleep0 mode, the data in rtccr is maintained and rtccr is cleared to "0". 15.3 function 15.3.1 low power c onsumption function real time clock has the low power consumption regist ers (poffcr2) that save power when the real time clock is not being used. setting poffcr2 to "0" disables the basic clock supply to real time clock to save power. note that this renders the real time clock unusable. setting poffcr2 to "1" enables the basic clock sup- ply to real time clock and allows the real time clock to operate. after reset, poffcr2 are initialized to "0", and this renders the real time clock unusable. when using the real time clock for the first time, be sure to set poffcr2 to "1" in the initial setting of the program (before the real time cloc k control registers are operated). do not change poffcr2 to "0" during the real time clock operation. otherwise real time clock may operate unexpectedly. 15.3.2 enabling/disabling th e real time clock operation setting rtccr to "1" enable s the real time clock operation. setting rtccr to "0" disables the real time clock operation. rtccr is cleared to "0" just after reset release. 15.3.3 selecting the inte rrupt generation interval the interrupt generation interval can be selected at rtccr. rtccr can be rewritten only when rtccr< rtcrun> is "0". if data is written into rtccr when rtccr is "1", the existing data remains effective. rtccr can be rewritten at the same time as enabling the real time clock operation, but it cannot be rewritten at the same time as disa bling the real time clock operation. rtcsel selects the interrupt generation interval 000 : 2 15 /fs (1.000 [s] @fs=32.768khz) 001 : 2 14 /fs (0.500 [s] @fs=32.768khz) 010 : 2 13 /fs (0.250 [s] @fs=32.768khz) 011 : 2 12 /fs (125.0 [ms] @fs=32.768khz) 100 : 2 11 /fs (62.50 [ms] @fs=32.768khz) 101 : 2 10 /fs (31.25 [ms] @fs=32.768khz) 110 : 2 9 /fs (15.62 [ms] @fs=32.768khz) 111 : 2 8 /fs (7.81 [ms] @fs=32.768khz) rtcrun enables/disables the real time clock opera- tion 0 : disable 1 : enable
page 195 TMP89FH46 ra000 15.4 real time clock operation 15.4.1 enabling the real time clock operation set the interrupt generation inte rval to rtccr, and at the same time, set rtccr to "1". when rtccr is set to "1", the binary counter for the real time clock st arts counting of the low- frequency clock. when the interrupt generation interval selected at rtccr is reached, a r eal time clock interrupt request (intrtc) is generated an d the counter continues counting. 15.4.2 disabling the real time clock operation clear rtccr to "0". when rtccr is cleared to "0", the binary count er for the real time clock is cleared to "0" and stops counting of the low-frequency clock.
page 196 15. real time clock (rtc) 15.4 real time clock operation TMP89FH46 ra000
page 197 TMP89FH46 ra001 16. asynchronous serial interface (uart) the TMP89FH46 contains 2 channels of asynchronous serial interfaces (uart). this chapter describes asynchronous serial interface 0 (uart0). for uar t1, replace the sfr addresses and pin names as shown in table 16-1 and table 16-2. table 16-1 sfr address assignment uartxcr1 (address) uartxcr2 (address) uartxdr (address) uartxsr (address) rdxbuf (address) tdxbuf (address) uart0 uart0cr1 (0x001a) uart0cr2 (0x001b) uart0dr (0x001c) uart0sr (0x001d) rd0buf (0x001e) td0buf (0x001e) uart1 uart1cr1 (0x0f54) uart1cr2 (0x0f55) uart1dr (0x0f56) uart1sr (0x0f57) rd1buf (0x0f58) td1buf (0x0f58) table 16-2 pin names serial data input pin serial data output pin uart0 rxd0 pin txd0 pin uart1 rxd1 pin txd1 pin
page 198 16. asynchronous serial interface (uart) 16.1 configuration TMP89FH46 ra001 16.1 configuration figure 16-1 asynchronous serial interface (uart) 8-bit counter 8-bit counter y a b c s s a by fcgck or fs match detection en en match detection comparator comparator start bit detection transmission start stop bit parity bit fcgck/2 6 fcgck/2 7 fcgck/2 8 ppga0 output (tca0 output) baud rate generator transmit rt clock receive rt clock 2 4 2 2 2 noise rejection circuit shift register shift register irda control s a by counter counter transmit control circuit receive control circuit selector frequency divider uart0cr1 uart0 control register 1 inttxd0 interrupt request intrxd0 interrupt request uart0 transmit data buffer uart0 receive data buffer rxd0 txd0 uart0cr1 rd0buf uart0cr2 uart0sr uart0dr uart0 baud rate register uart0 status register uart0 control register 2
page 199 TMP89FH46 ra001 16.2 control uart0 is controlled by the low power consumption registers (poffcr1), uart0 control registers 1 and 2 (uart0cr1 and uart0cr2) and the uart0 baud rate register (uart0dr). the operating status can be moni- tored using the uart status register (uart0sr). low power consumption register 1 poffcr1 76543210 (0x0f75) bit symbol - - - sbi0en - - uart1en uart0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 sbi0en i2c0 control 0 1 disable enable uart1en uart1 control 0 1 disable enable uart0en uart0 control 0 1 disable enable
page 200 16. asynchronous serial interface (uart) 16.2 control TMP89FH46 ra001 note 1: fcgck, gear clock; fs, low-frequency clock note 2: if the txe or rxe bit is set to "0" during the transmissi on or receiving of data, the operation is not disabled until th e data transfer is completed. at this time, the dat a stored in the transmit data buffer is discarded. note 3: even, pe and brg settings are common to transmission and receiving. note 4: set rxe and txe to "0" before changing brg. note 5: when brg is set to the tca0 output, the rt clock bec omes asynchronous and the start bit of the transmitted/received data may get shorter by a maximum of (u art0dr+1)/(transfer base clock frequency)[s]. if the pin is not used for the tca0 output, control the tca0 output by using the port function control register. note 6: to prevent stopbt, even, pe, irdasel and brg from being changed accidentally during the uart communication, the register cannot be rewritten during the uart operation. fo r details, refer to "16.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed". note 7: when the stop, idle0 or sleep0 mode is activated, txe and rxe are cleared to "0" and the uart stops. other bits keep their values. uart0 control register 1 uart0cr1 76543210 (0x001a) bit symbol txe rxe stopbt even pe irdasel brg - read/write r/w r/w r/w r/w r/w r/w r/w r after reset00000000 txe transmit operation 0: 1: disable enable rxe receive operation 0: 1: disable enable stopbt transmit stop bit length 0: 1: 1 bit 2 bits even parity selection 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity added irdasel txd pin output selection 0: 1: uart output irda output brg transfer base clock selection when syscr2 is "0" when syscr2 is "1" 0: fcgck fs 1: tca0 output
page 201 TMP89FH46 ra001 note 1: when a read instruction is executed on uart0cr2, bits 7 and 6 are read as "0". note 2: rtsel can be set to two kinds of rt clocks for the even- and odd-numbered bits of the transfer frame. for details, refer to "16.8.1 transfer baud rate calculation method". note 3: for details of the rxdnc noise rejection time , refer to "16.10 received data noise rejection". note 4: when the stop, idle0 or sleep0 mode is activated, the uart stops automatically but each bit value of uart0cr2 remains unchanged. note 5: when stopbr is set to 2 bits, the first bit of the stop bits (during data receiving) is not checked for a framing error. note 6: to prevent rtsel, rxdnc and stopbr from being changed accidentally during the uart communication, the register cannot be rewritten during the uart operation. for details, refer to "16.4 protection to prevent uart0cr1 and uart0cr2 registers from being changed". note 1: set uart0cr1 and uart0cr1 to "0" before c hanging uart0dr. for the set values, refer to "16.8 trans- fer baud rate". note 2: when uart0cr1 is set to the tca0 output, the value set to uart0dr has no meaning. note 3: when the stop, idle0 or sleep0 mode is activated, the uart stops automatically but each bit value of uart0dr remains unchanged. uart0 control register 2 uart0cr2 76543210 (0x001b) bit symbol - - rtsel rxdnc stopbr read/write r r r/w r/w r/w after reset00000000 rtsel selects the number of rt clocks odd-numbered bits of transfer frame even-numbered bits of transfer frame 000: 16 clocks 16 clocks 001: 16 clocks 17 clocks 010: 15 clocks 15 clocks 011: 15 clocks 16 clocks 100: 17 clocks 17 clocks 101: reserved 11*: reserved rxdnc selects the rxd input noise rejec- tion time (time of pulses to be removed as noise) 00: 01: 10: 11: no noise rejection 1 x (uart0dr+1)/(transfer base clock frequency) [s] 2 x (uart0dr+1)/(transfer base clock frequency) [s] 4 x (uart0dr+1)/(transfer base clock frequency) [s] stopbr receive stop bit length 0: 1: 1 bit 2 bits uart0 baud rate register uart0dr 76543210 (0x001c) bit symbol uart0dr7 uart0dr6 uart0dr5 uart0dr4 uart0dr3 uart0dr2 uart0dr1 uart0dr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 uart0 status register uart0sr 76543210 (0x001d) bit symbol perr ferr oerr - rbsy rbfl tbsy tbfl read/writerrrrrrrr after reset00000000
page 202 16. asynchronous serial interface (uart) 16.2 control TMP89FH46 ra001 note 1: tbfl is cleared to "0" automatically after an inttxd0 in terrupt request is generated, and is set to "1" when data is set to td0buf. note 2: when a read instruction is exec uted on uart0sr, bit 4 is read as "0". note 3: when the stop, idle0 or sleep0 mode is activated, each bit of uart0sr is cleared to "0" and the uart stops. note 1: when the stop, idle0 or sleep0 mode is activat ed, the rd0buf values become undefined. if received data is required, read it before activating the mode. note 1: when the stop, idle0 or sleep0 mode is activated, the td0buf values become undefined. perr parity error flag 0: 1: no parity error parity error ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrrun error overrun error rbsy receive busy flag 0: 1: before receiving or end of receiving on receiving rbfl receive buffer full flag 0: 1: receive buffer empty receive buffer full tbsy transmit busy flag 0: 1: before transmission or end of transmission on transmitting tbfl transmit buffer full flag 0: 1: transmit buffer empty transmit buffer full (transmit data writing is completed) uart0 receive data buffer rd0buf 76543210 (0x001e) bit symbol rd0dr7 rd0dr6 rd0dr5 rd0dr4 rd0dr3 rd0dr2 rd0dr1 rd0dr0 read/writerrrrrrrr after reset00000000 uart0 transmit data buffer td0buf 76543210 (0x001e) bit symbol td0dr7 td0dr6 td0dr5 td0dr4 td0dr3 td0dr2 td0dr1 td0dr0 read/writewwwwwwww after reset00000000
page 203 TMP89FH46 ra001 16.3 low power consumption function uart0 has a low power consumption register (poffcr1) that saves power consumption when the uart func- tion is not used. setting poffcr1 to "0" disables the basic clock supply to uart0 to save power. note that this ren- ders the uart unusable. setting poffcr1 to "1" enables the basic clock supply to uart0 and ren- ders the uart usable. after reset, poffcr1 is initialized to "0", and this renders the uart unusable. when using the uart for the first time, be sure to set poffcr1 to "1" in the initial setting of the program (before the uart control register is operated). do not change poffcr1 to "0" during the uart operation, otherwise uart0 may operate unex- pectedly.
page 204 16. asynchronous serial interface (uart) 16.4 protection to prevent uart0cr1 and uart0cr2 regis- ters from being changed TMP89FH46 ra001 16.4 protection to prev ent uart0cr1 and uart0cr2 registers from being changed the TMP89FH46 has a function that prot ects the registers from being change d so that the uart communication settings (for example, stop bi t and parity) are not changed accide ntally during the uart operation. specific bits of uart0cr1 and uart0cr2 can be changed only under the conditions shown in table 16-3. if a write instruction is executed on the regi ster when it is protected from being changed, the bits remain unchanged and keep their previous values. table 16-3 changing of uart0cr1 and uart0cr2 bit to be changed function conditions that allow the bit to be changed uart0cr1 uart0sr uart0cr1 uart0sr uart0cr1 transmit stop bit length both of these bits are "0" - - uart0cr1 parity selection all of these bits are "0" uart0cr1 parity addition uart0cr1 txd pin output selection both of these bits are "0" - - uart0cr1 transfer base clock selec- tion all of these bits are "0" uart0cr2 selection of number of rt clocks uart0cr2 selection of rxd pin input noise rejection time - - both of these bits are "0" uart0cr2 receive stop bit length
page 205 TMP89FH46 ra001 16.5 activation of stop , idle0 or sleep0 mode 16.5.1 transition of register status when the stop, idle0 or sleep0 mo de is activated, the uart stops automatically and each register becomes the status as shown in table 16-4. for the regi sters that do not hold their values, make settings again as needed after the operation mode is recovered. 16.5.2 transition of txd pin status when the idle0, sleep0 or stop mode is activated, the txd pin reverts to the status shown in table 16- 5, whether data is transmitted/r eceived or the operation is stopped. table 16-4 transition of register status 76543210 uart0cr1 txe rxe stopbt even pe irdasel brg - cleared to 0 cleared to 0 hold the value hold the value hold the value hold the value hold the value - uart0cr2 - - rtsel rxdnc stopbr -- hold the value hold the value hold the value hold the value hold the value hold the value uart0sr perr ferr oerr - rbsy rbfl tbsy tbfl cleared to 0 cleared to 0 cleared to 0 - cleared to 0 cleared to 0 cleared to 0 cleared to 0 uart0dr uart0dr7 uart0dr6 uart0dr5 uart0dr4 uart0dr3 uart0dr2 uart0dr1 uart0dr0 hold the value hold the value hold the value hold the value hold the value hold the value hold the value hold the value rd0buf rd0dr7 rd0dr6 rd0dr5 rd0dr4 rd0dr3 rd0dr2 rd0dr1 rd0dr0 indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate td0buf td0dr7 td0dr6 td0dr5 td0dr4 td0dr3 td0dr2 td0dr1 td0dr0 indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate indetermi- nate table 16-5 txd pin status when the st op, idle0 or sleep0 mode is activated uart0cr1 idle0 or sleep0 mode stop mode syscr1="1" syscr1="0" "0" h level h level hi-z "1" l level l level
page 206 16. asynchronous serial interface (uart) 16.6 transfer data format TMP89FH46 ra001 16.6 transfer data format the uart transfers data composed of th e following four elements. the data from the start bit to the stop bit is col- lectively defined as a "transfer frame". the start bit consists of 1 bit (l level) and the da ta consists of 8 bits. parity bits are determined by uart0cr1 that selects the presence or abse nce of parity and uart0cr1 that selects even- or odd-nu mbered parity. the bit length of the stop bit can be selected at uart0cr1. figure 16-2 shows the transfer data format. ? start bit (1 bit) ? data (8 bits) ? parity bit (selectable fr om even-numbered, odd-numbered or no parity) ? stop bit (selectable from 1 bit or 2 bits) figure 16-2 tran sfer data format 16.7 infrared data format transfer mode the txd0 pin can output data in the infr ared data format (irda) by the settin g of the irda output control register. setting uart0cr1 to "1" allows the txd0 pin to output data in the infrared data format. figure 16-3 example of infrar ed data format (comparison betw een normal out put and irda output) start 123456789101112 bit 0 stop 1 start bit 0 stop 1 stop 2 stop 1 stop 1 stop 2 start bit 0 bit 0 start bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity parity bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 1 0 1 0 0 1 1 stbt pe transfer frame uart output irda output start bit stop bit d0 d1 d2 d7 3/16 bit width
page 207 TMP89FH46 ra001 16.8 transfer baud rate the transfer baud rate of uart is set by uart0cr1, uart0dr and uart0cr2. table 16-6 and table 16-7 show the settings of uart0dr and uart0cr2 for general baud rates and operating fre- quencies. for independent calculation of transfer baud rates, re fer to "16.8.1 transfer baud rate calculation method". table 16-6 set values of uart0dr and uart0cr2 for transfer baud rate s (fcgck=10 to 1 mhz, uart0cr2=0y00) basic baud rate [baud] register operating frequency 10mhz 8mhz 7.3728 mhz 6.144 mhz 6mhz 5mhz 4.9152 mhz 4.19mhz 4mhz 2mhz 1mhz 128000 uart0dr 0x04 0x03 - 0x02 0x02 - - 0x01 0x01 0x00 - rtsel 0y011 0y011 - 0y000 0y011 - - 0y001 0y011 0y011 - error (+0.81%) (+0.81%) - (0%) (+0.81%) - - (-0.80%) (+0.81%) (+0.81%) - 115200 uart0dr 0x04 0x03 0x03 - 0x02 - - - 0x01 0x00 - rtsel 0y100 0y100 0y000 - 0y100 - - - 0y100 0y100 - error (+2.12%) (+2.12%) (0%) - (+2.12%) - - - (+2.12%) (+2.12%) - 76800 uart0dr 0x07 0x06 0x05 0x0 4 0x04 0x03 0x03 - 0x02 - - rtsel 0y001 0y010 0y000 0y000 0y011 0y001 0y000 - 0y100 - - error (-1.36%) (-0.79%) (0%) (0%) (+0.81%) (-1.36%) (0%) - (+2.12%) - - 62500 uart0dr 0x09 0x07 0x06 0x05 0x05 0x04 0x04 0x03 0x03 0x01 0x00 rtsel 0y000 0y000 0y100 0y001 0y000 0y 000 0y011 0y100 0y000 0y000 0y000 error (0%) (0%) (-0.87%) (-0.70%) (0%) (0%) (+1.48%) (-1.41%) (0%) (0%) (0%) 57600 uart0dr 0x0a 0x08 0x07 0x06 0x06 0x04 0x04 - 0x03 0x01 0x00 rtsel 0y000 0y011 0y000 0y010 0y010 0y100 0y100 - 0y100 0y100 0y100 error (-1.36%) (-0.44%) (0%) (+1.59%) (-0.79%) (+2.12%) (+0.39%) - (+2.12%) (+2.12%) (+2.12%) 38400 uart0dr 0x10 0x0c 0x0b 0x09 0x09 0x07 0x07 0x06 0x06 0x02 - rtsel 0y011 0y000 0y000 0y000 0y01 1 0y001 0y000 0y011 0y010 0y100 - error (-1.17%) (+0.16%) (0%) (0%) (+0.81%) (-1.36%) (0%) (+0.57%) (-0.79%) (+2.12%) - 19200 uart0dr 0x22 0x19 0x17 0x13 0x12 0x10 0x0f 0x0d 0x0c 0x06 0x02 rtsel 0y010 0y000 0y000 0y000 0y001 0y 011 0y000 0y011 0y000 0y010 0y100 error (-0.79%) (+0.16%) (0%) (0%) (-0.32%) (-1.17%) (0%) (+0.57%) (+0.16%) (-0.79%) (+2.12%) 9600 uart0dr 0x40 0x30 0x2f 0x27 0x26 0x22 0x1f 0x1c 0x19 0x0c 0x06 rtsel 0y000 0y100 0y000 0y000 0y000 0y 010 0y000 0y010 0y000 0y000 0y010 error (+0.16%) (+0.04%) (0%) (0%) (+0.16%) (-0.79%) (0%) (+0.34%) (+0.16%) (+0.16%) (-0.79%) 4800 uart0dr 0x8a 0x64 0x5f 0x4f 0x4d 0x40 0x3f 0x34 0x30 0x19 0x0c rtsel 0y010 0y001 0y000 0y000 0y000 0y 000 0y000 0y001 0y100 0y000 0y000 error (-0.08%) (+0.01%) (0%) (0%) (+0.16%) (+0.16%) (0%) (-0.18%) (+0.04%) (+0.16%) (+0.16%) 2400 uart0dr 0xf4 0xc9 0xbf 0x9f 0x92 0x8a 0x7f 0x6c 0x64 0x30 0x19 rtsel 0y100 0y001 0y000 0y000 0y100 0y 010 0y000 0y000 0y001 0y100 0y000 error (+0.04%) (+0.01%) (0%) (0%) (+0.04%) (-0.08%) (0%) (+0.11%) (+0.01%) (+0.04%) (+0.16%) 1200 uart0dr-----0xf40xff0xe80xc90x640x30 rtsel-----0y1000y0000y0100y0010y0010y100 error-----(+0.04%)(+0%)(-0.10%)(+0.01%)(+0.01%)(+0.04%)
page 208 16. asynchronous serial interface (uart) 16.8 transfer baud rate TMP89FH46 ra001 note 1: the overall error from the basic baud rate must be within 3%. even if the overall error is within 3%, the commu- nication may fail due to factors such as frequency errors in external controllers (for example, a personal computer) and oscillators and the load capaci ty of the communication pin. 16.8.1 transfer baud ra te calculation method 16.8.1.1 bit width adjustment using uart0cr2 the bit width of transmitted/received data can be finely adjusted by ch anging uart0cr2. the number of rt clocks per bit can be changed in a range of 15 to 17 clocks by changing uart0cr2. the rt clock is the transfer base clock, which is the pulses obtained by counting the clock selected at uart0cr1 the number of times of (uart0dr set value) + 1. especially, when uart0cr2 is set to "0y001" or "0y011", two types of rt clocks alternate at each bit, so that the pseudo baud rates of rt 15.5 clocks and rt 16.5 clocks can be generated. the number of rt clocks per bit of transfer frame is shown in figure 16-4. for example, when fcgck is 4 [mhz], uart0cr2 is set to "0y000" and uart0dr is set to "0x19", the baud rate calculated using the formula in figure 16-4 is expressed as: fcgck / (16 (uart0dr + 1) = 9615 [baud] these settings generate a baud rate close to 9600 [baud] (+0.16%). table 16-7 set values of uart0dr and uart0cr2 for transfer baud rates (fs=32.768 khz, uart0cr2=0y00) basic baud rate [baud] register operating frequency 32.768 khz 300 uart0dr 0x06 rtsel 0y011 error (+0.67%) 150 uart0dr 0x0d rtsel 0y011 error (+0.67%) 134 uart0dr 0x0e rtsel 0y001 error (-1.20%) 110 uart0dr 0x11 rtsel 0y001 error (+0.30%) 75 uart0dr 0x1c rtsel 0y010 error (+0.44%)
page 209 TMP89FH46 ra001 figure 16-4 fine adjustm ent of baud rate clock using uart0cr2 16.8.1.2 calculation of set values of uart0cr2 and uart0dr the set value of uart0dr for an operating frequency and baud rate can be calculated using the calcu- lation formula shown in figure 16-5. for example, to generate a basic baud rate of 38400 [baud] with fcgck=4 [mhz], calculate the set value of uart 0dr for each setting of uart0cr2 and com- pensate the calculated value to a positive number to obtain the generated baud rate as shown in figure 16- 6. basically, select the set value of uart0cr2 that has the smallest baud rate error from among the generated baud rates. in figure 16-6 , the setting of uart0cr2="0y010" has the smallest error among the calculated baud rates, an d thus the generated baud rate is 38095 [baud] ( ? 0.79%) against the basic baud rate of 38400 [baud]. note: the error from the basic baud rate should be accurate to within 3%. even if the error is within 3%, the communication may fail due to factors such as frequency errors of external controllers (for example, a personal computer) and oscillators and the load capacity of the communication pin. figure 16-5 uart0dr calculation method (when brg is set to fcgck) start 123456789101112 bit 0 stop 1 start bit 0 stop 1 stop 2 stop 1 stop 1 stop 2 start bit 0 bit 0 start bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity parity bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 1 0 1 0 0 1 1 stbt pe 000 001 010 011 100 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 17 15 16 17 16 16 15 15 17 16 fcgck [baud] 16 (uartdr+1) generated baud rate *when brg is set to fcgck 17 15 16 17 rtsel transfer frame fcgck [baud] 16.5 (uartdr+1) fcgck [baud] 15 (uartdr+1) fcgck [baud] 15.5 (uartdr+1) fcgck [baud] 17 (uartdr+1) number of rt clocks 000 fcgck [hz] 1 1 1 1 1 uartdr = 16 a [baud] uartdr set value rtsel 001 fcgck [hz] uartdr = 16.5 a [baud] 010 fcgck [hz] uartdr = 15 a [baud] 011 fcgck [hz] uartdr = 15.5 a [baud] 100 fcgck [hz] uartdr = 17 a [baud]
page 210 16. asynchronous serial interface (uart) 16.8 transfer baud rate TMP89FH46 ra001 figure 16-6 example of uart0dr calculation 000 4000000 [hz] 4000000 [hz] 4000000 [hz] 4000000 [hz] 4000000 [hz] 1 6 35714 [baud] ( 6.99%) 40404 [baud] ( 5.22%) 38095 [baud] ( 0.79%) 36866 [baud] ( 3.99%) 39216 [baud] ( 2.12%) 1 6 1 6 1 5 1 5 uartdr = 16 38400 [baud] uartdr calculation generated baud rate rtsel 4000000 [hz] 16 (6 + 1) 4000000 [hz] 16.5 (5 + 1) 4000000 [hz] 15 (6 + 1) 4000000 [hz] 15.5 (6 + 1) 4000000 [hz] 17 (5 + 1) 001 uartdr = 16.5 38400 [baud] 010 uartdr = 15 38400 [baud] 011 uartdr = 15.5 38400 [baud] 100 uartdr = 17 38400 [baud]
page 211 TMP89FH46 ra001 16.9 data sampling method the uart receive control circuit starts rt clock counting when it detects a fa lling edge of the input pulses to the rxd0 pin. 15 to 17 rt clocks are counted per bit and each clock is expressed as rtn (n=16 to 0). in a bit that has 17 rt clocks, rt16 to rt0 are counted. in a bit that has 16 rt clocks, rt15 to rt0 are coun ted. in a bit that has 15 rt clocks, rt14 to rt0 are counted (decrement). during count ing of rt8 to rt6, the uart receive control circuit samples the input pulses to the rxd0 pin to make a majority decision. the same level detected twice or more from among three samplings is processed as the data for the bit. the number of rt clocks can be changed in a range of 15 to 17 by setting uart0cr2. however, sam- pling is always executed in rt8 to rt6, even if the number of rt clocks is changed (figure 16-7). figure 16-7 data sampling in each case of uartcr2 rt15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 bit 0 start bit bit 0 start bit (b) uartcr2 is 001b rt clock internal received data rt15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 bit 0 start bit bit 0 start bit (a) uartcr2 is 000b rt clock rxd0 pin rxd0 pin rxd0 pin rxd0 pin rxd0 pin internal received data rt16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 bit 0 start bit bit 0 start bit (e) uartcr2 is 100b rt clock internal received data rt14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 bit 0 start bit bit 0 start bit (d) uartcr2 is 011b rt clock internal received data rt14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 bit 0 bit 1 bit 1 bit 1 bit 1 start bit bit 0 start bit (c) uartcr2 is 010b rt clock internal received data
page 212 16. asynchronous serial interface (uart) 16.9 data sampling method TMP89FH46 ra001 if "1" is detected in sampling of the start bit, for exam ple, due to the influence of noise, rt clock counting stops and the data receiving is suspended. su bsequently, when a falling e dge is detected in the input pulses to the rxd0 pin, rt clock counting restarts and the da ta receiving restarts with the start bit. figure 16-8 st art bit sampling rt15 14 13 12 11 10 9 8 7 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 bit 0 start bit start bit bit 0 rt clock rxd0 pin shift register noise bit 0 internal received data error because the start bit is 1 counting is suspended until the next falling edge is detected receiving continues because the start bit is 0 the received data is taken into the shift register a falling edge is detected a falling edge is detected
page 213 TMP89FH46 ra001 16.10received data noise rejection when noise rejection is enabled at uart0cr2, th e time of pulses to be regarded as signals is as shown in table 16-8. note 1: the transfer base clock frequency is the clock frequency selected at uartcr1. figure 16-9 received data noise rejection table 16-8 received data noise rejection time rxdnc noise rejection time [s] time of pulses to be regarded as signals 00 no noise rejection - 01 (uart0dr+1)/(transfer base clock frequency) 2 (uart0dr+1)/(transfer base clock frequency) 10 2 (uart0dr+1)/(transfer base clock frequency) 4 (uart0dr+1)/(transfer base clock frequency) 11 4 (uart0dr+1)/(transfer base clock frequency) 8 (uart0dr+1)/(transfer base clock frequency) receiving continues because the start bit is 0 the received data is taken into the shift register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 bit 0 start bit start bit bit 0 rt clock internal received data shift register bit 0 rxd0 pin noise noise is removed a falling edge is detected when the noise rejection circuit is used
page 214 16. asynchronous serial interface (uart) 16.11 transmit/receive operation TMP89FH46 ra001 16.11transmit/receive operation 16.11.1data transmit operation set uart0cr1 to "1". check uart0sr = "0 ", and then write data into td0buf (transmit data buffer). writing data into td0buf sets uart0sr to "1", transfers the data to the transmit shift register, and outputs the data sequentially from the txd0 pin. the data output includes a start bit, stop bits whose number is specified in uart0cr1 and a par ity bit if parity addition is specified. select the data transfer baud rate using uart0cr1, uart0cr2 and uart0dr. when data trans- mission starts, the transmit buffer full flag uart0sr is cleared to "0" and an inttxd0 interrupt request is generated. note 1: after data is written into td0buf, if new data is written into td0buf before the previous data is transferred to the shift register, the new data is written over t he previous data and is transferred to the shift register. note 2: under the conditions shown in table 16-9, the txd0 pin output is fixed at the l or h level according to the setting of uart0cr1. 16.11.2data receive operation set uart0cr1 to "1". when data is received vi a the rxd0 pin, the received data is transferred to rd0buf (receive data buff er). at this time, the transmitt ed data includes a start bit, stop bit( s) and a parity bit if parity addition is specified. when the stop bit(s) are r eceived, data only is ex tracted and transferred to rd0buf (receive data buffer). then the receive buff er full flag uart0sr is set and an intrxd0 interrupt request is generated. set the data tran sfer baud rate using uart0cr1, uart0cr2 and uart0dr. if an overrun error occurs when data is received, the data is not transferred to rd0buf (receive data buffer) but discarded; data in the rd0buf is not affected. table 16-9 txd0 pin output condition txd0 pin output irdasel="0" irdasel="1" when uart0cr1 is "0" h level l level from when "1" is written to uart0cr1 to when the trans- mitted data is written to td0buf when the stop, idle0 or sleep0 mode is active
page 215 TMP89FH46 ra001 16.12status flag 16.12.1parity error when the parity determined using the receive data bits differs from the received par ity bit, the parity error flag uart0sr is set to "1". at this tim e, an intrxd0 interrupt request is generated. if uart0sr is "1" when uart0sr is r ead, uart0sr will be cleared to "0" when rd0buf is read subsequently. (the rd0buf read value becomes undefined.) if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. figure 16-10 occurrenc e of parity error rxd0 pin input indeterminate data reading perr is cleared to 0 when rd0buf is read after reading perr=1. intrxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop reading of uart0sr reading of rd0buf rd0buf rxd0 pin input indeterminate not cleared data reading perr is cleared to 0 when rd0buf is read after reading perr=1. intrxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop reading of uart0sr reading of rd0buf rd0buf data reading
page 216 16. asynchronous serial interface (uart) 16.12 status flag TMP89FH46 ra001 16.12.2framing error if the internal and external baud rates differ or "0" is sampled as the stop bit of received data due to the influ- ence of noise on the rxd0 pin, the framing error flag uart0sr is set to "1". at this time, an intrxd0 interrupt request is generated. if uart0sr is "1" when uart0sr is r ead, uart0sr will be cleared to "0" when rd0buf is read subsequently. if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. figure 16-11 occurr ence of framing error rxd0 pin input a falling edge is detected ferr is generated if 0 is received in the sampling of the stop bit. ferr is cleared to 0 when rd0buf is read after reading ferr=1. ferr is cleared to 0 when rd0buf is read after reading ferr=1. sampling intrxd0 interrupt request uart0sr when the external baud rate is slower than the internally set baud rate when the external baud rate is faster than the internally set baud rate start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop reading of uart0sr reading of rd0buf rxd0 pin input a falling edge is detected a falling edge is detected ferr is generated if 0 is received in the sampling of the stop bit. sampling intrxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit4 bit5 reading of uart0sr reading of rd0buf rd0buf indeterminate data reading rd0buf indeterminate data reading
page 217 TMP89FH46 ra001 16.12.3overrun error if receiving of all data bits is co mpleted before the previous received data is read from rd0buf, the overrun error flag uart0sr is set to "1" and an intrxd 0 interrupt request is generated. the data received at the occurrence of the overr un error is discarded and the previous r eceived data is maintained. subsequently, if data is received while uart0sr is still "1", no intrxd0 interrupt request is generated, and the received data is dis carded. (figure 16-12) note that parity or framing errors in the discarded received data cannot be detected. (these error flags are not set.) that is to say, if these errors are detected together w ith an overrun error during the reading of uart0sr, they have occurred in the previous received da ta (the data stored in rd0buf). (figure 16-13) if uart0sr is "1" when uart0sr is read , uart0sr will be cleared to "0" when rd0buf is read subsequently. (figure 16-14) if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. (figure 16-14) figure 16-12 generation of intrxd0 interrupt request rxd0 pin input data a data a an interrupt request is generated. the flag is set. an interrupt request is generated. no interrupt request is generated. data b intrxd0 interrupt request uart0sr uart0sr start bit0 bit1 bit7 stop start bit0 bit1 bit7 stop rd0buf start bit0 bit1 bit7 stop data c the contents of data b are discarded and those of data a are maintained. the contents of data c are discarded and those of data a are maintained.
page 218 16. asynchronous serial interface (uart) 16.12 status flag TMP89FH46 ra001 figure 16-13 framing/parity erro r flags when an overrun error occurs rxd0 pin input data a data a a parity error occurs. an interrupt request is generated. the error flag is not set together with an overrun error. an interrupt request is generated. the flag is set. no interrupt request is generated. data b intrxd0 interrupt request when a parity error occurs in the first received data and a framing error occurs in the second data when a parity error occurs in the second received data uart0sr uart0sr start bit0 parity stop start bit0 parity stop rd0buf uart0sr uart0sr start bit0 parity stop start bit0 parity stop data c data d the contents of data b are discarded and those of data a are maintained. the contents of data c are discarded and those of data a are maintained. the contents of data d are discarded and those of data a are maintained. the parity is ok. the parity is ok. the flag is not set even if a framing error occurs. rxd0 pin input data a data a an interrupt request is generated. an interrupt request is generated. no interrupt request is generated. data b intrxd0 interrupt request uart0sr uart0sr start bit0 parity stop start bit0 parity stop rd0buf uart0sr start bit0 parity stop start bit0 parity stop data c data d the contents of data b are discarded and those of data a are maintained. the contents of data c are discarded and those of data a are maintained. the contents of data d are discarded and those of data a are maintained. a parity error occurs.
page 219 TMP89FH46 ra001 figure 16-14 clearance of overrun error flag rxd0 pin input data a data a reading of data a the contents of data b are discarded and those of data a are maintained. data b oerr is cleared to 0 when rd0buf is read after reading oerr=1. rbfl is cleared to 0 when rd0buf is read after reading rbfl=1. intrxd0 interrupt request uart0sr uart0sr start bit0 bit1 bit7 stop start bit0 bit1 bit7 stop reading of uart0sr reading of rd0buf rd0buf rxd0 pin input data a data a reading of data a the contents of data b are discarded and those of data a are maintained. data b oerr is cleared to 0 when rd0buf is read after reading oerr=1. rbfl is cleared to 0 when rd0buf is read after reading rbfl=1. intrxd0 interrupt request uart0sr uart0sr start bit0 bit1 bit7 stop start bit0 bit1 bit7 stop reading of uart0sr reading of rd0buf rd0buf reading of data a
page 220 16. asynchronous serial interface (uart) 16.12 status flag TMP89FH46 ra001 16.12.4receive data buffer full loading the received data in rd0b uf sets uart0sr to "1". if uart0sr is "1" when uart0sr is r ead, uart0sr will be cleared to "0" when rd0buf is read subsequently. if uart0sr is set to "1" after uart0sr is read, uart0sr will not be cleared to "0" when rd0buf is read subsequently. in this case, uart0sr will be cleared to "0" when uart0sr is read again and rd0buf is read. figure 16-15 occurrence of receive data buffer full rxd0 pin input data a data a reading of data a data b reading of data b data b rbfl is cleared to 0 when rd0buf is read after reading rbfl=1. intrxd0 interrupt request uart0sr start bit1 bit0 bit7 stop start bit0 bit1 bit7 stop reading of uart0sr reading of rd0buf rd0buf
page 221 TMP89FH46 ra001 16.12.5 transmit busy flag if transmission is completed with no waiting data in td0buf (when uart0sr="0"), uart0sr is cleared to "0". when transmission is restarted after data is written into td0buf, uart0sr is set to "1". at this time , an inttxd0 interrupt request is generated. figure 16-16 transmit busy flag and occurrence of transmit buffer full 16.12.6transmit buffer full when td0buf has no data, or when data in td0buf is transferred to the transmit shift register and trans- mission is started, uart0sr is cleared to "0". at this time, an inttxd0 interrupt request is gener- ated. writing data into td0buf sets uart0sr to "1". figure 16-17 occurrence of transmit buffer full txd0 pin input inttxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit6 bit7 stop writing of td0buf uart0sr uart0cr1 data a data b writing of data a writing of data b txd0 pin input inttxd0 interrupt request uart0sr start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop start bit0 bit1 bit2 bit3 bit6 bit7 stop writing of td0buf uart0sr uart0cr1 data a data b writing of data a writing of data b
page 222 16. asynchronous serial interface (uart) 16.13 receiving process TMP89FH46 ra001 16.13receiving process figure 16-18 shows an example of the r eceiving process. details of flag judg ments in the processing are shown in table 16-10 and table 16-11. if any framing error or parity error is detected, the received data has erro neous value(s). execute the error han- dling, for example, by discarding the received data read from rd0buf and receiving the data again. if any overrun error is detect ed, the receiving of one or more pieces of data is unfinished. it is impossible to deter- mine the number of pieces of da ta that could not be received. execute the error handling, for ex ample, by receiving data again from the beginning of the transfer. basically, an overrun error occurs when th e internal software process- ing cannot follow the data transfer speed. it is recommended to slow the transfer baud rate or modify the software to execute flow control. figure 16-18 example of receiving process note 1: if multiple interrupts are used in the intrxd0 interrupt subroutine, the interrupt should be enabled after reading uart0sr and rd0buf. receiving process end when no receive interrupt is used when a receive interrupt is used read uart0sr read rd0buf error handling error handling error handling error handling data processing (received data is valid) uart0sr 1 1 1 0 0 0 1 0 uart0sr parity error framing error overrun error parity error framing error overrun error uart0sr uart0sr intrxd0 interrupt subroutine reti read uart0sr read rd0buf data processing (received data is valid) 1 1 0 0 1 0 uart0sr uart0sr uart0sr
page 223 TMP89FH46 ra001 table 16-10 flag judgments when no receive interrupt is used rbfl ferr/perr oerr state 0 - 0 data has not been received yet. 0-1 some pieces of data could not be received during the previ- ous data receiving process (receiving of next data is completed in the period from when uart0sr is read to when rd0buf is read in the previous data receiving process.) 1 0 0 receiving has been completed properly. 101 receiving has been completed pr operly, but some pieces of data could not be received. 1 1 0 received data has erroneous value(s). 111 received data has erroneous value(s) and some pieces of data could not be received. table 16-11 flag judgments when a receive interrupt is used ferr/perr oerr state 0 0 receiving has been completed properly. 01 receiving has been completed properly, but some pieces of data could not be received. 1 0 received data has erroneous value(s). 11 received data has erroneous value(s) and some pieces of data could not be received.
page 224 16. asynchronous serial interface (uart) 16.14 ac properties TMP89FH46 ra001 16.14ac properties 16.14.1irda properties (v ss = 0 v, topr = ? 40 to 85 c) item condition min typ. max unit txd output pulse time (rt clock (3/16)) transfer baud rate = 2400 bps ? 78.13 ? s transfer baud rate = 9600 bps ? 19.53 ? transfer baud rate = 19200 bps ? 9.77 ? transfer baud rate = 38400 bps ? 4.88 ? transfer baud rate = 57600 bps ? 3.26 ? transfer baud rate = 115200 bps ? 1.63 ?
page 225 TMP89FH46 ra001 17. synchronous serial interface (sio) the TMP89FH46 contains 1 channel of high-speed 8-bit serial interfaces of the clock sync hronization type. table 17-1 sfr address assignment sioxcr (address) sioxsr (address) sioxbuf (address) serial interface 0 sio0cr (0x001f) sio0sr (0x0020) sio0buf (0x0021) table 17-2 pin names serial clock input/output pin serial data input pin serial data output pin serial interface 0 sclk0 pin si0 pin so0 pin
page 226 17. synchronous serial interface (sio) 17.1 configuration TMP89FH46 ra001 17.1 configuration figure 17-1 serial interface note: the serial interface input/output pins are also used as the i/o ports. the i/o port register settings are required to use these pins for a serial interface. for details, refer to the chapter of i/o ports. shift register on transmitter shift register on receiver control circuit shift clock internal clock port (note) port (note) msb/lsb selection port (note) internal bus internal bus sio0cr sio0sr sio0buf sio0buf intsio0 interrupt request so0 pin si0 pin sclk0 pin
page 227 TMP89FH46 ra001 17.2 control the synchronous serial interface sio0 is controlled by the low power consumption registers (poffcr2), the serial interface data buffer register (s io0buf), the serial interface control regi ster (sio0cr) and the serial interface status register (sio0sr). note 1: sio0buf is the data buffer for both transmission and rec eption. the last received data is read each time sio0buf is read. if sio0buf has never received data, it is read as "0". w hen data is written into it, the data is treated as the transmit data. low power consumption register 2 poffcr2 76543210 (0x0f76) bit symbol - - rtcen - - - - sio0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 rtcen rtc control 0 1 disable enable sio0en sio0 control 0 1 disable enable serial interface buffer register sio0buf 76543210 (0x0021) bit symbol sio0buf read/write r after reset00000000 serial interface buffer register sio0buf 76543210 (0x0021) bit symbol sio0buf read/write w after reset11111111
page 228 17. synchronous serial interface (sio) 17.2 control TMP89FH46 ra001 note 1: fcgck: gear clock [h z], fs: low-frequency clock [hz] note 2: after the operation is started by writing "1" to sios , writing to sioedg, siocks and siodir is invalid until sio0sr becomes "0". (sioedg, siocks and siodir can be changed at the same time as changing sios from "0" to "1".) note 3: after the operation is started by writing "1" to sios, no values other than"00" can be written to siom until siof become s "0" (if a value from "01" to "11" is written to siom, it is ignored). the transfer mode cannot be changed during the opera- tion. note 4: sios remains at "0", if "1" is writte n to sios when siom is "00" (operation stop). note 5: when sio is used in slow1/2 or sleep1 mode, be sure to set siocks to "110". if siocks is set to any other value, sio will not operate. when sio is used in slow1/2 or sl eep1 mode, execute communications with siocks="110" in advance or change siocks after sio is stopped. note 6: when stop, idle0 or sleep0 mode is activated, siom is automatically cleared to "00" and sio stops the operation. at the same time, sios is cleared to "0". however, the values set for sioedg, siocks and siodir are maintained. serial interface control register sio0cr 76543210 (0x001f) bit symbol sioedg siocks siodir sios siom read/write r/w r/w r/w r/w r/w after reset00000000 sioedg transfer edge selection 0 1 0: receive data at a rising edge and transmit data at a falling edge 1: transmit data at a rising edge and receive data at a falling edge siocks serial clock selection [hz] normal1/2 or idle1/2 mode slow1/2 or sleep1 mode 000 fcgck/2 9 - 001 fcgck/2 6 - 010 fcgck/2 5 - 011 fcgck/2 4 - 100 fcgck/2 3 - 101 fcgck/2 2 - 110 fcgck/2 fs/2 3 111 external clock input siodir transfer format (msb/lsb) selec- tion 0 1 lsb first (transfer from bit 0) msb first (transfer from bit 7) sios transfer operation start/stop instruction 0 1 0: operation stop (reserved stop) 1: operation start siom transfer mode selection and operation 00 operation stop (forced stop) 01 8-bit transmit mode 10 8-bit receive mode 11 8-bit transmit and receive mode
page 229 TMP89FH46 ra001 note 1: the oerr and uerr flags are cleared by reading sio0sr. note 2: the rend flag is cleared by reading sio0buf. note 3: writing "00" to sio0cr clears all the bits of sio0 sr to "0", whether the serial interface is operating or not. whe n stop, idle0 or sleep0 mode is activated, siom is automatical ly cleared to "00" and all the bits of sio0sr are cleared to "0". note 4: bit 1 to 0 of sio0sr are read "0". serial interface status register sio0sr 76543210 (0x0020) bit symbol siof sef oerr rend uerr tbfl - - read/writerrrrrrrr after reset00000000 siof serial transfer operation status monitor 0 1 transfer not in progress transfer in progress sef shift operation status monitor 0 1 shift operation not in progress shift operation in progress oerr receive overrun error flag 0 1 no overrun error has occurred at least one overrun error has occurred rend receive completion flag 0 1 no data has been received since the last receive data was read out at least one data receive operation has been executed uerr transmit underrun error flag 0 1 no transmit underrun error has occurred at least one transmit underrun error has occurred tbfl transmit buffer full flag 0 1 the transmit buffer is empty the transmit buffer has the data that has not yet been transmitted
page 230 17. synchronous serial interface (sio) 17.3 low power consumption function TMP89FH46 ra001 17.3 low power consumption function serial interface 0 has the low power co nsumption registers (poff cr2) that save power when the serial interface is not being used. setting poffcr2 to "0" disables the basic clock supply to serial interface 0 to save power. note that this renders the serial interface unusab le. setting poffcr2 to "1" enab les the basic clock supply to serial interface 0 and allows the se rial interface to operate. after reset, poffcr2 are initialized to "0", and this renders the serial interface un usable. when using the serial interface for the first time, be sure to set poffcr2 to "1" in the initial setting of the program (before the serial interface co ntrol registers are operated). do not change poffcr2 to "0" during the serial interface oper ation. otherwise serial interface 0 may operate unexpectedly.
page 231 TMP89FH46 ra001 17.4 functions 17.4.1 transfer format the transfer format can be set to either msb or lsb first by using sio0cr. setting sio0cr to "0" selects lsb first as the transfer fo rmat. in this case, the seri al data is transferred in sequence from the least significant bit. setting sio0cr to "1" selects msb first as the transfer format. in this case, the serial data is transferred in sequence from the most significant bit. 17.4.2 serial clock the serial clock can be selected by using sio0cr. setting sio0cr to "000" to "110" selects the inte rnal clock as the serial clock. in this case, the serial clock is output from the sclk0 pin. the serial data is transferred in synchronization with the edge of the sclk0 pin output. setting sio0cr to "111" select s an external clock as the serial clock. in this case, an external serial clock must be input to the sclk0 pin. the serial data is transferred in sync hronization with the edge of the external clock. the serial data transfer edge can be selected for both the external and internal clocks. for details, refer to "17.4.3 transfer edge selection". 17.4.3 transfer edge selection the serial data transfer edge can be selected by using siocr. when siocr is "0", the data is transmitted in synchronization with the falling edge of the clock and the data is received in synchronizat ion with the rising edge of the clock. when siocr is "1", the data is transmitted in synchronization with the rising edge of the clock and the data is received in synchronizat ion with the falling edge of the clock. table 17-3 transfer baud rate sio0cr serial clock [hz] fcgck=4mhz fcgck=8mhz fcgck=10mhz fs=32.768khz normal1/2 or idle1/2 mode slow1/2 or sleep1 mode 1-bit time ( s) baud rate (bps) 1-bit time ( s) baud rate (bps) 1-bit time ( s) baud rate (bps) 1-bit time ( s) baud rate (bps) 000 fcgck/2 9 - 128 7.813k 64 15.625k 51.2 19.531k - - 001 fcgck/2 6 - 16 62.5k 8 125k 6.4 156.25k - - 010 fcgck/2 5 - 8 125k 4 250k 3.2 312.5k - - 011 fcgck/2 4 - 4 250k 2 500k 1.6 625k - - 100 fcgck/2 3 - 2 500k 1 1m 0.8 1.25m - - 101 fcgck/2 2 - 1 1m 0.5 2m 0.4 2.5m - - 110 fcgck/2 fs/2 3 0.5 2m 0.25 4m 0.2 5m 244 4k table 17-4 transfer edge selection sio0cr data transmission data reception 0 falling edge rising edge 1 rising edge falling edge
page 232 17. synchronous serial interface (sio) 17.4 functions TMP89FH46 ra001 figure 17-2 transfer edge note:when an external clock input is us ed, 4/fcgck or longer is needed between the receive edge at the 8th bit and the transfer edge at the first bit of the next transfer. r1 r0 r2 r3 r4 r5 r6 r7 t1 t0 t2 t3 t4 t5 t6 t7 slck0 pin so0 pin si0 pin when siocr=0 r1 r0 r2 r3 r4 r5 r6 r7 t1 t0 t2 t3 t4 t5 t6 t7 sclk0 pin so0 pin si0 pin when siocr=1 c7 c6 d0 d1 d2 a7 a6 b0 b1 b2 tbi leading edge at the 1st bit (transmit edge) trailing edge at the 8th bit (receive edge) sclk0 pin so0 pin si0 pin symbol name minimum time tbi interval time between bytes 4/fcgck
page 233 TMP89FH46 ra001 17.5 transfer modes 17.5.1 8-bit transmit mode the 8-bit transmit mode is selected by setting sio0cr to "01". 17.5.1.1 setting before starting the transmit operati on, select the transfer edges at sio0cr, a transfer format at sio0cr and a serial cl ock at sio0cr. to use th e internal clock as the serial clock, select an appropriate serial clock at sio0 cr. to use an external clock as the serial clock, set sio0cr to "111". the 8-bit transmit mode is selected by setting sio0cr to "01". the transmit operation is started by writing the first byte of transmit data to sio0buf and then setting sio0cr to "1". writing data to sio0cr is invalid when the serial communication is in progress, or when sio0sr is "1". make these settings while th e serial communication is stopped. while the serial communication is in progress (sio0sr="1"), only writing "00" to sio0cr or writing "0" to sio0cr is valid. 17.5.1.2 starting the transmit operation the transmit operation is started by writing data to sio0buf and then setting sio0cr to "1". the transmit data is transferred from sio0buf to the shift register, and then transmitted as the serial data from the so0 pin according to the settings of si o0cr. the serial data becomes undefined if the transmit operation is started without writing any transmit data to sio0buf. in the internal clock operation, the serial clock of the selected baud rate is output from the sclk0 pin. in the external clock operation, an external clock must be supplied to the sclk0 pin. by setting sio0cr to "1", sio0sr are automatically set to "1" and an intsio0 interrupt request is generated. sio0sr is cleared to "0" when the 8th bit of the serial data is output. 17.5.1.3 transmit buffer and shift operation if data is written to sio0buf when the serial communication is in progress and the shift register is empty, the written data is transferred to the shif t register immediately. at this time, sio0sr remains at "0". if data is written to sio0buf when some data re mains in the shift register, sio0sr is set to "1". if new data is written to sio0buf in this stat e, the contents of sio0buf are overwritten by the new value. make sure that sio0sr is "0" before writing data to sio0buf. 17.5.1.4 operation on completion of transmission the operation on completion of the data transmission varies depending on the operating clock and the state of sio0sr.
page 234 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 (1) when the internal clock is used and sio0sr is "0" when the data transmission is completed, the sclk0 pin becomes the initial state and the so0 pin becomes the "h" level. sio0sr remains at "0 ". when the internal clock is used, the serial clock and data output is stopped until the next transmit data is written into sio0buf (automatic wait). when the subsequent data is written into sio0buf, sio0sr is set to "1", the sclk0 pin outputs the serial clock, and the transmit operation is restarted. an intsio0 interrupt request is gen- erated at the restart of the transmit operation. (2) when an external clock is used and sio0sr is "0" when the data transmission is co mpleted, the so pin keeps last output value. when an external serial clock is input to the sclk0 pin after comple tion of the data transmission, an undefined value is transmitted and the transmit underrun error flag sio0sr is set to "1". if a transmit underrun er ror occurs, data must not be written to sio0buf during the transmission of an undefined value. (it is recommended to finish the transmit operation by setting sio0cr to "0" or force the transmit operation to stop by setting sio0cr to "00".) the transmit underrun erro r flag sio0sr is cleared by reading sio0sr. (3) when an internal or external clock is used and sio0sr is "1" when the data transmission is completed, si o0sr is cleared to "0". the data in sio0buf is transferred to the shift register and the tr ansmission of subsequent data is started. at this time, sio0sr is set to "1" and an intsio0 interrupt request is generated. 17.5.1.5 stopping the transmit operation set sio0cr to "0" to stop the transmit oper ation. when sio0sr is "0", or when the shift operation is not in progress, the transmit operation is stopped immediately and an intsio0 interrupt request is generated. when sio0sr is "1", the tr ansmit operation is stopped after all the data in the shift register is transmitted (reserved stop). at this time, an intsio0 interrupt request is generated again. when the transmit operation is completed, sio0sr are cleared to "0". other sio0sr registers keep their values. if the internal clock has been used, the so0 pin auto matically returns to the "h" level. if an external clock has been used, the so0 pin keeps the last output value. to return the so0 pin to the "h" level, write "00" to sio0cr when the operation is stopped. the transmit operation can be for ced to stop by setting sio0cr to "00" during the operation. by setting sio0cr to "00" , sio0cr and sio0sr are cl eared to "0" and the sio stops the operation, regardless of the sio0sr value. the so0 pin becomes the "h" level. if the internal clock is selected, the sclk0 pin returns to the initial level.
page 235 TMP89FH46 ra001 figure 17-3 8-bit transmit mode (internal clock and reserved stop) figure 17-4 8-bit tr ansmit mode (internal cl ock and forced stop) so0 pin (output) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf ab c sio0cr sio0cr sio0sr sio0sr sio0sr data a data b writing data a writing data b writing data c reserved stop start operation an interrupt is generated after transmission in case of reserved stop the level is held for the period of the internal clock(1/2) automatic wait 01 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 write to sio0buf sio0buf ab c d sio0cr sio0cr sio0sr sio0sr sio0sr data a data b writing data a writing data b writing data c writing data d forced stop start operation 01 01 00 00 start operation bit0 bit1 bit2 bit3 bit4 bit5 data c forced stop forced stop has priority over reserved stop data is not held but becomes the h level clock output is stopped reserved stop
page 236 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 figure 17-5 8-bit trans mit mode (external clo ck and reserved stop) figure 17-6 8-bit tran smit mode (external clock and forced stop) so0 pin (output) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf ab c sio0cr sio0sr sio0sr sio0sr data a data b writing data a writing data b writing data c reserved stop start operation an interrupt is generated after transmission in case of reserved stop stopped while keeping the current level in the operation with an external clock returned to the h level by setting siocr1 to 00 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c sio0cr 01 00 so0 pin (output) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 write to sio0buf sio0buf abc d sio0cr sio0sr sio0sr sio0sr data a data c writing data a writing data b writing data c writing data d reserved stop start operation start operation bit0 bit1 bit2 bit3 bit4 bit5 data c forced stop forced stop has priority over reserved stop if two pieces of data are written, the latter data is effective when the operation is restarted after a forced stop, the last data written to the buffer is transmitted. data is not held but becomes the h level reserved stop sio0cr 01 01 00 00
page 237 TMP89FH46 ra001 figure 17-7 8-bit tr ansmit mode (external clock and occurrence of transmit underrun error) so0 pin (output) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf abc read sio0sr sio0cr sio0sr sio0sr sio0sr sio0sr data a data a data b writing data a writing data b reading sio0sr writing data c reserved stop start operation stopped while keeping the current level in the operation with an external clock returned to the h level by setting siocr1 to 00 transferred to the buffer immediately after writing bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data b data c transferred to the buffer immediately after writing sio0cr 01 00
page 238 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 17.5.2 8-bit receive mode the 8-bit receive mode is selected by setting sio0cr to "10". 17.5.2.1 setting as in the case of the transmit mode , before starting the receive operation, sel ect the transfer edges at sio0cr, a transfer form at at sio0cr and a se rial clock at sio0cr. to use the internal clock as the se rial clock, select an appropriate serial cloc k at sio0cr. to use an external clock as the serial clock, set sio0cr to "111". the 8-bit receive mode is selected by setting sio0cr to "10". reception is started by se tting sio0cr to "1". writing data to sio0cr is invalid when the serial communication is in progress, or when sio0sr is "1". make these settings while th e serial communication is stopped. while the serial communication is in progress (sio0sr="1"), only writing "00" to sio0cr or writing "0" to sio0cr is valid. 17.5.2.2 starting the receive operation reception is started by setting sio0cr< sios> to "1". external serial data is taken into the shift register from the si0 pin according to the settings of sio0cr. in the internal clock operation, the serial clock of the selected baud rate is output from the sclk0 pin. in the external clock operation, an external clock must be supplied to the sclk0 pin. by setting sio0cr to "1", sio0sr are automatically set to "1". 17.5.2.3 operation on completion of reception when the data reception is complete d, the data is transferred from th e shift register to sio0buf and an intsio0 interrupt request is generated. the receive completion flag sio0sr is set to "1". in the operation with the internal clock, the serial clock output is stopped until the receive data is read from sio0buf (automatic wait). at this time, sio0 sr is set to "0". by reading the receive data from sio0buf, sio0sr is set to "1", the serial clock output is restarted a nd the receive operation continues. in the operation with an external clock, data can be continuously received without reading the received data from sio0buf. in this case, data must be r ead from sio0buf before the subsequent data has been fully received. if the subsequent data is received comp letely before reading data from sio0buf, the over- run error flag sio0sr is se t to "1". when an overrun erro r has occurred, set sio0cr to "00" to abort the receive operation. the data received at the occurrence of an overrun error is discarded, and sio0buf holds the data value received before the occurrence of the overrun error. sio0sr is cleared to "0" by reading data from sio0buf. sio0sr is cleared by reading sio0sr. 17.5.2.4 stopping the receive operation set sio0cr to "0" to stop th e receive operation. wh en sio0sr is "0", or when the shift operation is not in progress, the op eration is stopped immediately. unli ke the transmit mode, no intsio0 interrupt request is generated in this state. when sio0sr is "1", the operation is stopped after the 8-b it data has been completely received (reserved stop). at this time, an in tsio0 interrupt request is generated.
page 239 TMP89FH46 ra001 after the operation has stopped completely, sio0sr are cleared to "0". other sio0sr registers keep their values. the receive operation can be forced to stop by se tting sio0cr to "00" during the operation. by setting sio0cr to "00" , sio0cr and sio0sr are cl eared to "0" and the sio stops the operation, regardless of the sio0sr value. if the internal clock is selected, the sclk0 pin returns to the initial level. figure 17-8 8-bit receive mode (internal clock and reserved stop) si0 pin (input) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf ac sio0cr sio0sr sio0sr sio0sr data a reading data a reading data c reserved stop automatic wait bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c sio0cr 10
page 240 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 figure 17-9 8-bit receive mode (internal clock and forced stop) figure 17-10 8-bit re ceive mode (external clock and reserved stop) si0 pin (input) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf a sio0cr sio0cr sio0sr sio0sr sio0sr data a reading data a returned to the initial level reserved stop forced stop forced stop start operation start operation automatic wait 10 00 00 10 bit0 bit1 bit2 bit3 bit0 bit1 bit2 data b data c returned to the initial level si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf abc sio0cr sio0sr sio0sr sio0sr data a reading data a reading data b reserved stop start operation bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data b bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c sio0cr 10
page 241 TMP89FH46 ra001 figure 17-11 8-bit receive mode (external clock and forced stop) figure 17-12 8-bit receive mode (external clock and occu rrence of overrun error) si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf ac sio0cr sio0cr sio0sr sio0sr sio0sr data a reading data a reading data c forced stop start operation start operation 10 00 10 data b data b is discarded data c si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 read sio0buf sio0buf a read sio0sr sio0cr sio0cr sio0sr sio0sr sio0sr sio0sr data a reading data a data b is discarded subsequent data is received completely before reading data a data c is discarded reading sui0sr forced stop start operation 10 00 data b data c
page 242 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 17.5.3 8-bit trans mit/receive mode the 8-bit transmit/receive mode is sel ected by setting sio0cr to "11". 17.5.3.1 setting before starting the transmit/receive operation, select the transfer edges at sio0cr, a trans- fer format at sio0cr and a serial clock at sio0cr< siocks>. to use the internal clock as the serial clock, select an appropriate serial clock at sio0cr. to use an external clock as the serial clock, set sio0cr to "111". the 8-bit transmit/receive mode is se lected by setting sio0cr to "11". the transmit/receive operation is st arted by writing the fi rst byte of transmit data to sio0buf and then setting sio0cr to "1". writing data to sio0cr is invalid when the serial communication is in progress, or when sio0sr is "1". make these settings while th e serial communication is stopped. while the serial communication is in progress (sio0sr="1"), only writing "00" to sio0cr or writing "0" to siocr is valid. 17.5.3.2 starting the transmit/receive operation the transmit/receive operation is started by writing data to sio0bu f and then setting sio0cr to "1". the transmit data is transferred from sio0buf to the shift register, and the serial data is transmit- ted from the so0 pin according to the settings of sio0cr. at the same time, the serial data is received from the si0 pin according to the settings of sio0cr. in the internal clock operation, the serial clock of the selected baud rate is output from the sclk0 pin. in the external clock operation, an external clock must be supplied to the sclk0 pin. the transmit data becomes undefi ned if the transmit/recei ve operation is starte d without writing any transmit data to sio0buf. by setting sio0cr to "1", sio0sr are automatically set to "1" and an intsio0 interrupt request is generated. sio0sr is cleared to "0" when the 8th bit of data is received. 17.5.3.3 transmit buffer and shift operation if any data is written to sio0buf when the serial communi cation is in progress and the shift register is empty, the written data is transferred to the shif t register immediately. at this time, sio0sr remains at "0". if any data is written to sio0buf when some data remains in the shift register, sio0sr is set to "1". if new data is written to sio0buf in this state, the contents of si o0buf are overwritten by the new value. make sure that sio0sr is "0" before writing data to sio0buf. 17.5.3.4 operation on completion of transmission/reception when the data transmissi on/reception is completed, sio0sr is set to "1" and an intsio0 interrupt request is generated. the operation varies depending on the operating clock.
page 243 TMP89FH46 ra001 (1) when the internal clock is used if sio0sr is "1", it is cleared to "0 " and the transmit/receive operation continues. if sio0sr is already "1", sio0sr is set to "1". if sio0sr is "0", the transmit/receive operatio n is aborted. the sclk0 pin becomes the initial state and the so0 pin becomes the "h" leve l. sio0sr remains at "0". when the subse- quent data is written to sio0buf, sio0sr is set to "1", the sclk0 pin outputs the clock and the transmit/receive op eration is restarted. to confirm the r eceive data, read it from sio0buf before writing data to sio0buf. (2) when an external clock is used the transmit/receive operation conti nues. if the external serial cl ock is input with out writing any data to sio0buf, the last data value set to sio0 buf is re-transmitted. at this time, the transmit underrun error flag sio0sr is set to "1". when the next 8-bit data is received completely before sio0buf is read, or in the state of sio0sr="1", sio0sr is set to "1". 17.5.3.5 stopping the transmit/receive operation set sio0cr to "0" to stop th e transmit/receive operation. when sio0sr is "0", or when the shift operation is not in progres s, the operation is stopped immediat ely. unlike the transmit mode, no intsio0 interrupt request is generated in this state. when sio0sr is "1", the operation is stopped af ter the 8-bit data is r eceived completely. at this time, an intsio0 interrupt request is generated. after the operation has stopped completely, sio0sr are cleared to "0". other sio0sr registers keep their values. if the internal clock has been used, the so0 pin auto matically returns to the "h" level. if an external clock has been used, the so0 pin keeps the last output value. to return the so0 pin to the "h" level, write "00" to sio0cr when the operation is stopped. the transmit/receive operation can be forced to stop by setting si o0cr to "00" during the operation. by setting sio0cr to "00", sio0 cr and sio0sr are cleared to "0" and the sio stops the operation, regardless of the sio0sr value. the so0 pin becomes the "h" level. if the internal clock is selected, the sclk0 pin returns to the initial level.
page 244 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 figure 17-13 8-bit transmi t/receive mode (i nternal clock and reserved stop) si0 pin (input) internal clock sclk0 pin (output) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf (write buffer) de fg sio0buf (read buffer) ab c sio0cr sio0sr sio0sr sio0sr sio0sr data a data b writing data d read sio0buf reading data a reading data b reading data c writing data e writing data f writing data g reserved stop start operation wait bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data d data e bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data f
page 245 TMP89FH46 ra001 figure 17-14 8-bit transmit/receive m ode (external clock and reserved stop) si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf (write buffer) de fg sio0buf (read buffer) ab c sio0cr sio0cr sio0sr sio0sr sio0sr sio0sr data a 11 00 data b writing data d read sio0buf reading data a reading data b reading data c writing data e writing data f writing data g reserved stop start operation bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data d data e bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data f
page 246 17. synchronous serial interface (sio) 17.5 transfer modes TMP89FH46 ra001 figure 17-15 8-bit transmit/rece ive mode (external clock, o ccurrence of transmit under- run error and occurrence of overrun error) si0 pin (input) sclk0 pin (input) intsio0 interrupt request bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 write to sio0buf sio0buf (write buffer) dfg sio0buf (read buffer) ac read sio0sr sio0cr sio0sr sio0sr sio0sr sio0sr sio0sr sio0sr data a data b writing data d read sio0buf reading data a reading data c writing data f writing data g reserved stop start operation bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data c so0 pin (output) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data d data d data f bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data g
page 247 TMP89FH46 ra001 17.6 ac characteristics figure 17-16 ac characteristics figure 17-17 interval time between bytes (v ss = 0 v, v dd = 4.5 v - 5.5 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit sclk cycle time t scy internal clock operation so pin and sclk pin load capacity=100 pf 2 / fcgck - - ns sclk "l" pulse width t scyl 1 / fcgck ? 25 -- sclk "h" pulse width t scyh 1 / fcgck ? 15 -- si input setup time t sis 60 - - si input hold time t sih 35 - - so output delay time t sod ? 50 -50 sclk cycle time t scy external clock operation so pin and sclk pin load capacity=100 pf 2 / fcgck - - sclk "l" pulse width t scyl 1 / fcgck - - sclk "h" pulse width t scyh 1 / fcgck - - si input setup time t sis 50 - - si input hold time t sih 50 - - so output delay time t sod 0-60 sclk low-level input voltage t sclkl 0- v dd 0.30 v sclk high-level input voltage t sclkh v dd 0.70 - v dd sclk pin t sis v sclkl v sclkh t scyl t scyh t scy t sod t sih si pin so pin c7 c6 d0 d1 d2 a7 a6 b0 b1 b2 tbi leading edge at the 1st bit (transmit edge) trailing edge at the 8th bit (receive edge) sclk0 pin so0 pin si0 pin symbol name minimum time tbi interval time between bytes 4/fcgck
page 248 17. synchronous serial interface (sio) 17.6 ac characteristics TMP89FH46 ra001
page 249 TMP89FH46 ra001 18. serial bus interface (sbi) the TMP89FH46 contains 1 channels of serial bus interface (sbi). the serial bus interface supports serial communication conf orming to the i 2 c bus standards. it has clock synchro- nization and arbitration functions, and supports the multi-ma ster in which multiple master s are connected on a bus. it also supports the unique free data format. 18.1 communication format 18.1.1 i 2 c bus the i 2 c bus is connected to devices via the sda0 and scl0 pins an d can communicate with multiple devices. figure 18-1 de vice connections communications are implemented between a master and slave. the master transmits the start conditi on, the slave addresses, the direction bit and the stop condition to the slave(s) connected to the bus, and transmits and receives data. the slave detects these conditions tr ansmitted from the master by the ha rdware, and transmits and receives data. the data format of the i 2 c bus that can communicate via the serial bus interface is shown in figure 18-2. the serial bus interface does not support the foll owing functions among those specified by the i 2 c bus stan- dards: 1. start byte 2. 10-bit addressing 3. sda and scl pins falling edge slope control vdd device 1 sda scl device 2 sda scl device n sda scl
page 250 18. serial bus interface (sbi) 18.1 communication format TMP89FH46 ra001 figure 18-2 data format of i 2 c bus 18.1.2 free data format the free data format is for communi cation between a master and slave. in the free data format, the slave address an d the direction bit are processed as data. figure 18-3 free data format 8 bits 1 1 or more 1 to 8 bits 1 1 s a c k a c k a c k p slave address data data 1 to 8 bits 1 r / w 8 bits 1 1 1 or more 1 or more 1 to 8 bits 1 1 1 s a c k a c k a c k p slave address data data slave address 1 to 8 bits 1 r / w 8 bits a c k r / w s (a) addressing format (b) addressing format (with restart) s r/w ack p : start condition : direction bit : acknowledge bit : stop condition 8 bits 1 1 or more 1 to 8 bits 1 1 s a c k a c k a c k p data data data 1 to 8 bits 1 (a) free data format s r/w ack p : start condition : direction bit : acknowledge bit : stop condition
page 251 TMP89FH46 ra001 18.2 configuration figure 18-4 serial bus interface 0 (sbi0) sbi0cr1 i2c0ar sbi0dbr sbi0cr2 sbi0sr2 clock control circuit software reset circuit transfer control circuit shift register data control circuit l o r t n o c t u p t u o / t u p n i sda scl noise canceller noise canceller c b t s r w s n i p / b b / x r t / t s m k c a k c a o n k c s s l a b r l 0 s a / s a a / l a / x r t / t s m b b a s intsbi interrupt request
page 252 18. serial bus interface (sbi) 18.3 control TMP89FH46 ra001 18.3 control the following registers are used to control the serial bus interface and monitor the op eration status. ? serial bus interface contro l register 1 (sbi0cr1) ? serial bus interface contro l register 2 (sbi0cr2) ? serial bus interface status register 2 (sbi0sr2) ? serial bus interface data buffer register (sbi0dbr) ?i 2 c bus address register (i2c0ar) in addition, the serial bus interface has low power consumpt ion registers that save power when the serial bus inter- face is not being used. note 1: when sbi0en is cleared to "0", the clock supply to the se rial bus interface is stopped. at this time, the data written to the serial bus interface control registers is invalid. when the serial bus interface is used, set sbi0en to "1" and then write the data to the serial bus interface control registers. low power consumption register 1 poffcr1 76543210 (0x0f75) bit symbol - - - sbi0en - - uart1en uart0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 sbi0en i2c0 control 0 1 disable enable uart1en uart1 control 0 1 disable enable uart0en uart0 control 0 1 disable enable serial bus interface control register 1 sbi0cr1 (0x0022) 76543210 bit symbol bc ack noack sck read/write r/w r/w r/w r/w after reset00000000
page 253 TMP89FH46 ra001 note 1: fcgck: gear clock [hz], fs: low -frequency clock oscill ation circuit clock note 2: don't change the contents of the registers when the star t condition is generated, the st op condition is generated or the data transfer is in progress. write data to the registers befor e the start condition is generated or during the period from when an interrupt request is generated for st opping the data transfer until it is released. note 3: after a software reset is generated, all the bits of sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 4: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. note 5: when fcgck is 4mhz, sck should be not set to 0y000, 0y001 or 0y010 because it is not poss ible to satisfy the bus speci- fication of fast mode. bc number of data bits bc ack=0 ack=1 number of clocks for data transfer number of data bits number of clocks for data transfer number of data bits 000: 8 8 9 8 001: 1 1 2 1 010: 2 2 3 2 011: 3 3 4 3 100: 4 4 5 4 101: 5 5 6 5 110: 6 6 7 6 111: 7 7 8 7 ack generation and counting of the clocks for an acknowledge signal ack master mode slave mode 0: not generating the clocks for an acknowledge signal. generate an interrupt request when the data transfer is finished (non-acknowledgement mode) generate an interrupt request when the data transfer is finished (non-acknowledgement mode) 1: generate the clocks for an acknowledge signal and an inter- rupt request when the data trans- fer is finished (acknowledgement mode) count the clocks for an acknowledge signal and generate an interrupt request when the data transfer is finished (acknowledgement mode) noack enables/disables the slave address match detection and the gen- eral call detection noack master mode slave mode 0: don?t care enable the slave address match detection and the general call detection 1: don?t care disable the slave address match detection and the general call detection sck high and low periods of the serial clock in the master mode time before the release of the scl pin in the slave mode sck t high (m/fcgck) t low (n/fcgck) fscl@fcgck= 8mhz fscl@fcgck= 4mhz mn 000: 9 12 381khz reserved (note5) 001: 11 14 320khz reserved (note5) 010: 15 18 242khz reserved (note5) 011: 23 26 163khz 82khz 100: 39 42 99khz 49khz 101: 71 74 55khz 28khz 110: 135 138 29khz 15khz 111: 263 266 15khz 8khz serial bus interface control register 2 sbi0cr2 (0x0023) 76543210 bit symbol mst trx bb pin sbim - swrst read/writewwwww r w after reset000100 0
page 254 18. serial bus interface (sbi) 18.3 control TMP89FH46 ra001 note 1: when sbi0cr2 is "0", no value can be written to sbi0cr2 except sbi0cr2. before writing values to sbi0cr2, write "1" to sbi0cr2 to activate the serial bus interface mode. note 2: don't change the contents of the registers, except sbi0cr2, when the start condition is generated, the stop condition is generated or the data transfer is in progress. write data to the registers before the start condition is generated or during the period from when an interrupt request is g enerated for stopping the data tr ansfer until it is released. note 3: make sure that the port is in a high state before switching the port mode to the serial bus interface mode. make sure th at the bus is free before switching the serial bus interface mode to the port mode. note 4: sbi0cr2 is a write-only register, and must not be accessed by using a read-modify-write in struction, such as a bit opera - tion. note 5: after a software reset is generated, all the bits of sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 6: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. note 1: * : unstable note 2: when sbi0cr2 becomes "0", sbi0sr is initialized. note 3: after a software reset is generated, all the bits of the sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 4: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. mst master/slave selection 0: slave 1: master trx transmitter/receiver selection 0: receiver 1: transmitter bb start/stop generation 0: generate the stop condition (when mst, trx and pin are "1") 1: generate the start condition (when mst, trx and pin are "1") pin cancel interrupt service request 0: - (cannot clear this bit by the software) 1: cancel interrupt service request sbim serial bus interface operation mode register 0: port mode 1: serial bus interface mode swrst software reset start bit the software reset starts by first writing "10" and next writing "01" serial bus interface status register 2 sbi0sr2 (0x0023) 76543210 bit symbol mst trx bb pin al aas ad0 lrb read/writerrrrrrrr after reset0001000* mst master/slave selection status monitor 0: slave 1: master trx transmitter/receiver selection status monitor 0: receiver 1: transmitter bb bus status monitor 0: bus free 1: bus busy pin interrupt service requests sta- tus monitor 0: requesting interrupt service 1: releasing interrupt service request al arbitration lost detection monitor 0: - 1: arbitration lost detected aas slave address match detection monitor 0: - 1: detect slave address match or "general call" ad0 "general call" detection monitor 0: - 1: detect "general call" lrb last received bit monitor 0: last received bit is "0" 1: last received bit is "1"
page 255 TMP89FH46 ra001 note 1: don't set i2c0ar to "0x00". if it is set to "0x00", the slave address is deemed to be matched when the i 2 c bus stan- dard start byte ("0x01") is received in the slave mode. note 2: don't change the contents of the registers when the star t condition is generated, the st op condition is generated or the data transfer is in progress. write data to the registers befor e the start condition is generated or during the period from when an interrupt request is generated for st opping the data transfer until it is released. note 3: after a software reset is generated, all the bits of the sbi0cr2 register except sbi0cr2 and the sbi0cr1, i2c0ar and sbi0sr2 registers are initialized. note 4: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. note 1: write the transmit data beginning with the most significant bit (bit 7). note 2: sbi0dbr has individual writing and reading buffers, and written data cannot be read out. therefore, sbi0dbr must not be accessed by using a read-m odify-write instruction, such as a bit operation. note 3: don't change the contents of the registers when the star t condition is generated, the st op condition is generated or the data transfer is in progress. write data to the registers befor e the start condition is generated or during the period from when an interrupt request is generated for st opping the data transfer until it is released. note 4: to set sbi0cr2 to "1" by writing the dummy data to sbi0dbr, write 0x00. writing any data other than 0x00 causes an improper value in the subsequently received data. note 5: when the operation is switched to stop, idle0 or slow mode, the sbi0cr2 register, except sbi0cr2, and the sbi0cr1, i2c0ar and sbi0dbr registers are initialized. 18.4 functions 18.4.1 low power c onsumption function the serial bus interface has a low power consumption re gister (poffcr1) that sa ves power when the serial bus interface is not being used. setting poffcr1 to "0" disa bles the basic clock supply to the serial bus interface to save power. note that this makes the serial bus interface unusab le. setting poffcr1 to "1" enables the basic clock supply to the serial bus interf ace and makes external interrupts usable. after reset, poffcr1 is initialized to "0", and this makes the serial bus interface unusable. when using the serial bus interface for the fi rst time, be sure to set poffcr1 to "1" in the initial setting of the program (before the serial bus in terface control regist ers are operated). do not change poffcr1 to "0" during the se rial bus interface operat ion, otherwise serial bus interface may operate unexpectedly. i 2 c bus address register i2c0ar (0x0024) 76543210 bit symbol sa0 als read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 sa slave address setting slave address in the slave mode als communication format selection 0: i 2 c bus mode 1: free data format serial bus interface data buffer register sbi0dbr (0x0025) 76543210 bit symbol sbi0dbr read/write r/w after reset00000000
page 256 18. serial bus interface (sbi) 18.4 functions TMP89FH46 ra001 18.4.2 selecting the slave address match detection and the general call detection sbi0cr1 enables and disables the slave address match detection and the general call detection in the slave mode. clearing sbi0cr1 to "0" enables the slave address match detection and the general call detection. setting sbi0cr1 to "1" disables the subsequent slave address match and general call detections. the slave addresses and "general call" sent from the master are ignored. no acknowledge- ment is returned and no interrupt request is generated. in the master mode, sbi0cr1 is igno red and has no influence on the operation. note:if sbi0cr1 is cleared to "0" during data transfer in the slave mode, it remains at "1" and returns an acknowledge signal of data transfer. 18.4.3 selecting the number of clocks for data transfer and selecting the acknowledge- ment or non-acknowledgment mode 1-word data transfer consists of data and an acknowledge signal. when the data tran sfer is finished, an inter- rupt request is generated. sbi0cr1 is used to select the number of bits of data to be transm itted/received subsequently. the acknowledgment mode is activated by setting sbi0cr1 to "1". the master device generates the clocks for an acknowl edge signal and outputs an acknowledge signal in the receiver mode. the slave device counts the clocks for an acknowledge signal and out puts an acknowledge sig- nal in the receiver mode. the non-acknowledgment mode is activated by setting sbi0cr1 to "0". the master device does not generate the clocks for an acknowledge signal. the sl ave device does not count the clocks for an acknowledge signal. 18.4.3.1 number of clocks for data transfer the number of clocks for data transfer is set by using sbi0cr1 and sbi0cr1. the acknowledgment mode is activated by setting sbi0cr1 to "1". in the acknowledgment mode, the ma ster device generates the clocks that correspond to the number of data bits, generates the clocks for an acknowledge signal, and generates an interrupt request. the slave device counts the clocks th at correspond to the data bits, c ounts the clocks for an acknowl- edge signal, and generates an interrupt request. the non-acknowledgment mode is activated by setting sbi0cr1 to "0". in the non-acknowledgment mode, th e master device generates the cloc ks that correspon d to the number of data bits, and generates an interrupt request. the slave device counts the clocks that correspond to the data bits, and generates an interrupt request.
page 257 TMP89FH46 ra001 figure 18-5 number of clo cks for data transfer and sbi 0cr1 and sbi0cr1 the relationship between the number of clocks for data transfer and sbi0cr1 and sbi0cr1 is shown in table 18-1. bc is cleared to "000" by the start condition. therefore, the slave address and the direction bit are always transferred in 8-bit units. in other cases, bc keeps the set value. note: sbi0cr1 must be set before transmitting or receiving a slave address. when sbi0cr1 is cleared, the slave address match detection and t he direction bit detection are not executed properly. 18.4.3.2 output of an acknowledge signal in the acknowledgment mode, the s da0 pin changes as follows during the period of the clocks for an acknowledge signal. ? in the master mode in the transmitter mode, the sda0 pin is rel eased to receive an acknowledge signal from the receiver during the period of the clocks for an acknowledge signal. in the receiver mode, the sda0 pin is pulled down to the low level and an acknowledge signal is generated during the period of the clocks for an acknowledge signal. ? in the slave mode when a match between the received slave addr ess and the slave address set to i2c0ar is detected or when a genera l call is received, the sda0 pin is pulled down to the low level and an acknowledge signal is generated during the period of the clocks for an acknowl- edge signal. table 18-1 relationship between the number of clocks for data transfer and sbi0cr1 and sbi0cr1 bc ack=0 (non-acknowledgment mode) ack=1 (acknowledgment mode) number of clocks for data transfer number of data bits number of clocks for data transfer number of data bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 22 33 44 56 11 sbi0cr1="110", sbi0cr1="0" s bi0cr1="011", sbi0cr1="1"
page 258 18. serial bus interface (sbi) 18.4 functions TMP89FH46 ra001 during the data transfer after the slave addr ess match is detected or a "general call" is received in the transmit ter mode, the sda0 pin is released to receive an acknowledge signal from the receiver during the period of the clocks for an acknowledge signal. in the receiver mode, the sda0 pin is pulled down to the low level and an acknowledge sig- nal is generated. table 18-2 shows the states of the scl0 and sda0 pins in the acknowledg- ment mode. note: in the non-acknowledgment mode, the clocks for an acknowledge signal are not generated or counted, and thus no acknowledge signal is output. 18.4.4 serial clock 18.4.4.1 clock source sbi0cr1 is used to set the high and low period s of the serial clock to be output in the master mode. table 18-2 states of the scl0 and sda0 pins in the acknowledgment mode mode pin condition transmitter receiver master scl0 - add the clocks for an acknowledge signal. add the clocks for an acknowl- edge signal sda0 - release the pin to receive an acknowledge signal output the low level as an acknowledge signal to the pin slave scl0 - count the clocks for an acknowledge signal count the clocks for an acknowledge signal sda0 when the slave address match is detected or a "general call" is received - output the low level as an acknowledge signal to the pin during transfer after the slave address match is detected or a "gen- eral call" is received release the pin to receive an acknowledge signal output the low level as an acknowledge signal to the pin sck t high (m/fcgck) t low (n/fcgck) mn 000: 9 12 001: 11 14 010: 15 18 011: 23 26 100: 39 42 101: 71 74 110: 135 138 111: 263 266
page 259 TMP89FH46 ra001 figure 18-6 scl output note: there are cases where the high period differs from t high selected at sbi0cr1 when the rising edge of the scl pin becomes blunt due to the load capacity of the bus. in the master mode, the hold time when the start condition is generated is t high [s] and the setup time when the stop condition is generated is t high [s]. when sbi0cr2 is set to "1" in the slave mode, the time that el apses before the release of the scl pin is t low [s]. in both the master and slave modes, the high level period must be 3/fcgck[s] or longer and the low level period must be 5/fcgck[s] or longer for the extern ally input clock, regardless of the sbi0cr1 set- ting. figure 18-7 scl input 18.4.4.2 clock synchronization in the i 2 c bus, due to the structure of the pin, in order to drive a bus with a wired and, a master device which pulls down a clock pulse to low will, in the fi rst place, invalidate the cl ock pulse of another master device which generates a high-level clock pulse. th erefore, the master outputting the high level must detect this to correspond to it. the serial bus interface circuit has a clock synchr onization functi on. this functi on ensures normal transfer even if there are two or more masters on the same bus. the example explains clock synchr onization procedures when two ma sters simultaneously exist on a bus. 1/fscl t low t high t = m / fcgck = n / fcgck high t low fscl = 1/(t high + ) t low scl output scl input t >= >= high t low t low t high
page 260 18. serial bus interface (sbi) 18.4 functions TMP89FH46 ra001 figure 18-8 example of clock synchronization as master 1 pulls down the scl pin to the low level at point "a", the scl line of the bus becomes the low level. after detecting this situation, master 2 resets counting a clock pulse in the high level and sets the scl pin to the low level. master 1 finishes counting a clock pulse in the low level at point "b" and sets the scl pin to the high level. since master 2 holds the scl line of the bus at the low level, master 1 waits for counting a clock pulse in the high level. after master 2 sets a clock pulse to the high level at point "c" and detects the scl line of the bus at the high level, master 1 starts co unting a clock pulse in the high level. then, the master, which has finished the counting a clock pulse in the high level, pulls down the scl pin to the low level. the clock pulse on the bus is determined by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the bus. 18.4.5 master/slave selection to set a master device, sbi0cr2 should be set to "1". to set a slave device, sbi0cr2 should be cleared to "0". when a stop condition on the bus or an arbitration lost is detected, sbi0cr2 is cleared to "0 " by the hardware. 18.4.6 transmitter/receiver selection to set the device as a transmitter, sbi0cr2 shoul d be set to "1". to set the device as a receiver, sbi0cr2 should be cleared to "0". for the i 2 c bus data transfer in the slave mode, sbi0cr2 is set to "1" by the hardware if the direction bit (r/ w ) sent from the master device is "1", a nd is cleared to "0" if the bit is "0". in the master mode, after an acknowledge signal is returned from the slav e device, sbi0cr2 is cleared to "0" by hardware if a transmi tted direction bit is "1", and is set to "1" by hardware if it is "0". when an acknowledge signal is not returned, the current condition is maintained. when a stop condition on the bus or an arbitration lost is detected, sbi0cr2 is cleared to "0" by the hardware. table 18-3 shows sbi0cr2 changing conditi ons in each mode an d sbi0cr2 value after changing. note:when sbi0cr1 is "1", the slave address match detection and the general call detection are disabled, and thus sbi0cr2 remains unchanged. count start abc scl pin (master 1) scl pin (master 2) scl (bus) count reset wait count reset
page 261 TMP89FH46 ra001 when the serial bus interface circuit op erates in the free data format, a slave address and a direction bit are not recognized. they are ha ndled as data just after generating the start condition. sbi0cr2 is not changed by the hardware. 18.4.7 start/stop condition generation when sbi0sr2 is "0", a slave address and a dir ection bit which are set to the sbi0dbr are output on a bus after generating a start condition by writing "1" to sbi0cr2 , sbi0cr2, sbi0cr2 and sbi0cr2. it is necessary to set sbi0cr1 to "1" before generating the start condition. figure 18-9 generati ng the start condition and a slave address when sbi0cr2 is "1", the sequence of generating the stop condition on the bus is started by writing "1" to sbi0cr2, sbi0cr2 and sbi0 cr2 and writing "0" to sbi0cr2. when a stop condition is generated. the scl line on a bus is pulled down to the low level by another device, a stop condition is generated after releasing the scl line. figure 18-10 stop condition generation the bus condition can be indicated by reading the contents of sbi0sr2. sbi0sr2 is set to "1" when the start condition on the bus is detected (bus busy state) and is cleared to "0" when the stop condition is detected (bus free state). table 18-3 sbi0cr1 operation in each mode mode direction bit changing condition trx after changing slave mode "0" a received slave address is the same as the value set to i2c0ar "0" "1" "1" master mode "0" ack signal is returned "1" "1" "0" slave address and direction bit start condition acknowledge signal 23456789 a3 a2 a1 a0 a4 a5 a6 r/w 1 scl0 pin sda0 pin intsbi0 interrupt request stop condition scl0 pin sda0 pin
page 262 18. serial bus interface (sbi) 18.4 functions TMP89FH46 ra001 18.4.8 interrupt serv ice request and release when a serial bus interface circuit is in the master mode and transferring a number of clocks set by sbi0cr1 and sbi0cr1 is complete, a serial bus interface interrupt request (intsbi0) is gener- ated. in the slave mode, a serial bus interface interrupt reque st (intsbi0) is generated when the above and follow- ing conditions are satisfied: ? at the end of the acknowledge signal when the recei ved slave address matches to the value set by the i2c0ar with sbi0cr1 set at "0" ? at the end of the acknowledge signal wh en a "general call" is received with sbi0cr1 set at "0" ? at the end of transferring or r eceiving after matching of the slave a ddress or receiving of "general call" when a serial bus interface interrupt request occurs, sbi0cr2 is cleared to "0". during the time that sbi0cr2 is "0", the scl0 pin is pulled down to the low level. figure 18-11 sbi0cr 2 and scl0 pin writing data to sbi0dbr sets sbi0cr2 to "1". the time from sbi0cr2 being set to "1" until the sbi0 pin is released takes t low . although sbi0cr2 can be set to "1" by the softwa re, sbi0cr2 can not be cleared to "0" by the software. 18.4.9 setting of seri al bus interface mode sbi0cr2 is used to se t serial bus interface mode. setting sbi0cr2 to "1" select s the serial bus interface mode. settin g it to "0" selects the port mode. set sbi0cr2 to "1" in order to set serial bus interface mode. before setting of serial bus interface mode, confirm serial bus interface pins in a hi gh level, and then, writ e "1" to sbi0cr2. and switch a port mode after confirming that a bus is free and set sbi0cr2 to "0". note:when sbi0cr2 is "0", no data can be written to sbi0cr2 except sbi0cr2. before setting values to sbi0cr2, write "1" to sbi0cr2 to activate the serial bus interface mode. 18.4.10software reset the serial bus interface circuit has a software reset functi on that initializes the seri al bus interface circuit. if the serial bus interface circuit locks up , for example, due to noise, it can be initialized by using this function. scl0 pin sbi0cr2 intsbi0 interrupt request 23 789 1 1 t low set sbi0cr2 to "1" or write data to sbi0dbr scl0 pin is pulled to low when sbi0cr2 is "0"
page 263 TMP89FH46 ra001 a software reset is generated by writing "10" and then "01" to sbi0cr2. after a software reset is generated, the serial bus inte rface circuit is initialized an d all the bits of sbi0cr2 register, except sbi0cr2 and the sbi0cr1, i2c0 ar and sbi0sr2 registers, are initialized. 18.4.11arbitration lo st detection monitor since more than one master device can exist simultane ously on a bus, a bus arbitration procedure is imple- mented in order to guarantee th e contents of transferred data. data on the sda line is used for bus arbitration of the i 2 c bus. the following shows an example of a bus arbitration procedure when two master devices exist simulta- neously on a bus. master 1 and master 2 output the same data until point "a". after that, when master 1 outputs "1" and master 2 outputs "0", since the sda line of a bus is wired and, the sda line is pulled down to the low level by master 2. when the scl line of a bus is pulled-up at point "b", the slave device reads data on the sda line, that is data in master 2. data transmitted from master 1 becomes invali d. the state in master 1 is called "arbitration lost". a master device which loses ar bitration releases the sda pin and the scl pin in order not to effect data transmitted from other masters with arbitration. when more than one master sends the same data at the first word, arbitration occurs continuously after the second word. figure 18-12 arbitration lost the serial bus interface circuit compares levels of a sd a line of a bus with its sda pin at the rising edge of the scl line. if the levels are unmatched, arbi tration is lost and sbi0sr2 is set to "1". when sbi0sr2 is set to "1", sbi0cr2 and sbi0cr2 are cleared to "0" and the mode is switched to a slave receiver mode . thus, the serial bus interface circui t stops output of cl ock pulses during data transfer after the sbi0sr2 is set to "1". after the data transfer is completed, sbicr2 is cleared to "0" and the scl pin is pulled down to the low level. sbi0sr2 is cleared to "0" by writing data to the sbi0dbr, reading data from the sbi0dbr or writing data to the sbi0cr2. ab scl (bus) sda pin (master 1) sda pin (master 2) sda (bus) the sda pin becomes "1" after losing arbitration.
page 264 18. serial bus interface (sbi) 18.4 functions TMP89FH46 ra001 figure 18-13 example when master b is a serial bus interface circuit 18.4.12slave address match detection monitor in the slave mode, sbi0sr2 is set to "1" wh en the received data is "general call" or the received data matches the slave address setting by i2 c0ar with sbi0cr1 set at "0" and the i 2 c bus mode is active (i2c0ar="0"). setting sbi0cr1 to "1" disables the subsequent slave address match and general call detections. sbi0sr2 remains at "0" even if a "general call" is received or the same slave address as the i2c0ar set value is received. when a serial bus interface circuit operates in the free data format (i2c0ar= "1"), sbi0sr2 is set to "1" after receiving the firs t 1-word of data. sbi0sr2 is cl eared to "0" by writing data to the sbi0dbr or reading data from the sbi0dbr. figure 18-14 changes in the slave address match detection monitor scl pin sda pin scl pin sda pin d4a 123 123 456789 12 3456789 master a master b stop clock output releasing sda pin and scl pin to high level as losing arbitration. d5a d6a d7a d3a d2a d1a d0a d6a d7a d5a d6a d7a sbi0sr2 sbi0cr2 sbi0cr2 intsbi0 interrupt request access to sbi0dbr or sbi0cr2 start condition output of an acknowledge signal slave address + direction bit sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w scl0 (bus) sda0 (bus) sda0 pin intsbi0 interrupt request writing or reading sbi0dbr
page 265 TMP89FH46 ra001 18.4.13general call detection monitor sbi0sr2 is set to "1" when sbi0cr1 is "0" and general call (all 8-bit received data is "0" immediately after a start condition) in a slave mode. setting sbi0cr1 to "1" disables the subsequent slave address match and general call detections. sbi0sr2 remains at "0" even if a "general call" is received. sbi0sr2 is cleared to "0" when a star t or stop condition is detected on a bus. figure 18-15 changes in the ge neral call detection monitor 18.4.14last receiv ed bit monitor the sda line value stored at the rising edge of the scl line is set to sbi0sr2. in the acknowledge mode, immediately after an interrupt request is generated, an acknowledge signal is read by reading the contents of sbi0sr2. figure 18-16 changes in the last received bit monitor 18.4.15slave address and address recognition mode specification when the serial bus interface circuit is used in the i 2 c bus mode, clear i2c0ar to "0", and set i2c0ar to the slave address. when the serial bus interface circuit is used with a fr ee data format not to recogn ize the slave address, set i2c0ar to "1". with a free data format, the slav e address and the direction bit are not recognized, and they are processed as data from immediately after the start condition. start condition stop condition output of an acknowledge signal general call 23456789 1 scl (bus) sda (bus) sda0 sbi0sr2 intsbi0 interrupt request acknowledgment 23456789 1 d7 d6 d5 d4 d3 d2 d1 d0 d6 d7 d5 d4 d3 d2 d1 d acknowledgment scl sda sbi0sr2
page 266 18. serial bus interface (sbi) 18.5 data transfer of i2c bus TMP89FH46 ra001 18.5 data transfer of i 2 c bus 18.5.1 device initialization set poffcr1 to "1". after confirming that the serial bus interface pin is high level, set sbi0cr2 to "1" to select the serial bus interface mode. set sbi0cr1 to "1", sbi0cr1 to "0" and sbi0cr1 to "000" to count the number of clocks for an acknowledge signal, to enable the slave address match detection and the general call detection, and set the data length to 8 bits. set t high and t low at sbi0cr1. set a slave address at i2c0ar and se t i2c0ar to "0" to select the i 2 c bus mode. finally, set sbi0cr2, sbi0cr2 and sb i0cr2 to "0", sbi0cr2 to "1" and sbi0cr2 to "00" for specifying the default setting to a slave receiver mode. note:the initialization of a serial bus interface circuit mu st be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition. if not, the data can not be received correctly because the other device starts trans ferring before an end of the initialization of a serial bus interface circuit. 18.5.2 start condition and slave address generation confirm a bus free status (sbi0sr2="0"). set sbi0cr1 to "1" and specify a slave address and a direction bit to be transmitted to the sbi0dbr. by writing "1" to sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2

, the start condi- tion is generated on a bus and then, the slave address a nd the direction bit which are set to the sbi0dbr are output. the time from generating the start condition until the falling sbi0 pin takes t high . an interrupt request occurs at the 9th falling edge of a scl clock cycle, and sbi0cr2 is cleared to "0". the scl0 pin is pulled down to the low level while sbi0cr2 is "0". when an interrupt request occurs, sbi0cr2 changes by the hardware accordin g to the direction bit only when an acknowledge signal is returned from the slave device. note 1: do not write a slave address to the sbi0dbr while data is transferred. if data is written to the sbi0dbr, data to be output may be destroyed. note 2: the bus free state must be confirmed by software within 98.0 s (the shortest transmitting time according to the standard mode i 2 c bus standard) or 23.7 s (the shortest transmitting time according to the fast mode i 2 c bus standard) after setting of the slave address to be output. only when the bus free state is confirmed, set "1" to sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2 to generate the start conditions. if the writing of slave address and setti ng of sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2 doesn't finish within 98.0 s or 23.7 s, the other masters may start the transferring and the slave address data written in sbi0dbr may be broken. example :initialize a device chk_port: cmp (p2prd), 0x0c ; checks whether the serial bus interface pin is at the high level jr nz, chk_port ld (sbi0cr2), 0x18 ; selects the serial bus interface mode ld (sbi0cr1), 0x16 ; selects the acknowledgment mode and sets sbi0cr1 to "110" ld (i2c0ar), 0xa0 ; sets the slave address to 1010000 and selects the i2c bus mode ld (sbi0cr2), 0x18 ; selects the slave receiver mode
page 267 TMP89FH46 ra001 figure 18-17 generati ng the start condition and the slave address 18.5.3 1-word data transfer check sbi0sr2 by the interrupt process after a 1-word data transfer is completed, and determine whether the mode is a master or slave. 18.5.3.1 when sbi0sr2 is "1" (master mode) check sbi0sr2 and determine whethe r the mode is a transmitter or receiver. (1) when sbi0sr2 is "1" (transmitter mode) check sbi0sr2. when sbi0sr2 is "1", a receiver does no t request data. imple- ment the process to generate a stop condition (described later) and te rminate data transfer. when sbi0sr2 is "0", the receiver requests subsequent data. when the data to be transmit- ted subsequently is other than 8 bits, set sbi0cr1 again, set sbi0cr1 to "1", and write the transmitted data to sbi0dbr. after writing the data, sbi0cr2 becomes "1", a serial clock pulse is generated for transfer- ring the subsequent 1-word data from the scl0 pin, and then the 1-word data is transmitted from the sda0 pin. after the data is transmitted, an interrupt request occurs. sbi0cr2 become "0" and the scl0 pin is set to the low level. if the data to be transferred is more than one word in length, repeat the procedure from the sbi0sr2 checking above. example :generate the start condition chk_bb: test (sbi0sr2).bb ; confirms that the bus is free jr f, chk_bb ld (sbi0dbr), 0xcb ; the transmission slav e address 0x65 and the direction bit "1" ld (sbi0cr2), 0xf8 ; write "1" to sbi0cr2, , and to "1" start condition slave address + direction bit 23456789 1 acknowledgem ent signal from a slave interrupt request signal sbi0cr1 scl0 pin sda0 pin sbi0cr2 is cleared to "0" when the direction bit is "1"and an acknowledge signal is returned. sbi0cr2
page 268 18. serial bus interface (sbi) 18.5 data transfer of i2c bus TMP89FH46 ra001 figure 18-18 exampl e when sbi0cr1="000" and sbi0cr1="1" (2) when sbi0sr2 is "0" (receiver mode) when the data to be transmitted subsequently is other than 8 bits, set sbi0cr1 again. set sbi0cr1< ack> to "1" and read the received data from the sbi0dbr (reading data is undefined immediately after a sl ave address is sent). after the data is read, sbi0cr2 becomes "1" by writing the dummy data (0x00) to the sbi0dbr. the serial bus interface ci rcuit outputs a serial clock pulse to the scl0 pin to transfer the subsequent 1-word data and sets the sda0 pin to "0" at the acknowledge signal timing. an interrupt request occurs and sbi0cr2 b ecomes "0". then a serial bus interface circuit outputs a clock pulse for 1-word data transfer and the acknowledge signal by writing data to the sbi0dbr or setting sbi0cr2 to "1" after reading the received data. figure 18-19 example when sbi0c r1="000" and sbi0cr1="1" to make the transmitter terminate transmission, execute foll owing procedure before receiving a last data. 1. read the received data. 2. clear sbi0cr1 to "0" and set sbi0cr1 to "000". 3. to set sbi0cr2 to "1", write a dummy data (0x00) to sbi0dbr. transfer 1-word data in which no clock is generated for an acknowledge signal by setting sbi0cr2 to "1". next, execute following procedure. 1. read the received data. 23456789 1 acknowledge signal from the receiver d7 d6 d5 d4 d3 d2 d1 d0 scl0 pin sda0 pin intsbi0 interrupt request sbi0cr2 write to sbi0dbr acknowledge signal to the transmitter 23456789 9 1 d7 new d7 d5 d6 d4 d3 d2 d1 d0 read sbi0dbr write to sbi0dbr sda0 pin scl0 pin sbi0cr2 intsbi0 interrupt request
page 269 TMP89FH46 ra001 2. clear sbi0cr1 to "0" and set sbi0cr1 to "001". 3. to set sbi0cr2 to "1", write a dummy data (0x00) to sbi0dbr. transfer 1-bit data by setting sbi0cr1 to "1". in this case, since the master de vice is a receiver, the sda line on a bus keeps the high level. the transmitter receives the high-level signal as a negative acknowledge signal. the receiver indicates to the transmitter that data transfer is complete. after 1-bit data is received and an interrupt request has occurred, ge nerate the stop condition to ter- minate data transfer. figure 18-20 termination of data tran sfer in the mast er receiver mode 18.5.3.2 when sbi0sr2 is "0" (slave mode) in the slave mode, a serial bus inte rface circuit operates either in the no rmal slave mode or in the slave mode after losing arbitration. in the slave mode, the conditions of generating the serial bus interf ace interrupt request (intsbi0) are follows: ? at the end of the acknowledge si gnal when the received slave addr ess matches the value set by the i2c0ar with sbi0cr1 set at "0" ? at the end of the acknowledge signal wh en a "general call" is received with sbi0cr1 set at "0" ? at the end of transferring or r eceiving after matching of slave ad dress or receiving of "general call" the serial bus interface circuit change s to the slave mode if arbitration is lost in the master mode. and an interrupt request occurs when the word data transf er terminates after losing arbitration. the generation of the interrupt request and the behavior of sbi0cr2 after losing arbitration are shown in table 18- 4. negative acknowledge signal to the transmitter 2345678 1 9 d7 d5 d6 d4 d3 d2 d1 d0 scl0 pin sda0 pin sbi0cr intsbi0 interrupt request after reading the reveived data, set sbi0cr1 to "001" and write dummy data (0x00) after reading the received data, clear sbi0cr1 to "0" and writing the dummy data (0x00)
page 270 18. serial bus interface (sbi) 18.5 data transfer of i2c bus TMP89FH46 ra001 when an interrupt request occurs, sbi0cr2 is reset to "0", and the scl0 pin is set to the low level. either writing data to the sbi0dbr or settin g sbi0cr2 to "1" releases the scl0 pin after taking t low . check sbi0sr2, sbi0sr2, sbi0sr2 and sbi0sr2 and implement pro- cesses according to conditions listed in table 18-5. note: in the slave mode, if the slave address set in i2c0ar is "0x00", a start byte "0x01" in i 2 c bus standard is received, the device detects slave address match and sbi0cr2 is set to "1". do not set i2c0ar to "0x00". table 18-4 the behavior of an interrupt request and sbi0cr2 after losing arbitration when the arbitration lost occurs during transmis- sion of slave address as a master when the arbitration lost occurs during transmis- sion of data as master transmitter interrupt request an interrupt request is generated at the termination of word-data transfer. sbi0cr2 sbi0cr2 is cleared to "0". table 18-5 operation in the slave mode sbi0sr2 sbi0sr2 sbi0sr2 sbi0sr2 conditions process 1 110 the serial bus interface circuit loses arbitration when transmitting a slave address, and receives a slave address of which the value of the direction bit sent from another master is "1". set the number of bits in 1 word to sbi0cr1 and write the transmitted data to the sbi0dbr. 0 10 in the slave receiver mode, the serial bus interface circui t receives a slave address of which the value of the direc- tion bit sent from the master is "1". 00 in the slave transmitter mode, the serial bus interface circuit finishes the trans- mission of 1-word data check sbi0sr2. if it is set to "1", set sbi0cr2 to "1" since the receiver does not request subsequent data. then, clear sbi0cr2 to "0" to release the bus. if sbi0sr2 is set to "0", set the number of bits in 1 word to sbi0cr1 and write the transmit- ted data to sbi0dbr since the receiver requests subsequent data. 0 1 11/0 the serial bus interface circuit loses arbitration when transmitting a slave address, and receives a slave address of which the value of the direction bit sent from another master is "0" or receives a "general call". write the dummy data (0x00) to the sbi0dbr to set sbi0cr2 to "1", or write "1" to sbi0cr2. 00 the serial bus interface circuit loses arbitration when transmitting a slave address or data, and terminates trans- ferring the word data. the serial bus interface circuit is changed to the slave mode. write the dummy data (0x00) to the sbi0dbr to clear sbi0sr2 to "0" and set sbi0cr2 to "1". 0 11/0 in the slave receiver mode, the serial bus interface circui t receives a slave address of which the value of the direc- tion bit sent from the master is "0" or receives "general call". write the dummy data (0x00) to the sbi0dbr to set sbi0cr2 to "1", or write "1" to sbi0cr2. 01/0 in the slave receiver mode, the serial bus interface circuit terminates the receipt of 1-word data. set the number of bits in 1-word to sbi0cr1, read the received data from the sbi0dbr and write the dummy data (0x00).
page 271 TMP89FH46 ra001 18.5.4 stop cond ition generation when sbi0cr2 is "1", a sequence of generati ng a stop condition is started by setting "1" to sbi0cr2, sbi0cr2 and sbi0cr2 and clearing sbi0cr2 to "0". do not modify the contents of sbi0cr2, sbi0cr2, sbi0cr2 and sbi0cr2 until a stop condi- tion is generated on a bus. when a scl line on a bus is pulled down by other devi ces, a serial bus interface circuit generates a stop con- dition after a scl line is released. the time from the releasing scl line until the generating the stop condition takes t high . figure 18-21 stop condition generation 18.5.5 restart restart is used to change the direction of data tr ansfer between a master device and a slave device during transferring data. the following explains how to restart th e serial bus interface circuit. clear sbi0cr2, sbi0cr2 and sbi0cr2 to "0" and set sbi0cr2 to "1". the sda0 pin retains the high level and the scl0 pin is released. since this is not a stop condition, the bus is a ssumed to be in a busy state from other devices. check sbi0sr2 until it becomes "0" to check that the scl0 pin of the seri al bus interface circuit is released. example :generate the stop condition ld (sbi0cr2), 0xd8 ; sets sbi0cr2, and to "1" and sbi0cr2 to "0" chk_bb: test (sbi0sr2).bb ;waits until the bus is set free jr t, chk_bb stop condition if the scl of the bus is pulled down by other devices, the stop condition is generated after it is released sda0 pin scl0 pin scl (bus) sbi0cr2 sbi0sr2 sbi0cr2="1" sbi0cr2="1" sbi0cr2="0" sbi0cr2="1"
page 272 18. serial bus interface (sbi) 18.5 data transfer of i2c bus TMP89FH46 ra001 check sbi0sr2 until it becomes "1" to check th at the scl line on the bus is not pulled down to the low level by other devices. after confirming that the bus stays in a free state, generate a start cond ition in the procedure "18.5.2 start condition and slave address generation". in order to meet the setup time at a restart, take at least 4.7 s of waiting time by the software in the standard mode i 2 c bus standard or at least 0.6 s of waiting time in the fast mode i 2 c bus standard from the time of restarting to confirm that a bus is free until the time to generate a start condition. note:when the master is in the receiver mode, it is ne cessary to stop the data transmi ssion from the slave device before the stop condition is generated. to stop the transmission, the master dev ice make the slave device receiving a negative acknowledge. therefore, sbi0sr2 is "1" before generating the restart and it can not be confirmed that scl line is not pulled down by ot her devices. please confirm the scl line state by read- ing the port. figure 18-22 timing di agram when restarting example :generate a restart ld (sbi0cr2), 0x18 ; sets sbi0cr2, and to "0" and sbi0cr2 to "1" chk_bb: test (sbi0sr2).bb ; waits until sbi0sr2 becomes "0" jr t, chk_bb chk_lrb: test (sbi0sr2).lrb ; wait s until sbi0sr2 becomes "1" jr f, chk_lrb . . ; wait time process by the software . ld (sbi0cr2), 0xf8 ; sets sbi0cr2, , and to "1" start condition 4.7 s min. in the normal mode or 0.6 s min. in the fast mode sbi0cr2="0" sbi0cr2="0" sbi0cr2="0" sbi0cr2="1" scl0 pin scl (bus) sda0 pin sbi0sr2 sbi0sr2 sbi0cr2 sbi0cr2="1" sbi0cr2="1" sbi0cr2="1" sbi0cr2="1"
page 273 TMP89FH46 ra001 18.6 ac specifications the ac specifications are as listed below. the operating mode (fast or standard) mode should be select ed suitable for frequency of fcgck. for these operating mode, refer to the following table. note: for m and n, refer to"18.4.4.1 clock source". figure 18-23 definition of timing (no. 1) table 18-6 ac specificati ons (circuit output timing) parameter symbol standard mode fast mode unit min. max. min. max. scl clock frequency f scl 0 fcgck / (m+n) 0 fcgck / (m+n) khz hold time (re)start condition. this period is followed by generation of the first clock pulse. t hd;sta m / fcgck - m / fcgck - s low-level period of scl clock (output) t low n / fcgck - n / fcgck - s high-level period of scl clock (output) t high m / fcgck - m / fcgck - s low-level period of scl clock (input) t low 5 / fcgck - 5 / fcgck - s high-level period of scl clock (input) t high 3 / fcgck - 3 / fcgck - s restart condition setup time t su;sta depends on the software - depends on the software - s data hold time t hd;dat 0 5 / fcgck 0 5 / fcgck s data setup time t su;dat 250 - 100 - ns rising time of sda and scl signals t r - 1000 - 300 ns falling time of sda and scl signals t f - 300 - 300 ns stop condition setup time t su;sto m / fcgck - m / fcgck - s bus free time between the stop condi- tion and the start condition t buf depends on the software - depends on the software - s time before rising of scl after sbicr2 is changed from "0" to "1" t su;scl n / fcgck - n / fcgck - s t low t f t f t su;sta t su;sto t buf t hd;sta t r t su;dat t hd;sta t high t hd;dat t f
page 274 18. serial bus interface (sbi) 18.6 ac specifications TMP89FH46 ra001 figure 18-24 definition of timing (no. 2) scl sbicr2 su;scl t
page 275 TMP89FH46 ra000 19. key-on wakeup (kwu) the key-on wakeup is a function for releasing the stop mode at the stop pin or at pins kwi7 through kwi0. 19.1 configuration figure 19-1 key-on wakeup circuit stop mode release signal (to be released if set to 1) syscr1 selector port port port port port rising edge detection 0 1 s y 76543210 kwucr0 (0x0fc4) port port port port 76543210 kwucr1 (0x0fc5) kwi0 kwi1 kwi2 kwi3 kwi4 kwi5 kwi6 kwi7 stop
page 276 19. key-on wakeup (kwu) 19.1 configuration TMP89FH46 ra000 19.2 control key-on wakeup control registers (kwucr0 and kwucr1) can be configured to designate the key-on wakeup pins (kwi7 through kwi0) as stop mode release pins and to specify the stop mode release levels of each of these designated pins. key-on wakeup control register 0 kwucr0 76543210 (0x0fc4) bit symbol kw3le kw3en kw2le kw2en kw1le kw1en kw0le kw0en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 kw3le stop mode release level of kwi3 pin 0: 1: low level high level kw3en input enable/disable control of kwi3 pin 0: 1: disable enable kw2le stop mode release level of kwi2 pin 0: 1: low level high level kw2en input enable/disable control of kwi2 pin 0: 1: disable enable kw1le stop mode release level of kwi1 0: 1: low level high level kw1en input enable/disable control of kwi1 pin 0: 1: disable enable kw0le stop mode release level of kwi0 pin 0: 1: low level high level kw0en input enable/disable control of kwi0 pin 0: 1: disable enable key-on wakeup control register 1 kwucr1 76543210 (0x0fc5) bit symbol kw7le kw7en kw6le kw6en kw5le kw5en kw4le kw4en read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset00000000 kw7le stop mode release level of kwi7 pin 0: 1: low level high level kw7en input enable/disable control of kwi7 pin 0: 1: disable enable kw6le stop mode release level of kwi6 pin 0: 1: low level high level kw6en input enable/disable control of kwi6 pin 0: 1: disable enable kw5le stop mode release level of kwi5 pin 0: 1: low level high level kw5en input enable/disable control of kwi5 pin 0: 1: disable enable kw4le stop mode release level of kwi4 pin 0: 1: low level high level kw4en input enable/disable control of kwi4 pin 0: 1: disable enable
page 277 TMP89FH46 ra000 19.3 functions by using the key-on wakeup function, the stop mode can be released at a stop pin or at kwim pin (m: 0 through 7). after resetting, the stop pin is the only stop mode release pin. to designate the kwim pin as a stop mode release pin, therefore, it is nece ssary to configure the key-on wakeup control register (kwucrn) (n: 0 or 1). because the stop pin lacks a function for disabli ng inputs, it can be designated as a pin for receiving a stop mode release signal, irrespective of whether the key-on wakeup function is used or not. ? setting kwucrn and p4pu registers to designate a key-on wakeup pin (kwim) as a stop mode release pin, set kwucrn to "1". after kwim pin is set to "1" at kwucrn, a specific stop mode release level can be specified for this pin at kwu crn. if kwucrn is set to "0", stop mode is released when an input is at a low level. if it is set to "1", stop mode is released when an input is at a high level. for example, if you want to release stop mode by inputting a high-level signal into a kwi0 pin, set kwucr0 to "1", " and kwucr0 to "1". each kwim pin can be connected to internal pull-up resistors. before connecting to internal pull-up resistors, the corresponding bits in the pull-up cont rol register (p4pu) at port p4 must be set to "1". ? starting stop mode to start the stop mode, set syscr1 to "1 " (level release mode), and syscr1 to "1". to use the key-on wakeup function, do not set sy scr1 to "0" (edge release mode). if the key-on wakeup function is used in edge release mo de, stop mode cannot be released, although a rising edge is input into the stop pin. this is because the kwim pin en abling inputs to be received is at a release level after the stop mode starts. ? releasing stop mode to release stop mode, input a high-level signal into the stop pin or input a specific release level into the kwim pin for which receipt of inputs is enabled. if you want to release stop mode at the kwim pin, rather than the stop pin, continue inputting a low-level signal into the stop pin throughout the period from when the stop mode is st arted to when it is released. if the stop pin or kwim pin is already at a release le vel when the stop mode starts, the following instruction will be executed without starting the stop mode (with no warm-up performed). note 1: if an analog voltage is applied to kwim pin for which receipt of inputs is enabled by the key-on wakeup control register (kwucrn) setting, a penetration current will fl ow. therefore, in this case, the analog voltage should be not applied to this pin. table 19-1 stop mode release level (edge) pin name release level (edge) syscr1="1" (level release mode) syscr1="0" (edge release mode) kwucrn="0" kwucrn="1" stop "h" level rising edge kwim "l" level "h" level don't use
page 278 19. key-on wakeup (kwu) 19.1 configuration TMP89FH46 ra000 example :a case in which stop mode is started with the release level of the stop pin set to a high level and the release level of kwi0 set to a low level (connected to an internal pull-up resistor of the kwi0 pin) di ; imf 0 set (p4pu).0 ; kwi0 (p40) connected to a pull-up resistor ld (kwucr0), 00000001b ; the kwi0 pin is set to enable inputs, and its release level is set to a low level. ld (syscr1), 10100000b ; starting in level release mode
page 279 TMP89FH46 ra001 20. 10-bit ad converter (adc) the TMP89FH46 has a 10-bit successive approximation type ad converter. 20.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 20-1. it consists of control registers adccr1 and adccr2 , converted value register s adcdrl and adcdrh, a da converter, a sample-hold circuit, a comparat or, a successive comparison circuit, etc. figure 20-1 10-bit ad converter note 1: before using the ad converter, set an appropriate va lue to the i/o port register which is also used as an analog input port. for details, see the section on "i/o ports". note 2: the da converter current (iref) is automatica lly cut off at times other than during ad conversion. 2 4 10 10 8 2 ainen s r d a r/2 r/2 r ack amd ad converted value registers 1 and 2 ad converter control registers 1 and 2 f b d a f c o e intadc sain n successive approximation circuit adccr2 adcdrl adcdrh adccr1 sample-hold circuit a s en shift clock da converter input selector y reference voltage analog comparator 3 control circuit vss varef avdd ain0 ain7
page 280 20. 10-bit ad converter (adc) 20.2 control TMP89FH46 ra001 20.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects an analog channel in which to perform ad conversion, selects an ad conversion operation mode, and controls the start of the ad converter. 2. ad converter control register 2 (adccr2) this register selects the ad conve rsion time, and monitors the operating status of the ad converter. 3. ad converted value registers (adcdrh and adcdrl) these registers store the digital values generated by the ad converter.
page 281 TMP89FH46 ra001 note 1: do not perform the following operations on the a dccr1 register while ad c onversion is being executed (adccr2="1"). - changing sain - setting ainen to "0" - changing amd (except a forced stop by setting amd to "00") - setting adrs to "1" note 2: if you want to disable all analog input channels, set ainen to "0". note 3: although analog input pins are also used as input/output ports, it is recommended for the purpose of maintaining the acc u- racy of ad conversion that you do not execute input/output in structions during ad conversion. additionally, do not input widely varying signals into the por ts adjacent to analog input pins. note 4: when stop, idle0 or slow mode is started, adrs, amd a nd ainen are initialized to "0". if you use the ad converter after returning to normal mode, you must reconfigure adrs, amd and ainen. note 5: after the start of ad conversion, adrs is automatically cleared to "0" ("0" is read). ad converter control register 1 adccr1 76543210 (0x0034) bit symbol adrs amd ainen sain read/write r/w r/w r/w r/w after reset00000000 adrs ad conversion start 0: 1: - ad conversion start amd ad operating mode 00: 01: 10: 11: ad operation disable, forcibly stop ad operation single mode reserved repeat mode ainen analog input control 0: 1: analog input disable analog input enable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 reserved reserved reserved reserved reserved reserved reserved reserved
page 282 20. 10-bit ad converter (adc) 20.2 control TMP89FH46 ra001 note 1: make sure that you make the ack setting when ad conversion is in a halt condition (adccr2="0"). note 2: make sure that you write "0" to bit 3 of adccr2. note 3: if stop, idle0 or slow mode is started, eocf and adbf are initialized to "0". note 4: if the ad converted value register (adcdrh) is read, eocf is cleared to "0". it is also cleared to "0" if ad conversion is started (adccr1="1") without reading adcdrh after completing ad conversion in single mode. note 5: if an instruction to read adccr2 is executed, 0 is read from bits 3 through 5. ad converter control register 2 adccr2 76543210 (0x0035) bit symbol eocf adbf - - "0" ack read/writerrrrw r/w after reset00000000 eocf ad conversion end flag 0: 1: before conversion or during conversion conversion end adbf ad conversion busy flag 0: 1: ad conversion being halted ad conversion being executed ack ad conversion time select (exam- ples of ad conversion time are shown in the table below) 000: 001: 010: 011: 100: 101: 110: 111: 39/fcgck 78/fcgck 156/fcgck 312/fcgck 624/fcgck 1248/fcgck reserved reserved table 20-1 ack settings and conver sion times relative to frequencies frequency (fcgck) ack setting conversion time 10mhz 8mhz 4mhz 2mhz 5mhz 2.5mhz 1mhz 0.5mhz 0.25 mhz 000 39/fcgck - - - 19.5 s - 15.6 s39.0 s 78.0 s 156.0 s 001 78/fcgck - - 19.5 s 39.0 s 15.6 s 31.2 s78.0 s 156.0 s- 010 156/fcgck 15.6 s19.5 s39.0 s 78.0 s 31.2 s 62.4 s 156.0 s- - 011 312/fcgck 31.2 s39.0 s78.0 s 156.0 s 62.4 s 124.8 s- - - 100 624/fcgck 62.4 s78.0 s 156.0 s - 124.8 s- - - - 101 1248/fcgck 124.8 s 156.0 s------- 11* reserved note 1: spaces indicated by "-" in the above table mean that it is prohibited to establish c onversion times in these spaces. fcgck: high frequency os cillation clock [hz] note 2: above conversion times do not include the time shown below. - time from when adccr1 is set to 1 to when ad conversion is started - time from when ad conversion is finished to wh en a converted value is stored in adcdrl and adcdrh. if ack = 00*, the longest conversion time is 10/fcgck (s). if ack = 01*, it is 32/fcgc k (s). if ack = 10*, it is 128/fcgck(s). note 3: the conversion time must be longer than the following time by analog reference voltage (varef). - varef = 4.5 to 5.5 v 15.6 s or longer - varef = 2.7 to 5.5 v 31.2 s or longer - varef = 2.2 to 5.5 v 124.8 s or longer
page 283 TMP89FH46 ra001 note 1: a read of adcdrl or adcdrh must be read after the intadc interrupt is generated or after adccr2 becomes "1". note 2: in single mode, do not read adcdrl or adcdrh during ad conversion (adccr2="1"). (if ad conversion is fin- ished in the interim between a read of adcdrl and a read of adcdrh, the intadc interrupt request is canceled, and the conversion result is lost.) note 3: if stop, idle0 or slow mode is started, adcdrl and adcdrh are initialized to "0". note 4: if adccr1 is set to "00", adcdrl and adcdrh are initialized to "0". note 5: if an instruction to read adcdrh is executed, "0" is read from bits 7 through 2. note 6: if ad conversion is finished in repeat mode in the in terim between a read of adcdrl and a read of adcdrh, the previ- ous converted value is retained without overwriting the ad c onverted value register. in this case, the intadc interrupt request is canceled, and the conversion result is lost. ad converted value register (lower side) adcdrl 76543210 (0x0036) bit symbol ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 read/writerrrrrrrr after reset00000000 ad converted value register (upper side) adcdrh 76543210 (0x0037)bit symbol------ad09ad08 read/writerrrrrrrr after reset00000000
page 284 20. 10-bit ad converter (adc) 20.3 functions TMP89FH46 ra001 20.3 functions the 10-bit ad converter operates in either single mode in which ad conversion is performed only once or repeat mode in which ad conversion is performed repeatedly. 20.3.1 single mode in single mode, the voltage at a designated analog input pin is ad converted only once. setting adccr1 to "1" after setting adccr1 to "01" allows ad conversion to start. adccr1 is automatically clea red after the start of ad conver sion. as ad conversion starts, adccr2 is set to "1". it is cleared to "0" if ad conversion is finished or if ad conversion is forced to stop. after ad conversion is finished, the conversion resu lt is stored in the ad converted value registers (adcdrl and adcdrh), adccr2 is set to "1 ", and the ad conversion finished interrupt (intadc) is generated. the ad converted value re gisters (adcdrl and adcdrh) should be usually read according to the intadc interrupt processing routine. if the upper side (adcdrh) of the ad converted value register is read, adccr2 is cleared to "0". note:do not perform the following operations on the ad ccr1 register when ad conversion is being executed (adccr2="1"). if the following operations are perfo rmed, there is the possibi lity that ad conversion may not be executed properly. ? changing the adccr1 setting ? setting adccr1 to "0" ? changing the adccr1 setting (except a forced stop by setting amd to "00") ? setting adccr1 to "1" figure 20-2 single mode 20.3.2 repeat mode in repeat mode, the voltage at an analog input pin designated at adccr1 is ad converted repeat- edly. setting adccr1 to "1" afte r setting adccr1 to "11" al lows ad conversion to start. after the start of ad conversion, adccr1 is automatically cleared. after the first ad conversion is finished, the conversion result is stored in the ad converted va lue registers (adcdrl and adcdrh), adccr2 is set to "1", and the ad conversion finished interrupt (intadc) is generated. after this interrupt is generated, the second (nex t) ad conversion starts immediately. status of adcdrl and adcdrh clearing eocf based on the conversion result read of conversion result read of conversion result read of conversion result read of conversion result adccr2 intadc interrupt request adccr2 adccr1 result of the first conversion result of the second conversion indeterminate ad conversion start ad conversion start read of adcdrh read of adcdrl
page 285 TMP89FH46 ra001 the ad converted value registers (adcdrl and addrh) should be read before the next ad conversion is finished. if the next ad conversion is finished in the interim between a read of adcdrl and a read of adcdrh, the previous converted value is retained without overwriting the ad converted value registers (adcdrl and adcdrh). in this case, the intadc inte rrupt request is not generated, and the conversion result is lost. (see figure 20-3.) to stop ad conversion, write "00" (ad operation disable) to adccr1 . as "00" is written to adccr1, ad conversion stops imme diately. in this case, the convert ed value is not stored in the ad converted value register. as ad conversion starts, adccr2< adbf> is set to "1". it is cleared to "0" if "00" is written to amd. figure 20-3 repeat mode 20.3.3 ad operation disable and forced stop of ad operation if you want to force the ad converter to stop when ad conversion is ongoing in single mode or if you want to stop the ad converter when ad conversion is ongoing in repeat mode, set adccr1 to "00". if adccr1 is set to "00", register s adccr2, adccr2, adcdrl, and adcdrh are initialized to "0". status of adcdrl and adcdrh a read of the conversion result will clear eocf. the intadc interrupt request is not generated in the interim between a read of adcdrl and a read of adcdrh. read of conversion result read of conversion result a dccr2 intadc interrupt conversion operation a dccr1 ad conversion start adccr1 11 00 ad conversion is suspended. the conversion result is not stored. read of adcdrh read of adcdrl read of conversion result read of conversion result read of conversion result read of conversion result indeterminate result of the 1st conversion result of the 2nd conversion result of the 3rd conversion result of the 4th conversion result of the 4th conversion result of the 3rd conversion
page 286 20. 10-bit ad converter (adc) 20.4 register setting TMP89FH46 ra001 20.4 register setting 1. set the ad converter control regist er 1 (adccr1) as described below: ? from the ad input channel select (sain), select the channel in which ad conversion is to be per- formed. ? set the analog input control (ainen) to "analog input enable". ? at amd, specify the ad operating mode (single or repeat mode). 2. set the ad converter control regist er 2 (adccr2) as described below: ? at the ad conversion time (ack), specify the ad conversion time. fo r information on how to specify the conversion time, refer to the ad c onverter control register 2 and table 20-1. 3. after the above two steps are completed, set "1" on the ad conversion start (adr s) of the ad converter control register 1 (adccr1), and ad conversion starts immediately if single mode is selected. 4. as ad conversion is finished, the ad conversion end flag (eocf) of the ad converter control register 2 (adccr2) is set to "1", the ad co nversion result is stored in the ad converted value registers (adcdrh and adcdrl), and the intadc interrupt request is generated. 5. after the conversion result is read from the ad c onverted value register (adcdrh), eocf is cleared to "0". eocf will also be cleared to "0" if ad convers ion is performed once again before reading the ad con- verted value register (adcdrh). in this case, the previous conversion result is retained until ad conver- sion is finished. 20.5 starting stop/idle0/slow modes if stop/idle0/slow mode is st arted, registers adccr1, adccr2, adcdrl and adcdrh are initialized to "0". if any of these modes is started during ad conversion, ad conver- sion is suspended, and the ad converter stops (registers are likewise initialized). when restored from stop/ idle0/ slow mode, ad conversion is not automatically restarted. therefore, registers must be reconfigured as necessary. if stop/idle0/slow mode is started during ad conversi on, analog reference voltage is automatically discon- nected and, therefore, th ere is no possibility of current flowing into the analog reference voltage. example: after selecting the conversion time 15.6 s at 10 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, store the conversion result in the hl register. the operation mode is single mode. : (port setting) ; before setting ad converter registers, make an appropriate port regis- ter setting.(for further details, refer to the section that describes i/o ports.) ld (adccr1), 0y00110011 ; select ain3. ld (adccr2), 0y00000011 ; select conversion time (156/fcgck) and operation mode. set (adccr1). 7 ; adrs = 1 (ad conversion start) sloop : test (adccr2). 7 ; eocf = 1 ? jrs t, sloop ld hl, (adcdrl) ; read result data
page 287 TMP89FH46 ra001 20.6 analog input voltage and ad conversion result analog input voltages correspond to ad-converted , 10-bit digital values, as shown in figure 20-4. figure 20-4 relationships between analog input voltages and ad-converted values (typical values) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad-converted value varef ? vss
page 288 20. 10-bit ad converter (adc) 20.7 precautions about the ad converter TMP89FH46 ra001 20.7 precautions about the ad converter 20.7.1 analog input pin voltage range analog input pins (ain0 through ain7) should be used at voltages from varef to vss. if any voltage out- side this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain, and converted values on other pins will also be affected. 20.7.2 analog input pins used as input/output ports analog input pins (ain0 to ain7) are also used as input/output ports. in using one of analog input pins (ports) to execute ad conversion, input/output instructions at all other pins (ports) must not be executed. if they are executed, there is the possibil ity that the accuracy of ad conversi on may deteriorate. this also applies to pins other than analog input pins; if one pin recei ves inputs or generates outputs, noise may occur and its adjacent pins may be affected by that noise. 20.7.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 20-5. the higher the output imped- ance of the analog input source, the more susceptible it becomes to noise. therefor e, make sure the output impedance of the signal source in your design is 5 k ? or less. it is recommended that a capacitor be attached externally. figure 20-5 analog input equivalent ci rcuit and example of input pin processing da converter analog comparator r nal resistance: r nal capacitance: #!undefined!# k ? (typ) da converter aini analog comparator internal resistance: permissible signal source impedance: internal capacitance: 5 k ? (typ) 5 k ? (max) note) i = 7 to 0 c = 22 pf (typ.)
page 289 TMP89FH46 ra003 21. flash memory the TMP89FH46 has flash memory of 16384 bytes. a writ e and erase to be performed on flash memory can be controlled in the following three modes: - mcu mode in mcu mode, the flash memory is accessed by the cp u control, and the flash memory can be executed the erasing and writing without affect ing the operations of a running appl ication. therefore, this mode is used for software debugging and firmware change after shipment of the TMP89FH46. - serial prom mode in serial prom mode, the flash memory is accesse d by the cpu control. use of the serial interface (uart and sio) enables the flash memory to be controlled by the small number of pins. the TMP89FH46 used in serial prom mode supports on -board programming, which enables users to pro- gram flash memory after the microcon troller is mounted on a user board. - parallel prom mode the parallel prom mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provid ed by a third party. high-speed access to th e flash memory is available by control- ling address and data signals dir ectly. to receive a support service for the program writer, please ask a toshiba sales representative. in mcu and serial prom modes, flash memory control registers (flscr1 and flscr2 ) are used to control the flash memory. this chapter describes how to access the flash memory using the mcu and serial prom modes.
page 290 21. flash memory TMP89FH46 ra003 21.1 flash memory control the flash memory is controlled by the fl ash memory control register 1 (flscr1 ), flash memory control register 2 (flscr2), and flash memory standby control register (flsstb). note 1: if "0xd5" is set on flscr2 with flscr1 set to "101", the flash memory goes into an active state, and mcu consumes the same amount of current as it does during a read. flash memory control register 1 flscr1 76543210 (0x0fd0) bit symbol flsmd barea farea - - read/write r/w r/w r/w r/w r/w after reset01000000 flsmd flash memory command sequence and toggle control 010: 101: others: disable command sequence and toggle execution enable command sequence and toggle execution reserved barea bootrom mapping control mcu mode serial prom mode 0: 1: hide bootrom show bootrom - show bootrom farea flash memory area select control 00: assign the data area 0xc000 through 0xffff to the data area 0xc000 through 0xffff (standard mapping). 01: reserved 10: assign the code area 0xc000 through 0xffff to the data area 0xc000 through 0xffff. 11: reserved note 1: it is prohibited to make a setting in "reserved". note 2: the flash memory control register 1 has a double-buffer st ructure comprised of the register flscr1 and a shift register. writing "0xd5" to the register flscr2 allows a register setti ng to be reflected and take effect in the shift register. this means that a register setting value does not take effect until "0 xd5" is written to the register flscr2. the value of the shift register can be checked by reading the register flscrm. note 3: flsmd must be set to either "0y010" or "0y101". flash memory control register 2 flscr2 76543210 (0x0fd1) bit symbol cr1en read/write w after reset******** cr1en flscr1 register enable/disable control 0xd5 others enable a change in the flscr1 setting reserved
page 291 TMP89FH46 ra003 note 1: flscrm is the register that checks the value of the shift register of the flash memory control register 1. note 2: flsmdm turns into "1" only if flsmd="101" becomes effective. note 3: if an instruction to read flscrm is executed, "0" is read from bits 7 and 6. note 4: in serial prom mode, "1" is always read from baream. flash memory control register 1 monitor flscrm 76543210 (0x0fd1) bit symbol flsmdm baream faream romselm read/writerrrr r r after reset00000000 flsmdm monitoring of flscr1 status 0 1 flscr1="101" setting disabled flscr1="101" setting enabled baream monitoring of flscr1 status value of currently enabled flscr1 faream monitoring of flscr1 status value of currently enabled flscr1 romselm monitoring of flscr1 status value of currently enabled flscr1
page 292 21. flash memory TMP89FH46 ra003 note 1: a value can be written to fstb only by using a program that resides in ram. a value written using a program residing in the flash memory will be invalidated. note 2: if fstb is set to "1", do not execute instructions to fe tch or read data from or write data to the flash memory. if they are executed, a flash standby reset will occur. note 3: if an instruction to read flsstb is ex ecuted, "0" is read from bits 7 through 0. note 1: a read or write can be performed on the spcr register only in serial prom mode. if a write is performed on this register in mcu mode, the port input control does not function. if a read is performed on the spcr register in mcu mode, "0" is read from bits 7 through 0. note 2: all i/o ports are controlled by pi n0, except the ports rxd0, txd0 and sclk0 which are used in serial prom mode. by using pin1, the sclk0 pin can be configured separately from other pins. flash memory standby control register flsstb 76543210 (0x0fd2) bit symbol fstb read/writerrrrrrrw after reset00000000 fstb flash memory standby control 0 1 disable flash memory standby enable flash memory standby port input control register (this regist er works only in serial prom mode) spcr 76543210 (0x0fd3) bit symbol pin1 pin0 read/writerrrrrrr/wr/w after reset01000000 pin1 port input control (sclk0 pin) in serial prom mode in serial prom mode in mcu mode 0 1 port input disabled port input enabled input enabled for all ports nonfunctional whatever settings are made "0" is read pin0 port input control (except rxd0, txd0 and sclk0) in serial prom mode 0 1 port input disabled port input enabled
page 293 TMP89FH46 ra003 21.2 functions 21.2.1 flash memory command sequence execution and toggl e control (flscr1 ) to prevent inadvertent writes to th e flash memory due to program error or microcontroller malfunction, the execution of the flash memory command sequence and the toggle operation can be disabled (the flash memory can be write protected) by making an appropriate control register setting (write protect). to enable the execu- tion of the command sequence and th e toggle operation, set flscr1 to "0y101", and then set "0xd5" on flscr2. to disable the execu tion of the command sequence, set flscr1 to "0y010", and then set "0xd5" on flscr2. if the command sequence or the toggle operation is exe- cuted with the execution of the command sequence and the toggle operation set to "disable", the executed com- mand sequence or toggle operation takes no effect. after a reset, flscr1 is initialized to "0y010" to disable the execution of the command sequence. flscr1 should normally be set to " 0y010" except when a write or erase is to be per- formed on the flash memory. note 1: if "0xd5" is set on flscr2 with flscr1 set to "101", the flash memory goes into an active state, and mcu consumes the same amount of current as it does during a read. note 2: if flscr1 is set to "disable", subsequent commands (write instructions) generated are rejected but a command sequence being exec uted is not initialized. if you want to set flscr1 to "disable", yo u must finish all command sequences and verify that the flash memory is ready to be read.
page 294 21. flash memory TMP89FH46 ra003 21.2.2 flash memory area switching (flscr1) to perform an erase or write on the flash memory, a memory transfer instruction (command sequence) must be executed. if a memory transfer instruction is used to read or write data, a read or write can be performed only on the data area. to perform an erase or write on th e code area, therefore, part of the code area must be temporarily switched to the data area. this switching be tween data and code areas is performed by making the appropriate flscr1 setting. by setting "0xd5" on flscr2 after sett ing flscr1 to "10", 0xc000 through 0xffff (area c1) in the code area is mapped to 0xc000 through 0xffff (area d1) in the data area. to restore the flash memory to the initial state of mapping, set flscr1 to "00", and then set "0xd5" on flscr2. all flash memory areas can be acce ssed by performing the appropriate steps described above and then exe- cuting the memory transfer instruction on 0xc000 through 0xffff (area d1) in the data area. additionally, access to areas to which memory is not assigned should be avoided by executing an instruction or specifying such an area by us ing jump or call instructions. figure 21-1 area switching usi ng the flscr1 setting 0xc000 through 0xffff (area d1) in the data area and 0xc000 through 0xffff (area c1) in the code area are mirror areas; these two areas refer to the same physical address in memory. therefore, an erase or write must be performed on one of these tw o mirror areas. for exampl e, if a write is performed on 0xc000 in the data area with flscr1 set to "10" after perf orming a write on 0xc000 in the data area with flscr1 set to "00", data is overwritten. to write data to the flash memory that already has data writ- ten to it, existing data must first be erased from the flash memory by performi ng a sector erase or chip erase, and then data must be written. 0xffff 0xffff data area if flscr = 00 code area 0x0000 0x0000 sfr ram 0x0fff flash flash 0x0000 sfr ram 0x0fff area c1 area d1 if flscr = 10 flash flash 0xffff 0x0000 0xffff data area code area area c1 area c1 bytes bytes bytes bytes 0xbfff 0xc000 0xbfff 0xc000 0xbfff 0xc000 0xbfff 0xc000
page 295 TMP89FH46 ra003 21.2.3 ram area swit ching (syscr3) if "0xd4" is set on syscr4 after syscr3 is set to "1" in mcu mode, ram is mapped to the code area. to restore the ram area to the initial stat e of mapping, set syscr3 to "0", and then set "0xd4" on syscr4. in serial prom mode, ram is mapped to the code area, irrespective of the syscr3 setting. 21.2.4 bootrom area sw itching (flscr1) if "0xd5" is set on flscr2 after flscr1 is set to "1" in mcu mode, 0x1000 through 0x17ff in the code and data areas is masked by flash memory, and 2k-byte (first half of 4kb) bootrom is mapped. if you do not want to map bootrom, set "0xd5" on flscr2 after setting flscr1 to "0". a set of codes for programming flash memory in se rial prom mode are built into bootrom, and a sup- port program (api) for performing an er ase or write on flash memory in a simple manner is also built into one part in the bootrom area. theref ore, by calling a subroutine in the support program after bootrom is mapped, it is possible to erase, write and read flash memory easily. in serial prom mode, bootrom is mapped to 0x1000 through 0x17ff in the data area and 0x1000 through 0x1fff in the code area, irrespective of the flscr1 se tting. barea is always "1", and the set barea value remains unchanged, even if data is written. "1" is always read from barea.
page 296 21. flash memory TMP89FH46 ra003 figure 21-2 show /hide switching for bootrom and ram 21.2.5 flash memory standby control (flsstb) to access the flash memory again after setting flsstb< fstb> to "1", set flsstb to "0" by using a program allocated to ram. if the flash memory is accessed with flsstb se t to "1," a flash standby reset will occur. flsstb is the register provided to maintain the compatibility with the previous product version. it must normally be set to "0". in using flsstb built into the TMP89FH46, the following point should be noted: flsstb can be configured only by usi ng a program allocated to ram. if it is configured by using a program allocated to the flash memory, the configured value will be invalidated and does not take effect. data area if syssr4=0 flscr1=0 if syssr4=1 flscr1=0 code area 0x0000 0x003f 0x0040 0xxxxx 0x1000 0xffff 0x0000 0xffff sfr data area if syssr4=0 flscr1=1 if syssr4=1 flscr1=1 code area ram in serial prom mode note : xxxxh is end of ram address. bootrom 0x0000 0x003f 0x0040 0xxxxx 0x1000 0x17ff 0x1800 0xffff sfr ram bootrom 0x0000 0x1000 0x17ff 0x1800 0xffff data area code area data area code area bootrom 0x0000 0x003f 0x0040 0xxxxx 0x1000 0x17ff 0x1800 0xffff sfr ram ram bootrom 0x0000 0x003f 0x0040 0xxxxx 0x1000 0x17ff 0x1800 0xffff data area code area bootrom 0x0000 0x003f 0x0040 0xxxxx 0x1000 0x17ff 0x1800 0xffff sfr ram ram bootrom 0x0000 0x003f 0x0040 0xxxxx 0x1000 0x17ff 0x1800 0xffff 0x0000 0x003f 0x0040 0xxxxx 0x1000 0xffff sfr ram ram 0x0000 0x003f 0x0040 0xxxxx 0xxxxx+1 0xffff
page 297 TMP89FH46 ra003 if an interrupt occurs when the interrupt vector is assigned to the flash memory area (syscr3 = "0" is effective), fstb is automatically initialized to "0", and then the interrupt vector of the flash memory area is read. if an interrupt occurs when the interr upt vector is assigned to the ram area (syscr3 = "1" is effective), fstb is not cleared to "0", and then the interrupt vect or of the ram area is read. in this case, the ram area should be designated as a referential address of interrupt vector. if the flash memory area is designated as a referential address of interrupt vector, a flash standby reset occurs after an interrupt is gener- ated. 21.2.6 port input control re gister (spcr) in serial prom mode, the input levels of all ports, except the ports rxd0 and txd0 used in serial prom mode, are physically fixed after a reset is released. this is designed to prevent a penetration current from flow- ing through unused ports (port inputs and functional peripheral inputs, wh ich are also used as ports, are dis- abled). to access the flash memory using the ram loader mode and a method other than the uart, therefore, port inputs must be set to "enable". to enable the sc lk0 port input, set spcr to "1". to enable port inputs other than rxd0, txd0 and sclk0 port inputs, set spcr to "1". in mcu mode, the spcr register does not function.
page 298 21. flash memory TMP89FH46 ra003 21.3 command sequence in mcu and serial prom modes, the command sequence consists of six commands (jedec compatible), as shown in table 21-1. note 1: specify the address and data to be written (refer to table 21-2 about ba). note 2: the area to be erased is specified with the upper 4 bits of the address (refer to table 21-3 about sa). note 3: do not start the stop, idle0, idle1, idle2, sleep1 or sleep0 mode while a command sequence is being executed or a task specified in a command sequence is bei ng executed (write, erase or id entry). note 4: # ; 0xc through 0xf should be specifi ed as the upper 4bits of the address. usually , it is recommended that 0xf is speci- fied. note 5: xxx ; don?t care 21.3.1 byte program this command writes the flash memory in units of one byte. the address and data to be written are specified in the 4th bus write cycle. the range of addresses that can be specified is shown in table 21-2. for example, to write data to 0xc000 in the data area, set flscr1 to "0y00", set "0xd5" on flscr2, and then specify 0xc000 as an addre ss in the 4th bus write cycle. the t ime needed to write each byte is 40 s maximum. the next command sequence cannot be executed if an ongoing write operation is not completed. to check the completion of the write operation, perform read operations twice on the same address in the flash memory, and perform polling until the same data is read from the flash memory. during the write operation, bit 6 is reversed each time a read is performed. note 1: to rewrite data to addresses in the flash memory where data (including 0xff) is already written, make sure that you erase the existing data by performing a se ctor erase or chip erase before writing data. note 2: the data and code areas become mirror areas. as you access these areas, you are brought to the same physical address in memory. when performing a byte progr am, make sure that you write data to either of these two areas, not both. note 3: do not perform a byte program on areas other than those shown in table 21-2. table 21-1 command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle adddataadddataadddataadddataadddataadddata 1 byte program 0x#555 0xaa 0x#aaa 0x55 0x#555 0xa0 ba (note 1) data (note 1) ---- 2 sector erase (partial erase in units of 4kb) 0x#555 0xaa 0x#aaa 0x55 0x#55 5 0x80 0x#555 0xaa 0x#aaa 0x55 sa (note 2) 0x30 3 chip erase (all erase) 0x#555 0xaa 0x#aaa 0x55 0x#555 0x80 0 x#555 0xaa 0x#aaa 0x55 0x#555 0x10 4 product id entry 0x#555 0xaa 0x#aaa 0x55 0x#555 0x90 - - - - - - 5product id exit0xxx0xf0---------- 6 security program 0x#555 0xaa 0x#a aa 0x55 0x#555 0xa5 0xff7f 0x00 - - - - table 21-2 range of addresses specifiable (ba) write area flscr1 address specified by instruction (address of 4th bus write cycle) area d1 (data area) 0xc000 through 0xffff 00 0xc000 through 0xffff area c1 (code area) 0xc000 through 0xffff 10 0xc000 through 0xffff
page 299 TMP89FH46 ra003 21.3.2 sector erase (4-kbyte partial erase) data in the erased area is 0xff. note 1: the data and code areas become mirror areas. as you access these areas, you are brought to the same physical address in memory. when performing a sector eras e, make sure that you erase data from either of these two areas, not both. note 2: do not perform a sector erase on areas other than those shown in table 21-3. 21.3.3 chip erase (all erase) this command erases the entire flash memory. the time needed to erase it is 30 ms maximum. the next command sequence cannot be executed if an ongo- ing erase operation is not completed. to check the completion of the eras e operation, perfor m read operations twice on the same address in the flash memory, and perfor m polling until the same data is read from the flash memory. during the erase operation, bit 6 is reversed each time a read is performed. data in the erased area is 0xff. 21.3.4 product id entry this command activates the product id mode. if an instruction to read th e flash memory is executed in prod- uct id mode, the vendor id, flash id and security status can be read from the flash memory. this command erases the flash memory in units of 4 kbytes. the flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address. th e range of addresses that can be specified is shown in table 21-3. for exampl e, to erase 4 kbytes from 0xc000 through 0xcfff in the code area, set flscr1 to "0y10", set "0xd5" on flscr2, and then specify either 0xc000 or 0xcfff as the 6th bus write cycle. the sector erase command is effective only in mcu and serial prom modes, and it cannot be used in parallel prom mode. the time needed to erase 4 kbytes is 30 ms maximu m. the next command sequence cannot be executed if an ongoing erase operation is not complete d. to check the completion of the erase operation, perform read opera- tions twice on the same address in the flash memory, a nd perform polling until the same data is read from the flash memory. during the erase operation, bit 6 is reversed each time a read is performed. table 21-3 range of addresses specifiable erase area flscr1 address specified by instruction (address of 6th bus write cycle) area d1 (data area) 0xc000 through 0xcfff 00 0xc000 through 0xcfff 0xd000 through 0xdfff 0xd000 through 0xdfff 0xe000 through 0xefff 0xe000 through 0xefff 0xf000 through 0xffff 0xf000 through 0xffff area c1 (code area) 0xc000 through 0xcfff 00 0xc000 through 0xcfff 0xd000 through 0xdfff 0xd000 through 0xdfff 0xe000 through 0xefff 0xe000 through 0xefff 0xf000 through 0xffff 0xf000 through 0xffff
page 300 21. flash memory 21.4 toggle bit (d6) TMP89FH46 ra003 21.3.5 product id exit this command is used to exit the product id mode. 21.3.6 security program if the security program is enabled, the flash memory is write and read protected in parallel prom mode, and the flash memory overwrite comma nd and the ram loader command canno t be executed in serial prom mode. to disable the security program, the chip erase must be performed. to check whet her the security program is enabled or disabled, read 0xff7f in product id mode. refer to table 21-4 for further details. the time needed to enable or disable the security program is 40 s maximum. the next comman d sequence cannot be executed until the security program setting is completed. to check the completion of the security program setting, per- form read operations twice on the same address in th e flash memory, and perform polling until the same data is read. when the security program se tting is being made, bit 6 is reversed each time a read is performed. 21.4 toggle bit (d6) after the flash memory write, the chip erase, and the security program co mmand sequence are executed, the value of the 6th bit (d6) in data read by a read operation is reversed each time a read is performed. this bit reversal can be used as a software mechanism for checking the completio n of each operation. normal ly, perform read operations twice on the same address in the flash memory, and perfor m polling until the same data is read from the flash mem- ory. after the flash memory write, the chip erase, and the s ecurity program command sequ ence are executed, the toggle bit read by the first read operation is always "1". note 1: if flscr1 is set to "disable", the toggle bit is not reversed. note 2: do not read the toggle bit by using a 16-bit transfer in struction. if the toggle bit is read using a 16-bit transfer instruction, the toggle bit does not function properly. note 3: because the instruction cycle is longer than the write time in slow mode, the value is not reversed, even if the toggle bit is read right after the byte program is performed. table 21-4 values to be read in product id mode address meaning read value 0xf000 vendor id 0x98 0xf001 flash id 0x4d 0xff7f security status 0xff: security program disabled other than 0xff: security program enabled
page 301 TMP89FH46 ra003 21.5 access to the flash memory area a read or a program fetch cannot be performed on the whol e of the flash memory area if data is being written to the flash memory, if data in flash memory is being erased or if a security setting is being made in the flash memory. when performing these operation on the flash memory area, the flash memory cannot be directly accessed by using a program in the flash memory; the fl ash memory must be accessed using a program in the bootrom area or the ram area. data can be written to and read from the flash memory area in units of one byte. data in the flash memory can be erased in units of 4 kbytes, and all data in the flash memo ry can be erased at one stro ke. a read can be performed using one memory transfer instruction. a write or erase, however, must be performed using more than one memory transfer instruction because the command sequence met hod is used. for information on the command sequence, refer to table 21-1. note 1: to allow a program to resume control on the flash memory area that is rewritten, it is recommended that you let the program jump (return) after verifying that the program has been written properly. note 2: do not reset the mcu (including a reset generated due to internal factors) when data is being written to the flash memory, data is being erased from the flash memory or the security command is being executed. if a reset occurs, there is the possibility that data in the fl ash memory may be rewritten to an unexpected value. 21.5.1 flash memory cont rol in serial prom mode the serial prom mode is used to access the flash memory by using a control program provided in the bootrom area. since almost all opera tions relating to access to the flas h memory can be controlled simply using data supplied through the serial interface (uart or sio), it is not necessary to operate the control regis- ter for the user. for details of the seri al prom mode, see "serial prom mode". to access the flash memory in serial prom mode by using a user-speci fic program or peripheral functions other than uart and sio, it is n ecessary to execute a control progra m in the ram area by using the ram loader command of the serial prom mode. how to execute this control program is described in "21.5.1.1 how to transfer and write a control pr ogram to the ram area in ram loader mode of the serial prom mode". 21.5.1.1 how to transfer and write a control program to the ram area in ram loader mode of the serial prom mode how to execute a control pr ogram in the ram area in serial prom mode is described below. a control program to be executed in the ram area must be generated in the intel-hex format and be transferred using the ram loader of the serial prom mode. steps 1 and 2 shown below are controlled by a program in the bootrom, and other steps are con- trolled by a program transferred to the ram area. the following procedure is linked with a program example to be explained later. 1. transfer the write control program to the ram area in ram loader mode. 2. jump to the ram area. 3. set a nonmaskable interrupt vector in the ram area. 4. set flscr1 to "0y101", and specify the area to be erased by making the appropriate flscr1 setting. (make the appropriate flscr1 setting as required.) then set "0xd5" on flscr2. 5. execute the erase command sequence. 6. read the same flash memory address twice consecutively. (repeat step 6 until the read values become the same.) 7. specify the area (area erased in step 5 above) to which data is written by making the appropriate flscr1 setting. (make the appropriate flscr1 setting as required.) then set "0xd5" on flscr2. 8. execute the write command sequence. 9. read the same flash memory address twice consecutively. (repeat step 9 until the read values become the same.)
page 302 21. flash memory 21.4 toggle bit (d6) TMP89FH46 ra003 10. set flscr1 to "0y010", and then set "0xd5" on flscr2 (to disable the execution of the command sequence). note 1: if the ram loader is used in serial prom mode, the bootrom disables (di) a maskable interrupt, and the interrupt vector area is designated as a ram area (syscr3="1"). considering that a nonmaskable interrupt may be generated unexpectedly, it is recommended that vector addresses corresponding these interrupts (intundef, intswi: 0x01f8 to 0x01f9, wdt: 0x01fc to 0x01fd) be established and that an interrupt service routine be defined inside the ram area. note 2: if a certain interrupt is used in the ram loader program, a vector address corresponding to that inter- rupt and the interrupt service routine must be establis hed inside the ram area. in this case, it is rec- ommended that a nonmaskable interrupt be handled as explained in note 1. note 3: do not set syscr3 to "0" by using the ram loader program. if an interrupt occurs with syscr3 set to "0", the bootrom area is referenced as a vector address and, therefore, the program will not function properly. example: a case in which a program is transferred to ram, the sector erase is performed on 0xe000 through 0xefff in the code area, and then data of 0x3f is written to 0xe500. main section code abs = 0x0100 ; #### set a nonmaskable interrupt vector inside the ram area #### (step 3) ld hl,0x01fc ; set intundef and intswi interrupt vectors ldw (hl),sintswi ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),sintwdt ; #### sector erase and write process #### ld hl,0xf555 ; variable for command sequence ld de,0xfaaa ; variable for command sequence ; sector erase process (step 5) ld c,0x00 ; set upper address ld ix,0xe000 ; set middle and lower addresses call ssectorerase ; perform a sector erase (0xe000) ; write process (step 8) ld c,0x00 ; set upper address ld ix,0xe500 ; set middle and lower addresses ld b,0x3f ; data to be written call sbyteprogram ; write process (0xe500) ; #### execute the next main program #### : : ; execute the main program j xxxxx ; #### program to be executed in ram #### ssectorerase: call saddconv ; address conversion process ; sector erase pro- cess ld (hl),e ; 1st bus write cycle (note 1) ld (de),l ; 2nd bus write cycle (note 1) ld (hl),0x80 ; 3rd bus write cycle (note 1) ld (hl),e ; 4th bus write cycle (note 1) ld (de),l ; 5th bus write cycle (note 1) ld (ix),0x30 ; 6th bus write cycle (note 1) jsramopend ; write process sbyteprogram: call saddconv ; convert address ld (hl),e ; 1st bus write cycle (note 1) ld (de),l ; 2nd bus write cycle (note 1) ld (hl),0xa0 ; 3rd bus write cycle (note 1) ld (ix),b ; 4th bus write cycle (note 1) ; end process sramopend nop ; (note 2) nop ; (note 2) nop ; (note 2) sloop1: ld a,(ix) ; (step 6,9) cmp a,(ix) j nz,sloop1 ; loop until the read values become the same ld (flscr1),0x40 ; disable the execut ion of command sequence (step 10) ld (flscr2),0xd5 ; reflect the flscr1 setting ret ; return to flash memory ; convert address (steps 4 and 7)
page 303 TMP89FH46 ra003 note 1: in using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more than three machine cycles or arrange write instructions in such a way that they are generated at intervals of three or more machine cycles. if a 16-bit tr ansfer instruction is used or if write instructions are executed at intervals of two machine cycl es, the flash memory co mmand sequence will not be transmitted properly, and a malfunction may occur. note 2: if a read of the flash memory (toggle operation) is to be performed after a write instruction is gener- ated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals of three or more machine cycles; mach ine cycles are counted from when the last xth bus write cycle is generated to when each instruction is generated. three nop instructions are normally used. if the interval between instructions is short, the toggle bit does not operation correctly. saddconv: ld wa,ix swap c and c,0x10 swap w and w,0x08 or c,w xor c,0x08 shrc c or c,0xa0 ld (flscr1),c ; enable the execution of command sequence. make the farea setting. ld (flscr2),0xd5 ; reflect the flscr1 setting ld wa,ix test c.3 j z,saddconvend or w,0x80 ld ix,wa saddconvend: ret ; interrupt subrou- tine sintwdt: : : ; error processing retn sintswi: : : ; error processing retn
page 304 21. flash memory 21.4 toggle bit (d6) TMP89FH46 ra003 21.5.2 flash memory control in mcu mode in mcu mode, a write can be performed on the flash memory by executing a control program in ram or using a support program (api) provided inside bootrom. 21.5.2.1 how to write to the flash memory by transferring a control program to the ram area this section describes how to execute a control program in ram in mcu mode. a control program to be executed in ram must be acquired and stored in the flash memory or it must be imported from an out- side source through a communication pin. (the follow ing procedure assumes that a program copy is pro- vided inside the flash memory.) steps 1 through 5 and 11 shown below concern the control by a program in the flash memory, and other steps concern the control by a progra m transferred to ram. the following procedure is linked with a pro- gram example to be described later. 1. set the interrupt master enable flag to "disable (di)" (imf "0"). 2. transfer the write control program to ram. 3. establish the nonmaskable inte rrupt vector in the ram area. 4. after setting both syscr3 and syscr3 to "1", set "0xd4" on flscr4. then allocate ram to the code area, and switch the vector area to the ram area. 5. invoke the erase processing program in th e ram area by generatin g a call instruction. 6. set flscr1 to "0y101", and specify the area to be erased by making the appropriate flscr1 setting. (make the appropriate flscr1 setting, as necessary.) then set "0xd5" on flscr2. 7. execute the erase command sequence. 8. perform a read on the same address in the flas h memory twice consecutively. (repeat this step until the read values become the same.) 9. after setting flscr1 to "0y010" and flscr1 to "0y00", set "0xd5" on flscr2. (this disables the execution of the command sequence and returns farea to the initial state of mapping.) 10. generate the ret instruction to return to the flash memory. 11. invoke the write program in the ram area by generating a call instruction. 12. set flscr1 to "0y101", and make the appropriate flscr1 setting to specify the area (area erased by performing step 7 above) on which a write is to be performed. (make the appropriate flscr1 setting, as necessary.) then set "0xd5" on flscr2. 13. execute the write command sequence. 14. perform a read on the same address in the flash memory twice consecutively. (repeat this step until the read values become the same.) 15. after setting flscr1 to "0y010" an d flscr1 to "0y00", set "0xd5" on flscr2. (this disables the execution of the command sequence and returns farea to the initial state of mapping.) 16. generate the ret instruction to return to the flash memory. note 1: before writing data to the flash memory from the ram area in mcu mode, the vector area must be switched to the ram area by using syscr3, data must be written to the vector addresses (intundef, intswi: 0x01f8 to 0x01f9, intwdt : 0x01fc to 0x01fd) that correspond to non- maskable interrupts, and the interrupt subroutine (ram area) must be defined. this allows you to trap the errors that may occur due to an unexpected nonmaskable interrupt during a write. if syscr3 is set in the flash memory area and if an unexpected interrupt occurs during a write, a malfunction may occur because the vector area in the flash memory cannot be read properly. note 2: before using a certain interrupt in mcu mode, the vector address corresponding to that interrupt and the interrupt service routine must be established in side the ram area. in this case, the nonmaskable interrupt setting must be made, as explained in note 1.
page 305 TMP89FH46 ra003 note 3: before jumping from the flash memory to the ram area, ram must be allocated to the code area by making the appropriate syscr3 setting (setting made in step 4 in the procedure described on the previous page). example: case in which a program is transferred to ram, a sector erase is performed on 0xe000 through 0xefff in the code area, and then 0x3f data is written to 0xe500. cramstartadd equ 0x0200 ; ram start address main section code abs = 0x1000 di ; disable interrupts (step 1) ; #### transfer the program to ram #### (step 2) ld hl,cramstartadd ld ix,sramprogstart sramloop: ld a,(ix) ; transfer the program from sramprogstart to ld (hl),a ; sramprogend to cramstartadd. inc hl inc ix cmp ix,sramprogend jnz,sramloop ; #### set a nonmaskable interrupt vector inside the ram area #### (step 3) ld hl,0x01fc ; set intundef and intswi interrupt vectors ldw (hl),sintswi - sramprogstart + cramstartadd ld hl,0x01f8 ; set intwdt interrupt vector ldw (hl),sintwdt - sramprogstart + cramstartadd ; #### allocate ram to the code area. switch the vector area to ram #### (step 4) ld (syscr3),0x06 ; set rarea and rvctr to "1" ld (syscr4),0xd4 ; enable code ; #### sector erase and write process #### ld hl,0xf555 ; variable for command sequence ld de,0xfaaa ; variable for command sequence ; sector erase process (step 5) ld c,0x00 ; set upper addresses ld ix,0xe000 ; set middle and lower addresses call sramstartadd ; perform a sector erase (0xe000) ; write process (step 11) ld c,0x00 ; set upper addresses ld ix,0xe500 ; set middle and lower addresses ld b,0x3f ; data to be written call sbyteprogram - sramprogstart + cramstartadd ; write process (0xe500) ; #### execute the next main program #### : : ; execute the main program j xxxxx ; #### program to be executed in ram #### sramprogstart: ssectorerase: call saddconv - sramprogstart + cramstartadd ; address conversion process ; sector erase process (step 7) ld (hl),e ; 1st bus write cycle (note 1) ld (de),l ; 2nd bus write cycle (note 1) ld (hl),0x80 ; 3rd bus write cycle (note 1) ld (hl),e ; 4th bus write cycle (note 1) ld (de),l ; 5th bus write cycle (note 1) ld (ix),0x30 ; 6th bus write cycle (note 1) jsramopend ; write process (step 13) sbyteprogram call saddconv - sramprogstart + cramstartadd ; address conversion process ld (hl),e ; 1st bus write cycle (note 1) ld (de),l ; 2nd bus write cycle (note 1) ld (hl),0xa0 ; 3rd bus write cycle (note 1) ld (ix),b ; 4th bus write cycle (note 1) ; end process sramopend: nop ; (note 2) nop ; (note 2) nop ; (note 2)
page 306 21. flash memory 21.4 toggle bit (d6) TMP89FH46 ra003 note 1: in using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of more than three machine cycles or arrange write instructions in such a way that they are generated at intervals of three or more machine cycles. if a 16-bit tr ansfer instruction is used or if write instructions are executed at intervals of two machine cycl es, the flash memory co mmand sequence will not be transmitted properly, and a malfunction may occur. note 2: if a read of the flash memory (toggle operation) is to be performed after a write instruction is gener- ated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at intervals of three or more machine cycles; mach ine cycles are counted from when the last xth bus write cycle is generated to when each instruction is generated. three nop instructions are normally used. if the interval between instructions is short, the toggle bit does not operation correctly. sloop1: ld a,(ix) ; (steps 8,14) cmp a,(ix) j nz,sloop1 ; loop until the read values become the same ld (flscr1),0x40 ; disable the execution of command sequence (steps 9 and 15) ld (flscr2),0xd5 ; reflect the flscr1 setting ret ; return to flash memory ; address conversion process (steps 6 and 12) saddconv: ld wa,ix swap c and c,0x10 swap w and w,0x08 or c,w xor c,0x08 shrc c or c,0xa0 ld (flscr1),c ; enable the execution of command sequence. make the farea setting. ld (flscr2),0xd5 ; reflect the flscr1 setting ld wa,ix test c.3 j z,saddconvend or w,0x80 ld ix,wa saddconvend: ret ; interrupt subroutine sintwdt: : : ; error processing retn sintswi: : : ; error processing retn sramprogend: nop example: case in which data is read from 0xf 000 in the code area and stored at 0x98 in ram ld (flscr1),0xa8 ; select area c1 ld (flscr2),0xd5 ; reflect the flscr1 setting ld a,(0xf000) ; read data from 0xf000 ld (0x98),a ; store data at 0x98 ld (flscr1),0x40 ; select area d0 ld (flscr2),0xd5 ; reflect the flscr1 setting
page 307 TMP89FH46 ra003 21.5.2.2 how to write to the flash memory by using a support program (api) of bootrom this section describes how to perform an erase and a write on the flash memory by using a support pro- gram (api) of bootrom in mcu mode. example: case in which a sector erase is performed on 0xe000 through 0xefff in the data area, and then data at 0x0100 through 0x01ff is written to 0xe000 through 0xe0ff in the data area. .btwrite equ 0x1010 ; write data to the flash memory .bterasesec equ 0x1012 ; sector erase .bterasechip equ 0x1014 ; chip erase .btgetrp equ 0x1016 ; check the status of the security program .btsetrp equ 0x1018 ; configure the security program main section code abs = 0xf000 ; initial setting ld (flscr1),0x50 ; set barea to "1" (note) ld (flscr2),0xd5 ; reflect the flscr1 setting ; sector erase process (api) ld a,0x0e ; specify the area to be erased (0xe000 through 0xefff) ld c,0xd5 ; enable code call (.bterasesec) ; execute sector erase ; write process ld hl,0xe000 ; flash start address (address where data is written) ld iy,0x0100 ; ram start address sloop1: ld c,0x00 ; address where data is written (bit 16) ld wa,hl ; address where data is written (bits 15 to 0) ld e,(iy) ; data to be written ld (sp-),0xd5 ; enable code call (.btwrite) ; write data to the flash memory (1 byte) inc iy ; increment flash address inc hl ; increment ram address cmp l,0x00 ; finish 256-byte write? j nz,sloop1 ; return to sloop1 if the number of bytes is less than 256 ; end process ld (flscr1),0x40 ; set barea to "0" ld (flscr2),0xd5 example: whether the security program is enabled or disabled is checked. if it is disabled, it is enabled. .btwrite equ 0x1010 ; write data to the flash memory .bterasesec equ 0x1012 ; sector erase .bterasechip equ 0x1014 ; chip erase .btgetrp equ 0x1016 ; check the status of the security program .btsetrp equ 0x1018 ; enable the security program main section code abs = 0xf000 ; initial setting ld (flscr1),0x50 ; set barea to "1" ld (flscr2),0xd5 ; reflect the flscr1 setting ; check the status of the security program ld a,0xd5 ; enable code ld c,0x00 ; set 0x00 (note 1) call (.btgetrp) ; check the status of the security program cmp a,0xff j nz,sskip ; go to sskip if the security program is enabled ; security program enable process (api) ld a,0xd5 ; enable code ld c,0x00 ; set 0x00 (note 1) call (.btsetrp) ; enable the security program sskip ld (flscr1),0x40 ; set barea to "0"
page 308 21. flash memory 21.4 toggle bit (d6) TMP89FH46 ra003 note 1: make sure that you set the c register to "0x00". ld (flscr2),0xd5 ::
page 309 TMP89FH46 ra002 22. serial prom mode 22.1 outline the TMP89FH46 has a 4k-byte bootrom (mask rom) for programming to flash memory. bootrom is available in serial prom mode. the serial prom mode is controlled by rxd0/si0 pins, txd0/so0 pins, mode pin, and reset pin. in serial prom mode, communication is performed via the uart or sio. 22.2 security in serial prom mode, two security functions are provided to prevent illegal memory access attempts by a third party: password and security program functions. for more s ecurity-related information, refer to "22.12 security". table 22-1 operating range in serial prom mode parameter min max unit power supply voltage 4.5 5.5 v high frequency 1 10 mhz
page 310 22. serial prom mode 22.3 serial prom mode setting TMP89FH46 ra002 22.3 serial prom mode setting 22.3.1 serial prom mode control pins to execute on-board programming, ac tivate the serial prom mode. table 22-2 shows the pin setting used to activate the serial prom mode. note: before you activate the serial prom mode, you must set the rxd0/si0/p21 and txd0/so0/p20 pins to high (h) level by using a pull-up resistor. note 1: if other parts are mounted on a user board, they may interfere with data being communicated through these communica- tion pins during on-board programming. it is recommended that these parts be somehow isolated to prevent the pins from being affected. table 22-2 serial prom mode setting pin setting rxd0 / si0 / p21 pin h level txd0 / so0 / p20 pin h level mode, reset pin table 22-3 pin functions in serial prom mode pin name (in serial prom mode) input/out- put function pin name (in mcu mode) txd0 / so0 output serial prom mode control/serial data output (see note 1) txd0 / so0 / p20 rxd0 / si0 input serial prom mode control/serial data input rxd0 / si0 / p21 reset input serial prom mode control reset mode input serial prom mode control mode sclk0 input serial clock input (if sio is used) these ports are in the high-impedance state in the serial prom mode. if the uart is used, the port input is physically fixed to a spec ified input level in order to prevent a penetration current. to enable the port input, the spcr must be set to "1" by operating the ram loader control program. sclk0 vdd power supply 4.5 v to 5.5 v avdd power supply connect to vdd. vss power supply 0 v avss power supply connect to vss. varef power supply leave open or apply reference voltage. input/output port other than rxd0 and txd0 input/out- put these ports are in the high-impedance state in the serial prom mode. the port input is physically fixed to a specified input level in order to prevent a penetration current (the port input is disabled). to enable the port input, the spcr must be set to "1" by operating the ram loader control pro- gram. xin input connect a resonator to make these pins self-oscillate. xout output
page 311 TMP89FH46 ra002 figure 22-1 serial prom mode pin setting note 1: in the case of access using the uart, the control of the sclk0 pin is unnecessary. note 2: for information on other pin settings, refer to "table 22-3 pin functions in serial prom mode". vdd vdd sclk0 rxd0 (p21) txd0 (p20) reset mode external control pull-up resistors xin xout vss gnd TMP89FH46 (4.5 v to 5.5 v)
page 312 22. serial prom mode 22.4 example connection for on-board writing TMP89FH46 ra002 22.4 example connectio n for on-board writing figure 22-2 shows example connections to perform on-board writing. figure 22-2 example connec tions for on-board writing note 1: if other parts on a target board interfere with the uart communication in serial prom mode, disconnect these pins by using a jumper or switch. note 2: if the reset control circuit on a target board interferes with the startup of serial prom mode, disconnect the circuit by using a jumper, etc. note 3: for information on other pin settings, refer to "table 22-3 pin functions in serial prom mode". vdd if uart is used serial prom mode mcu mode vdd mode rxd0 (p21) txd0 (p20) reset pc control pull-up resistors level converter xin xout vss gnd external control board target board rc power-on reset circuit reset control other parts (note 1) (note 2) vdd if sio is used serial prom mode mcu mode vdd mode si0 (p21) so0 (p20) reset pull-up resistors microcomputer, etc. xin xout vss gnd external control board target board rc power-on reset circuit reset control other parts (note 1) (note 2) sclk0 (p22) TMP89FH46 TMP89FH46 (4.5 v to 5.5 v) (4.5 v to 5.5 v)
page 313 TMP89FH46 ra002 22.5 activating the serial prom mode activate the serial prom mode by performing the follow ing procedure. for information on the detailed timing, refer to "22.14.1 reset timing". 1. supply power to the vdd pin. 2. set the reset and mode pins to low. 3. set the rxd0/si0/p21 and txd0/so0/p20 pins to high. 4. wait until the power supply and clock oscillation stabilize. 5. set the reset and mode pins from low to high. 6. input the matching data 0x86 or 0x30 to the rxd0/si0/p21 pins after the setup period has elapsed.
page 314 22. serial prom mode 22.6 interface specifications TMP89FH46 ra002 22.6 interface specifications the serial prom mode supports two communication methods: uart and sio. the communication method is selected based on the first serial data value received after a reset. to execute an on-board program, the communication format of the external controller (personal computer, micro- controller, etc.) must be set as described below. 22.6.1 sio communication - transfer rate: 250 kbps (max.) - data length: 8 bits - slave (external clock) - hardware flow control (so0 pin) if the TMP89FH46 receives serial data "0x30" af ter a reset, it starts the sio communication. in the sio communication, the TMP89FH46 functions as a slave device. therefore, the external controller must supply the TMP89FH46 with a serial clock (sclk0 pin) for synchronization. if the TMP89FH46 is not outputting serial data, it contro ls the hardware flow by using the so0 pin. if inter- nal data processing is not completed yet, though data has been received, the so0 pin outputs the l level. if internal data processing has progressed to a near-complet ion state or if it has been completed, the so0 pin out- puts the h level. the external controller must check the status of the so0 pin before it starts to supply a serial clock. for information on the communication timings of each operation command, refer to " 1.11 ac characteris- tics (sio) ". 22.6.2 uart communication - baud rate: 9600 to 128000 bps (automatic detection) - data length: 8 bits (lsb first) - parity bit: none - stop bit: 1 bit if the TMP89FH46 receives serial data "0x86" after a re set, it starts the uart communication. it also mea- sures the pulse width of the received data (0x86), and automatically establishes the reference baud rate. in all subsequent data communication trans actions, this reference baud rate is used. for information on the commu- nication timings of each operatio n command, refer to "22.14 ac characteristics (uart)". usable baud rates differ depending on the operating frequency and are shown in table 22-4. however, there is the possibility of data communication not working prop erly, even if a baud rate shown in table 22-4 is used, because data communication is affected by frequency errors of a resonator of the external controller (personal computer, etc.), the load cap acity of a communication pin, and various other factors.
page 315 TMP89FH46 ra002 note 1: " " means a usable baud rate. "-" means an unusable baud rate. table 22-4 usable baud ra tes as a general guideline 9600 bps 19200 bps 38400 bps 57600bps 115200 bps 128000 bps 10 mhz ????? 8 mhz ????? 7.3728 mhz ???? - 6.144 mhz ?? -- 6 mhz ????? 5 mhz ?? --- 4.9152 mhz ??? -- 4.19 mhz ?? -- 4 mhz ????? 2 mhz ??? -- 1 mhz ? - --
page 316 22. serial prom mode 22.7 memory mapping TMP89FH46 ra002 22.7 memory mapping figure 22-3 shows memory maps in serial prom and mcu modes. in serial prom mode, the bootrom (mask rom) is mapped to the 0x1000 through 0x17ff in the data area and 0x1000 through 0x1fff in the code area respectively. to write data to or erase data from flash memory by using the ram loader comm and (hereafter called the 0x60 command) and an original pr ogram, data write or erase operations must be performed while switching between areas by using the flash memory control registers (flscr1 and 2) . for information on how to specify addresses, refer to flash memory. when the command to write data to flash memory (hereafter cal led the 0x30 command) or the command to erase data from flash memory (hereafter called the 0xf0 co mmand) is executed, bootrom automatically converts addresses. therefore, as the address of flash memory, speci fy an address equivalent to that specified in mcu mode (if flscr1="0"), namely, 0xc000 through 0xffff. figure 22-3 memory mapping 22.8 operation commands in serial prom mode, the commands shown in table 22 -5 are used. after a reset is released, the TMP89FH46 goes into a standby state and awaits the arrival of matching data 1 (0x86 or 0x30). 0xffff data area if flscr1=0 (mcu mode) code area 0x003f 0x0000 0x0040 0xffff data area if flscr1=1 (mcu mode) code area data area code area 0x003f 0x0000 0x0040 0x17ff 0x1000 0xffff 0x0000 0x17ff 0x1000 0xffff 0x003f 0x0000 0x0040 0x17ff 0xc000 0xc000 0xc000 0xffff 0x0000 0xc000 0xc000 0xc000 0x1000 0xffff 0x0000 0x1fff 0x1000 bootrom (2048 bytes bootrom (2048 bytes bootrom (2048 bytes bootrom (4096 bytes flash flash flash sfr ram ram sfr sfr flash flash flash ram if serial prom mode
page 317 TMP89FH46 ra002 each command is outlined below. for detailed information on how each command works, refer to 22.8.1 and sub- sequent sections. 1. flash memory erase command either chip erase (total erase of flash memory) or sector erase (e rase of flash memory in 4k-byte units) can be used to erase the data in flash memory. data in the erased area is 0xff. if the security pro- gram is enabled or if the option code epfc_op is 0xff, the flash erase command of sector erase cannot be executed. to disable the security program setting, execute the flash erase command of chip erase. before erasing the data in flash memory, the TMP89FH46 performs password authentication excep t where a product is a blank product or epfc_op is 0xff. if a password is not authenticated, the fl ash memory erase command is not executed. 2. flash memory write command data can be written in single-byte units to a speci fied address in flash memory. provision the external controller so that it transmits data to write as binary data in the in tel hex format. if errors do not occur until the end record is reached, the TMP89FH46 calculates checksums in the entire flash memory area (0xc000 through 0xffff), and returns the calculation resu lts. if the security prog ram is enabled, the flash memory write command cannot be executed. in this case, execute chip erase beforehand by using the flash memory erase command. befo re executing the flash memory wr ite command, the TMP89FH46 per- forms password authentication except wh ere a product is a blank product. if a password is not authenti- cated, the flash memory writ e command is not executed. 3. flash memory read command data can be read from a specifie d address in flash memory in single-byte units. provision the external controller so that it tran smits the address in memory where a read starts, as well as the number of bytes. after outputting the number of data equal to the nu mber of bytes, the tmp8 9fh46 calculates the check- sums of the output data, and returns the calculation re sults. if the security program is enabled, the flash memory read command cannot be executed. in this case, execute chip erase beforehand by using the flash memory erase command. before executing the flash memory read comm and, the TMP89FH46 per- forms password authenticatio n except where a product is blank. if a password is not authenticated, the flash memory read command is not executed. table 22-5 operation command in serial prom mode command data operation command description 0x86 or 0x30 setup (matching data 1, 2) after a reset is released, the serial prom mode always starts operation with this command. if matching data 1 is 0x86, communication starts in the uart format. if matching data 1 is 0x30, communication starts in the sio format. 0xf0 flash memory erase data in the flash memory area (address 0xc000 through 0xffff) can be erased. 0x30 flash memory write data can be written to the flash memory area (address 0xc000 through 0xffff). 0x40 flash memory read data can be read from the flash memory area (address 0xc000 through 0xffff). 0x60 ram loader data can be written to a spec ified ram area (address 0x0060 through 0x083f). 0x90 flash memory sum output 0xff check data and 2-byte checksums of the entire flash memory area (address 0xc000 through 0xffff) are output in descending order (from upper to lower bytes). 0xc0 product id code output product id codes are output. 0xc3 flash memory status output the security progr am status and other status codes are output. 0xd0 mask rom emulation setting flash products of 124k or 96kbytes ca n be provisioned to emulate a small- capacity mask rom product. 0xfa flash memory security setting the security program setting is enabled.
page 318 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 4. ram loader command the ram loader transfers the intel he x format data sent by the external controller to the built-in ram. if it completes the data transfer normally, it calculates the checksums, transmits the calculation results, jumps to the ram address specified by the first data record, and starts to execute the user program. if the security program is enable d, the ram loader command is not executed. in this case, execute chip erase beforehand by using the flash memo ry erase command. before execu ting the ram loader command, the TMP89FH46 performs password authentication except wh ere a product is blank. if a password is not authenticated, the ram loader command is not executed. 5. flash memory sum output command checksums in the entire flash memory area (0xc000 through 0xffff) are calculated, and the calcula- tion results are returned. 6. product id code output code this is a code output used to identify a product. the output code consists of information on the rom area and on the ram area respectively. the external cont roller reads this code to identify the product to which data is to be written. 7. flash memory status output code the status of 0xffe0 through 0xffff and that of th e security program are outp ut. the external control- ler reads this code to identify the status of flash memory. 8. mask rom emulation setting command 9. flash memory security setting command this command is used to prohibit the reading or writing of data in flash memory in parallel mode. in serial prom mode, the flash memo ry write command and ram loader command are prohibited. to dis- able the flash memory security program, execute ch ip erase by using the fl ash memory erase command. this command is nonfunctional in the TMP89FH46. it becomes functional if used for a product with flash memory of more than 96kbytes.
page 319 TMP89FH46 ra002 22.8.1 flash memory erase command (0xf0) table 22-6 shows the flash memory erase commands. note 1: "0x** 3" means that the device goes into an id le state after transmitting 3 bytes of 0x**. note 2: for information on the erase area specification, refer to "22.8.1.1 specifying the erase area". for information on check - sums, refer to "22.10 checksum (sum)". for informat ion on passwords, refer to "22.12.1 passwords". note 3: do not transmit a password string if 0xfffa of a flash memory is 0xff, or blank product. (however, the password count storage address and the password comparison start address must be transmitted.) note 4: if a value less than 0x20 is transmitted at the n-th - 2 by te (execution of sector erase) and if 0xfffa of flash memory is 0xff, the TMP89FH46 goes into an idle state. note 5: when a password error occurs, the TMP89FH46 stops communication and goes into an idle state. therefore, when a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 6: if a communication error occurs during the transfer of a password address or a password string, the TMP89FH46 stops communication and goes into an idle state. therefore, when a pa ssword error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. table 22-6 flash memory erase commands transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xf0) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xf0) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address bit 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address bit 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address bit 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address bit 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address bit 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address bit 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : m-th byte password string - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted n-th - 2 byte erase area specification baud rate after adjustment - n-th - 1 byte - baud rate after adjustment ok: checksum (upper byte) (note 3) error: no data transmitted n-th byte - baud rate after adjustment ok: checksum (lower byte) (note 3) error: no data transmitted n-th + 1 byte (wait for the next operation command data) baud rate after adjustment -
page 320 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.1.1 specifying the erase area the flash memory erase command is us ed to specify an area in flash memo ry to be erased at n-th-2 byte; specifically, erasec is used to specify the address of an area to be erased. if data of less than 0x20 is specified, sector erase (e rasing flash memory in 4k-byte units) is executed.. executing sector erase with 0xfffa memory set to "0xff" or with the security program enabled will cause the device to go into an infinite loop state. if data of more than 0x20 is specified, chip erase (total erasure of flash me mory) is executed, and the security program in flash memory is disabled. therefore, to disable th e security program in flash memory, execute chip erase, not sector erase. erase area specification data (data at n-th-2 bytes) 76543210 erasec erasec erase area start address 0x00 reserved 0x01 reserved 0x02 reserved 0x03 reserved 0x04 reserved 0x05 reserved 0x06 reserved 0x07 reserved 0x08 reserved 0x09 reserved 0x0a reserved 0x0b reserved 0x0c 0xc000 - 0xcfff 0x0d 0xd000 - 0xdfff 0x0e 0xe000 - 0xefff 0x0f 0xf000 - 0xffff 0x10 reserved 0x11 reserved 0x12 reserved 0x13 reserved 0x14 reserved 0x15 reserved 0x16 reserved 0x17 reserved 0x18 reserved 0x19 reserved 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved 0x20 or more chip erase (erasure of the entire area)
page 321 TMP89FH46 ra002 note 1: if sector erase is performed on an area where flash memory does not exist, the TMP89FH46 stops communication, and goes into an idle state. note 2: if reserved data is transmitted, the tmp89fh4 6 stops communication, and goes into an idle state.
page 322 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.2 flash memory write command (operation command: 0x30) table 22-7 shows the transfer format s of flash memory write commands. note 1: "0x** 3" means that the device goes into an idle state after trans mitting 3 bytes of 0x**. for further information, refer to table 22-18. note 2: for information on the intel hex format, refer to "22.11 intel hex format (binary)". for information on checksums, refer to "22.10 checksum (sum)". for information on passwords, refer to "22.12.1 passwords". note 3: if the area 0xffe0 through 0xffff is all 0xff, password authentication is not performed and, therefore, the password string need not be transmitted. the password count stor age address and password comparison start address, however, must be specified, even for a blank product. if the passw ord count storage address and/or password comparison start address is/are incorrect, a password error occurs, the TMP89FH46 stops communication, and it goes into an idle state. table 22-7 transfer formats of flash memory write commands transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x30) - baud rate after adjustment baud rate after adjustment ok: echo back data (0x30) - error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : m-th byte password string (note) - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th+1 byte : n-th-3 byte intel hex format (binary) baud rate after adjustment - - n-th-2 byte - baud rate after adjustment ok: 0x55 overwrite detect: 0xaa n-th-1 byte - baud rate after adjustment ok: checksum (high) (note 3) error: no data transmitted n-th byte - baud rate after adjustment ok: checksum (low) (note 3) error: no data transmitted n-th+1 byte (wait for the next operation command data) baud rate after adjustment -
page 323 TMP89FH46 ra002 therefore, if a password error occurs, initialize the tmp8 9fh46 by using the reset pin, and restart the serial prom mode. note 4: if the security program is enabled in flash memory or if a password error occurs, the TMP89FH46 stops communication, and goes into an idle state. therefore, if a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 5: if a communication error occurs during the transfer of a password address or a password string, the TMP89FH46 stops communication and goes into an idle state. therefore, when a pa ssword error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 6: if all data in flash memory are the same data, make sure that you never write data to the address 0xffe0 through 0xffff. if data is written to this address, a password er ror occurs, and the subsequent operations cannot be performed. note 7: the n-th-2 byte is a flag for detecting an overwrite. if memory contents at an address where data is to be written are o ther than 0xff, the n-th-2 byte is 0xaa (data is not written to this address, and the data write routine is skipped). the check- sum at the n-th-1 byte or n-th byte is calculated based on data in which data in memory areas where data was not written are included. therefore, if an overwrite is detected, the checksum of transmitted data does not match that at the n-th-1 byte or n-th byte.
page 324 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.3 flash memory read co mmand (operation command: 0x40) table 22-8 shows the transfer format s of the flash memory read command. table 22-8 transfer formats of the flash memory read command transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x40) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x40) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : m-th byte password string - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + 1 byte m-th + 2 byte read start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + 3 byte m-th + 4 byte read start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + 5 byte m-th + 6 byte read start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + 7 byte m-th + 8 byte number of bytes to read 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + 9 byte m-th + 10 byte number of bytes to read 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + 11 byte m-th + 12 byte number of bytes to read 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted
page 325 TMP89FH46 ra002 note 1: "0x** 3" means that the device goes into an idle state after trans mitting 3 bytes of 0x**. for further information, refer to table 22-18. note 2: for information on checksums, refe r to "22.10 checksum (sum)". for information on passwords, refer to "22.12.1 pass- words". note 3: if the area 0xffe0 through 0xffff is all 0xff, password authentication is not performed and, therefore, the password string need not be transmitted. the password count stor age address and password comparison start address, however, must be specified, even for a blank product. if the passw ord count storage address and/or password comparison start address are/is incorrect, a password error occurs; the tm p89fh46 stops communication and goes into an idle state. therefore, if a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 4: if the security program is enabled in flash memory or if a password error occurs, the TMP89FH46 stops communication, and goes into an idle state. therefore, if a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 5: if a communication error occurs during the transfer of a password address or a password string, the TMP89FH46 stops communication and goes into an idle state. therefore, when a pa ssword error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 6: if the number of bytes received at the m-th + 7 byte, m-th + 9 byte or m-th + 11 byte is more than 0x000000 or the size of internal memory, the TMP89FH46 stops communication and goes into an idle state. table 22-9 transfer formats of the flash memory read command transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom m-th + 13 byte : n-th - 2 byte baud rate after adjustment baud rate after adjustment memory data memory data n-th - 1 byte - baud rate after adjustment ok: checksum (high) error: no data transmitted n-th byte - baud rate after adjustment ok: checksum (low) error: no data transmitted n-th + 1 byte (wait for the next operation command data) baud rate after adjustment -
page 326 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.4 ram loader command (operation command: 0x60) table 22-10 shows the transfer form ats of the ram loader command. note 1: "0x** 3" means that the device goes into an idle state after trans mitting 3 bytes of 0x**. for further information, refer to table 22-18. note 2: for information on the intel hex format, refer to "22.11 intel hex format (binary)". for information on checksums, refer to "22.10 checksum (sum)". for information on passwords, refer to "22.12.1 passwords". note 3: if the area 0xffe0 through 0xffff is all 0xff, password authentication is not performed and, therefore, the password string need not be transmitted. the password count stor age address and password comparison start address, however, must be specified, even for a blank product. if the passw ord count storage address and/or password comparison start address are/is incorrect, a password error occurs; the tm p89fh46 stops communication and goes into an idle state. therefore, if a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. table 22-10 transfer formats of the ram loader command transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x60) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x60) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : m-th byte password string - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted m-th + xx byte : n-th - 2 byte intel hex format (binary) baud rate after adjustment baud rate after adjustment - - n-th - 1 byte - baud rate after adjustment ok: checksum (high) (note 3) error: no data transmitted n-th byte - baud rate after adjustment ok: checksum (low) (note 3) error: no data transmitted ram - the program jumps to the start address of ram in which the first transferred data is written, and executes itself.
page 327 TMP89FH46 ra002 note 4: after sending a password string, do not send the end record only. if the TMP89FH46 receives the end record after receiv- ing a password string, it may malfunction. note 5: if the security program is enabled in flash memory or if a password error occurs, the TMP89FH46 stops communication, and goes into an idle state. therefore, if a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 6: if a communication error occurs during the transfer of a password address or a password string, the TMP89FH46 stops communication and goes into an idle state. therefore, when a pa ssword error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode.
page 328 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.5 flash memory sum output command (operation command: 0x90) table 22-11 shows the transfer formats of the flash memory sum output command. note 1: "0x** 3" means that the device goes into an idle state after trans mitting 3 bytes of 0x**. for further information, refer to table 22-18. note 2: for information on checksums, refer to "22.10 checksum (sum)". note 3: if data to be included in the checksum are all 0xff, the 7th byte becomes 0xaa. if any one piece of data to be included in the checksum is other than 0x ff, the 7th byte becomes 0x55. table 22-11 transfer formats of the flash memory sum output command transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0x90) - baud rate after adjustment baud rate after adjustment - ok: no data transmitted (0x90) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte - baud rate after adjustment 0x55 : - 0xaa: all data are 0xff. 8th byte - baud rate after adjustment ok: checksum (high) (note 2) error: no data transmitted 9th byte - baud rate after adjustment ok: checksum (low) (note 2) error: no data transmitted 10th byte (wait for the next operation command data) baud rate after adjustment -
page 329 TMP89FH46 ra002 22.8.6 product id code output comm and (operation co mmand: 0xc0) table 22-12 shows the transfer formats of the product id code output command. note 1: "0x** 3" means that the device goes into an idle state after trans mitting 3 bytes of 0x**. for further information, refer to table 22-18. note 2: the rom size code at the 14th byte is shown in table 22-13. note 3: 16th through 21st bytes show the range of addresses in flash memory where data can be written. table 22-12 transfer formats of the product id code output command transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment -(automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xc0) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xc0) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte baud rate after adjustment 0x3a start mark 8th byte baud rate after adjustment 0x13 number of transfer data (from 9th to 27th bytes) 9th byte baud rate after adjustment 0x03 length of address (3 bytes) 10th byte baud rate after adjustment 0xfd reserved 11th byte baud rate after adjustment 0x00 reserved 12th byte baud rate after adjustment 0x00 reserved 13th byte baud rate after adjustment 0x00 reserved 14th byte (note 2) 0x40 rom size code 15th byte baud rate after adjustment 0x01 rom block count (1 block) 16th byte (note 3) baud rate after adjustment 0x00 first address of rom (upper byte) 17th byte (note 3) baud rate after adjustment 0xc0 first address of rom (middle byte) 18th byte (note 3) baud rate after adjustment 0x00 first address of rom (lower byte) 19th byte (note 3) baud rate after adjustment 0x00 end address of rom (upper byte) 20th byte (note 3) baud rate after adjustment 0xff end address of rom (middle byte) 21st byte (note 3) baud rate after adjustment 0xff end address of rom (lower byte) 22nd byte (note 4) baud rate after adjustment 0x00 first address of ram (upper byte) 23rd byte (note 4) baud rate after adjustment 0x00 first address of ram (middle byte) 24th byte (note 4) baud rate after adjustment 0x60 first address of ram (lower byte) 25th byte (note 4) baud rate after adjustment 0x00 end address of ram (upper byte) 26th byte (note 4) baud rate after adjustment 0x08 end address of ram (middle byte) 27th byte (note 4) baud rate after adjustment 0x3f end address of ram (lower byte) 28th byte baud rate after adjustment 0xyy yyh : checksum of transfer data (complement of 2 of the sum total from 9th through 27th bytes) 29th byte (wait for the next operation command data) baud rate after adjustment -
page 330 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 note 4: 22nd through 27th bytes show the flash memory area and ra m area that can be used by the ram loader. because the range of addresses shown here does not include the work area us ed by bootrom, it is smaller than the size of a ram built into an actual product. table 22-13 rom size code (14th byte) 76543210 romsize "0" "0" "0" TMP89FH46 specified value (0100 0000) romsize data on the flash memory size 00010 : 4kbytes 00100 : 8kbytes 01000 : 16kbytes 10000 : 32kbytes 11000 : 48kbytes 11110 : 60kbytes 10001 : 96kbytes 11111 : 124kbytes read only
page 331 TMP89FH46 ra002 22.8.7 flash memory stat us output command (0xc3) table 22-14 shows the flash me mory status output commands. note 1: "xxh 3" means that the device goes into an idle state after transmitting 3 bytes of xxh. note 2: for detailed information on the status code 1, refer to "22.8.7.1 flash memory status code". table 22-14 flash memory status output commands transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the exter- nal controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment -(automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xc3) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xc3) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte baud rate after adjustment 0x3a start mark 8th byte baud rate after adjustment 0x04 byte count (from 9th through 12th bytes) 9th byte baud rate after adjustment 0x00 to 0x7f status code 1 10th byte baud rate after adjustment 0x00 reserved 11th byte baud rate after adjustment 0x00 reserved 12th byte baud rate after adjustment 0x00 reserved 13th byte baud rate after adjustment checksum (complement of 2 of the sum total from 9th through 12th bytes) 14th byte (wait for the next operation command data) baud rate after adjustment -
page 332 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.7.1 flash memory status code the flash memory status code is 7-byte data. it show s the status of the flash memory security program and that of the address from 0xffe0 to 0xffff. restrictions are placed on the execu tion of some operation commands, de pending on the contents of the status code 1. detailed information on this is shown in the table below. if the s ecurity program is enabled, three commands cannot be executed: the flash memory write command, ram loader mode command, and sector erase command. to exec ute these commands, chip erase mu st be performed on flash memory before they are executed. table 22-15 flash memory status code data description in the case of TMP89FH46 1st start mark 0x3a 2nd number of transfer data (4 bytes from 3rd through 6th bytes) 0x04 3rd status code 0x00 through 0x1f (see information below) 4th reserved 0x00 5th reserved 0x00 6th reserved 0x00 7th checksum of transfer data (complement of 2 of the sum total of 3rd through 6th bytes) if 3rd data is 0x00: 0x00 if 3rd data is 0x01: 0xff if 3rd data is 0x02: 0xfe if 3rd data is 0x03: 0xfd : status code 1 76543210 epfc dafc rpena blank initial value (**** ****) epfc password string judgment when the flash memory erase command is executed (status of 0xfffa) 0: 1: to skip the judgment of a password string (to judge pnsa and pcsa only) to judge a password string, pnsa, and pcsa dafc security program check of the on- chip debugging function (ocd) (status of 0xfffb) 0: 1: to skip the security program check at the start of ocd to perform the security program check at the start of ocd rpena status of the flash memory security program 0: 1: status in which the security program is disabled status in which the security program is enabled blank status of 0xffe0 through 0xffff 0: 1: if data in the area 0xffe0 through 0xffff are all 0xff if data in the area 0xffe0 through 0xffff are other than 0xff
page 333 TMP89FH46 ra002 note: : a command can be executed. pass: a password is required to execute a command. : a command cannot be executed. (after a command is echoed back, the TMP89FH46 stops communication, and goes into an idle state.) rpena blank epfc dafc flash memory overwrite command, flash memory read command, and ram loader command flash memory sum out- put command, product id output command, and status output command flash memory erase command flash memory security setting command chip erase sector erase 0000 ?? 1000 ? 01 0* pass ? pass 1* pass pass pass 11 0* ? pass 1* pass pass
page 334 22. serial prom mode 22.8 operation commands TMP89FH46 ra002 22.8.8 mask rom emulat ion setting command (0xd0) table 22-16 shows the mask rom emulation setting command. this command is nonfunctional in the TMP89FH46. it b ecomes functional if used for a product with flash memory of more than 96kbytes. note 1: "xxh 3" means that the device goes into an idle state after transmitting 3 bytes of xxh. table 22-16 command to change the mask rom emulation setting number of transfer bytes transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment -(automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xd0) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xd0) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte set value baud rate after adjustment baud rate after adjustment - ok: echo back data (0xd1) error: no data transmitted 9th byte (wait for the next operation command data) baud rate after adjustment -
page 335 TMP89FH46 ra002 22.8.9 flash memory secu rity setting command (0xfa) table 22-17 shows the flash memory security setting command. note 1: "xxh 3" means that the device goes into an idle state after transmitting 3 bytes of xxh. note 2: for information on passwords, refer to "22.12.1 passwords". note 3: if the flash memory security setti ng command is executed for a blank product or if a password error occurs for a non-bla nk product, the TMP89FH46 stops communication and goes into an idle state. therefore, if a password error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 4: if a communication error occurs during the transfer of a password address or password string, the TMP89FH46 stops communication and goes into an idle state. therefore, if a pass word error occurs, initialize the TMP89FH46 by using the reset pin, and restart the serial prom mode. note 5: if the flash memory security is not enabled, it becomes possible to read rom data freely in parallel prom mode. make sure that you enable the flash memory security in mass production. table 22-17 flash memory security setting command transfer byte transfer data from the external controller to TMP89FH46 baud rate transfer data from TMP89FH46 to the external controller boot rom 1st byte 2nd byte matching data 1 (0x86 or 0x30) - automatic adjustment baud rate after adjustment - (automatic baud rate adjustment) ok: echo back data (0x86 or 0x30) error: no data transmitted 3rd byte 4th byte matching data 2 (0x79 or 0xcf) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0x79 or 0xcf) error: no data transmitted 5th byte 6th byte operation command data (0xfa) - baud rate after adjustment baud rate after adjustment - ok: echo back data (0xfa) error: 0xa1 3, 0xa3 3, 0x63 3 (note 1) 7th byte 8th byte password count storage address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 9th byte 10th byte password count storage address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 11th byte 12th byte password count storage address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 13th byte 14th byte password comparison start address 23 to 16 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 15th byte 16th byte password comparison start address 15 to 08 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 17th byte 18th byte password comparison start address 07 to 00 baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted 19th byte : m-th byte password string - baud rate after adjustment baud rate after adjustment - ok: no data transmitted error: no data transmitted n-th byte - baud rate after adjustment ok: 0xfb (note 3) error: no data transmitted n-th + 1 byte (wait for the next command data) baud rate after adjustment -
page 336 22. serial prom mode 22.9 error code TMP89FH46 ra002 22.9 error code table 22-18 shows the error codes that the tm p89fh46 transmits when it detects errors. note: if a password error occurs, the TMP89FH46 does not transmit an error code. table 22-18 error codes data transmitted meaning of error data 0x63, 0x63, 0x63 operation command error 0xa1, 0xa1, 0xa1 framing error in the received data 0xa3, 0xa3, 0xa3 overrun error in the received data
page 337 TMP89FH46 ra002 22.10checksum (sum) for the following operation commands, a checksum is returned to verify the a ppropriateness of the result of com- mand execution: - flash memory erase command (0xf0) - flash memory write command (0x30) - flash memory sum output command (0x30) - flash memory read command (0x40) - ram loader command (0x60) - product id code output command (0xc0) - flash memory status output command (0xc3) 22.10.1calculation method the checksum (sum) is calculated with the sum of all bytes, and the obtained result is returned as a word. the data is read in single-byte units, and th e calculated result is returned as a word. example: in the case of the product id code output command and flash memory status output command, however, a different calculation method is used. for more information, refer to table 22-19. 22.10.2calculation data table 22-19 shows the data for which a checksum is calculated for each command. 0xa1 if the data to be calculated cons ists of four bytes as shown on the left, the checksum of the data is as follows: 0xb2 0xa1 + 0xb2 + 0xc3 + 0xd4 = 0x02ea sum (high)= 0x02 sum (low)= 0xea 0xc3 0xd4 table 22-19 data for which a checksum is calculated operation command calculation data description flash memory erase command all data in the erased area of flash mem- ory (whole or part of flash memory) when the sector erase is executed, only the erased area is used to calculate the checksum. in the case of the chip erase, an entire area of the flash memory is used. flash memory write command data in the entire area of flash memory even if a part of the flash memo ry is written, the checksum of the entire flash memory area (0xc000 to 0xffff) is calcu- lated. the data length, address, record type and checksum in intel hex format are not included in the checksum. flash memory sum output com- mand flash memory read command data in the read area of flash memory ram loader command ram data written in the first received ram address through the last received ram address the length of data, address, record type and checksum in intel hex format are not included in the checksum. product id code output command 9th through 18th bytes of transferred data for details, refer to "22.8.6 product id code output command (operation command: 0xc0)". flash memory status output com- mand 9th through 12th bytes of transferred data for details, refer to table "table 22-14 flash memory status output commands".
page 338 22. serial prom mode 22.11 intel hex format (binary) TMP89FH46 ra002 22.11intel hex format (binary) for the following two commands, the intel hex format is used in part of the transfer format: - flash memory write command (0x30) - ram loader command (0x60) for information on the definition of the intel hex format, refer to table 22-20. data is in binary form. the start mark ":" must be transmitted as binary data of 0x3a. 1. after receiving the checksum of each data record, the TMP89FH46 goes into a wait state and awaits the arrival of the start mark (0x3a ":") of the next data record. although the external controller transmits data other than 0x3a between records, the TMP89FH46 ignores such data when it is in this wait state. 2. the external controller must be provisioned so that after it transmits the checksu m of end record, it goes into a wait state and does not transmit any data until the arrival of 3-byte data (overwrite detection, upper and lower bytes of the check sum). (3-byte data is used if the flas h memory write command is used. if the ram loader command is used, the exte rnal controller awaits the arrival of 2-byte data, or upper and lower bytes of the checksum.) 3. if a receiving error or intel hex format error occurs, the TMP89FH46 goes into an idle state without return- ing an error code to the external controller. the intel hex format er ror occurs in the following cases: - if the record type is other than 00h, 01h, or 02h - if a checksum error of the intel hex format occurs - if the data length of an extended record (record type = 0x02) is not 0x02 - if the TMP89FH46 receives the data record after receiving an extended record (record type = 0x02) whose segment address is more than 0x2000 - i the data length of the end record (record type = 0x01) is not 0x00 - if the offset address of an extended re cord (record type = 0x02) is not 0x0000 table 22-20 definition of the intel hex format (1) (2) (3) (4) (5) (6) start mark data length (1 byte) offset address (2 bytes) record type (1 byte) data checksum (1 byte) data record (record type = 00) 3a number of data in a data field starting byte stor- age address * specified using big-endian 00 data (1 to 255 bytes) (2) data length (3) offset address (4) record type (5) data complement of 2 of the sum total of the above end record (record type = 01) 3a 00 00 00 01 none (2) data length (3) offset address (4) record type complement of 2 of the sum total of the above extended record (record type = 02) 3a 02 00 00 02 segment address (2 bytes) * specified using big-endian (2) data length (3) offset address (4) record type (5) segment address complement of 2 of the sum total of the above
page 339 TMP89FH46 ra002 22.12security in serial prom mode, two security f unctions are provided to prohibit illegal memory acce ss attempts by a third party: password and security program functions. 22.12.1passwords a password is one of the security functions, and can be used when the TMP89FH46 operates in serial prom mode or when the on-chip debugging function (hereafte r called ocd) is used. specifically, a password can be established by using data (part of user memory) in fl ash memory. if a password is established, a password authentication process must be performed to execute the flash memory read comm and, flash memory write command, and other operat ion commands. in the case of the ocd, the password authentication process is required prior to the start of the ocd system. in parallel prom mode, there are no access-related re strictions using a password. to establish the access- related restrictions that work in both serial and para llel prom modes, the security program must be set to an appropriate setting. 22.12.1.1how a password can be specified with the TMP89FH46, any piece of data in flash memory (8 or mo re consecutive bytes) can be speci- fied as a password. a password thus specified is authenticated by comparing a password string transmit- ted by the external controller with the memory data string of mcu where the password is specified. the area where a password can be specified is 0xc000 through 0xfeff in flash memory. 22.12.1.2password structure a password consists of three components: pnsa, pcsa, and a password string. figure 22-4 shows the password structure (example of a transmitted password). ? pnsa (password count storage address) a 3-byte address is specified in the area 0xc 000 through 0xfeff. the memory data of a specified address is the number of bytes of a password string. if the memory data is less than 0x07 or if an address is outside the specifi ed address range, a password error occurs. the memory data specified here is defined as n. ? pcsa (password comparison start address) a 3-byte address is specified in the area 0xc000 through 0xfeff-n. an address thus speci- fied is the starting address to be used to compar e with a password string. if an address is outside the specified address range, a password error occurs. ? password string data of 8 bytes to 255 bytes (=n) must be sp ecified as a password string. memory data and a password string are compared by a specified num ber "n" of bytes; a comparison starts at an address specified by pcsa. if there is a mismatch as a result of th is comparison or if data of 3 or more consecutive bytes is specified, a pa ssword error occurs, and the TMP89FH46 goes into an idle state. in this idle state, external devices cannot communicate with the TMP89FH46. to resume communication, the TMP89FH46 must be restarted in serial prom mode by using the reset pin.
page 340 22. serial prom mode 22.12 security TMP89FH46 ra002 figure 22-4 password structure (e xample of a password transmitted) 0x08 0x01 0x02 0x03 0x04 0x05 0x08 0xf012 0xf107 0xf108 flash memory 0xf109 0xf10a 0xf10b 0xf10c 0x00 0xf0 0x12 0xf1 0x00 0x07 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 pnsa pcsa password string 0x06 0x07 0xf10d 0xf10e 0x08 is the number of passwords. 8 bytes compare example: pnsa=0xf012 pcsa=0xf107 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are assumed. rxd/si pin mcu
page 341 TMP89FH46 ra002 22.12.1.3password setting, cancellation and authentication ? password setting because a password is created by using part of a user program, a special password setting routine is unnecessary. a password can be set by simply writing a program to flash memory. ? password cancellation to cancel a password, chip erase (all erase) must be performed on flash memory. a pass- word is canceled when flash memo ry is all initialized to 0xff. ? password authentication if there is data other than 0xff in any one byte of data written to the address 0xffe0 through 0xffff of the TMP89FH46, a product is c onsidered a non-blank product, and password authentication is required to ex ecute an operation command. in this password authentication process, pnsa, pcsa and a password string are used. an operation command is executed only if a password has been successfully authenti cated. if a password is unsuccessfully authenti- cated, the TMP89FH46 goes into an idle state. if all data written to the address 0xffe0 th rough 0xffff are 0xff, a product is considered blank, and no password authentication is perfor med. to execute some special operation com- mands, however, pnsa and pcsa are still require d (a password string is not required) even if a product is blank. in this cas e, the addresses defined in tabl e 22-21 must be selected as pnsa and pcsa. whether a product is blank or non-blank can be confirmed by executing the status output command. the operation commands that require pnsa and pcsa (password string) for them to be exe- cuted are as follows: - flash memory erase command (0xf0) - flash memory write command (0x30) - flash memory read command (0x40) - ram loader command (0x60) - flash memory security setting command (0xfa) 22.12.1.4password values and setting range a password must be set in accordance with the condi tions shown in table 22-21. if a password created without meeting these conditions is used, a password error occurs. in this case, the TMP89FH46 does not transmit data and goes into an idle state. table 22-21 password values and setting range password blank product (note 1) non-blank product pnsa (password count storage address) 0xc000 pnsa 0xfeff 0xc000 pnsa 0xfeff pcsa (password comparison start address) 0xc000 pcsa 0xfeff 0xc000 pcsa 0xff00 - n n (password count) *8 n password string not required (notes 4 and 5) required (note 3)
page 342 22. serial prom mode 22.12 security TMP89FH46 ra002 note 1: *: don?t care. note 2: when addresses from 0xffe0 through 0xffff are filled with "0xff", the product is recognized as a blank product. note 3: the data including the same consecutive data (three or more bytes) cannot be used as a password. (a password error occurs during password authentication. the TMP89FH46 does not transmit any data and goes into an idle state.) note 4: in flash memory writing mode or ram loader mode, the bl ank product receives the intel hex format data immediately after receiving pcsa; it does not receive pass word strings. in this case, the subs equent processing is performed correctly because the TMP89FH46 keeps ignoring incoming data until the star t mark (0x3a ":") in the intel hex format is detected, even if the external controller transmits the dummy password string. however, if the dummy password string contains "0x3a", it is detected as the start mark erroneously, and the mi crocontroller enters the halt mode. if this causes a problem, do not transmit the dummy password strings. note 5: in executing the flash memory erase command, do not transmit a password string to a blank product.
page 343 TMP89FH46 ra002 22.12.2security program the security program can be used in parallel and serial prom modes an d for ocd. it has a special memory for protection, and a special command is required to make this protection setting. if the security program is enabled, the reading or writing of flash memory in para llel prom mode is prohibited. in serial prom mode, the read and write of flash memory and other operation commands cannot be used. in performing ocd, two options about system startup are provided: prohibiting the system startup by using an option code and starting the system by password authentication. 22.12.2.1how the security program functions with the TMP89FH46, you can cont rol the read of flash memory by writing protection-related informa- tion to a specially-designed memory. because protectio n-related information is wr itten to this specially- designed memory, no user memory resource are required. 22.12.2.2enabling or disabling the security program ? enabling the security program to enable the security program, execute the flash memory security setting command. ? disabling the security program to disable the security program, execute ch ip erase of the flash memory erase command.
page 344 22. serial prom mode 22.12 security TMP89FH46 ra002 22.12.3option codes if a specified option code is placed at a specified address inside th e interrupt vector area, whether password string authentication is pe rformed or not when execu ting the flash memory erase command and whether the security program is checked or not when starting ocd can be designated. - erase password free code epfc_op (0xfffa) if changes are frequently made to a program during software devel opment, there are cases in which a password may get lost. in this case, you can cance l the password string authentication of the flash memory erase command (0xf0) by setting the erase password free code (epfc_op). epfc_op is assigned to 0xfffa in the vector area. allocate 0xff to this epfc _op to cancel the password string of the flash memory erase command (0xf0). it is recommended that the password string au thentication of the flas h memory erase command (0xf0) be enabled during mass production by a llocating data other than 0xff to epfc_op. only chip erase can cancel the password stri ng authentication by using the flash memory erase command. if sector erase is execu ted with epfc_op set to 0xff, the TMP89FH46 goes into an idle state. commands other than th e flash memory erase command cannot cancel the password string authentication. - ocd security program free code dafc_op (0xfffb) with the TMP89FH46, you can enable the security program to prevent illegal access attempts by a third party. if the security program is enable d, restrictions are impos ed on operation commands related to memory access, and the startup of ocd. the security program should be usually enabled at the time of shipment. if there is the possibility that the ocd may be used by keeping the contents of memory intact, it is possible to directly start the ocd by setting the ocd security program free code (dafc_op) and thereby skipping the security program check (the password string authen tication, however, is still required). dafc_op is assigned to 0xfffb in the vector area. to skip th e security program check at the startup of the ocd, assign 0xff to dafc_op. in th is case, the security program check is not per- formed, and the ocd can be started by performing only the password string authentication. if dafc_op is not 0xff, whether the ocd can be used or not is determined by the status of the security program. if the ocd is started with the security program enab led, the TMP89FH46 stops communication and goes into an id le state. to use the ocd when the TMP89FH46 is in this idle state, chip erase must be exec uted for flash memory by using the flash memory erase command (0xf0). if the security program is disabled, the ocd can be started by performing only the password string authentication. table 22-22 option codes symbol function address set value epfc_op password string authentication when the flash memory erase command is executed 0xfffa 0xff : the password string authentication is skipped (only pnsa and pcsa are authenticated). other than 0xff: the password string, pnsa, and pcsa are authenticated. dafc_op security program check when the ocd is started 0xfffb 0xff: the security program check is skipped. other than 0xff: the security program check is per- formed.
page 345 TMP89FH46 ra002 example :case in which the passwor d authentication and ocd security program authentication are disabled vector section romdata abs = 0xfffa db db 0xff 0xff ; cancel the password string during the erase operation (epfc_op) ; permit access when the ocd is started (dafc_op)
page 346 22. serial prom mode 22.12 security TMP89FH46 ra002 22.12.4recommended settings table 22-23 shows the option codes and r ecommended security program settings. note 1: in parallel prom mode, chip erase can be performed irrespective of the option code setting. note 2: if the security program is not enabled in parallel prom m ode, rom data can be read with no restrictions. make sure that in parallel prom mode, you always enable t he security program to protect rom data. table 22-23 option codes and recommended security program settings device status serial prom mode parallel prom mode ocd epfc_op (0xfffa) dafc_op (0xfffb) security program memory read erase memory read erase at the time of debug- ging during software development 0xff 0xff disable password string required possible possible possible can be used in quantity production 0xff 0xff enable impossible possible impossible possible can be used other than 0xff cannot be used other than 0xff 0xff password string required can be used other than 0xff cannot be used
page 347 TMP89FH46 ra002 22.13flowchart figure 22-5 flowchart start setup receive data receive data receive data receive data receive data =0x30 (flash memory write command) receive data =0x90 (flash memory sum output command) s1o mode uart mode transmit uart data (0x86) transmit s1o data (0x30) transmit uart data (0x79) transmit data (0x30) transmit data (checksum of the entire area) transmit data (detect double writes) transmit data (detect all 0xff) transmit data (checksum of the entire area) transmit data (0xd1) transmit data (0xfb) transmit data (0xf0) transmit data (0x40) transmit s1o data (0xcf) received data = 0x86 receive data = 0x30 0x86 receive data = 0x79 receive data receive data change flscr1 receive data = 0xcf 0xcf 0x79 execute a write calculate checksum closed loop security program check blank check password check ng ok 0x55 : there is no error. 0xaa: there is an error. (double writes are detected) 0x55 : - 0xaa: all data are 0xff. disabled non-blank product blank product enabled receive data =0x60 (ram loader command) transmit data (0x60) jump to the user program in ram execute a write closed loop blank check password check ng ok closed loop blank check password check ng ok disabled enabled receive data =40h (flash memory read command) receive data =0xf0 (flash memory erase command) transmit data (0xd0) receive data =d0h (mask rom emulation setting command) blank check enable security program closed loop password check ng ok receive data =0xfa (security program enable command) transmit data (0xfa) transmit data (0x90) receive data =0xc0 (product id code output command) transmit data (product id code) transmit data (checksum) transmit data (read data) transmit data (0xc0) receive data =0xc3 (status output command) transmit data (status) transmit data (0xc3) security program check dafc-op and epfc-op check blank check transmit data (checksum of the erased area) receive data chip erase (erase the entire area) sector erase (erase in 4kb units) received data blank check closed loop disabled execute an erase closed loop epfc-op epfc-op password check ng ok 0x20 < 0x20 0xff 0xff perform password check not perform password check = ffh = 0xff disable security program disabled enabled non-blank product blank product non-blank product non-blank product non-blank product blank product blank product blank product enabled security program check security program check security program check
page 348 22. serial prom mode 22.14 ac characteristics (uart) TMP89FH46 ra002 22.14ac characteristics (uart) table 22-24 uart timing-1 parameter symbol clock frequency (fcgck) minimum required time at fcgck = 1 mhz at fcgck = 10 mhz time from when mcu receives 0x86 to when it echoes back cmeb1 approx. 660 660 s 66 s time from when mcu receives 0x79 to when it echoes back cmeb2 approx. 540 540 s 54 s time from when mcu receives an operation command to when it echoes back cmeb3 approx. 300 300 s 30 s time required to calculate the checksum (flash memory) cmfsm approx. 746670 (16kb) 0.8 s 75 ms time required to calculate the checksum (ram) cmrsm approx. 160 160 s 16 s time when mcu receives intel hex data to when it transmits over- write detection data cmwr approx. 200 200 s 20 s time from when mcu receives data (number of read bytes) to when it transmits memory data cmrd approx. 430 430 s 43 s time from when mcu receives data (mask rom emulation setting data) to when it echoes back cmem2 approx. 420 420 s 42 s time required to enable the security program cmrp approx. 1080 1.08 ms 108 s table 22-25 uart timing-2 parameter symbol clock frequency (fcgck) minimum required time at fcgck = 1 mhz at fcgck = 10 mhz time required to keep mode and reset pins at l after power-on rssup - 10 ms time from when mode and reset pins are set to h to the accep- tance of rxd rxsup - 20 ms time from when mcu echoes back 0x86 to the acceptance of rxd cmtr1 approx. 140 140 s 14 s time from when mcu echoes back 0x79 to the acceptance of rxd cmtr2 approx. 90 90 s9 s time from when mcu echoes back an operation command to the acceptance of rxd cmtr3 approx. 270 270 s 27 s time from when the execution of a current command is completed to the acceptance of the next operation command cmnx approx. 1100 1.1 ms 110 s
page 349 TMP89FH46 ra002 22.14.1reset timing figure 22-6 reset timing 22.14.2flash memory erase command (0xf0) figure 22-7 flash memory erase command rxd (0x86) rxsup rssup cmeb1 cmtr1 (0x79) txd reset mode vdd (0x86) (0x79) cmeb2 cmeb3 operation command cmtr2 cmtr3 [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0xf0) cmtr3 [23:16] [15:8] pcsa password string area to be erased checksum [7:0] rxd txd cmnx cmfsm next command
page 350 22. serial prom mode 22.14 ac characteristics (uart) TMP89FH46 ra002 22.14.3flash memory write command (0x30) figure 22-8 flash memory write command 22.14.4flash memory read command (0x40) figure 22-9 flash memory read command [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0x30) cmtr3 [23:16] [15:8] pcsa password string intelhex checksum overwrite detection intelhex(end record) [7:0] (0x3a) rxd txd cmwr cmnx cmfsm next command (0x00) (0x00) (0x01) (0xff) (0x55) or (0xaa) [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0x40) cmtr3 [23:16] [15:8] pcsa password string read start address checksum memory data [7:0] [23:16] [15:8] [7:0] number of read bytes [23:16] [15:8] [7:0] rxd txd cmnx cmrd next command
page 351 TMP89FH46 ra002 22.14.5ram loade r command (0x60) figure 22-10 ram loader command 22.14.6flash memory su m output command (0x90) figure 22-11 flash memo ry sum output command 22.14.7product id code output command (0xc0) figure 22-12 product id code output command [23:16] [15:8] pnsa [7:0] [15:8] [7:0] rxd txd (0x60) cmtr3 [23:16] [15:8] pcsa password string intelhex checksum intelhex(end record) [7:0] (0x3a) rxd txd cmnx cmrsm next command (0x00) (0x00) (0x01) (0xff) cmfsm rxd txd (0x90) (0x55) or (0xaa) ff check checksum cmnx [15:8] [7:0] next command rxd txd (0xc0) product id code cmnx next command
page 352 22. serial prom mode 22.14 ac characteristics (uart) TMP89FH46 ra002 22.14.8flash memory stat us output command (0xc3) figure 22-13 flash memory status output command 22.14.9mask rom emulati on setting command (0xd0) figure 22-14 mask rom em ulation setting command 22.14.10flash memory secu rity setting command (0xfa) figure 22-15 flash memory security setting command rxd txd (0xc3) status code cmnx next command [23:16] [15:8] pnsa [7:0] 0xfb rxd txd (0xfa) cmtr3 [23:16] [15:8] pcsa password string echo back [7:0] rxd txd cmnx cmrp next command
page 353 TMP89FH46 ra000 23. on-chip debug function (ocd) the TMP89FH46 has an on-chip debug function. using a combination of this function and the toshiba on-chip debug emulator rte870/c1, the user is able to perform software debugging in the on-board environment. this emu- lator can be operated from a debugger installed on a pc so that the emulation and debugging functions of an applica- tion program can be used to modify a program or for other purposes. this chapter describes the control pins needed to use the on-chip debug function and how a target system is con- nected to the on-chip debug function. for more detailed information on how to use the on-chip debug emulator rte870/c1, refer to the emulator operating manual. 23.1 features the on-chip debug function of the tm p89fh46 has the following features: ? debugging can be performed in much the same way as when a microcontroller p ackaged with the mcu is used. ? the debugging function can be realized using two communication control pins. ? useful on-chip debug functions include the following: - 8 breaks function are provided (one of which can also be used as an event function). - a trace function that allows the newe st two branch instructions to be stored in real time is provided. - functions to display active memory and to overwrite active memory are provided. ? built-in flash memory can be erased and written. 23.2 control pins the on-chip debug function uses two pins for communication and four pins for power supply, reset and mode con- trol. the pins used for the on-chip debug function are shown in table 23-1. ports p20 and p21 are used as communication control pins of the on-chip debug function. if the on-chip debug emulator rte870/c1 is used, therefor e, the port functions and the functions of uart0 and sio0, which are also used as ports, cannot be debugged. note 1: to use all on-chip debug functions, the po wer supply voltage must be within the range 4.5 v to 5.5 v . if it is within the range 2.7 v to 4.5 v, functional limitations occur with some of t he debug functions. for more detailed information, refer to the emulator operating manual. table 23-1 pins used for the on-chip debug function pin name (during on-chip debugging) input/out- put function pin name (in mcu mode) ocdck input communication control pin (clock control) (note 1) p20 / txd0 / so0 ocdio i/o communication control pin (data control) p21 / rxd0 / si0 reset input reset control pin reset mode input mode control pin mode vdd power supply 4.5 v to 5.5 v (note 1) vss power supply 0 v input and output ports other than p20 and p21 i/o can be used for an a pplication in a target system xin input to be connected to an oscillator to put these pins in a state of self-oscillation xout output
page 354 23. on-chip debug function (ocd) 23.3 how to connect the on-chip debug emulator to a target system TMP89FH46 ra000 23.3 how to connect the on-chip debug emulator to a target system to use the on-chip debug function, the specific pins on a target system must be connected to an external debugging system. the on-chip debug emulator rte870/c1 can be connected to a target system via an interface control cable. toshiba provides a connector for this interface control cable as an accessory tool. mounting this connector on a target system will make it easier to use the on-chip debug function. the connection between the on-chip deb ug emulator rte870/c1 and a target system is shown in figure 23-1. figure 23-1 how the on-chip debug emul ator rte870/c1 is connec ted to a target system note 1: ports p20 and p21 are used as communication contro l pins of the on-chip debug function. if the on-chip debug emulator rte870/c1 is used, therefore, the port functi ons and the functions of uart0 and sio0, which are also used as ports, cannot be debugged. if the emulator is discon nected to be used as a single mcu, the functions of ports p20 and p21 can be used. to use the on-chip debug function, however, p20 and p21 should be discon- nected using a jumper, switch, etc. if there is the possi bility of other parts affecting the communication control. note 2: if the reset control circuit on an application board affects the control of t he on-chip debug function, it must be dis- connected using a jumper, switch, etc. note 3: the power supply voltage vdd must be provided by a ta rget system. the vdd pin is connected to the emulator so that the level of voltage appropriate for driving comm unication pins can be obtained by using the power supply of a target system. the connection of the vdd pin is fo r receiving the power supply voltage, not for supplying it from the emulator side to a target system. 23.4 security the TMP89FH46 provides two security functions to preven t the on-chip debug function from being used through illegal memory access attempted by a third person: a passwor d function and a security pr ogram function. if a pass- word is set on the TMP89FH46, it is necessary to authen ticate the password for using the on-chip debug function. by setting both a password and the security program on the tmp89f h46, it is possible to prohibit the use of all on-chip debug functions. furthermore, by using the option code, the on-chip debug function only can be used even if the security program is en abled. however, to use the on-chip debug func tion in this setting, a password authentication process is required. for information on how to set a password and to enable the read protection and option code, refer to "serial prom mode". during on-chip debugging mcu mode vdd mode ocdck (p20) ocdio (p21) reset usb connection xin xout vss on-chip debug emulator rte870/c1 interface control cable connectors pc (host system) target system reset control other parts (note 1) (note 2) (note 3) vdd (note 3) level shifter (provided power supply by target system) control circuit (provided power supply by bus power) TMP89FH46
page 355 TMP89FH46 ra000 24. input/output circuit 24.1 control pins the input/output circuitries of the TMP89FH46 control pins are shown below. control pin i/o circuitry remarks xin xout input output refer to the p0 ports in the chapter of input/output ports. xtin xtout input output refer to the p0 ports in the chapter of input/output ports. reset input refer to the p1 ports in the chapter of input/output ports. mode input r = 100 ? (typ.) r
page 356 24. input/output circuit 24.1 control pins TMP89FH46 ra000
page 357 TMP89FH46 ra002 25. electrical characteristics 25.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins ratings unit supply voltage v dd ? 0.3 to 6.0 v input voltage v in1 p0, p1, p2 (excluding p23 and p24), p4, p7, p8, p9, pb (tri-state port) ? 0.3 to v dd + 0.3 v v in2 p23, p24 (sink open drain port) ? 0.3 to v dd + 0.3 v in3 ain0 to ain7 (analog input voltage) ? 0.3 to a vdd + 0.3 output voltage v out1 ? 0.3 to v dd + 0.3 v output current (per pin) i out1 p0, p1, p2 (excluding p23 and p24), p4, p7, p8, p9, pb (tri-state port) ? 1.8 ma i out2 p0, p1, p2, p4, p9 (pull-up resistor) ? 0.4 i out3 p0, p1, p2, p4, p74 to p77, p8, p9 (tri-state port) 3.2 i out4 p70 to p73, pb (large current port) 30 output current (total) i out1 p0, p1, p2 (excluding p23 and p24), p4, p7, p8, p9, pb (tri-state port) ? 30 i out2 p0, p1, p2, p4, p9 (pull-up resistor) ? 4 i out3 p0, p1, p2, p4, p74 to p77, p8, p9 (tri-state port) 60 i out4 p70 to p73, pb (large current port) 120 power dissipation (topr = 85 c) p d 250 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85
page 358 25. electrical characteristics 25.2 operating conditions TMP89FH46 ra002 25.2 operating conditions the operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under oper ating conditions other than the operating conditions (supply voltage, operating temperature range, sp ecified ac/dc values etc.), malfunc tion may occur. thus, when designing products which include this device, ensure that the op erating conditions for the device are always adhered to. 25.2.1 mcu mode (flash programming or erasing) figure 25-1 clock gear (fcg ck) and high-frequency clock (fc) (v ss = 0 v, topr = ? 10 to 40 c) parameter symbol pins condition min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high level v ih1 mode pin v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low level v il1 mode pin v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 clock frequency fc xin, xout v dd 4.5 v 1.0 10.0 mhz fcgck 0.25 10.0 5.5 4.5 0.250 1 10 [mhz] gear clock(fcgck) frequency range [v] 5.5 4.5 [mhz] high-frequency clock(fc) frequency range [v] 10
page 359 TMP89FH46 ra002 25.2.2 mcu mode (except fl ash programming or erasing) figure 25-2 clock gear (fcg ck) and high-frequency clock (fc) (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min max unit supply voltage v dd fc = 10.0 mhz normal1, 2 modes idle0, 1, 2 modes 2.7 5.5 v fc = 8.0 mhz 2.2 fcgck = 10.0 mhz 4.3 fcgck = 4.2 mhz 2.7 fcgck = 2.0 mhz 2.2 fs = 32.768 khz slow1, 2 modes sleep0, 1 modes stop mode input high level v ih1 mode pin v dd 4.5 v v dd 0.70 v dd v v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 mode pin v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 2.2 to 5.5 v 1.0 8.0 mhz v dd = 2.7 to 5.5 v 1.0 10.0 fcgck v dd = 2.2 to 5.5 v 0.25 2.0 v dd = 2.7 to 5.5 v 4.2 v dd = 4.3 to 5.5 v 10.0 fs xtin, xtout v dd = 2.2 to 5.5 v 30.0 34.0 khz 5.5 4.3 2.7 0.250 2 1 2 4 4.2 4.2 10 [mhz] gear clock(fcgck) frequency range [v] 2.2 5.5 4.3 2.7 [mhz] high-frequency clock(fc) frequency range fc, fc/2 or fc/4 can be used as gear clock (fcgck). only fc/2 or fc/4 can be used as gear clock (fcgck). only fc/4 can be used as gear clock (fcgck). [v] 2.2 8 8.4 10
page 360 25. electrical characteristics 25.2 operating conditions TMP89FH46 ra002 25.2.3 serial prom mode figure 25-3 clock gear (fcg ck) and high-frequency clock (fc) (v ss = 0 v, topr = ? 10 to 40 c) parameter symbol pins condition min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high voltage v ih1 mode pin v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low voltage v il1 mode pin v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 clock frequency fc xin, xout v dd 4.5 v 1.0 10.0 mhz fcgck 0.25 10.0 5.5 4.5 0.250 1 10 [mhz] gear clock(fcgck) frequency range [v] 5.5 4.5 [mhz] high-frequency clock(fc) frequency range [v] 10
page 361 TMP89FH46 ra002 25.3 dc characteristics note 1: typical values show those at topr = 25 c and v dd = 5.0 v. note 2: input current i in3 : the current through pull-up resistor is not included. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 5.5 v v in = v mode = 5.5 v/0 v ? 0.9 ? v input current i in1 mode ?? 2 a i in2 p0, p1, p2, p4, p5, p7, p8, p9, pb i in3 reset , stop input resistance r in2 reset pull-up v dd = 5.5 v, v in = v mode = 0 v 100 220 500 k ? r in3 p0, p1, p2 (excluding p23 and p24), p4, p9 pull-up 30 50 100 output leakage current i lo1 p23, p24 (skin open drain port) v dd = 5.5 v, v out = 5.5 v ?? 2 a i lo2 p0, p1, p2 (excluding p23 and p24), p4, p5, p7, p8, p9, pb (tri- state port) v dd = 5.5 v, v out = 5.5 v/0 v ?? 2 output high voltage v oh except p23, p24, xout, xtout v dd = 4.5 v, i oh = ? 0.7 ma 4.1 ?? v output low voltage v ol except xout, xtout v dd = 4.5 v, i ol = 1.6 ma ?? 0.4 output low current i ol p70 to p73, pb (large current port) v dd = 4.5 v, v ol = 1.0 v ? 20 ? ma
page 362 25. electrical characteristics 25.3 dc characteristics TMP89FH46 ra002 note 1: typical values shown are topr = 25 c and v dd = 5.0 v, unless otherwise specified. note 2: i dd does not include i ref . it is the electrical current in the state in which the peripheral circuitry has been operated. note 3: v in : the input voltage on the pin except mode pin, v mode : the input voltage on the mode pin note 4: when performing a write or erase on the flash memory or activating a security program in the flash memory, make sure that the operating temperature topr is within the range ? 10 c to 40 c. if the temperature is outside this range, the result- ant performance cannot be guaranteed. note 5: in slow1 mode, the difference between the peak current and the average current becomes large. note 6: each supply current in slow2 mode is equi valent to that in idle0, idle1 and idle2 modes. note 7: when a program operates in the flash memory or when dat a is being read from the flash memory, the flash memory oper- ates intermittently, and a peak current flows, as shown in figure 25-4. in this case, the supply current i dd (in normal1, normal2 and slow1 modes) is defined as the sum of the average peak current and mcu current. note 8: if a write or erase is performed on the flash memory or a security program is enabled in the flash memory, an instanta- neous peak current flows, as shown in figure 25-5. note 9: the circuit of a power supply must be designed such as to enable the supply of a peak curr ent. this peak current causes the supply voltage in the device to fluctuate. connect a bypass capacitor of about 0.1 f near the power supply of the device to stabilize its operation. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit supply current in normal 1, 2 modes (note 7) i dd (note 8) v dd = 5.5 v v in = 5.3 v/0.2 v v mode = 5.3v/0.1v fcgck = 10.0 mhz fs = 32.768 khz when a program operates on flash memory ? 14.5 20.0 ma when a program operates on ram ? 9.5 12.5 supply current in idle0, 1, 2 modes ? 5.5 7.5 supply current in normal 1, 2 modes (note 7) v dd = 5.5 v v in = 5.3 v/0.2 v v mode = 5.3v/0.1v fcgck = 8.0 mhz fs = 32.768 khz when a program operates on flash memory ? 13 ? when a program operates on ram ? 8 ? supply current in idle0, 1, 2 modes ? 4.5 ? supply current in slow1 mode (notes 5 and 7) v dd = 3.0 v v in = 2.8 v/0.2 v v mode = 2.8v/0.1v fs = 32.768 khz when a program operates on flash memory ? 20 39 a when a program operates on ram ? 11 30 supply current in sleep1 mode ? 10 24 supply current in sleep0 mode ? 922 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v v mode = 5.3v/0.1v ? 10 25 peak current of inter- mittent operation (notes 7 and 9) i ddrp-p v dd = 5.5 v v in = 5.3 v/0.2 v v mode = 5.3v/0.1v when a program operates on flash memory or when data is being read from flash memory ? 10 ? ma v dd = 3.0v v in = 2.8 v/0.2 v v mode = 2.8v/0.1v ? 2 ? current for writing to flash memory, erasing and security program (notes 4, 8 and 9) i ddew v dd = 5.5 v v in = 5.3 v/0.2 v v mode = 5.3v/0.1v ? 26 ?
page 363 TMP89FH46 ra002 figure 25-4 intermittent operation of flash memory figure 25-5 current when an erase or write is being pe rformed on the flash memory n program counter (pc) n+1 n+2 n+3 1 machine cycle mcu current i [ma] ddp-p typical current momentary flash current maximum current sum of average momentary flash current and mcu current internal write signal t bd , t sce last write cycle of each of the byte program, security program, chip erase and sector erase i [ma] ddew internal data bus program counter (pc) 1 machine cycle
page 364 25. electrical characteristics 25.4 ad conversion characteristics TMP89FH46 ra002 25.4 ad conversi on characteristics note 1: the total error includes all errors except a quantizati on error, and is defined as the ma ximum deviation from the ideal con- version line. note 2: conversion times differ with va riation in the power supply voltage. (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 3.5 ?? analog input voltage range v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 5.5 v v ss = a vss = 0.0 v ? 0.6 1.0 ma non-linearity error v dd = a vdd = 5.0 v v ss = a vss = 0.0v v aref = 5.0v ?? 2 lsb zero point error ?? 2 full scale error ?? 2 to t a l e r r o r ?? 2 (v ss = 0.0 v, 2.7 v v dd < 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.5 ?? analog input voltage range v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 4.5 v v ss = a vss = 0.0 v ? 0.5 0.8 ma non-linearity error v dd = a vdd = 2.7 v v ss = a vss = 0.0v v aref = 2.7v ?? 2 lsb zero point error ?? 2 full scale error ?? 2 to t a l e r r o r ?? 2 (v ss = 0.0 v, 2.2 v v dd < 2.7 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 0.9 ? a vdd v power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.2 ?? analog input voltage range v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 2.7 v v ss = a vss = 0.0 v ? 0.3 0.5 ma non-linearity error v dd = a vdd = 2.2 v v ss = a vss = 0.0v v aref = 2.2 v ?? 4 lsb zero point error ?? 4 full scale error ?? 4 to t a l e r r o r ?? 4
page 365 TMP89FH46 ra002 note 3: the voltage to be input to the ain input pin must be within the range v aref to v ss . if a voltage outside this range is input, converted values will become indeterminate, and conv erted values of other channels will be affected. note 4: analog reference voltage range: ? v aref = v aref ? v ss note 5: if the ad converter is not used, fix the a vdd and v aref pins to the v dd level. 25.5 power-on reset ci rcuit characteristics figure 25-6 power-on reset operation timing note: care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluc- tuations in the power supply voltage (v dd ). note 1: because the power-on reset releasing voltage and the power-on reset detecting voltage change relative to one another, the detected voltage will never become inverted. note 2: a clock output by an osci llating circuit is used as the input clock for a warming-up counter. be cause the oscillation fr e- quency does not stabilize until an os cillating circuit stabilizes, some errors may be included in the warming-up time. note 3: boost the power supply voltage such that t vdd becomes smaller that t pwup . (v ss = 0 v, topr = ? 40 to 85 c) symbol parameter min. typ. max. unit v proff power-on reset releasing voltage note 1.85 2.02 2.19 v v pron power-on reset detecting voltage note 1.75 1.85 1.95 t proff power-on reset releasing response time ? 0.01 0.1 ms t pron power-on reset detecting response time ? 0.01 0.1 t prw power-on reset minimum pulse width 1.0 ?? t pwup warming-up time after a reset is cleared ? 102 x 2 9 /fc ? s t vdd power supply rise time ?? 5ms power supply voltage (v dd ) v proff operating voltage v pron t vdd t ppw t pron warm-up counter start t pwup t proff power-on reset signal cpu and peripheral circuit reset signal warm-up counter clock
page 366 25. electrical characteristics 25.6 voltage detecting circuit characteristics TMP89FH46 ra002 25.6 voltage detecting circuit characteristics figure 25-7 operation timing of the voltage detecting circuit note: care must be taken in system designing since the power-on reset circuit may not fulfill its functions due to the fluc- tuations in the power supply voltage (v dd ). (v ss = 0 v, topr = ? 40 to 85 c) symbol parameter min. typ. max. unit t vltoff voltage detection releasing response time ? 0.01 0.1 ms t vlton voltage detecting detection response time ? 0.01 0.1 t vltpw voltage detecting minimum pulse width 1.0 ?? level of detected voltage operating voltage power supply voltage (v dd ) signal to request the voltage detection interrupt t vlton t vltpw t vltoff voltage detection reset signal
page 367 TMP89FH46 ra002 25.7 ac characteristics 25.7.1 mcu mode (flash programming or erasing) 25.7.2 mcu mode (except fl ash programming or erasing) (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = ? 10 to 40 c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.100 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external clock operation (xin input). fc = 10.0 mhz ? 50.0 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, v dd = 4.3 v to 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.100 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external clock operation (xin input). fc = 10.0 mhz ? 50.0 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, v dd = 2.7 v to 4.3 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.238 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external clock operation (xin input). fc = 10.0 mhz ? 50.0 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl
page 368 25. electrical characteristics 25.8 flash characteristics TMP89FH46 ra002 25.7.3 serial prom mode 25.8 flash characteristics 25.8.1 write characteristics (v ss = 0 v, v dd = 2.2 v to 2.7 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.500 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external clock operation (xin input). fc = 8.0 mhz ? 62.5 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = ? 10 to 40 c) parameter symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.100 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1 modes high-level clock pulse width t wch for external clock operation (xin input). fc = 10.0 mhz ? 50.0 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, topr = ? 10 to 40 c) parameter symbol condition min typ. max number of guaranteed writes to flash memory ?? 100 times flash memory write time ?? 40 s flash memory erase time chip erase ?? 30 ms sector erase ?? 30
page 369 TMP89FH46 ra002 25.9 recommended osc illating condition- 1 note 1: to ensure stable oscillation, the re sonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: the product numbers and specifications of the resonators supplied by murata manufacturing co., ltd. are subject to change. for up to date information, please refer to the following http://www.murata.com             (1) high-frequency oscillation (2) low-frequency oscillation
page 370 25. electrical characteristics 25.10 handling precaution TMP89FH46 ra002 25.10handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0 ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95% - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition.
page 371 TMP89FH46 ra002 25.11revision history rev description ra002 "25.5 power-on reset circuit characteristics" revised table (i pwup unit) from "ms" to "s".
page 372 25. electrical characteristics 25.11 revision history TMP89FH46 ra002
page 373 TMP89FH46 ra000 26. package dimensions lqfp48-p-0707-0.50d rev 01 unit: mm
page 374 26. package dimensions TMP89FH46 ra000
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