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as4c64m16d1 confidential 1 rev. 2 .0 oct . /2014 revision history as4c64m16d1 C 66 - pin tsop ii package revision details date rev 1.0 preliminary datasheet sep 201 4 rev 2 speed grade option changed -5(400mhz) to -6(333mhz) oct 2014
as4c64m16d1 confidential 2 rev. 2 .0 oct . /2014 64 m x 16 bit ddr1 synchronous dram (sdram) confidential advanced (rev . 2 . 0 , oct . /20 1 4 ) features high speed data transfer rates with system frequency up to 200mhz - data mask for write control - four banks con troll ed by ba0 & ba1 - programmable cas latency: 2, 2.5, 3 - programmable wrap sequence: sequential or interleave - p rogrammable burst length: 2, 4, 8 for sequential type 2, 4, 8 for interleave type - automatic and controlled precharge command - power down mode - auto refresh and self refresh - refresh interval: 8192 cycles/64 ms - available in 66 pin tsop ii - sstl - 2 co mpatible i/os - double data rate (ddr) - bidirectional data strobe (dqs) for input and output data, active on both edges - on - chip dll aligns dq and dqs transitions with ck transitions - ck - vdd = 2.5v 0.2v, vddq = 2.5v 0.2v vdd = 2.6v 0.1v, vddq = 2.6v 0.1v (ddr400) - tras lockout supported - concurrent auto precharge option is supported all parts are rohs compliant description the as4c64m16d1 is a four bank ddr dram organized as 4 banks x 16mbit x 16. the as4c64m16d1 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. all of the controls, address, circuits are synchronized with the positive edge of an externally supplied clock. i/o transactions are occurring on both edges of dqs. operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapl ess data rate is possible depending on burst length, cas latency and speed grade of the device. -6 ddr 333 clock cycle time (t ck2 ) 7.5ns clock cycle time (t ck2.5 ) 6ns clock cycle time (t ck3 ) 6ns system frequency (f ck max ) 166 mhz table 1 . speed grade i nformation speed grade clock frequency cas latency t rcd (ns) t rp (ns) ddr1 - 333 166 mhz 3 1 8 1 8 table 2. ordering information product part no org temperature package as4c 64m16d1 - 6 tcn 64m x 16 commercial 0c to 70c 66 - pin tsop ii as4c64m16d1 - 6 ti n 64m x 16 industrial - 40c to 85c 66 - pin tsop ii
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as4c64m16d1 confidential 35 rev. 2 .0 oct . /2014 idd max specifications and conditions ( v ddq =2.5v + 0.2v, v dd =2.5 + 0.2v, for ddr400 v ddq =2.6v + 0.1v, v dd =2.6 + 0.1v ) conditions version symbol - 6 unit ope rating current - one bank active - precharge; trc=trcmin; tck=tckmin; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per idd0 85 ma clock cycle operating current - one bank operation; one b ank open, bl=2 idd1 1 05 ma precharge power - down standby current; all banks idle; power - down mode; idd2p 6 ma cke = =vih(min); a ll banks idle; cke > = vih(min); tck=tckmin; address and other control inputs changing once per clock cycle; vin = idd2f 3 0 ma vref for dq, dqs and dm precharge quiet standby current; cs# > = vih(min); all banks idle; cke > = vih (min); tck=tckmin; address and other control inputs stable with keeping idd2q 25 ma >= vih(min) or == vih(min); cke>=vih(min); one bank active; active - precharge; trc= trasm ax ; tck=tckmin; dq, dqs and dm inputs changing twice per clock cycle; address and ot h e r control inputs changing once per clock cycle idd3n 35 ma operating current - burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tckmin; 50% of data c hanging at every burst; idd4r 1 15 ma lout = 0 m a operating current - burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; tck=tckmin; dq, dm and dqs idd4w 1 45 ma inputs changing twice per clock cycle, 50% of input data changing at every burst auto refresh current; trc = trfcmin; tck=tckmin; burst refresh; address and con trol inputs changing once per clock cycle; data bus inputs are stable trefc= trfc (min) idd5 1 85 ma trefc=7.8ms idd5a 9 ma self - refresh current; cke =< 0.2v; external clock should be on; tck=tckmin. idd6 3 ma operating current - four bank operation; four bank interleaving with bl=4 idd7 23 0 ma
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as4c64m16d1 confidential 38 rev. 2 .0 oct . /2014 electrical characteristics and ac timing - absolute specifications ( v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v, for ddr400 v ddq = +2.6v 0.1v, v dd = +2.6v 0.1v ) ac characteristics - 6 parameter symbol min max units notes access window of dqs from ck/ck t ac - 0.7 0.7 ns ck high - level width t ch 0.45 0.55 t ck 30 ck low - level width t cl 0.45 0.55 t ck 30 clock cycle time cl = 3 t ck (3) 6 12 ns 52 cl = 2.5 t ck (2.5) 6 12 ns 52 cl = 2 t ck (2) 7.5 12 ns 52 dq and dm input hold time relative to dqs t dh 0.4 5 ns 26,31 dq and dm input setup time relative to dqs t ds 0.4 5 ns 26,31 auto precharge write recovery t dal - t ck 54 + precharge time dq and dm input pulse width (for each input) t dipw 1.75 ns 31 access window of dqs from ck/ck t dqsck - 0. 6 0. 6 ns dqs input high pulse width t dqsh 0.35 t ck dqs input low pulse width t dqsl 0.35 t ck dqs - dq skew, dqs to last dq valid, t dqsq 0.40 ns 25,26 per group, per access write command to first dqs latching transition t dqss 0.7 5 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 t ck half clock period t hp t ch, ns 34 t cl data - out high - impedance window from ck/ck t hz - 0.7 +0.7 ns 18 data - out low - impedance window from ck/ck t lz - 0.7 +0.7 ns 18
as4c64m16d1 confidential 39 rev. 2 .0 oct . /2014 ac characteristic s - 6 parameter symbol min max units notes address and control input hold time t ih f 0. 75 ns 14 (fast slew rate) address and control input setup time t is f 0. 75 ns 14 (fast slew rate) address and control input hold time t ih s 0. 80 ns 14 (slow slew rate) address and control input setup time t is s 0. 80 ns 14 (slow slew rate) control & address input width (for each input) t ipw 2.2 ns 53 load mode register command cycle time t mrd 2 t ck dq - dqs hold, dqs to first dq to go non - valid, t qh t hp ns 25, 26 per access - t qhs data hold skew factor t qhs 0.5 5 ns active to precharge command t ras 4 2 70,000 ns 35 active to read with auto precharge t rap 1 8 ns 46 command active to active/auto refresh t rc 60 ns command period auto refresh command period t rfc 120 ns 50 active to read or write delay t rcd 1 8 ns precharge command period t rp 1 8 ns dqs read preamble t rpre 0.9 1.1 t ck 42 dqs read postamble t rpst 0.4 0.6 t ck active bank a to active bank b command t rrd 1 2 ns dqs write preamble t wpre 0.25 t ck dqs write preamble setup time t wpres 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 t ck 19 write recovery time t wr 15 ns internal write to read command delay t wtr 1 t ck data valid output window na t qh - t dqsq ns 25 ave rage periodic refresh interval t refi 7.8 us terminating voltage delay to vdd t vtd 0 ns exit self refresh to non - read command t xsnr 75 ns exit self refresh to read command t xsrd 200 t ck
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as4c64m16d1 confidential 53 rev. 2 .0 oct . /2014 * = device must be in the "all banks idle" state prior to entering self refresh mode ** = txsnr is required before any non-read command can be applied, and txsrd (200 cycles of clk) are required before a read command can be applied.
as4c64m16d1 confidential 54 rev. 2 .0 oct . /2014 figure 42 - read - without auto precharge ck /ck command nop nop pre read cke col n ra ra a10 ba0, ba1 bank x *bank x don't care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = "don't care", if a10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times dq dm dqs c ase 1: t ac/tdqsck = min c ase 2: t ac/tdqsck = max dq dqs nop nop act nop nop nop valid valid valid dis ap one bank all banks t ck t ch t cl t is t is t ih t ih t is t is t ih t ih t ih t is t ih t rpre t rpre t rp t t ra cl = 2 t min hz t max hz t min lz t max lz t max lz t min ac t max t min t max ac bank x do n do n dqsck rpst dqsck rpst t min lz start! autoprecharge x4:a0-a9,a11,a12 x8:a0-a9, a11 x16:a0-a9 x8:a12 x16:a11, a12
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as4c64m16d1 confidential 61 rev. 2 .0 oct . /2014 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice.

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