ret y rt - glass passivated junction chip - ideal for automated placement - low profile package - ultra fast recovery time for high efficiency - halogen-free according to iec 61249-2-21 definition molding compound, ul flammability classification rating 94v-0 base p/n with suffix "g" on packing code - halogen-free terminal: matte tin plated leads, solderable per jesd22-b102 meet jesd 201 class 1a whisker test v rrm v v rms v v dc v i f(av) a trr ns cj pf t j o c t stg o c document number: ds_d1309019 version: d13 note 1: pulse test with pw=300 s, 1% duty cycle taiwan semiconductor esh 1 b esh 1 c 100 150 200 70 105 140 o c/w operating junction temperature range storage temperature range - 55 to +175 - 55 to +175 maximum reverse recovery time (note 2) 15 typical thermal resistance r jl r ja 3585 100 150 200 0.90 1 maximum reverse current @ rated vr t j =25 t j =125 i r maximum dc blocking voltage maximum average forward rectified current 1 maximum instantaneous forward voltage (note 1) @ 1 a v f v peak forward surge current, 8.3 ms single half sine-wave superimposed on rated load i fsm 30 note 2: reverse recovery test conditions: i f =0.5a, i r =1.0a, i rr =0.25a u n i t maximum repetitive peak reverse voltage maximum rms voltage esh 1 d typical junction capacitance (note 3) 16 a 25 a polarity: indicated by cathode band weight: 0.06 g (approximately) m ax i m u m rat i n gs an d elect ri cal ch aract eri st i cs (t a =25 unless otherwise noted) param et er sy m bol esh1b thru ESH1D surface mount ultra fast rectifiers feat u res - moisture sensitivity: level 1, per j-std-020 note 3: measured at 1 mhz and applied reverse voltage of 4.0v d.c. - compliant to rohs directive 2011/65/eu and in accordance to weee 2002/96/ec m ech an i cal dat a case: do-214ac (sma) do-214ac (sma) downloaded from: http:///
part n o. note 1: "x" defines voltage from 100v (esh1b) to 200v (ESH1D) part n o. ESH1D ESH1D (ta=25 unless otherwise noted) document number: ds_d1309019 version: d13 descri pt i on 7,500 / 13" paper reel esh1b thru ESH1D rat i n gs an d ch aract eri st i cs cu rv es ESH1D r3 r3 ESH1D r3g pack i n g code green com pou n d code folded sma orderi n g i n form at i on ex am ple taiwan semiconductor r3 g green compound preferred p/n f2 folded sma esh1x (note 1) r3 suffix "g" sma 1,800 / 7" plastic reel f4 folded sma 7,500 / 13" plastic reel sma 7,500 / 13" paper reel r2 1,800 / 7" plastic reel pack i n g code green com pou n d code pack age pack i n g m2 sma 7,500 / 13" plastic reel f3 0 0.2 0.4 0.6 0.8 1 1.2 75 85 95 105 115 125 135 145 155 165 175 average forward current (a) lead temperature ( o c) fig.1 forward current derating curve resister or inductive load 0 5 10 15 20 25 30 1 10 100 peak forward surge current (a) number of cycles at 60 hz fig. 2 maximum non-repetitive forward surge current 8.3ms single half sine wave jedec method 0.1 1 10 100 0 20 40 60 80 100 120 140 instantaneous reverse current ( a) percent of rated peak reverse voltage (%) fig. 4 typical reverse characteristics tj=25 tj=125 0.1 1 10 100 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 instantaneous forward current (a) forward voltage (v) fig. 3 typical forward characteristics pulse width=300 s 1% duty cycle downloaded from: http:///
min max min max a 1.27 1.58 0.050 0.062 b 4.06 4.60 0.160 0.181 c 2.29 2.83 0.090 0.111 d 1.99 2.50 0.078 0.098 e 0.90 1.41 0.035 0.056 f 4.95 5.33 0.195 0.210 g 0.10 0.20 0.004 0.008 h 0.15 0.31 0.006 0.012 p/n = specific device code g = green compound yw = date code f = factory code document number: ds_d1309019 version: d13 unit (inch) 0.0660.060 0.155 0.095 0.215 m ark i n g di agram c3 . 9 3 d2 . 4 1 e5 . 4 5 symbol unit (mm) a1 . 6 8 b1 . 5 2 pack age ou t li n e di m en si on s dim. unit (mm) unit (inch) su ggest ed pad lay ou t esh1b thru ESH1D taiwan semiconductor 1 10 100 0.1 1 10 100 capacitance (pf) reverse voltage (v) fig. 5 typical junction capacitance f=1.0mhz vslg=50mvp-p downloaded from: http:///
ret y rt assumes no responsibility or liability for any errors inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied,to any intellectual property rights is granted by this document. except as provided in tsc's terms and conditions of sale for such products, tsc assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of tsc products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or seling these products for use in such applications do so at their own risk and agree to fully indemnify tsc for any damages resulting from such improper use or sale. document number: ds_d1309019 version: d13 esh1b thru ESH1D taiwan semiconductor n ot ic e specifications of the products displayed herein are subject to change without notice. tsc or anyone on its behalf, downloaded from: http:///
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