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this is information on a product in full production. september 2015 docid026578 rev 5 1/25 STGIF5CH60TS-L sllimm? - 2 nd series ipm, 3-phase inverter, 8 a, 600 v short-circuit rugged igbts datasheet - production data features ? ipm 8 a 600 v 3-phase igbt inverter bridge including 2 control ics for gate driving and freewheeling diodes ? 3.3 v, 5 v ttl/cmos inputs with hysteresis ? internal bootstrap diode ? undervoltage lockout ? smart shutdown function ? short-circuit protection ? shutdown input/fault output ? separate open emitter outputs ? built-in temperature sensor ? comparator for fault protection ? short-circuit rugged tfs igbts ? very fast, soft recovery diodes ? 85 k ? ntc ul 1434 ca 4 recognized ? fully isolated package ? isolation rating of 1500 vrms/min applications ? 3-phase inverters for motor drives ? home appliances such as washing machines, refrigerators, air conditioners and sewing machine description this second series of sllimm (small low-loss intelligent molded module) provides a compact, high performance ac motor drive in a simple, rugged design. it combines new st proprietary control ics (one ls and one hs driver) with an improved short-circuit rugged trench gate field- stop (tfs) igbt, making it ideal for 3-phase inverter systems such as home appliances and air conditioners. sllimm? is a trademark of stmicroelectronics. table 1. device summary order code marking package packaging STGIF5CH60TS-L gif5ch60ts-l sdip2f-26l tube www.st.com
contents STGIF5CH60TS-L 2/25 docid026578 rev 5 contents 1 internal schematic and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 tso output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 ntc thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
docid026578 rev 5 3/25 STGIF5CH60TS-L internal schematic and pin description 25 1 internal schematic and pin description figure 1. internal schematic diagram and pin configuration /vlgh +vlgh 6'2' &lq *1' 762 1: 19 9errw8 1& +lq8 9errw: 9errw9 9ff+ +lq: +lq9 /lq8 *1' 9ff/ /lq: /lq9 18 : 9 8 3 7 7
internal schematic and pin description STGIF5CH60TS-L 4/25 docid026578 rev 5 table 2. pin description pin symbol description 1nc- 2 vbootu bootstrap voltage for u phase 3 vbootv bootstrap voltage for v phase 4 vbootw bootstrap voltage for w phase 5 hinu high-side logic input for u phase 6 hinv high-side logic input for v phase 7 hinw high-side logic input for w phase 8 vcch high-side low voltage power supply 9 gnd ground 10 linu low-side logic input for u phase 11 linv low-side logic input for v phase 12 linw low-side logic input for w phase 13 vccl low-side low voltage power supply 14 sd /od shutdown logic input (active low) / open-drain (comparator output) 15 cin comparator input 16 gnd ground 17 tso temperature sensor output 18 nw negative dc input for w phase 19 nv negative dc input for v phase 20 nu negative dc input for u phase 21 w w phase output 22 v v phase output 23 u u phase output 24 p positive dc input 25 t2 ntc thermistor terminal 2 26 t1 ntc thermistor terminal 1
docid026578 rev 5 5/25 STGIF5CH60TS-L absolute maximum ratings 25 2 absolute maximum ratings (t j = 25c unless otherwise noted). table 3. inverter parts symbol parameter value unit v pn supply voltage between p -n u , -n v , -n w 450 v v pn(surge) supply voltage surge between p -n u , -n v , -n w 500 v v ces collector-emitter voltage each igbt 600 v i c continuous collector current each igbt (t c = 25 c) 8 a continuous collector current each igbt (t c = 80 c) 5 i cp peak collector current each igbt (less than 1ms) 16 a p tot total dissipation at t c =25c each igbt 30 w t scw short-circuit withstand time, v ce = 300 v, t j = 125 c, v cc = v boot = 15 v, v in = 0 to 5 v 5s table 4. control parts symbol parameter min max unit v cc supply voltage between v cch -gnd, v ccl -gnd -0.3 20 v v boot bootstrap voltage -0.3 619 v v out output voltage between u, v, w and gnd v boot - 21 v boot + 0.3 v v cin comparator input voltage -0.3 20 v v in logic input voltage applied between hinx, linx and gnd -0.3 15 v v sd /od open drain voltage -0.3 7 v i sd /od open drain sink current - 10 ma v tso temperature sensor output voltage -0.3 5.5 v i tso temperature sensor output current - 7 a table 5. total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heat sink plate (ac voltage, t = 60sec.) 1500 vrms t j power chips operating junction temperature -40 to 175 c t c module case operation temperature -40 to 125 c
absolute maximum ratings STGIF5CH60TS-L 6/25 docid026578 rev 5 table 6. thermal data symbol parameter value unit r th(j-c) thermal resistance junction-case single igbt 5 c/w thermal resistance junction-case single diode 9
docid026578 rev 5 7/25 STGIF5CH60TS-L electrical characteristics 25 3 electrical characteristics (t j = 25c unless otherwise noted) table 7. inverter parts symbol parameter test condition min typ max unit i ces collector-cut off current v ce = 600 v, v cc = v boot = 15 v - 100 a v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 to 5 v, i c = 5 a, 1. applied between hinx, linx and gnd for x = u, v, w -1.51.95 v v cc = v boot = 15 v, v in (1) = 0 to 5 v, i c = 8 a, -1.7 v f diode forward voltage v in (1) = 0, i c = 5 a - 2.1 2.7 v v in (1) = 0, i c = 8 a - 2.4 v inductive load switching time and energy (2) 2. t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving condition. t on turn-on time v dd = 300 v, v cc = v boot = 15 v, v in (1) = 0 to 5 v, i c = 5 a -265 ns t c(on) cross-over time on - 110 t off turn-off time - 305 t c(off) cross-over time off - 92 t rr reverse recovery time -100 e on turn-on switching loss -90 j e off turn-off switching loss -60 e rr reverse recovery energy loss 5.6 t on turn-on time v dd = 300 v, v cc = v boot = 15 v, v in (1) = 0 to 5 v, i c = 8 a -282 ns t c(on) cross-over time on - 126 t off turn-off time - 295 t c(off) cross-over time off - 90 t rr reverse recovery time -100 e on turn-on switching loss -163 j e off turn-off switching loss -86 e rr reverse recovery energy loss 9.2
electrical characteristics STGIF5CH60TS-L 8/25 docid026578 rev 5 figure 2. switching time test circuit figure 3. switching time definition 7 7 7df *d 9ff 9 ,qsxw & 9&& &,1 /,1 /9 * *1' 6' / 9gg 9&& +,1 +9* 287 *1' %227 5vg v ce i c i c v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce (a) turn-on (b) turn-off t rr 100% i c 100% i c v in v ce t off t c(off) v in(off) 10% v ce 10% i c am09223v1
docid026578 rev 5 9/25 STGIF5CH60TS-L electrical characteristics 25 table 8. control / protection parts symbol parameter test condition min typ max unit v il low logic level voltage 0.8 v v ih high logic level voltage 2 v i inh in logic ?1? input bias current in x =15v 80 150 200 a i inl in logic ?0? input bias current in x =0v 1 a high side v cc_hys v cc uv hysteresis 1.2 1.4 1.7 v v cch_th(on) v cch uv turn-on threshold 11 11.5 12 v v cch_th(off) v cch uv turn-off threshold 9.6 10.1 10.6 v v bs_hys v bs uv hysteresis 0.5 1 1.6 v v bs_th(on) v bs uv turn-on threshold 10.1 11 11.9 v v bs_th(off) v bs uv turn-off threshold 9.1 10 10.9 v i qbsu under voltage v bs quiescent current v bs = 9 v, hinx (1) = 5v; 55 75 a i qbs v bs quiescent current v cc = 15 v, hinx (1) = 5v 125 170 a i qccu under voltage quiescent supply current v cc = 9 v, hinx (1) = 0 190 250 a i qcc quiescent current v cc = 15 v, hinx (1) = 0 560 730 a r ds(on) bs driver on resistance 150 ? low side v cc_hys v cc uv hysteresis 1.1 1.4 1.6 v v ccl_th(on) v ccl uv turn-on threshold 10.4 11.6 12.4 v v ccl_th(off) v ccl uv turn-off threshold 9.0 10.3 11 v i qccu under voltage quiescent supply current v cc = 10 v, sd pulled to 5v through r sd = 10k ? , cin = linx 1) = 0; 600 800 a i qcc quiescent current v cc = 15 v, sd = 5v, cin = linx 1) = 0; 700 900 a v ssd smart sd unlatch threshold 0.5 0.6 0.75 v i sdh sd logic ?1? input bias current sd = 5v 25 50 70 a i sdl sd logic ?0? input bias current sd =0v 1 a
electrical characteristics STGIF5CH60TS-L 10/25 docid026578 rev 5 note: comparator stay enabled even if v cc is in uvlo condition but higher than 4 v. temperature sensor output v tso temperature sensor output voltage t j = 25 c 1.4 v i tso_snk temperature sensor sink current capability 0.1 ma i tso_src temperature sensor source current capability 4ma 1. applied between hinx, linx and gnd for x = u, v, w table 9. sense comparator (v cc = 15 v, unless otherwise is specified) symbol parameter test condition min typ max unit i cin cin input bias current v cin =1v -0.2 0.2 a v ref internal reference voltage 460 510 560 mv v od open drain low level output voltage i od = 5ma 500 mv t cin_sd c in comparator delay to sd sd pulled to 5v through r sd =10k ? ; measured applying a voltage step 0-1v to pin cin 50% cin to 90% sd 150 230 320 ns sr sd sd fall slew rate sd pulled to 5v through r sd =10k ? ; c l =1nf through sd and ground; 90% sd to 10% sd 25 v/s table 8. control / protection parts (continued) symbol parameter test condition min typ max unit
docid026578 rev 5 11/25 STGIF5CH60TS-L fault management 25 4 fault management the device integrates an open-drain output connected to sd pin. as soon as a fault occurs the open-drain is activated and lvgx outputs are forced low. two types of fault can be pointed out: ? overcurrent (oc) sensed by the internal comparator (see more detail in section 4.2: smart shutdown function ); ? undervoltage on supply voltage (v cc ); each fault enables the sd open drain for a different time; refer to the following table 10: fault timing . actually the device remains in a fault condition (sd at low logic level and lvgx outputs disabled) for a time also depending on rc network connected to sd pin. the network generates a time contribution that adds up to the internal value. figure 4. overcurrent timing (without contribution of rc network on sd ) table 10. fault timing symbol parameter event time sd open-drain enable time result oc over-current event 20 s 20 s 20s oc time uvlo under-voltage lock out event 50 s50s 50s until the vcc_ls exceed the vcc_ls uv turn on threshold uvlo time *,3*)65
fault management STGIF5CH60TS-L 12/25 docid026578 rev 5 figure 5. uvlo timing (without contribution of rc network on sd ) 4.1 tso output the device integrates temperature sensor. a voltage proportional to die temperature is available on tso pin. when this function is not used the pin can be left floating. 4.2 smart shutdown function the device integrates a comparator committed to the fault sensing function. the comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. the output signal of the comparator is fed to an integrated mosfet with the open drain output available on sd input. when the comparator triggers, the device is set in shutdown state and its outputs are all set to low level. *,3*)65
docid026578 rev 5 13/25 STGIF5CH60TS-L fault management 25 figure 6. smart shutdown timing waveforms in case of overcurrent event note: r on_od = v od /5 ma see tab le 9 ; r pd_sd (typ) = 5 v/i sdh /,1 /9* 6' rshqgudlqjdwh lqwhuqdo frps 9uhi &,1 3527(&7,21 )dvwvkxwgrzq wkhgulyhurxwsxwvduhvhwlq6'vwdwh lpphgldwho\diwhufrpsdudwruwuljjhulqj hyhqliwkh6'vljqdokdvqrw\hwuhdfkhg wkhorzhulqsxwwkuhvkrog uhdoglvdeohwlph w 2& w w 6' )52072 &21752//(5 9 %,$6 60$57 6' /2*,& & 6' 5 6' 5 21b2' 5 3'b6' 6+87'2:1&,5&8,7 zkhuh o u $*/@4% w w
fault management STGIF5CH60TS-L 14/25 docid026578 rev 5 in common over-current protection architectures the comparator output is usually connected to the sd input and an rc network is connected to this sd line in order to provide a mono- stable circuit, which implements a protection time that follows the fault condition. differently from the common fault detection systems, the device smart shutdown architecture allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual outputs switch-off. in fact the time delay between the fault and the outputs turn off is no more dependent on the rc value of the external network connected to the pin. in the smart shutdown circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. at the same time the internal logic turns on the open drain output and holds it on until the sd voltage goes below the v ssd threshold and t oc time is elapsed. the driver outputs restart following the input pins as soon as the voltage at the sd pin reaches the higher threshold of the sd logic input. the smart shutdown system provides the possibility to increase the time constant of the external rc network (that is the disable time after the fault event) up to very large values without increasing the delay time of the protection.
docid026578 rev 5 15/25 STGIF5CH60TS-L typical application circuit 25 5 typical application circuit figure 7. typical application circuit 976217& )dxow /lq: /lq9 /lq8 +lq: +lq9 +lq8 976217& & & & &errw: &errw9 &errw8 5 5 5 & & & 5 5 5 & & & 1& 9errw8 9errw9 9errw: +lq8 +lq9 +lq: 9ff+ *1' & & 9ff 9f f &yf f &yff &762 &6' 56' 0,&52&21752//(5 3:5b*1' wr0&8rsdps &6) 56) 5vkxqw & &ygf 0 /lq8 /lq9 /lq: 9ff/ 6'2' &lq *1' 762 1: 19 18 : 9 8 3 7 7 /vlgh +vlgh &72 572 99 976217& '] '] '] '] '] 9 9 6*1b*1 '
recommendations STGIF5CH60TS-L 16/25 docid026578 rev 5 6 recommendations 1. input signals hin, lin are active-high logic. a 500 k ? (typ.) pull-down resistor is built-in for each high side input. to prevent input signal oscillation, the wiring of each input should be as short as possible and the use of rc filters (r1, c1) on each input signal is suggested. the filters should be done with a time constant of about 100 ns and must be placed as close as possible to the ipm input pins. 2. the bypass capacitor cvcc (aluminum or tantalum) is recommended to reduce the transient circuit demand on the power supply. in addition, a decoupling capacitor c 2 (100 to 220 nf, with low esr and low esl) is suggested, to reduce high frequency switching noise distributed on the power supply lines. it must be placed as close as possible to each vcc pin and in parallel to the bypass capacitor. 3. the use of rc filter (rsf, csf) for preventing protection circuit malfunction is recommended. the time constant (rsf x csf) should be set to 1us and the filter must be placed as close as possible to the cin pin. 4. the sd is an input/output pin (open drain type if used as output). it should be pulled up to mcu power supply (3.3/5 v) by a resistor higher than 1.0 k ? in order to keep i od lower than 5 ma. the filter on sd has to be sized to get a desired re-starting time after a fault event and placed as close as possible to the sd pin. 5. to increase the noise immunity of the tso thermal sensor, it is recommended to parallel a decoupling capacitor c tso between 1nf and 10nf. similarly, if the ntc thermistor is available and used, it is recommended to parallel a decoupling capacitor c ot between 10nf and 100nf. in both cases, the capacitors must be placed close to the mcu. 6. the decoupling capacitor c 3 (100 to220 nf, with low esr and low esl) in parallel with each c boot is recommended to filter high frequency disturbances. both c boot and c 3 must be placed as close as possible to the u,v,w and v boot pins. bootstrap negative electrodes should be connected to u,v,w terminals directly and separated from the main output wires. 7. a zener diode (dz1) between each v cc pin and gnd, and in parallel (dz2) with each cboot is suggested in order to prevent overvoltage. 8. the decoupling capacitor c 4 (100 to 220 nf, with low esr and low esl) in parallel with the electrolytic capacitor cvdc is recommended, in order to prevent surge destruction. both capacitors c 4 and cvdc should be placed as close as possible to the ipm (c 4 has priority over cvdc). 9. by integrating an application-specific type hvic inside the module, direct coupling to the mcu terminals without an opto-coupler is possible. 10. low inductance shunt resistors should be used for phase leg current sensing 11. in order to avoid malfunctions, the wiring between n pins, the shunt resistor and pwr_gnd should be as short as possible. 12. it is recommended to connect sgn_gnd to pwr_gnd at only one point (near the terminal of shunt resistor), in order to avoid any malfunction due to power ground fluctuation.
docid026578 rev 5 17/25 STGIF5CH60TS-L recommendations 25 table 11. recommended operating conditions symbol parameter test condition min typ max unit v pn supply voltage applied between p-nu, n v , n w 300 400 v v cc control supply voltage applied between v cc -gnd 13.5 15 18 v v bs high side bias voltage applied between v booti -out i for i = u, v, w 13 18 v t dead blanking time to prevent arm-short for each input signal 1.0 s f pwm pwm input signal -40 c < t c < 100 c -40 c < t j < 125 c 20 khz t c case operation temperature 100 c
ntc thermistor STGIF5CH60TS-L 18/25 docid026578 rev 5 7 ntc thermistor figure 8. ntc resistance vs. temperature table 12. ntc thermistor symbol parameter test condition min typ max unit r 25 resistance t = 25c 85 - k ? r 125 resistance t = 125c 2.6 - k ? b b-constant t = 25c to 100c 4092 - k t operating temperature range -40 125 c n ? ?& *,3*)65
docid026578 rev 5 19/25 STGIF5CH60TS-L ntc thermistor 25 figure 9. ntc resistance vs. temperature - zoom n ?& 0lq 0d[ 7\s *,3*)65
electrical characteristics (curves) STGIF5CH60TS-L 20/25 docid026578 rev 5 8 electrical characteristics (curves) figure 10. output characteristics figure 11. v ce(sat) vs collector current ,*%72& , & $ 9 &( 9 9 && 9 9 9 ,*%79&(& 9 &(vdw 9 , & $ 9 && 9 7 - ?& 7 - ?& figure 12. diode vf vs forward current figure 13. e on switching loss vs collector current ,*%7'9) 9 ) 9 , ) $ 7 - ?& 7 - ?& ,*%76/& ( 21 p- , & $ 7 - ?& 7 - ?& 9 '' 99 && 9 errw 9
docid026578 rev 5 21/25 STGIF5CH60TS-L electrical characteristics (curves) 25 figure 14. e off switching loss vs collector current figure 15. vtso output characteristics vs lvic temperature ,*%76/& ( 2)) p- , & $ 7 - ?& 7 - ?& 9 '' 99 && 9 errw 9 ,*%79762 9 762 9 7?& figure 16. thermal impedance for sdip2f-26l igbt ,*%7=7+ . w s v
package mechanical data STGIF5CH60TS-L 22/25 docid026578 rev 5 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid026578 rev 5 23/25 STGIF5CH60TS-L package mechanical data 25 figure 17. sdip2f-26l type l mechanical drawing table 13. sdip2f-26l type l mechanical dimensions (1) 1. all dimensions are expressed in millimeters. ref. dimensions ref. dimensions ref. dimensions a 38.00 0.50 b3 29.40 0.50 e4 2.54 0.20 a1 1.22 0.25 c 3.50 0.20 f 0.60 0.15 a2 1.22 0.25 c1 5.50 0.50 f1 0.50 0.15 a3 35.00 0.30 c2 14.00 0.50 f 2.10 0.15 c 1.50 0.05 e 3.556 0.200 f1 1.10 0.15 b 24.00 0.50 e1 1.778 0.200 r 1.60 0.20 b1 12.00 e2 7.62 0.20 t 0.400 0.025 b2 14.40 0.50 e3 5.08 0.20 v 0 / 5 8450803_b
revision history STGIF5CH60TS-L 24/25 docid026578 rev 5 10 revision history table 14. document revision history date revision changes 20-jun-2014 1 initial release. 07-aug-2014 2 updated chapter 8: package mechanical data. 26-jun-2015 3 text and formatting changes throughout document on cover page: - updated title, features and description in section 1: internal schematic and pin description : - updated figure 1 and table 2 in section 2: absolute maximum ratings : - updated table 3 , table 4 , table 5 and table 6 in section 3: electrical characteristics : - updated table 7 , figure 2 , table 8 and table 9 in section 4: fault management : - updated figure 6 in section 5: typical application circuit : - updated figure 7 in section 6: recommendations : - updated recommendations list and added table 11 in section 8: electrical characteristics (curves) : - added figure 10 , figure 11 , figure 12 , figure 13 , figure 14 , figure 15 and figure 16 datasheet promoted from preliminary data to production data. 23-jul-2015 4 updated title in cover page and table 3 . 09-sep-2015 5 modified: description and features in cover page minor text changes
docid026578 rev 5 25/25 STGIF5CH60TS-L 25 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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