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figure 1. block diagram. description note: all data is also valid for pbl 3764a/6, except maximum ratings for battery voltage. (see next page) the pbl 3764a/4 subscriber line interface circuit (slic) is a bipolar integrated circuit in 90 v technolo- gy which replaces the conventional transformer based analog line interface circuit in digital loop carrier, pabx and other telecommunications equipment with a modern, compact solid state design. not only is required pcb area reduced, but lesser component weight and height result as well. the pbl 3764a/4 has been optimized for low cost and to require only a minimum of external components. the pbl 3764a/4 is an improved version of the pbl 3764 with an internal saturation guard programming resistor. the pbl 3764a/4 programmable, constant-current feed system can operate with battery supply voltages key features battery feed characteristics programmable via external resistors; feed characteristics independent of slic battery supply variations battery supply voltage as low as 21 v for power efficient line card designs ring relay driver loop current, ground key and ring trip detection functions programmable loop current detector threshold hybrid function with all types of codec/filter devices programmable line terminating impedance, complex or real pbl 3764 a subscriber line interface circuit (slic) down to 21 v to reduce line card power dissipation. the slic incorporates loop current, ground key and ring trip detection functions as well as a ring relay driver. two-to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the slic in conjunction with either a conventional codec/filter or with a programmable codec/filter (e.g. slac, sicofi, combo ii). the programmable line terminating impedance could be complex or real to fit every market. longitudinal line voltages are suppressed by a feedback loop in the slic. longitudi- nal balance specifications exceed bellcore and eia requirements. the pbl 3764a/4 packages are 22-pin dual-in-line or 28-pin plcc. the pbl 3764a/6 package is 28-pin plcc. ring trip detector ring relay driver input decoder and control off-hook detector vf signal transmission two-wire interface ground key detector ringrly c1 c2 e0 e1 det rdc rsg rd vtx rsn 9 16 15 13 12 14 17 11 2 21 19 dt dr tiipx hpr hpt ringx vcc vee vbat agnd bgnd 3 4 5 1 22 6 8 20 10 18 7 line feed controller and longitudinal signal suppression
2 pbl 3764 a 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 maximum ratings parameter symbol min max unit temperature, humidity storage temperature range t stg -60 +150 c operating junction temperature range t j -25 +140 c power supply, -40 c t amb 85 c v cc with respect to agnd v cc -0.5 6.5 v v ee with respect to agnd v ee -6.5 0.5 v v bat with respect to bgnd for pbl 3764a/4 v bat -70 v ee + 0.6 v v bat with respect to bgnd for pbl 3764a/6 v bat -85 v ee + 0.6 v power dissipation continuous power dissipation at t amb 70 cp d 1.5 w peak power dissipation at t amb = 70 c, t < 100 ms, t rep > 1 sec. p dp 4w ground voltage between agnd and bgnd v g -0.3 0.3 v relay driver ring relay supply voltage, note 4 v ring 012v ring relay current i ring 50 ma ring trip comparator input voltage v dt , v dr v bat 0v input current i dt , i dr -5 5 ma digital inputs, outputs (c1, c2, e0, e1, det) input voltage v id 0v cc v output voltage (det disabled) v od 0v cc v input current (det enabled) i od 5ma tipx and ringx terminals, -40 c t amb 85 c, v bat = -50v tipx or ringx voltage, continuous (referenced to agnd), note 1 v ta , v ra v bat 2v tipx or ringx, pulse < 10 ms, t rep > 10 s, note 1 v ta , v ra v bat - 20 5 v tipx or ringx, pulse < 1 s, t rep > 10 s, note 1 v ta , v ra v bat - 40 10 v tip or ring, pulse < 250 ns, t rep > 10 s, note 2 v ta , v ra v bat - 70 15 v tipx or ringx current i lt, i lr 70 ma recommended operating conditions parameter symbol min max unit v cc with respect to agnd v cc 4.75 5.25 v v ee with respect to agnd v ee -5.25 -4.75 v v bat with respect to bgnd, note 3 v bat -58 -24 v notes 1. a diode in series with the v bat input increases the permitted continuous voltage and pulse < 10 ms to -85 v. a pulse 1 s is increased to the greater of |-70 v| and |v bat - 40v|. 2. r f1 , r f2 20 ? is also required. pulse is supplied to tip and ring outside r f1 , r f2 . 3. -24v pbl 3764 a 3 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 figure 3. longitudinal to metallic (b lme ) and longitudinal to four-wire (b lfe ) balance 1 << 150 ? , r lt = r lr = 300 ? c r t = 600 k ? , r rx = 300 k ? figure 2. overload level, v tro , two-wire port 1 << r l , r l = 600 ? c r t = 600 k ? , r rx = 300 k ? electrical characteristics -40 c t amb 85 c, note 10, v cc = +5v 5 %, v ee = -5v 5%, v bat = -48v, agnd = bgnd, r dc1 =r dc2 =41.7k ? , c hp =10nf, c dc = 1.5 f, z l =600 ? unless otherwise specified. all pin number references in the text and figures refer to the 22-pin dip unless otherwise indicated. ref parameter fig conditions min typ max unit two-wire port overload level, v tro 2z l = 600 ? , 1% thd note 1 3.1 v peak input impedance, z tr note 2 longitudinal impedance, z lot , z lor 0 < f < 100 hz 10 35 ? /wire longitudinal current limit, i lot , i lor active state 27 ma rms /wire stand-by state 8.5 ma rms /wire longitudinal to metallic balance, b lm ieee standard 455-1985 0.2 khz f 3.4 khz 0 c t amb 70 c6370 db -40 c t amb 85 c5870 db longitudinal to metallic balance, b lme 3 0.2 khz f 3.4 khz e lo b lme = 20 ?log v tr 0 c t amb 70 c6370 db -40 c t amb 85 c5870 db longitudinal to four-wire balance, b lfe 3 0.2 khz f 3.4 khz e lo b lfe = 20 ?log v tx 0 c t amb 70 c6370 db -40 c t amb 85 c5870 db metallic to longitudinal balance, b mle 4 0.2 khz < f < 3.4 khz 50 55 db e tr b mle = 20 ?log ,e rx = 0 v lo i ldc r l v tro c r t r rx e rx tipx 5 ringx 6 vtx 21 rsn 19 pbl 3764a/4 v tr c r t r rx v tx tipx 5 ringx 6 vtx 21 rsn 19 pbl 3764a/4 r lt r lr e l o
4 pbl 3764 a 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 ref parameter fig conditions min typ max unit figure 5. overload level, v txo , four-wire transmit port 1 << r l , r l = 600 ? c r t = 600 k ? , r rx = 300 k ? figure 4. metallic to longitudinal and four-wire to longitudinal balance 1 << 150 ? , r lt =r lr = 300 ? c r t = 600 k ? , r rx = 300 k ? four-wire to longitudinal balance, b fle 4 0.2 khz < f < 3.4 khz 50 55 db e rx b fle = 20 log v lo e tr source removed two-wire return loss, r |z tr + z l | r = 20 log |z tr - z l | z tr z l = nom. 600 ? 0.2 khz f 0.5 khz 25 db 0.5 khz f 1.0 khz 27 db 1.0 khz f 3.4 khz, note 9 23 db tipx idle voltage, v ti active, i l = 0, r sg = 0 ? -1.5 v stand-by, i l = 0 0.6 v ringx idle voltage, v ri active, i l = 0, r sg = 0 ? -46.5 v stand-by, i l = 0 -48 v tipx-ringx open loop i l = 0, r sg = 0 ? 43.0 45.0 47.0 v metallic voltage, v tr v bat = -52v four-wire transmit port (vtx) overload level, v txo 5 load impedance > 20 k ? , 3.1 v peak 1% thd, note 3 output offset voltage, ? v tx 0 c t amb 70 c -30 30 mv -40 c t amb 85 c -40 40 mv output impedance, z tx 0.2 khz f 3.4 khz <5 20 ? four-wire receive port (rsn) receive summing node (rsn) dc voltage i rsn = 0 ma 0 v receive summing node (rsn) impedance 0.2 khz f 3.4 khz <10 20 ? receive summing node (rsn) 0.3 khz f 3.4 khz 1000 ratio current (i rsn ) to metallic loop current (i l ) gain, rsn e tr r lr c v l o r t r rx e rx r lt tipx 5 ringx 6 vtx 21 rsn 19 pbl 3764a/4 i ldc r l c r t r rx v txo e l tipx 5 ringx 6 vtx 21 rsn 19 pbl 3764a/4
pbl 3764 a 5 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 frequency response two-wire to four-wire, g 2-4 6 0.3 khz < f < 3.4 khz relative to 0 dbm, 1.0 khz. e rx = 0 v 0 c t amb 70 c -0.13 0.13 db -40 c t amb 85 c -0.20 0.20 db four-wire to two-wire, g 4-2 6 0.3 khz < f < 3.4 khz relative to 0 dbm, 1.0 khz. e g = 0 v 0 c t amb 70 c -0.13 0.13 db -40 c t amb 85 c -0.20 0.20 db four-wire to four-wire, g 4-4 6 0.3 khz < f < 3.4 khz relative to 0 dbm, 1.0 khz. e l = 0 v 0 c t amb 70 c -0.13 0.13 db -40 c t amb 85 c -0.20 0.20 db insertion loss two-wire to four-wire, g 2-4 6 0 dbm, 1.0 khz, note 4 v tx g 2-4 = 20 log , e rx = 0 v tr 0 c t amb 70 c -0.13 0.13 db -40 c t amb 85 c -0.20 0.20 db four-wire to two-wire, g 4-2 6 0 dbm, 1.0 khz, notes 4, 5 v tr g 4-2 = 20 log , e l = 0 e rx 0 c t amb 70 c -0.13 0.13 db -40 c t amb 85 c -0.20 0.20 db gain tracking two-wire to four-wire 6 ref. -10 dbm, 1.0 khz, note 7 +3 dbm to +7 dbm -0.15 0.15 db -40 dbm to +3 dbm -0.1 0.1 db -55 dbm to -40 dbm -0.2 0.2 db four-wire to two-wire 6 ref. -10 dbm, 1.0 khz, note 8 -40 dbm to +7 dbm -0.1 0.1 db -55 dbm to -40 dbm -0.2 0.2 db noise idle channel noise at two-wire c-message weighting 8.5 12 dbrnc (tipx-ringx) or four-wire (v tx ) output psophometrical weighting -81.5 -78 dbmp note 6 harmonic distortion two-wire to four-wire 0 dbm, 1.0 khz test signal -65 -54 db four-wire to two-wire 0.3 khz < f < 3.4 khz -65 -54 db ref parameter fig conditions min typ max unit figure 6. frequency response, insertion loss, gain tracking. 1 << r l , r l = 600 ? c r t = 600 k ? , r rx = 300 k ? v tr e rx i dcmet r l c r t r rx v tx e l tipx 5 ringx 6 vtx 21 rsn 19 pbl 3764a/4
6 pbl 3764 a 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 ref parameter fig conditions min typ max unit battery feed characteristics constant loop current, i l 2500 0.92 i l i l 1.08 i l ma i l =, r dc1 , r dc2 n k ? r dc1 + r dc2 stand-by state loop current, i l ,v bat - 3 0.8 i l i l 1.2 i l ma i l =t a = 25 c tolerance range r l + 1800 loop current detector loop current detector threshold r d = 33 k ? on-hook to off-hook, i lthoff 0 c t amb 70 c 12.2 465/r d 15.7 ma -40 c t amb 85 c 11.3 465/r d 16.9 ma loop current detector threshold r d = 33k ? off-hook to on-hook, i lthon 0 c t amb 70 c 10.7 405/r d 13.8 ma -40 c t amb 85 c 9.8 405/r d 14.7 ma loop current detector r d =33k ? hysteresis, ? i lth 0 c t amb 70 c 1.0 60/r d 2.7 ma -40 c t amb 85 c 0.7 60/r d 2.9 ma ground key detector i ltipx and i ringx current difference, ? i lon ,0 c t amb 70 c 9 12 16 ma to trigger the ground key detector -40 c t amb 85 c 6.5 12 17.5 ma i ltipx and i lringx current difference, ? i loff ,0 c t amb 70 c 4711ma to return the triggered ground key -40 c t amb 85 c 2.5 7 12 ma detector to idle state hysteresis, ? i lgk | ? i lon - ? i loff | 0 c t amb 70 c 358ma -40 c t amb 85 c 059ma ring trip detector offset voltage, ? v dtr source resistance, r s = 0 ? -20 20 mv input bias current, i b i b = (i dt + i dr )/2 -500 -100 na input resistance unbalanced 1m ? balanced 3m ? input common mode range, v dt , v dr v bat +1 -2 v ring relay driver saturation voltage, v ol i ol = 25 ma 0.2 0.6 v off state leakage current, i lk v oh = 12 v 10 a digital inputs (c1, c2, e0, e1) input low voltage, v il 0 0.8 v input high voltage, v ih 2.0 v cc v input low current, i il v il = 0.4 v c1, c2 -400 a e0, e1 -100 a input high current, i ih v ih = 2.4 v 40 a detector output (det) output low voltage, v ol i ol = 2 ma 0.45 v output high voltage,v oh i oh = 100 a 2.7 v internal pull-up resistor 8 15 25 k ? delay time e0 to det transition high to low, t dhl 71 s transition low to high, t dlh 72 s
pbl 3764 a 7 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 ref parameter fig conditions min typ max unit power dissipation (v bat = -48v) p 1 open circuit state, c1, c2 = 0, 0 40 70 mw stand-by state, p 2 c1, c2 = 1, 1; on-hook 60 85 mw active state, c1, c2 = 0, 1 p 3 on-hook, r l = ? 200 300 mw p 4 off-hook, r l = 600 ? 1.1 1.4 w power supply currents v cc current, i cc open circuit state 1.7 2.8 ma v ee current, i ee c1, c2 = 0, 0 1.0 2.0 ma v bat current, i bat on-hook 0.5 1.2 ma v cc current, i cc stand-by state 2.1 3.5 ma v ee current, i ee c1, c2 = 1, 1 1.0 2.0 ma v bat current, i bat on-hook 0.9 1.6 ma v cc current, i cc active state 5.1 9.5 ma v ee current, i ee c1, c2 = 0,1 2.0 4.0 ma v bat current, i bat on-hook 3.3 5.2 ma power supply rejection ratios v cc to 2- or 4-wire port active state 43 45 db v ee to 2- or 4-wire port c1, c2 = 0,1 40 45 db v bat to 2- or 4-wire port 50hz < f< 3400hz, v n = 100mv rms 40 45 db v bat to 2- or 4-wire port v n = 2 v pp, note 11 40 45 db temperture guard junction threshold temperature, t jg 150 c thermal resistance 28-pin plcc , rjp28plcc junction to terminals 3, 6, 10, 17, 24 13 c/w connected together, note 12 22-pin pdip, rjp22dip 13,5 c/w notes 1. the overload level is specified at the two-wire port with the signal source at the four-wire receive port. 2. the two-wire impedance is programmable by selection of external component values according to: z trx = z t /|g 2-4 rsn | where: z trx = impedance between the tipx and ringx terminals z t = programming network between the vtx and rsn terminals g 2-4 = transmit gain, nominally = 1 srn = receive current gain, nominally = -1000 (current defined as positive when flowing into the receive summing node (rsn), and when flowing from tip to ring). 3. the overload level is specified at the four-wire transmit port, v tx , with the signal source at the two-wire port. note that the gain from the two-wire port to the four-wire transmit port is g 2-4 = 1. 4. fuse resistors r f impact the insertion loss as explained in the text, section transmission. the specified insertion loss is for r f = 0. 5. the specified insertion loss tolerance does not include errors caused by external components. 6. the two-wire idle noise is specified with the port terminated in 600 ? (r l ) and with the four-wire receive port grounded (e rx = 0; see figure 5). the four-wire idle noise at v tx is specified with the two-wire port terminated in 600 ? (r l ). the noise specification is with respect to a 600 ? impedance level at v tx . the four-wire receive port is grounded (e rx = 0). 7. the level is specified at the two-wire port. 8. the level is specified at the four-wire receive port and referenced to a 600 ? impedance level. 9. higher return loss values can be achieved by adding a reactive component to r t , the two-wire terminating impedance programming resistance, e.g., by dividing r t into two equal halves and connecting a capacitor from the common point to ground. for r t = 600 k ? this capacitor would be approximately 30 pf. increasing c hp to 0.033 f improves low-frequency return loss. 10. the -40 c - +85 c values are tested, while the 0 c - +70 c values are given as an indication. 11. psrr for v bat is reduced to min. 37 db when the plcc package is used. 12. junction to ambient thermal resistance will be dependent on external thermal resistance from v bat terminals to ambient.
8 pbl 3764 a 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 figure 8. pin configuration, 28-pin plcc and 22-pin dual-in-line package, top view. e0 det 10% 90% t dhl t dhl figure 7. detector output delay time. ringrly rsg e1 e0 vbat det dr vbat dt rd hpr hpt vtx vcc vbat bgnd ringx ringx tipx tipx c2 c1 rdc agnd rsn vbat 5 6 7 8 9 10 11 25 24 23 22 21 20 19 4 3 2 1 28 27 26 12 13 14 15 16 17 18 sense sense vee vbat hpr rd dr tipx ringx bgnd vcc ringrly vbat rsg 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 hpt vtx vee rsn agnd rdc c1 c2 det e0 e1 dt pbl 3764a/4 pbl 3764a/4
pbl 3764 a 9 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 pin description refer to figure 8. note: all pin number references in the text and figures refer to the 22-pin dip unless otherwise specified. dip plcc symbol description 1 ring sense ringx sense is internally connected to ringx. ringx sense is used during manufacturing, but require no connections in slic applications, i.e. leave open. 7 2 bgnd ground. should be tied together with agnd (pin 18). 3 vbat these pins marked vbat are used for heat sinking and internally connected to vbat 8 4 vcc +5v power supply 9 5 ringrly ring relay driver output. open collector. sinks 50 ma to gnd. 10 6 vbat battery supply voltage, -24v to -58v. negative with respect to gnd (pins 7, 18). 11 7 rsg the internal saturation guard programming resistor, r sg , connects from this terminal to v ee (pin 20). refer to section "battery feed" for detailed information. 12 8 e1 ttl compatible enable input. enables desired detector to be gated to the det (pin 14) output. refer to section "enable inputs" for detailed information. 13 9 e0 ttl compatible enable input. enables the det (pin 14) output when set to logic level low and disables the det output when set to logic level high. refer to section "enable inputs" for detailed information. 10 vbat these pins marked vbat are used for heat sinking and internally connected to vbat. 14 11 det detector output. inputs c1 (pin 16) and c2 (pin 15) together with enable inputs e0 (pin 13) and e1 (pin 12) select one of the three detectors to be connected to the det output. a logic low at the enabled det output indicates a triggered detector condition. the det output is open collector with internal pull-up resistor (approximately 15 k ? to v cc (pin 8)). 15 12 c2 c1 and c2 are ttl compatible inputs controlling the slic operating states. 16 13 c1 refer to section "control inputs" for details. 17 14 rdc constant current feed is programmed by two resistors connected in series from this pin to the receive summing node (rsn, pin 19). the resistor junction point is decoupled to gnd to isolate the ac signal components. 18 15 agnd ground. should be tied together with bgnd (pin 7). 19 16 rsn receive summing node. 1000 times the current (dc and ac) flowing into this pin equals the metallic (transversal) current flowing from ringx (pin 6) to tipx (pin 5). programming networks for constant current feed, two-wire impedance and receive gain connect to the receive summing node. 17 vbat these pins marked vbat are used for heat sinking and internally connected to vbat. 20 18 vee -5v power supply. 21 19 vtx transmit vf output. the ac voltage difference between tipx (pin 5) and ringx (pin 6), the ac metallic voltage, is reproduced as an unbalanced gnd referenced signal at v tx with a gain of one. the two-wire impedance programming network connects between v tx and rsn (pin 19). 22 20 hpt tip side of ac/dc separation capacitor c hp . other end of c hp capacitor connects to pin 1, hpr. 1 21 hpr ring side of ac/dc separation capacitor chp. other end of chp connects to pin 22, hpt. 2 22 rd off-hook detector programming resistor r d in parallel with filter capacitor c d connect from r d to v ee . 3 23 dt inputs to the ring trip comparator. with dr more positive than dt the detector output, det (pin 14), is at logic level low, indicating off-hook condition. the ring trip network connects to these two inputs. 24 vbat these pins marked vbat are used for heat sinking and internally connected to vbat. 4 25 dr inputs to the ring trip comparator. with dr more positive than dt the detecor output, det (pin 14), is at logic level low, indicating off-hook condition. the ring trip network connects to these two inputs. 26 tipx sense tipx sense is internally connected to tipx. tipx sense is used during manufacturing, but require no connections in slic applications, i.e. leave open. 27 tipx the tipx and ringx pins connect to the tip and ring leads of the two-wire interface via overvoltage 28 ringx protection components and ring relay (and optional test relays). }
10 pbl 3764 a 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 functional description and applications information four-wire to ttwo-wire gain from (1), (2) and (3) with e l = 0: v tr z t z l g 4-2 == - v rx z rx z t /1000 + 2r f + z l for applications where z t /1000 + 2r f is chosen to be equal to z l , the expression for g 4-2 simplifies to: z t 1 g 4-2 = - z rx 2 four-wire to four-wire gain from (1), (2) and (3) with e l = 0: v tx z t z l + 2r f g 4-4 == v rx z rx z t /1000 + 2r f + z l hybrid function the pbl 3764a/4 slic forms a particularly flexible and compact line interface when used with programmable codec/filters. the programmable codec/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. in addition, the transmit and receive gain may be adjusted. please, refer to the programmable codec/filter data sheets for design information. the hybrid function can also be implemented utilizing the uncommitted amplifier in conventional codec/filter combinations. please, refer to figure 10. via impedance z b a current proportional to v rx is injected into the summing node of the combination codec/filter amplifier. as can be seen from the expression for the four-wire to four-wire gain a voltage proportional to v rx is returned to v tx . this voltage is converted by r tx to a current flowing into the same summing node. these currents can be made to cancel by letting: v tx v rx += 0(e l = 0) r tx z b the four-wire to four-wire gain, g 4-4 , includes the required phase shift and thus the balance network z b can be calculated from: v rx z b = - r tx v tx z rx z t /1000 + 2r f + z l = r tx z t z l + 2r f example: calculate r b for the line interface shown in figure 12. 261 10 3 523 10 3 / 1000 + 2 40 + 600 r b = 20 10 3 523 10 3 600 + 2 40 = 17.66 k ? (i.e. standard value 17.8 k ? , 1%) if calculation of the z b formula above yields a balance network containing an inductor, an alternate method is recommended. contact ericsson microelectronics for assistance. longitudinal impedance a feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. thus longitudinal disturbances will appear as longitudinal currents and the tipx and ringx terminals will experience very = = = transmission general a simplified ac model of the transmission circuits is shown in figure 9. circuit analysis yields: v tr = v tx + i l 2r f (1) v tx v rx i l + = (2) z t z rx 1000 v tr = e l i l z l (3) where: v tx is a ground referenced unity gain version of the ac metallic voltage between the tipx and ringx terminals. v tr is the ac metallic voltage between tip and ring. e l is the line open circuit ac metallic voltage. i l is the ac metallic current. r f is a fuse resistor. z l is the line impedance. z t determines the slic tipx to ringx impedance. z rx controls four- to two-wire gain. v rx is the analog ground referenced receive signal. two-wire impedance to calculate z tr , the impedance presented to the two-wire line by the slic including the fuse resistors r f , let: v rx = 0. from (1) and (2): z tr = z t /1000 + 2r f thus with z tr and r f known: z t = 1000 (z tr 2r f ) example: calculate z t to make z tr = 900 ? in series with 2.16 f. r f = 40 ? 1 z t = 1000 (900 + 2 40) j 2.16 10 -6 which yields: z t = 820 k ? in series with 2.16 nf. it is always necessary to have a high ohmic resistor in parallel with the capacitor. this gives a dc-feedback loop for low frequency which ensures stability and reduces noise. two-wire to four-wire gain from (1) and (2) with v rx = 0: v tx z t /1000 g 2-4 == v tr z t /1000 + 2r f figure 9. simplified ac transmission circuit. pbl 3764a/4 + - 1 + - 21 vtx 19 rsn i l /1000 tipx 5 ringx 6 + - e l + - tip ring r f r f z tr z t v tx v rx z rx i l i l r hp + - z l v tr
pbl 3764 a 11 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 r lot = r lor = longitudinal resistance/wire v lo = longitudinal voltage at tipx, ringx i lo = longitudinal current. capacitors c tc and c rc the capacitors designated c tc and c rc in figure 12, connected between tipx and ground as well as between ringx and ground, are recommended as an addition to the overvoltage protection network. very fast transients, appearing on tip and ring, may pass by the diode and scr clamps in the overvoltage protection network, before these devices have had time to activate and could damage the slic. c tc and c rc short such very fast transients to ground. the recommended value for c tc and c rc is 2200 pf. higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. c tc and c rc contribute a metallic impedance of 1/( f c tc ) 1/( f c rc ), a tipx to ground impedance of 1/(2 f c tc ) and a ringx to ground impedance of 1/(2 f c rc ). ac - dc separation capacitor, c hp the high pass filter capacitor connected between terminals 21 and 20 provides the figure 10. hybrid function. small longitudinal voltage excursions, leaving metallic voltages well within the slic common mode range. this is accomplished by comparing the instantaneous two-wire longitudinal voltage to an internal longitudinal reference voltage, v loref . v loref = v bat = v t + v r 2 2 where v t and v r are tip and ring ground referenced voltages without any longitudinal component. as shown below, the slic appears as 20 ? per wire to longitudinal disturbances. it should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. refer to figure 11. circuit analysis yields: v lo = i lo r lo 1000 which reduces to r lot = r lor = v lo /i lo = 20 k ? /1000 = 20 ? where: r lo = 20 k ? separation between circuits sensing tip- ring dc conditions and circuits processing ac signals. a c hp value of 10 nf will position the low end frequency response 3db break point at 48 hz (f 3db ) according to f 3db = 1/(2 r hp c hp ) where r hp 330 k ? . battery feed the block diagram in figure 13 shows the pbl 3764a/4 battery feed system. for a tip to ring dc voltage v tr less than the saturation guard reference voltage v sgref , the slic emulates a constant- current feed characteristic. the constant current is independent of the actual battery voltage, v bat , connected to the slic. with the tip to ring dc voltage v tr exceeding v sgref , the feed characteristic changes to a nearly-constant voltage feed. this is to prevent the tip and ring drive amplifiers from distorting the ac signal as might have otherwise occurred due to insufficient voltage margin between v tr and v bat (pin 6). thus the slic automatically adjusts the tip to ring dc voltage v tr to the maximum safe value. with the slic in the stand-by state (c 1 , c 2 = 1,1) a resistive feed characteristic is enabled. the following text explains the three battery feed cases in more detail. case 1: slic in the active state; v tr < v sgref . in the active state c1 = 0 and c2 = 1. in this operating state tip to ring voltages v tr less than v sgref cause the block titled saturation guard (figure 13) to be disabled, i.e. its output is equal to zero. for this case circuit analysis yields: 2.5v r dc1 + r dc2 = 1000 i ldc where: i ldc = constant loop current (independant of the loop resistance r l ) r dc1 + r dc2 = the programming resistance which sets the constant loop current for tip to ring voltages v tr less than v sgref the pbl 3764a/4 thus emulates a constant current feed with the magnitude of the constant current set by the resistors, r dc1 and r dc2 . capacitor c dc at the r dc1 - r dc2 common point removes vf signals from the battery feed control loop. c dc is calculated according to: figure 11. longitudinal impedance. + - v t combination codec/filter r tx r fb z b z rx z t vtx rsn v rx pbl 3764a/4 19 21 + - 1 + v t + v r 2 + v lo i lo v loref i lo 1 2 / 1 2 / tip tipx 5 ringx 6 c hp r f 20 hpt 22 hpr 1 r hp / 2 r hp / 2 v t + v lo v r + v lo ring i lo / 1000 v lo r f 20 r lo 20k pbl 3764a/4
12 pbl 3764 a 1522 pbl 3764 uen rev.c ericsson microelectronics ab, april 2001 figure 13. battery feed (c1, c2 = 0,1 active state) figure 12. single-channel subscriber line interface with pbl 3764a/4 and combination codec/filter. u1 slic (subscriber line interface circuit) pbl 3764a/4 u2 combination codec/filter, e.g. tp3054 or programmable codec/ filter, e.g. slac u3 secondary protection (e.g. texas instruments tisp pbl2) k r relay, 2c contacts, 12v coil d 1 , d 2 diode, e.g. 1n4004 r f1 , r f2 line resistor, 40 ? , 1% r 1 , r 3 200 k ? , 5%, 1/4 w r 2 910 k ? , 5%, 1/4 w r 4 1.2 m ? , 5%, 1/4 w r b 17.8 k ? , 1%, 1/4 w r bat 5.1 ? , 5%, 1/4 w r d 39 k ? , 5%, 1/4 w r dc1 , r dc2 41.2 k ? , 5%, 1/4 w r fb 24.3 k ? , 1%, 1/4 w r rx 261 k ? , 1%, 1/4 w r sg short circuit r t 523 k ? , 1%, 1/4 w r tx 20 k ? , 1%, 1/4 w r rt 150 ? , 5%, 2w c bat 0.47 f, 20%, v bat +20 v c dc 1.5 f, 20%, 10v c hp 0.01 f, 20%, 100v c rt 0.39 f, 20%, 100v c tc , c rc 2200 pf, 20%, 100v c tisp 220nf, 20%, 100v note 1. the ground terminals of the secondary protection should be connected to the ground terminal of the slic, and to the common ground on the printed board assembly with a track as short and wide as possible, preferable a groundplane. +5v c v b tisp u 3 k1 k2 ag k1 k2 r rt r c rt r 2 -5v r d tip ring v bat k r to other line interfaces ptc ringing (v bat +90v ) rms c hp u 1 + - codec/filter r b r t r rx r tx u 2 r dc1 c dc c bat d 2 d 1 r bat -5v r sg c rc c tc +5v 3 r f1 r f2 1 hpr 2 rd 3 dt 4 dr 5 tipx 6 ringx 7 bgnd 8 vcc 9 ringrly 10 vbat 11 rsg hpt 22 vtx 21 vee 21 rsn 19 agnd 18 rdc 17 c1 16 c2 15 det 14 e0 13 e1 12 system control interface r fb r 1 -5v r dc2 r 4 v b note 1 + - 1 + - comp. tipx 5 ringx 6 pbl 3764a/4 rsg 11 saturation guard r dc2 v sg i ldc r l r sg bgnd v bat v sg ref c dc i ldc v tr 0.6 19 rsn 17 rdc v tr > v sg ref 1 v tr < v sg ref 0 v ee v tr - 2.5 v i ldc 1000 r dc1 v sg ref = 12.9 + 4.9 10 5 17300+r sg v sg = -7.7 - 2.9 10 5 17300+r sg
pbl 3764 a 13 1522 pbl 3764 uen rev.c ? ericsson microelectronics ab, april 2001 figure 17. tip-ring voltage as a function of loop resistance. v bat = -24 v, r sg = curve a: i const = 50 ma curve b: i const = 40 ma curve c: i const = 30 ma curve d: i const = 20 ma figure 15. tip-ring voltage as a function of loop resistance. v bat = -48 v, r sg = 4 k ? curve a: i const = 35 ma curve b: i const = 30 ma curve c: i const = 25 ma curve d: i const = 20 ma figure 14. loop current as a function of loop resistance. v bat = -48 v, r sg = 4 k ? curve a: r dc1 + r dc2 = 71,4 k ? curve b: r dc1 + r dc2 = 83,3 k ? curve c: r dc1 + r dc2 = 100 k ? curve d: r dc1 + r dc2 = 125 k ? figure 16. loop current as a function of loop resistance. v bat = -24 v, r sg = curve a: r dc1 + r dc2 = 50.0 k ? curve b: r dc1 + r dc2 = 62.5 k ? curve c: r dc1 + r dc2 = 83.3 k ? curve d: r dc1 + r dc2 = 125.0 k ? 15 20 25 30 35 i l 0 500 1000 1500 2000 r l loop resistance (ohm) loop current (ma) a b c d 0 10 20 30 40 v tr 0 500 1000 1500 2000 r l loop resistance (ohm) tip-ring voltage (v) a b c d 5 15 30 40 50 i l 0 500 1000 1500 2000 r l loop resistance (ohm) loop current (ma) a b c d 10 20 25 35 45 0 5 10 15 20 v tr 0 500 1000 1500 2000 r l loop resistance (ohm) tip-ring voltage (v) a c d b
14 pbl 3764 a 1522 pbl 3764 uen rev.c ? ericsson microelectronics ab, april 2001 figure 18. overload level, v tro as a function of v margin . max. v margin = maximum v bat - v trdc required for distortion free transmission of a given v tro . figure 20. power dissipation. curve a: conventional 2 x 400 ? resistive feed curve b: pbl 3764a/4, -48v, 30ma curvec: pbl 3764a/4, -28v, 30ma v bat = -48v curve a: i const = 20ma curve b: i const = 25ma curve c: i const = 30ma curve d: i const = 35ma figure 19. loop resistance at i l = 18ma as a function of v margin at open loop. v tro (v peak ) 2 1 0 5678 v margin (v) typ. max. 1900 2000 2100 2200 45 6 78 ri ll (ohm) at = 18ma ab d 9 v margin (v) c 0 1 2 3 0 500 1000 1500 2000 r l loop resistance (ohm) p (w) a b c
pbl 3764 a 15 1522 pbl 3764 uen rev.c ? ericsson microelectronics ab, april 2001 temperature guard a ring to ground short circuit fault condition as well as other improper operating conditions may cause excessive slic power dissipation. if junction temperature increases beyond 150 c, the temperature guard will trigger, causing the slic to be set to a high- impedance state. in this high-impedance state, power dissipation is reduced and the junction temperature will return to a safe value. once below 150 c, the slic is returned back to its normal operating mode and will remain in that state, assuming the fault condition has been removed. as long as the temperature guard is triggered, the loop current detector will stay in active state. pbl 3764a/4 long loop vf transmission to ensure that the maximum vf signal intended to be received/transmitted by the slic will not experience limiting in the tipx (pin 27) /ringx (pin 28) drive amplifiers at long loops, the saturation guard must be correctly progammed. the section, battery feed, case 2 describes how to calculate a value for the saturation guard programming resistor r sg . loop monitoring functions the loop current, ground key and ring trip detectors report their status through a common output, det (pin 11). the detector to be connected to det is selected via the four bit wide control interface c1, c2, e0, e1. please refer to section control inputs for a description of the control interface. loop current detector the loop current value at which the loop current detector changes state is programmable by selecting the value of resistor r d . r d connects between pins rd (22) and vee (18). figure 21 shows a block diagram of the loop current detector. the two-wire interface produces a current flowing out of pin rd (22): i rd = i ltipx - i lringx /600 = i l /300 where i ltipx and i lringx are currents flowing into the tipx and ringx terminals and i l is the loop current. the voltage generated by i rd across the programming resistor r d is compared to an internal reference by a comparator with hysteresis. the hyste- resis causes the on-hook to off-hook loop current detect threshold, i lthoff , to be slightly larger than the off-hook to on-hook detector threshold, i lthon . a logic low it is possible to increase the maximum loop resistance at minimum allowable loop current by reducing the voltage margin v margin = |v bat | - v trmax from the 8v suggested above. doing so will, however, reduce the overload level from 3.1 v peak as shown in figure 18. figure 19 shows the typical maximum loop resistance at 18ma as a function of the voltage margin for several values of programmed constant-current feed and v bat = -48 v. case 3: slic in the stand-by state. in the stand-by state c1 = 1 and c2 = 1. with the slic operating in the stand-by, power saving, state the tip and ring drive amplifiers are disconnected and a resistive battery feed is engaged. the loop current can be calculated from: v bat - 3 v i ldc r l + 1800 ? where: i ldc = loop current r l = loop resistance v bat = battery supply voltage pbl 3764a/4 power dissipation the short circuit slic power dissipation p shtot is p shtot = i lsh ( v bat - i lsh 2r f ) + p 3 where: v bat is the battery voltage connected to the slic at pin 10, r f is the line resistance, 40 ? 2.5v i lsh = 1000 is the constant loop current. r dc1 + r dc2 p 3 is on-hook, active state power dissipation (typ. 200 mw @ v bat = -48 v). note that a short circuited loop is not a normal operating condition. the terminating equipment will add some dc resistance (200 ? to 300 ? ) even if the wire resistance is near 0 ? . figure 20 compares line feed power dissipation as a function of loop resistance for three cases: feed resistor dissipation for a conventional 2 400 ? resistive feed, pbl 3764a/4 with 30 ma constant current feed and v bat =-48 v and pbl 3764a/4 with 30 ma constant current feed and v bat = -28 v. the diagram illustrates the significant pbl 3764a/4 power saving compared to the 2 400 ? feed. -17300 -17300 11 c dc = t ( + ), where t = 30ms r dc1 r dc2 note that r dc1 = r dc2 yields minimum c dc value. case 2: slic in the active state v tr > v sgref in the active state c1 = 0 and c2 = 1. the saturation guard reference voltage is user programmable according to: 4.9 10 5 v sgref = 12.9.+ (17300) + r sg where: r sg = saturation guard reference programming resistor in ? . v sgref = saturation guard reference voltage in volts. once the dc metallic voltage, v tr , exceeds the saturation guard reference voltage, v sgref the saturation guard becomes active and the following expression describes the battery feed characteristic: 16.7 + 4.9 10 5 /(r sg + 17300) v tr = r l r l + (r dc1 + r dc2 ) / 653 where r sg , r l and v tr have the same meaning as described above. at open loop, i.e. r l , the saturation guard limits the tip-ring voltage to: v tr = 16.7 + (4.9 10 5 ) / (r sg + 17300) figures 14 through 17 illustrate the pbl 3764a/4 loop feed with v bat = -48v and v bat = -24v. for applications where the tip-to-ring dc voltage, v tr , approaches the v bat value. r sg should be adjusted as follows: as a general guideline, adjust r sg in the v tr expression above to yield v trmax |v bat | - 8v at maximum loop resistance. maintaining v tr below this limit ensures vf signal transmission through the slic without clipping. r sg can be calculated from: 4.9 10 5 r sg = ( | v bat | - v margin ) [1+(r dc +r dc2 )/653r l ] -16.7v where: v margin = 8v to allow a maximum overload level, v tro , of 3.1v. if transmission is required at open loop, i.e., r l , the above expression simplifies to: 4.9 10 5 r sg = |v bat | - v margin - 16.7v in applications where the longest possible two-wire loop length is important,
16 pbl 3764 a 1522 pbl 3764 uen rev.c ? ericsson microelectronics ab, april 2001 monitored by the ring trip comparator input dt via the network r 3 , r 4 and c rt . input dr is set to a reference voltage by resistors r 1 and r 2 . with the line on-hook (no dc current) dt is more positive than dr and the det output will report logic level high, i.e. the detector is not tripped. when the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor r rt and will cause input dt to become more negative than input dr. this changes output det to logic level low, i.e. tripped detector condition. the system controller (or line card processor) responds by de- energizing the ring relay, i.e. ring trip complete filtering of the 20 hz ac component at terminal dt is not necessary. a toggling det output can be figure 21. loop current and ground key detectors. figure 22. ring trip network. examined by a software routine to determine the duty cycle. when the det output is at logic level low for more than half the time, off-hook condition is indicated. relay driver the pbl 3764a/4 slic incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 ma. the drive transistor emitter is connected to bgnd. an external inductive kick-back clamp diode must be employed to protect the drive transistor. control inputs the pbl 3764a/4 slic has two ttl compatible control inputs, c1 and c2. a decoder in the slic interprets the results at the det (pin 11) output when the loop current exceeds the on-hook to off-hook detect threshold, i lthoff : the programming resistor r d value can be calculated for a desired i lthoff from r d = 465/i lthoff . r d is in k ? for i lthoff in ma.the off-hook to on-hook threshold, i lthon , for a known r d is i lthon = 405/r d . a logic high results at the det output when the loop current is less than i lthon . the c d filter capacitor is calculated according to c d = t/r d with time constant t = 0.5 ms. note that c d may not be required if det is software filtered. ground key detector the ground key detector circuit examines the difference in tipx and ringx currents. should the current difference exceed the threshold value, ? i lon , the detector is triggered. as the current difference decreases the detector is reset at current threshold ? i loff . ? i lon > ? i loff , i.e. the detector has hysteresis. the triggered detector results in a logic low at the det (pin 11) output, assuming the ground key detector has been selected via the four-bit control input (c1, c2, e0, e1). for ? i lon and ? i loff numerical values please refer to table electrical character- istics . ring trip detector ring trip detection is accomplished by connecting an external network to a comparator in the slic with inputs dt (pin 23) and dr (pin 25). the ringing source can be balanced or unbalanced superimposed on v bat . the unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. a ring relay driven by the slic ring relay driver connects the ringing source to tip and ring. the ring trip function is based on a polarity change at the comparator input when the line goes off-hook. in the on- hook state no dc current flows through the loop and the voltage at comparator input dt is more positive than the voltage at input dr. when the line goes off-hook, while the ring relay is energized, dc current flows and the comparator input voltage reverses polarity. figure 22 is an example of a ring trip detection network. this network is applicable, when the ring voltage superimposed on v bat is injected on the ring lead of the two-wire port. the dc voltage across sense resistor r rt is pbl 3764a/4 + - 2-wire interface input decoder mux tipx 5 ringx 6 16 c 1 15 c 2 14 det 13 e 0 r d c d - 5v v cc 20 v ee 2 r d 1.25v i ltipx i lringx 2 300 i ltipx - i lringx 12 e 1 ground key det. + - pbl 3764a/4 ring tip k r e rg r 4 c rt r rt v bat dt 3 dr 4 r 3 r 2 r 1
pbl 3764 a 17 1522 pbl 3764 uen rev.c ? ericsson microelectronics ab, april 2001 note 1 for operating states 9-16 active detectors are as for operating states 1-8. the det output is, however, disabled and remains at logic level high regardless of detector status. note 2 for operating states 1- 8 the det output is enabled and will report the status of the active detector. logic level low indicates a triggered detector. state e0 e1 c1 c2 slic operating state active detector det output 1 0000 open circuit no active detector logic level high 2 0001 active ground key detector ground key status 3 0010 ringing ring trip detector ring trip status 4 0011 stand-by ground key detector ground key status 5 0100 open circuit no active detector logic level high 6 0101 active loop current detector loop current status 7 0110 ringing ring trip detector ring trip status 8 0111 stand-by loop current detector loop current status 9 1000 open circuit 10 1001 active 11 1010 ringing 12 1011 stand-by note 1 logic level high 13 1100 open circuit note 1 14 1101 active 15 1110 ringing 16 1111 stand-by table 1. slic operating states in the stand-by state the line drive amplifiers are disconnected. the loop feed is converted to resistive form according to: v bat -3 v i l r l + 1800 ? where: i l = loop current (a) v bat = battery supply voltage (v) r l = loop resistance ( ? ) the standby short circuit loop current (i lsh ) for v bat = -28v is then limited to: i lsh 13.9 ma. both the loop current and ground key detectors are activated in this operating state. inputs e0 and e1 control the selection of one of these detectors to be gated to the det output. please, refer to section enable inputs . table 1 summarizes the above description of the control inputs. enable inputs (e0, e1) two ttl compatible enable inputs e0 (pin 13) and e1 (pin 12) control the function of the det (pin 14) output. e0, when set to logic level low, enables signal transmission is inhibited. control input conditions and sets up the commanded operating state. open circuit state (c1, c2 = 0, 0) in the open circuit state the tipx and ringx line drive amplifiers as well as other circuit blocks are powered down. this causes the slic to present a high impedance to the line. power dissipation is at a minimum. no detectors are active. ringing state (c1, c2 = 1, 0) the ring relay driver and the ring trip detector are activated. tipx and ringx are in the high impedance state and active state (c1, c2 = 0, 1) tipx is the terminal closest to ground and sources loop current while ringx is the more negative terminal and sinks loop current. vf signal transmission is normal. both the loop current and the ground key detectors are activated. inputs e0 and e1 control the selection of one of these detectors to be gated to the det output. please, refer to section enable inputs. stand-by state (c1, c2 = 1, 1) the det output, which is a collector output with internal pull-up resistor (approx. 15 k ? ). a det output at logic level low indicates triggered detector condition (loop current above threshold current, ground key depressed or telephone off-hook during the ringing cycle). a det output at logic level high indicates a non triggered detector condition. e0, when set to logic level high, disables the det output; i.e. it appears as a resistor connected to v cc . e1, when set to logic level low, gates the ground key detector to the det output. e1, when set to logic level high, gates the loop detector to the det output. table 1 summarizes the above description of the enable inputs. overvoltage protection the pbl 3764/a4 slic must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. refer to maximum ratings, tipx and ringx terminals, for maximum allowable continuous and transient voltages that may be applied to the slic. the circuit shown in figure 12 utilizes series resistors together with a programmable overvoltage protector (e g texas instrument tisp pbl2), serving as a secondary protection. the protection network in figure 12 is designed to meet requirements in itu-t k20, table 1. the tisp pbl2 is a dual forward- conducting buffered p-gate overvoltage protector. the protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage,v bat ). as the protection voltage will track the negative supply voltage the overvoltage stress on the slic is minimized. positive overvoltages are clamped to ground by an internal diode. negative overvoltages are initially clamped close to the slic negative supply rail voltage. if sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition, clamping the overvoltage close to ground. a gate decoupling capacitor, c tisp is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. without the capacitor even the low inductance in the
power-up sequence the voltage at pin vbat sets the substrate voltage, which must at all times be kept more negative than the voltage at any other pin to prevent possible latch-up. the optimal power-up sequency is ground and v bat , then other supplies and signal leads. however, v cc may be connected before v bat and if the v bat supply voltage shuld be absent, a diode with a 2a current rating connected with its cathode to vee and anode to vbat ensures the presence of the most-negative supply voltage at the vbat pin. the vbat pin should not be applied at a faster rate than corresponds to the time constant formed by a 5.1 ? resistor in series with the vbat pin and a 0.47 f capacitor from the vbat pin to ground. this rc network may be shared by several slics. information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson microelectronics ab. these products are sold only according to ericsson microelectronics general conditions of sale, unless otherwise confirmed in writing. specifications subject to change without notice. this product is an original ericsson product protected by us, european and other patents. track to the v bat supply will limit the current and delay the activation of the thyristor clamp. the fuse resistors r f serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. ericsson microelectronics ab offers a series of thick film resistors networks (e g pbr 51- series and pbr 53-series) designed for this application. also devices with a built in resetable fuse function is offered (e g pbr 52-series) including positive temperature coefficient (ptc) resistors, working as resetable fuses, in series with thick film resistors. note that it is important to always use ptc s in series with resistors not sensitive to temperature, as the ptc will act as a capacitance for fast transients and therefore the ability to protect the slic will be reduced. if there is a risk for overvoltages on the v bat terminal on the slic, then this terminal should also be protected. printed circuit board layout care in pcb lay-out is essential for proper pbl 3764a/4 function. the components connecting to the rsn pin (16) should be in close proximity of that pin such that no interference is injected into the rsn terminal. ground plane surrounding the rsn pin is advisable. the two ground pins agnd and bgnd should be connected together on the pcb at the device location. ordering information package temp. range part no. pdip tube -40 to 85 c pbl3764/4ns plcc tube -40 to 85 c pbl3764/4qns plcc tube -40 to 85 c pbl3764/6qns plcc tape & reel -40 to 85 c pbl3764/4qnt plcc tape & reel -40 to 85 c pbl3764/6qnt ericsson microelectronics se-164 81 kista, sweden telephone: +46 8 757 50 00 internet: www.ericsson.se/microelectronics for local sales contacts, please refer to our website or call: int + 46 8 757 47 00, fax: +46 8 757 47 76 data sheet 1522-pbl 3764+ uen rev. c ? ericsson microelectronics ab, april 2001

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