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nhd - 2.7 - 12864wdw 3 graphic oled display module nhd - newhaven display 2.7 - 2.7 diagonal size 12864 - 128 x 64 pixel resolution wd - model w - emitting color: white 3 - +3 .3 v power supply newhaven display international, inc. 2661 galvin ct. elgin il, 60124 ph: 847 - 844 - 8795 fax: 847 - 844 - 8796 www.newhavendisplay.com nhtech@newhavendisplay.com nhsales@newhavendisplay.com
[ 2 ] document revision history revision date description changed by - 6/9 / 2017 initial release ml 1 7/25/2017 upda te storage temperature range ml functions and features ? 128 x 64 pixel resolution ? built - in ssd1322 controller ? parallel or s erial mpu interface ? single, low voltage p ower s upply ? power options via on - board jumpers ? rohs compliant
1 2 3 4 5 6 a b c d b c d 1 2 3 4 5 6 mechanical drawing a [3] the informaton contained herein is the exclusive property of newhaven display internatonal, inc. and shall not be copied, reproduced, and/or disclosed in any format without permission. nhd-2.7-12864wdw3 06/09/17 date unit part number: mm gen. tol. 0.3 rev descripton date notes: 1. display color: white 2. interface: 8-bit 68xx/80xx parallel, 3-/4-wire spi 3. controller: ssd1322 74.20 77 82 42.50 47.50 16.87 2.50 p2.54*19 = 48.26 4 - 2.50 61.41 (a.a.) 63.41 (v.a.) 30.69 (a.a.) 32.69 (v.a.) 20-?1.0 2.50 6 (max) 1 55.40 1 20 active ar ea 2.7" 128 x 64 pixels s e g m e n t 1 1 2 , 1 1 3 ( c o l u mn 1 2 8 ) c o m m o n 6 3 ( r o w 1 ) c o m m o n 0 ( r o w 6 4 ) s e g m e n t 3 6 6 , 3 67 ( c o l u m n 1 ) c o m m o n 1 2 7 ( r o w 1 ) c o m m o n 6 4 ( r o w 6 4 ) driver ic memory mapping ( 256 x 64 in 480 x 12 8 ) (0,28) (0,0) (0,92) 0.45 0.48 0.45 0.48 2 - initial release 6/9/17 proprietary detail a detail a
[ 4 ] interface description parallel interface: pin no. symbol external connection function description 1 v ss power supply ground 2 vdd power supply su pply voltage for oled module 3 n . c . ( bc _ vdd ) - no connect by default. can be configured to provide independent supply voltage (2.8 v C 12v dc) for boost converter. (refer to on - board jumper options section below) 4 d/c mpu data/command select signal, d/c=0: command, d/c=1: data 5 r/w or /wr mpu 6800 - interface: read/write select sign al, r/w=1: read, r/w=0: write 8080 - interface: active low write signal 6 e or /rd mpu 6800 - interface: operation enable signal, falling edge triggered 8080 - interface: active low read signal 7 - 14 db0 C db7 mpu 8 - bi t b i - directional data b us 15 n . c . (vcc) - no connect by default . can be configured for external vcc (+15v) . (refer to on - board jumper options table below) 16 /res mpu active low reset signal 17 /cs mpu active low chip select signal 18 /shdn (n.c.) mpu active low shutdown control pin for boost converter ( pulled high via on - board 15k? resistor) can be made a no connect by removing resistor r1. 19 bs1 mpu mpu interface select signal 20 bs0 mpu mpu interface select signal serial interface: pin no. symbol external connection function description 1 v ss power supply ground 2 vdd power supply supply voltage for oled module 3 n . c . (bc _vdd) - no connect by default. can be configured to provide independent supply voltage (2.8 v C 12v dc) for boost converter. (refer to on - board jumper options table below) 4 d/c mpu data/command select signal, d/c=0: command, d/c=1: data (t ie low for 3 - wire serial interface) 5 - 6 vss power supply ground 7 sclk mpu serial clock signal 8 sdin mpu serial data input signal 9 n . c . - no connect 10 - 14 vss power supply ground 15 n . c . (vcc) - no connect by default. can be configured for external vcc (+15v) . (refer to on - board jumper options section below) 16 /res mpu active low reset signal 17 /cs mpu active low chip select signal 18 /shdn (n.c.) mpu active low shutdown control pin for boost converter ( pulled high via on - board 15k? resistor) can be made a no connect by removing resistor r1. 19 bs1 mpu mpu interface select signal 20 bs0 mpu mpu interface select signal
[ 5 ] interface selection mpu interface pin selections pin name 6800 parallel 8 - bit interface 8080 parallel 8 - bit interface 3 - wire serial interface 4 - wire serial interface bs1 1 1 0 0 bs0 1 0 1 0 mpu interface pin assignment summery bus interface data/command interface control signals d7 d6 d5 d4 d3 d2 d1 d0 e r/w /cs d/c /res 8 - bit 6800 d[7:0] e r/w /cs d/c /res 8 - bit 8080 d[7:0] /rd /wr /cs d/c /res 3 - wire spi tie low nc sdin sclk tie low /cs tie low /res 4 - wire spi tie low nc sdin sclk tie low /cs d/c /res on - board jumper options default jumper setting r4 r5 r7 description close open open (d efault) oled controller and boost converter + oled panel are powered from vdd (pin #2) . this allows the full module to be powered by a single low - voltage suppl y. jumper option #1 - independent supply voltage for boost converter (bc_vdd) r4 r5 r7 description open close open boost converter + oled panel are powered f rom bc_vdd (pin #3) . oled controller is still powered from vdd (pin #2) . this allows for increased efficiency through the boost converter, by allowing a supply voltage up to +12v at its input, bc_vdd (pin #3). jumper option #2 C external supply voltage for oled panel (vcc) r4 r5 r7 description open open close oled panel is powered from vcc (pin #15) C boost converter is not used. oled controller is still powered from vdd (pin #2). this allows for maximum module efficiency, and drastically reduced total current consumption. default jumper setting jumper option #1 jumper option #2 for detailed electrical information on each j umper o ption, please see the electrical characteristics table below.
[ 6 ] e lectrical characteristics values for current shown below are based on the recommended initialization provided on page 12 . item symbol condition min. typ. max. unit operating temperature range t op absolute max - 40 - +85 ? c storage temperature range t st absolute max - 40 - +85 ? c default jumper setting supply voltage for module vdd - 2.8 3.3 3.5 v supply current for module idd vdd=3.3v, 50% on - 215 235 ma vdd=3.3v, 100% on - 345 375 ma jumper option #1 supply voltage for module vdd - 2.8 3.3 3.5 v supply voltage for boost converter bc_vdd - 2.8 - 12 v supply current for module idd vdd=3.3v - 190 305 a supply current for boost converter idd bc bc_vdd=5.0v, 50% on - 135 150 ma bc_vdd=5.0v, 100 % on - 200 215 ma bc_vdd=12 .0v, 50% on - 60 70 ma bc_vdd=12.0v, 100 % on - 80 90 ma jumper option #2 supply voltage for module vdd - 2.8 3.3 3.5 v supply voltage for oled panel vcc - 14.5 15 15.5 v supply current for module idd vdd=3.3v - 180 300 a supply current for oled panel icc vcc=15v, 50% on - 45 50 ma vcc=15v, 100% on - 60 70 ma sleep mode current idd sleep - - 25 120 a h level input v ih - 0.8*vdd - vdd v l level input v il - vss - 0.2*vdd v h level output v oh - 0.9*vdd - vdd v l level output v ol - vss - 0.1*vdd v note: the electrical characteristics shown above for jumper option #1 and jumper option #2 apply only when the on - board jumpers are configured accordingly. by default, only default jumper setting supply voltage and current (in bold) nee d to be considered. for details, see on - boa rd jumper options section on previous page. optical characteristics values for brightness shown below are based on the recommended initialization provided on page 12 . item symbol condition min. typ. max. unit optimal viewing angles top ? y+ - - 85 - ? bottom ? y - - 85 - ? left x - - 85 - ? right x+ - 85 - ? contrast ratio c r - > 1 0 ,0 00:1 - - - response time rise t r - - 15 - n s fall t f - - 15 - n s brightness l br 50% on (checkerboard) 60 80 130 cd/m 2 lifetime - t a =25c, l br =80 cd/m 2 30 ,000 - - h rs - t a =25c, l br =60 cd/m 2 50 ,000 - - hrs note : lifetime at typ ical temperature is based on accelerated high - temperature operation. lifetime is tested at average 50% pixels on and is rated as hours until half - brightness . to extend the life of the display, lower values may be used fo r the contrast setting registers C see below table of commands for details. controller information built - in ssd1322 controller. for details, view full datasheet at http://www.newhavendisplay.com/app_notes/ssd132 2.pdf
[ 7 ] table of commands instruction code description reset value d/c hex db7 db6 db5 db4 db3 db2 db1 db0 enable grayscale table 0 00 0 0 0 0 0 0 0 0 enable the grayscale table settings. (see command 0xb8) set column address 0 1 1 15 a[6:0] b[6:0] 0 * * 0 a6 b6 0 a5 b5 1 a4 b4 0 a3 b3 1 a2 b2 0 a1 b1 1 a0 b0 set column start and end address a[6:0]: column start address. range: 0 - 119d b[6:0]: column end address. range: 0 - 119d 0 119d write ram command 0 5c 0 1 0 1 1 1 0 0 enable mcu to write data into ram read ram command 0 5d 0 1 0 1 1 1 0 1 enable mcu to read data from ram set row address 0 1 1 75 a[6:0] b[6:0] 0 * * 1 a6 b6 1 a5 b5 1 a4 b4 0 a3 b3 1 a2 b2 0 a1 b1 1 a0 b0 set row start and end address a[6:0]: row start address. range: 0 - 127d b[6:0]: row end address. range: 0 - 127d 0 127d set re - map 0 1 1 a0 a[5:0] b[4] 1 0 * 0 0 * 1 a5 0 0 a4 b4 0 0 0 0 a2 0 0 a1 0 0 a0 1 a[0] = 0; horizontal address increment a[0] = 1; vertical address increment a[1] = 0; disable column address remap a[1] = 1; enable column address remap a[2] = 0; disable nibble remap a[2] = 1; enable nibble remap a[4] = 0; scan from com0 to com[n - 1] a[4] = 1; scan from com[n - 1] to com0 a[5] = 0; disable com split odd/even a[5] = 1; enable com split odd/even b[4] = 0; disable dual com mode b[4] = 1; enable dual com mode note: a[5] must be 0 if b[4] is 1. 0 0 0 0 0 0 set display start line 0 1 a1 a[6:0] 1 * 0 a6 1 a5 0 a4 0 a3 0 a2 0 a1 1 a0 set display ram display start line register from 0 - 127. 0 set display offset 0 1 a2 a[6:0] 1 * 0 a6 1 a5 0 a4 0 a3 0 a2 1 a1 0 a0 set vertical shift by com from 0~127. 0 display mode 0 a4~ a7 1 0 1 0 0 x2 x1 x0 0xa4 = entire display off 0xa5 = entire display on, all pixels grayscale level 15 0xa6 = normal display 0xa7 = inverse display 0xa6 enable partial display 0 1 1 a8 a[6:0] b[6:0] 1 0 0 0 a6 b6 1 a5 b5 0 a4 b4 1 a3 b3 0 a2 b2 0 a1 b1 0 a0 b0 turns on partial mode. a[6:0] = address of start row b[6:0] = address of end row (b[6:0] > a[6:0]) exit partial display 0 a9 1 0 1 0 1 0 0 1 exit partial display mode function selection 0 1 ab a[0] 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 a0 a[0] = 0; external vdd a[0] = 1; internal vdd regulator 1
[ 8 ] set sleep mode on/off 0 ae~af 1 0 1 0 1 1 1 x0 0xae = sleep mode on (display off) 0xaf = sleep mode off (display on) set phase length 0 1 b1 a[7:0] 1 a7 0 a6 1 a5 1 a4 0 a3 0 a2 0 a1 1 a0 a[3:0] = p1. phase 1 period of 5 - 31 dclk clocks a[7:4] = p2. phase 2 period of 3 - 15 dclk clocks 9 7 set display clock divide ratio / oscillator frequency 0 1 b3 a[7:0] 1 a7 0 a6 1 a5 1 a4 0 a3 0 a2 1 a1 1 a0 a[3:0] = 0000; divide by 1 a[3:0] = 0001; divide by 2 a[3:0] = 0010; divide by 4 a[3:0] = 0011; divide by 8 a[3:0] = 0100; divide by 16 a[3:0] = 0101; divide by 32 a[3:0] = 0110; divide by 64 a[3:0] = 0111; divide by 128 a[3:0] = 1000; divide by 256 a[3:0] = 1001; divide by 512 a[3:0] = 1010; divide by 1024 a[3:0] >= 1011; invalid a[7:4] = set the oscillator frequency. frequency increases with the value of a[7:4]. range 0000b~1111b. 0 1100b vsl / display enhancement 0 1 1 b4 a[1:0] b[7:3] 1 1 b7 0 0 b6 1 1 b5 1 0 b4 0 0 b3 1 0 1 0 a1 0 0 a0 1 a[1:0] = 00b; enable external vsl a[1:0] = 10b; internal vsl b[7:3] = 11111b; enhanced low gs display quality b[7:3] = 10110b; normal 10b 10110b set gpio 0 1 b5 a[3:0] 1 * 0 * 1 * 1 * 0 a3 1 a2 0 a1 1 a0 a[1:0] = 00; gpio0 input disabled a[1:0] = 01; gpio0 input enabled a[1:0] = 10; gpio0 output low a[1:0] = 11; gpio0 output high a[3:2] = 00; gpio1 input disabled a[3:2] = 01; gpio1 input enabled a[3:2] = 10; gpio1 output low a[3:2] = 11; gpio1 output high 10b 10b set second pre - charge period 0 1 b6 a[3:0] 1 * 0 * 1 * 1 * 0 a3 1 a2 1 a1 0 a0 sets the second precharge period a[3:0] = dclks 1000b set grayscale table 0 1 1 1 1 1 1 1 b8 a1[7:0] a2[7:0] . . . a14[7:0] a15[7:0] 1 a1 7 a2 7 . . . a14 7 a15 7 0 a1 6 a2 6 . . . a14 6 a15 6 1 a1 5 a2 5 . . . a14 5 a15 5 1 a1 4 a2 4 . . . a14 4 a15 4 1 a1 3 a2 3 . . . a14 3 a15 3 0 a1 2 a2 2 . . . a14 2 a15 2 0 a1 1 a2 1 . . . a14 1 a15 1 0 a1 0 a2 0 . . . a14 0 a15 0 sets the gray scale pulse width in units of dclk. range 0 - 180d. a 1 [ 7 :0] = gamma setting for gs1 a 2 [ 7 :0] = gamma setting for gs2 . . . a 14 [ 7 :0] = gamma setting for gs14 a 15 [ 7 :0] = gamma setting for gs15 note: 0 < gs1 < gs2 < gs3 < gs14 < gs15 the setting must be followed by command 0x00.
[ 9 ] select default linear gray scale table 0 b9 1 0 1 1 1 0 0 1 sets linear grayscale table gs0 pulse width = 0 gs0 pulse width = 0 gs0 pulse width = 8 gs0 pulse width = 16 . . . gs0 pulse width = 104 gs0 pulse width = 112 set pre - charge voltage 0 1 bb a[4:0] 1 * 0 * 1 * 1 a4 1 a3 0 a2 1 a1 1 a0 set precharge voltage level. a[4:0] = 0x00; 0.20*vcc . . a[4:0] = 0x3e; 0.60*vcc 0x17 set vcomh voltage 0 1 be a[3:0] 1 * 0 * 1 * 1 * 1 a3 1 a2 1 a1 0 a0 sets the vcomh voltage level a[3:0] = 0x00; 0.72*vcc . . a[3:0] = 0x04; 0.8*vcc . . a[3:0] = 0x07; 0.86*vcc 0x04 set contrast control 0 1 c1 a[7:0] 1 a7 1 a6 0 a5 0 a4 0 a3 0 a2 0 a1 1 a0 double byte command to select 1 out of 256 contrast steps. contrast increases as the value increases. 0x7f master contrast control 0 1 c7 a[3:0] 1 * 1 * 0 * 0 * 0 a3 1 a2 1 a1 1 a0 a[3:0] = 0x00; reduce output for all colors to 1/16 a[3:0] = 0x01; reduce output for all colors to 2/16 . . a[3:0] = 0x0e; reduce output for all colors to 15/16 a[3:0] = 0x0f; no change 0x0f set multiplex ratio 0 1 ca a[6:0] 1 * 1 a6 0 a5 0 a4 1 a3 0 a2 1 a1 0 a0 set mux ratio to n+1 mux n=a[6:0]; from 16mux to 128mux (0 to 14 are invalid) 127d set command lock 0 1 fd a[2] 1 0 1 0 1 0 1 1 1 0 1 a2 0 1 1 0 a[2] = 0; unlock oled to enable commands a[2] = 1; lock oled from entering commands 0x12 for detailed instruction information, view full ssd1322 datasheet here (pages 32 - 47) : http://www.newhavendisplay.com/app_notes/ssd1322.pdf
[ 10 ] mpu interface 6800 - mpu parallel interface the parallel interface consists of 8 bi - directional data pins, r/w, d/c, e, and /cs. a low on r/w indicates write operation, and high on r/w indicates read operation. a low on d/c indicates command read or write, and high on d/c indicates data read or write. the e input serves as data latch signal, while /cs is low. data is latched at the falling edge of e signal. function e r/w /cs d/c write command 0 0 0 read status 1 0 0 write data 0 0 1 read data 1 0 1 8080 - mpu parallel interface the parallel interface consists of 8 bi - directional data pins, /rd, /wr, d/c, and /cs. a low on d/c indicates command read or write, and high on d/c indicates data read or write. a rising edge of /rs input serves as a data read latch signal while /cs is low. a rising edge of /wr input serves as a data/command write latch signal while /cs is low. function /rd /wr /cs d/c write command 1 0 0 read status 1 0 0 write data 1 0 1 read data 1 0 1 s erial interface (4 - wire) the 4 - wire serial interface consists of serial c lock ( sclk ), s erial d ata ( sdin ) , data/command ( d/c ) , and chip select ( /cs ). d0 acts as scl k and d1 acts as sdin. d2 must be left as a no connect d3~d7, e, and r/w should be connected to gnd. function /rd /wr /cs d/c d0 write command tie low tie low 0 0 write data tie low tie low 0 1 sdin is shifted into an 8 - bit shift register on every rising edge of sclk in the order of d7, d6,d0. d/c is sampled on every eighth clock and the data byte in the shift register is written to the gd d ram or command register in the same clock. note: read functionality is not available in serial mode.
[ 11 ] serial interface (3 - wire) the 3 - wire serial interface consist s of serial clock (sclk), serial d ata in ( sdin ) , and chip select ( /cs ) . d0 acts as sclk and d1 acts as sdin. d2 must be left as a no connect. d3~d7, e, r/w , and d/c should be connected to ground . function /rd /wr /cs d/c d0 write command tie low tie low 0 tie low write data tie low tie low 0 tie low sdin is shifted into an 9 - bit shift register on every rising edge of s clk in the order of d/c, d7, d6, d0. d/c (first bit of the sequential data) will determine if the following data byte is written to the display data ram (d/c = 1) or the command register (d/c = 0). note: read functionality is not available in serial mode. for d etailed timing information for each interface mode, view full ssd1322 datasheet here (pages 50 - 54) : http://www.newhavendisplay.com/app_notes/ssd1322.pdf recommended initialization void nhd12864wdy3_init( void ){ digitalwrite(res, low ); //pull /res (pin #16) low delayus( 200 ); //keep /res low for minimum 200s digitalwrite(res, high ); //pull /res high delayus( 200 ); //wait minimum 200s before sending commands writecommand( 0x ae ); //display off writecommand( 0x b3 ); //set clk div. & osc freq. writedata( 0x 91 ); writecommand( 0 x ca ); //set mux ratio writedata( 0 x 3f ); writecommand( 0 x a2 ); //set offset writedata( 0 x 00 ); writecommand( 0 x ab ); //function selection writedata( 0 x 01 ); writecommand( 0 x a0 ); //set re - map writedata ( 0x 16 ); writedata( 0 x 11 ); writecommand( 0x c7 ); //master contrast current writedata( 0x 0f ); writecommand( 0x c1 ); //set contrast current writedata( 0x 9f ); writecommand( 0x b1 ); //set phase length writedata( 0x f2 ); writecommand( 0x bb ); //set pre - charge voltage writedata( 0 x 1f ); writecommand( 0x b4 ); //set vsl writedata( 0x a0 ); writedata( 0 x fd ); writecommand( 0x be ); //set vcomh writedata( 0x 04 ); writecommand( 0x a6 ); //set display mode writecommand( 0x af ); //display on }
[ 12 ] example software routines void s etcolumn( unsigned char xstart, unsigned char xend){ writecommand( 0x15 ); //set column (x - axis) start/end address writedata(xstart); //column start; 28 is left - most column writedata(xend); //column end; 91 is right - most column } void s etrow( unsigned char ystart, unsigned char yend){ writecommand( 0x75 ); //set row (y - axis) start/end address writedata(ystart); //row start; 0 is top row writedata(yend); //row end; 63 is bottom row } void cleardisplay ( void ){ unsigned int i; s etcolumn( 28 , 91 ); //set column (x - axis) start/end address s etrow( 0 , 63 ); //set row (y - axis) start/end address writeram(); //single byte command (0x5c) to initiate pixel data write to gddram; for (i= 0 ;i< 4096 ;i++){ // ((91 - 28)+1)*((63 - 0)+1) writedata( 0x00 ); writedata( 0x00 ); } } void w rite2pixels( unsigned char xpos, unsigned char ypos, unsigned char pixel1, unsigned char pixel2){ if (pixel1>= 1 ) pixel1 = 0xff ; //set 1st pixel value to on else pixel1 = 0x00 ; //set 1st pixel value to off if (pixel2>= 1 ) pixel2 = 0xff ; //set 2nd pixel value to on else pixel2 = 0x00 ; //set 2nd pixel value to off if (xpos> 127 ) xpos = 127 ; //boundary check (min xpos = 0, max xpos = 127) xpos = xpos/ 2 ; //account for gddram address mapping xpos+= 28 ; //account for gddram address mapping if (ypos> 63 ) ypos = 63 ; //boundary check (min ypos = 0, max ypos = 63) s etcolumn(xpos,xpos); //set column (x - axis) start/end address s etrow(ypos,ypos); //set row (y - axis) start/end address writeram(); //single byte command (0x5c) to initiate pixel data write to gddram; writedata(pixel1); //write 1st of 2 pixels to the display writedata(pixel2); //write 2nd of 2 pixels to the display } void d isplayarray12864( const unsigned char arr[]){ //display 128x64 monochrome bitma p, horizontal pixel arrangement, 8 - pixels per byte unsigned int i, j; s etcolumn( 28 , 91 ); //set column (x - axis) start/end address s etrow( 0 , 63 ); //set row (y - axis) start/end address writeram(); //single byte command (0x5c) to initiate pix el data write to gddram; for (i= 0 ;i< 1024 ;i++){ //translate each byte/bit into pixel data for (j= 0 ;j< 8 ;j++){ if (((arr[i]< [ 13 ] quality information test item content of test test condition note high temperature storage test the e ndurance of the display at high storage temperature . + 85 ? c , 240 hrs 2 low temperature storage test the e ndurance of the display at low sto rage temperature . - 4 0 ? c , 240 hrs 1,2 high temperature operation test the e ndurance of the display by applying electric stress (voltage & current) a t high t emperature. + 85 ? c , 240h rs 2 low temperature operation test the e ndurance of the display by applying electric stress (voltage & current) a t low t emperature . - 4 0 ? c , 240 hrs 1 ,2 high temperature / humidity operation test the e ndurance of the display by applying electric stress (voltage & current) a t high t emperature with high humidity. + 6 0 ? c , 90% rh, 240 hrs 1,2 thermal shock resistance test the e ndurance of the display by applying electric stress (voltage & current) during a cycle of low and high t emperatures . - 40 ? c , 30min - > + 25?c, 5min - > + 8 5 ? c, 30min = 1 cycle 10 0 cycles vibration test test the e ndura nce of the display by a pplying vibration to simulate transportation and use. 10 - 22hz, 15mm amplitude. 22 - 500hz, 1.5g 30min in each of 3 directions x,y,z 3 atmospheric pressure test test the endurance of the display by applying atmospheric pressure to simulate transportation by air. 115mbar, 40hrs 3 static electricity test test the endurance of the display by applying electric static discharge. vs=800v, rs=1.5k , cs=100pf one time note 1: no condensation to be observed. note 2: conducted after 2 hour s of storage at 25 ? c, 0%rh. note 3: test performed on product itself, not inside a container . evaluation criteria: 1: display is fully functional during operational tests and after all tests, at room temperature. 2: no observable defects. 3: luminance >50% of initial value. 4: current consumption within 50% of initial value precautions for using oleds/ lcds/lcms see precautions at www.newhavendisplay.com/specs/precautions.pdf warranty information see terms & conditions at http://www.newhavendisplay.com/index.php?main_page=terms

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