View DS1388Z-3TR_8970956.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds1388 i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated? website at www.maximintegrated.com. general description the ds1388 i 2 c real-time clock (rtc), supervisor, and eeprom is a multifunction device that provides aclock/calendar, programmable watchdog timer, power- supply monitor with reset, and 512 bytes of eeprom. the clock provides hundredths of seconds, seconds, minutes, and hours, and operates in 24-hour or 12-hour format with an am/pm indicator. the calendar provides day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. a watchdog timer provides a reset for an unre- sponsive microprocessor. it is programmable in 10ms intervals from 0.01 to 99.99 seconds. a temperature- compensated voltage reference and comparator circuit monitors the status of v cc . if a primary power failure is detected, the device automatically switches to thebackup supply and drives the reset output to the active state. the backup supply maintains time and date operation in the absence of v cc . when v cc returns to nominal levels, the reset is held low for a period to allowthe power supply and processor to stabilize. the device also has a pushbutton reset controller, which debounces a reset input signal. the device is accessed through an i 2 c serial interface. applications portable instrumentspoint-of-sale equipment network interface cards wireless equipment features ? fast (400khz) i 2 c interface ? rtc counts hundredths of seconds, seconds,minutes, hours, day, date, month, and year with leap year compensation valid up to 2100 ? programmable watchdog timer ? automatic power-fail detect and switch circuitry ? reset output with pushbutton reset inputcapability ? 512 x 8 bits of eeprom ? integrated trickle-charge capability for backupsupply ? three operating voltages: 5.0v, 3.3v, and 3.0v ? low timekeeping voltage down to 1.3v ? -40? to +85? temperature range ? ul recognized so top view + ds1388 sclsda gnd 12 8 7 v cc rst x2 v backup x1 3 4 6 5 pin configuration rst v cc x1 scl x2 cpu v cc sda gnd v cc rpu rpu = t r /c b rpu v cc crystal v backup ds1388 typical operating circuit 19-4984; rev 4 4/13 + denotes a lead(pb)-free/rohs-compliant package. ordering information part temp range pin-package top mark ds1388z-5+ -40c to +85c 8 so (150 mils) ds1388-5 ds1388z-33+ -40c to +85c 8 so (150 mils) ds138833 ds1388z-3+ -40c to +85c 8 so (150 mils) ds1388-3 downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 2 maxim integrated ds1388 absolute maximum ratings recommended dc operating conditions (t a = -40? to +85?, unless otherwise noted.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc or v backup pins relative to ground.............................................-0.3v to +6.0v voltage range on inputs relative to ground ...............................................-0.3v to (v cc + 0.3v) junction-to-ambient thermal resistance ( ja ) (note 1)..170?/w junction-to-case thermal resistance ( jc ) (note 1) ......40?/w operating temperature range (noncondensing) .............................................-40? to +85? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units ds1388z-5 4.5 5 5.5 ds1388z-33 2.97 3.3 3.63 supply voltage v cc (note 3) ds1388z-3 2.7 3 3.3 v logic 1 v ih (note 3) 0.7 x v cc v cc + 0.3 v logic 0 v il (note 3) -0.3 +0.3 x v cc v pullup voltage (scl, sda), v cc = 0v v pu 5.5 v v backup voltage v backup (note 3) 1.3 3.0 5.5 v ds1388z-5 4.15 4.33 4.50 ds1388z-33 2.70 2.88 2.97 power-fail voltage v pf (note 3) ds1388z-3 2.45 2.60 2.70 v dc electrical characteristics( v cc = v cc(min) to v cc(max) , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units r1 (notes 4, 5) 250 r2 (note 6) 2000 trickle-charger current-limiting resistors r3 (note 7) 4000 input leakage (scl) i li -1 +1 a i/o leakage (sda) i lo -1 +1 a i/o leakage ( rst ) i lorst (note 8) -200 +10 a sda logic 0 output (v ol = 0.15 x v cc ) i oldout 3 ma note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layerboard. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 3 ds1388 dc electrical characteristics (continued)( v cc = v cc(min) to v cc(max) , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v cc > 2v; v ol = 0.4v 3.0 1.8v < v cc < 2v; v ol = 0.2 x v cc 3.0 ma rst logic 0 output i olsir 1.3v < v cc < 1.8v; v ol = 0.2 x v cc 250 a ds1388z-5 600 ds1388z-33 250 v cc active current, eeprom read, i 2 c read/write access i ccer (note 9) ds1388z-3 225 a ds1388z-5 1.0 ds1388z-33 0.70 v cc active current, eeprom write cycle i ccew (note 9) ds1388z-3 0.65 ma ds1388z-5 270 ds1388z-33 100 150 v cc standby current i ccs (note 10) ds1388z-3 140 a v backup leakage current (v backup = 3.7v, v cc = v cc(max) ) i backuplkg 15 100 na t a = +25c (guaranteed by design) 200k eeprom write/erase cycles t wr t a = -40c to +85c (guaranteed by design) 50k cycles dc electrical characteristics( v cc = 0v , v backup = 3.7v, t a = +25?, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v backup current, osc on ( eosc = 0), sda = scl = 0v i backup (note 11) 410 550 na v backup current, osc off ( eosc = 1), sda = scl = 0v (data retention) i backupdr (note 11) 10 100 na downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 4 maxim integrated ds1388 ac electrical characteristics(v cc = v cc(min) to v cc(max) , t a = -40? to +85?, unless otherwise noted.) (note 2) parameter symbol condition min typ max units fast mode 100 400 scl clock frequency f scl standard mode 0 100 khz fast mode 1.3 bus free time between a stop and start condition t buf standard mode 4.7 s fast mode 0.6 hold time (repeated) start condition (note 12) t hd:sta standard mode 4.0 s fast mode 1.3 low period of scl clock t low standard mode 4.7 s fast mode 0.6 high period of scl clock t high standard mode 4.0 s fast mode 0.6 setup time for a repeated start condition t su:sta standard mode 4.7 s fast mode 0 0.9 data hold time (notes 13, 14) t hd:dat standard mode 0 s fast mode 100 data setup time (note 15) t su:dat standard mode 250 ns fast mode 300 rise time of both sda and scl signals (note 16) t r standard mode 20 + 0.1c b 1000 ns fast mode 300 fall time of both sda and scl signals (note 16) t f standard mode 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 s capacitive load for each bus line c b (note 16) 400 pf i/o capacitance (sda, scl, rst ) c i/o +25c 10 pf pushbutton debounce pb db 160 180 ms reset active time t rst 160 180 ms eeprom write cycle time t wee 8 10 ms oscillator stop flag (osf) delay t osf (note 17) 20 ms downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 5 ds1388 power-up/power-down characteristics(t a = -40? to +85?) (note 2) (figures 1, 2) parameter symbol conditions min typ max units v cc detect to recognize inputs (v cc rising) t rst (note 18) 160 180 ms v cc fall time; v pf(max) to v pf(min) t f 300 s v cc rise time; v pf(min) to v pf(max) t r 0 s outputs v cc v pf(max) inputs high impedance rst don't care valid recognized recognized valid v pf(min) t rst t rpu t r t f v pf v pf figure 1. power-up/down timing t rst pb db rst figure 2. pushbutton reset timing downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 6 maxim integrated ds1388 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in write protection. note 2: limits at -40? are guaranteed by design and are not production tested. note 3: all voltages are referenced to ground. note 4: measured at v cc = typ, v backup = 0v, register 0ah, block 0h = a5h. note 5: the use of the 250 trickle-charge resistor is not allowed at v cc > 3.63v and should not be enabled. note 6: measured at v cc = typ, v backup = 0v, register 0ah, block 0h = a6h. note 7: measured at v cc = typ, v backup = 0v, register 0ah, block 0h = a7h. note 8: the rst pin has an internal 50k pullup resistor to v cc . note 9: i cca ?cl clocking at max frequency = 400khz. note 10: specified with i 2 c bus inactive. note 11: measured with a 32.768khz crystal attached to x1 and x2. note 12: after this period, the first clock pulse is generated. note 13: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 14: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 15: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch thelow period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 16: c b ?otal capacitance of one bus line in pf. note 17: the parameter t osf is the period of time that the oscillator must be stopped for the osf flag to be set over the voltage range of 0v v cc v cc(max) and 1.3v v backup 3.7v. note 18: if the oscillator is disabled or stopped, rst goes inactive after t rst plus the startup time of the oscillator. downloaded from: http:///
v cc falling vs. rst delay ds1388 toc04 v cc falling (v/ms) reset delay ( s) 10 1 0.1 100 1000 10,000 10 0.01 100 v cc = v pf + 0.1v to 0v i backup supply current voltage vs. temperature ds1388 toc02 temperature ( c) supply current (na) 65 50 35 20 5 10 -25 300 350 400 450 500 550 600250 -40 80 v backup = 3v oscillator frequency vs. supply voltage ds1388 toc03 supply (v) frequency (hz) 5.3 4.8 3.8 4.3 2.3 2.8 3.3 1.8 32768.05 32768.10 32768.15 32768.20 32768.25 32768.30 32768.35 32768.40 32768.4532768.00 1.3 i backup supply current voltage vs. v backup ds1388 toc01 v backup (v) supply current (na) 5.3 4.9 4.5 4.1 3.7 3.3 2.9 2.5 2.1 1.7 300 350 400 450 500250 1.3 v cc = 0v typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) maxim integrated 7 i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom ds1388 downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 8 maxim integrated ds1388 pin description block diagram pin name function 1 x1 2 x2 connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6.0pf. pin x1 is the input to the oscillator and can optionally be connected to an external 32. 768khz osc illator. the output of the internal oscillator, pin x2, is left unconnected if an external oscillat or is connected to pin x1. 3 v backup connection for a secondary power supply. supply voltage must be he ld between 1.3v and 5.5v for proper operation. this pin can be connected to a primary cell, such as a lithium butt on cell. additionally, this pin can be connected to a rechargeable cell or a super cap when used with the tr ickle-charge feature. if not used, this pin must be connected to ground. ul recognized to ensure against reverse charging current when used with a lithium battery ( www.maimintegrated.com/qa/info/ul/ ). 4 gnd ground 5 sda serial data output. sda is the input/output for the i 2 c serial interface. this pin is open drain and requires an external pullup resistor. 6 scl serial clock input. scl is the clock input for the i 2 c interface and is used to synchronize data movement on the serial interface. 7 rst active-low, open-drain reset output. this pin indicates the stat us of v cc relative to the v pf specification. as v cc falls below v pf , the rst pin is driven low. when v cc exceeds v pf , for t rst , the rst pin is driven high impedance. the active-low, open-drain output is com bined with a debounced pushbutton input function. this pin can be activated by a pushbutton reset request. it has an internal 50k nominal value pullup resistor to v cc . no external pullup resistors should be connected. if the crystal oscillator is disabled, the startup time of the oscilla tor is added to the t rst delay. 8 v cc dc power pin for primary power supply block 2 block 1 block 0 clock and calendar registers power control and trickle charger i 2 c interface eeprom interface eeprom eeprom watchdog timer status control/ trickle x2 x1 v cc gnd v backup rst sda scl c l c l ds1388 downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 9 ds1388 detailed description the ds1388 i 2 c rtc, supervisor, and eeprom is a multifunction device that provides a clock/calendar,programmable watchdog timer, power-supply monitor with reset, and 512 bytes of eeprom. the clock pro- vides hundredths of seconds, seconds, minutes, and hours, and operates in 24-hour or 12-hour format with an am/pm indicator. the calendar provides day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. a watchdog timer provides a reset for an unresponsive microprocessor. it is programmable in 10ms intervals from 0.01 to 99.99 seconds. a temperature-compensat- ed voltage reference and comparator circuit monitors the status of v cc . if a primary power failure is detected, the device automatically switches to the backup supplyand drives the reset output to the active state. when v cc returns to nominal levels, the reset is held low for a period to allow the power supply and processor to sta-bilize. the device also has a pushbutton reset con- troller, which debounces a reset input signal. the device is accessed through an i 2 c serial interface. operation the ds1388 operates as a slave device on the i 2 c bus. access is obtained by implementing a start conditionand providing a device identification code followed by data. subsequent registers can be accessed sequen- tially until a stop condition is executed. see the block diagram , which shows the main elements of the serial real-time clock. power control the power-control function is provided by a precise,temperature-compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written andread when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the regis- ters are maintained from the v backup source until v cc is returned to nominal levels (table 1). after v cc returns above v pf , read and write access is allowed after rst goes high (figure 1). on first application of power to the device, the time anddate registers are set to 00/00/00 00 00:00:00 (dd/mm/yy dow hh:mm:ss). the user should initial- ize all rtc registers to valid date and time settings. oscillator circuit the ds1388 uses an external 32.768khz crystal. theoscillator circuit does not require any external resistors or capacitors to operate. table 2 specifies several crystal parameters for the external crystal. using a crystal with the specified characteristics, the startup time is usually less than one second. supply condition read/write access powered by v cc < v pf , v cc < v backpup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc parameter symbol min typ max units nominalfrequency f o 32.768 khz seriesresistance esr 50 k loadcapacitance c l 6p f * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for addi- tional specifications. table 1. power controltable 2. crystal specifications* downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 10 maxim integrated ds1388 clock accuracy the accuracy of the clock is dependent upon the accu-racy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit can result in the clock running fast. figure 3 shows a typical pc board layout for isolation of the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real-time clock s for detailed information. address map figure 4 shows the address map for the ds1388. thememory map is divided into three blocks. the memory block accessed is determined by the value of the block address bits in the slave address byte. the timekeep- ing registers reside in block 0h. during a multibyte access of the timekeeping registers, when the internal address pointer reaches 0ch, it wraps around to loca- tion 00h. on an i 2 c start or address pointer incre- menting to location 00h, the current time is transferredto a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to reread the registers in case the main registers update during a read. the eeprom is divided into two 256-byte blockslocated in blocks 1h and 2h. during a multibyte read of the eeprom registers, when the internal address point- er reaches ffh, it wraps around to location 00h of the block of eeprom specified in the block address. during a multibyte write of the eeprom registers, when the internal address pointer reaches the end of the cur- rent 8-byte eeprom page, it wraps around to the beginning of the eeprom page. see the write operation section for details. to avoid rollover issues when writing to the time anddate registers, all registers should be written before the hundredths-of-seconds register reaches 99 (bcd). hundredths-of-seconds generator the hundredths-of-seconds generator circuit shown inthe block diagram is a state machine that divides the incoming frequency (4096hz) by 41 for 24 cycles and40 for 1 cycle. this produces a 100hz output that is slightly off during the short term, and is exactly correct every 250ms. the divide ratio is given by: ratio = [41 x 24 + 40 x 1] / 25 = 40.96 thus, the long-term average frequency output is exactly 100hz. local ground plane (layer 2) crystal gnd x2 x1 note: avoid routing signal lines in the crosshatched area (upper left quadrant) of the package unless there is a ground plane between the signal line and the device package. figure 3. layout example downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 11 ds1388 address blk word bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 0h 00h tenth seconds hundredths of seconds hundredths of seconds 00C99 0h 01h 0 10 seconds seconds seconds 00C59 0h 02h 0 10 minutes minutes minutes 00C59 am / pm 10 hour 0h 03h 0 12/ 24 10 hour hours hours 1C12+ am /pm 00C23 0h 04h 0 0 0 0 x day day 01C07 0h 05h 0 0 10 date date date 01C31 0h 06h 0 0 x 10 month month month 01C12 0h 07h 10 year year year 00C99 0h 08h watchdog tenths of seconds watchdog hundredths of seconds watchdog hundredth seconds 00C99 0h 09h watchdog ten seconds watchdog seconds watchdog seconds 00C99 0h 0ah tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger 0h 0bh osf wf 0 0 0 0 0 0 flag 0h 0ch eosc 0 0 0 0 0 wde wd/ rst control 1h 00Cffh 256 x 8 eeprom eeprom 00Cffh 2h 00Cffh 256 x 8 eeprom eeprom 00Cffh figure 4. address map note: unless otherwise specified, the state of the registers is not defined when power (v cc and v backup ) is first applied. x = general-purpose read/write bit. 0 = always reads as a zero. clock and calendar the time and calendar information is obtained by read-ing the appropriate register bytes. figure 4 illustrates the rtc registers. the time and calendar are set or ini- tialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap years through 2099. the day-of-week register increments at midnight. values that correspond to the day-of-week are user-defined but must be sequential (i.e., if 1equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined oper- ation. the ds1388 can be run in either 12-hour or 24- hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit with logic-high being pm. in the 24-hour mode, bit 5 is the 20-hour bit (20?3 hours). changingthe 12/ 24 bit requires that the hours data be re-entered in the proper format. downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 12 maxim integrated ds1388 watchdog alarm counter the contents of the watchdog alarm counter, which is aseparate two-byte bcd down counter, are accessed in the address range 08h?9h in block 0h. it is programma- ble in 10ms intervals from 0.01 to 99.99 seconds. when this counter is written, both the counter and a seed regis- ter are loaded with the desired value. when the counter is to be reloaded, it uses the value in the seed register. when the counter is read, the current counter value is latched into a register, which is output on the serial data line and the watchdog counter reloads the seed value. if the counter is not needed, it can be disabled and used as a 16-bit cache of battery-backed ram by set- ting the wde bit in the control register to logic 0. if all 16 bits of the watchdog alarm counter are written to a zero when wde = 1, the counter is disabled and the wf bit is not set. when the wde bit in the control register is set to a logic 1 and a non-zero value is written into the watchdog reg- isters, the watchdog alarm counter decrements every 1/100 second, until it reaches zero. at this point, the wf bit in the flag register is set. if wd/ rst = 1, the rst pin is pulsed low for t rst and access to the ds1388 is inhibited. at the end of t rst , the rst pin becomes high impedance, and read/write access to the ds1388 isenabled. the wf flag remains set until cleared by writ- ing wf to logic 0. the watchdog alarm counter can be reloaded and restarted before the counter reaches zero by reading or writing any of the watchdog alarm counter registers. the wf flag and wde bit must be set to zero before writing the watchdog registers. after writing the watchdog regis- ters, wde must be set to one to enable the watchdog. power-up/down, reset, and pushbutton reset functions a precision temperature-compensated reference andcomparator circuit monitors the status of v cc . when an out-of-tolerance condition occurs, an internal power-failsignal is generated that blocks read/write access to the device and forces the rst pin low. when v cc returns to an in-tolerance condition, the internal power-fail sig-nal is held active for t rst to allow the power supply to stabilize, and the rst pin is held low. if the eosc bit is set to a logic 1 (to disable the oscillator in battery-back-up mode), the internal power-fail signal and the rst pin are kept active for t rst plus the oscillator startup time. access is inhibited whenever rst is low. the ds1388 provides for a pushbutton switch to beconnected to the rst output pin. when the ds1388 is not in a reset cycle, it continuously monitors the rst signal for a low-going edge. if an edge is detected, thepart debounces the switch by pulling the rst pin low and inhibits read/write access. after the internal timerhas expired, the part continues to monitor the rst line. if the line is still low, it continues to monitor the line look-ing for a rising edge. upon detecting release, the part forces the rst pin low and holds it low for t rst . special-purpose registers the ds1388 has three additional registers (control,flag, and trickle charger) that control the real-time clock, watchdog, and trickle charger. flag register (00bh) bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator has stopped or wasstopped for some period of time and may be used to judge the validity of the clock and calendar data. this bit is edge triggered and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a stop condition. the follow- ing are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on both v cc and v backup are insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (i.e., noise, leak- age, etc.). this bit remains at logic 1 until written to logic 0. thisbit can only be written to logic 0. attempting to write osf to logic 1 leaves the value unchanged. bit 6: watchdog alarm flag (wf). a logic 1 in this bit indicates that the watchdog counter reached zero. ifwde and wd/ rst are set to 1, the rst pin pulses low for t rst when the watchdog counter reaches zero and sets wf = 1. at the completion of the pulse, the wf bitremains set to logic 1. writing this bit to logic 0 clears the wf flag. this bit can only be written to logic 0. attempting to write logic 1 leaves the value unchanged. bits 5 to 0: these bits read as zero and cannot be modified. flag register (00bh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 o s fw f000000 downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 13 ds1388 control register (00ch) bit 7: enable oscillator ( eosc ). when set to logic 0, the oscillator is started. when set to logic 1, the oscillatoris stopped when the ds1388 switches to battery power. this setting can be used to conserve battery power when timekeeping operation is not required. this bit is cleared (logic 0) when power is first applied. when the ds1388 is powered by v cc , the oscillator is always on regardless of the status of the eosc bit. the clock can be halted whenever the timekeeping functions are notrequired, which minimizes v bat current (i backupdr ). bits 6 to 2: these bits read as zero and cannot be modified.bit 1: watchdog enable (wde). when set to logic one, the watchdog counter is enabled. when set tologic 0, the watchdog counter is disabled, and the two registers can be used as nv ram. this bit is cleared (logic 0) when power is first applied. bit 0: watchdog reset (wd/ rst ). this bit enables the watchdog alarm output to drive the rst pin. when the wd/ rst bit is set to logic 1, rst pulses low for t rst if wde = 1 and the watchdog counter reaches zero.when the wd/ rst bit is set to logic 0, the rst pin is not driven by the watchdog alarm; only the watchdogflag bit (wf) in the flag register is set to logic 1. this bit is logic 0 when power is first applied. trickle-charge register (00ah) the simplified schematic of figure 5 shows the basiccomponents of the trickle charger. the trickle-charge select (tcs) bits (bits 4?) control the selection of thetrickle charger. to prevent accidental enabling, only a pattern on 1010 enables the trickle charger. all other patterns disable it. the trickle charger is disabled when power is first applied. the diode-select (ds) bits (bits 2 and 3) select whether or not a diode is connected between v cc and v backup . if ds is 01, no diode is selected, yet if ds is 10, a diode is selected. the routbits (bits 0 and 1) select the value of the resistor con- nected between v cc and v backup . table 3 shows the resistor selected by the resistor select (rout) bits andthe diode selected by the diode-select (ds) bits. warning: the rout value of 250 must not be select- ed whenever v cc is greater than 3.63v. the user determines the diode and resistor selectionaccording to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following exam- ple. assume that a system power supply of 3.3v is applied to v cc and a super cap is connected to v backup . also, assume that the trickle charger has been enabled with a diode and resistor r2 betweenv cc and v backup . the maximum current i max would be calculated as follows: i max = (3.3v - diode drop) / r2 (3.3v - 0.7v) / 2k 1.3ma as the super cap charges, the voltage drop betweenv cc and v backup decreases and therefore the charge current decreases. control register (00ch) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 00000w d e w d / rst table 3. trickle-charge register tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 function x x x x 0 0 x x disabled x x x x 1 1 x x disabled x x x x x x 0 0 disabled 10100101n o diode, 250 resistor 10101001 one diode, 250 resistor 10100110n o diode, 2k resistor 10101010 one diode, 2k resistor 10100111n o diode, 4k resistor 10101011 one diode, 4k resistor 00000000 initial default value?isabled downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 14 maxim integrated ds1388 eeprom the ds1388 provides 512 bytes of eeprom organizedinto two blocks of 256 bytes. each 256-byte block is divided into 32 pages consisting of 8 bytes per page. the eeprom can be written one page at a time. page write operations are limited to writing bytes within a sin- gle physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page size (8 bytes) and end at addresses that are integer multiples of [page size -1]. for example, page 0 contains word addresses 00h to 07h. similarly, page 1 contains word addresses 08h to 0fh. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. therefore, it is necessary for the application software to prevent page write operations that would attempt to cross a page boundary. i 2 c serial data bus the ds1388 supports a bidirectional i 2 c bus and data transmission protocol. a device that sends data ontothe bus is defined as a transmitter and a device receiv- ing data is defined as a receiver. the device that con- trols the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and gener- ates the start and stop conditions. the ds1388 operates as a slave on the i 2 c bus. connections to the bus are made through the open-drain i/o lines sdaand scl. within the bus specifications, a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum clock rate) are defined. the ds1388 works in both modes. the following bus protocol has been defined (figure 6): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the dataline while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have beendefined: bus not busy: both data and clock lines remain high.start data transfer: a change in the state of the data line from high to low, while the clock line is high,defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line is high,defines a stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line isstable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. r1 250 r2 2k r3 4k v cc v backup bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle-charge register (00ah) 1 0f 16 select note: only 1010b enables charger 1 of 2 select 1 of 3 select tcs 0-3 = trickle-charge select ds 0-1 = diode select rout 0-1 = resistor select figure 5. programmable trickle charger downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 15 ds1388 each data transfer is initiated with a start conditionand terminated with a stop condition. the number of data bytes transferred between the start and the stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge(ack) after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the ds1388 does not generate any acknowledge bits if access to the eeprom is attempted during an internal pro- gramming cycle. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by generating a not-acknowledge (nack) bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figures 7 and 8 detail how data transfer is accom-plished on the i 2 c bus. depending upon the state of the r/ w bit, two types of data transfer are possible: data transfer from a master transmitter to a slavereceiver. the first byte transmitted by the master is the slave address. next follows a number of databytes. the slave returns an acknowledge bit after each received byte. data are transferred with the most significant bit (msb) first. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is trans- mitted by the master. the slave then returns anacknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a nack is returned. the master device generates all the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeat- ed start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data are transferred with the most significant bit (msb) first. sda scl idle 1? 8 9 1? 8 9 1? 8 9 start condition stop condition repeated start slave address r/w ack ack data ack/ nack data msb first msb lsb msb lsb repeated if more bytes are transferred figure 6. i 2 c data transfer overview downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 16 maxim integrated ds1388 device addressing the slave address byte is the first byte received follow-ing the start condition from the master device. the slave address byte consists of a 4-bit control code. for the ds1388, this is set as 1101 binary for read and write operations. the next three bits of the slave address byte are the block select bits (b2, b1, b0). b2 is always logic 0 for the ds1388. these bits are used by the master device to select which of the three blocks in the memory map are to be accessed. these bits are the three most significant bits of the word address. the last bit of the slave address byte defines the operation to be performed. when set to 1, a read operation is selected; when set to 0, a write operation is selected. write operation slave receiver mode (write mode) following the start condition from the master, thedevice code (4 bits); the block address (3 bits); and the r/ w bit, which is logic-low, is placed onto the bus by the master transmitter. this indicates to the ds1388that a byte with a word address follows after the ds1388 has generated an acknowledge bit during the ninth clock cycle. the next byte transmitted by the master is the word address and will set the internal address pointer of the ds1388, with the ds1388 acknowledging the transfer on the ninth clock cycle. the master device can then transmit zero or more bytes of data, with the ds1388 acknowledging the transfer on the ninth clock cycle. the master generates a stop condition to terminate the data write. byte write the write-slave address byte and word address aretransmitted to the ds1388 as described in the slave receiver mode section. the master transmits one data byte, with the ds1388 acknowledging the transfer onthe ninth clock cycle. the master then generates a stop condition to terminate the data write. this initiates the internal write cycle, and, if the write was to the eeprom, the ds1388 does not generate acknowledge signals during the internal eeprom write cycle. eeprom page write the write-slave address byte, word address, and thefirst data byte are transmitted to the ds1388 in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to 8 data bytes to the ds1388, which are temporarily stored in the on-chip page buffer and are written into the memo- ry after the master has transmitted a stop condition. data bytes within the page that are not written remain unchanged. the internal address pointer automatically increments after each byte is written. if the master should transmit more than 8 data bytes prior to generating the stop condition, the address pointer rolls over and the previously received data is overwritten. as with the byte write operation, once the stop condi- tion is received an internal write cycle begins. rtc multibyte write writing multiple bytes to the rtc works much the sameway as the eeprom page write, except that the entire contents of block 0h can be written at once. the 8-byte page size limitation does not apply to the block 0. if the master should transmit more bytes than exists in block 0 prior to generating the stop condition, the internal address pointer rolls over and the previously received data is overwritten. as with the byte write operation, once the stop condition is received an internal write cycle begins. slave address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 1 0 1 b 2b 1b 0r / w operation control code block select r/ w read clock 1101 000 1 write clock 1101 000 0 read lower block of eeprom 1101 001 1 write lower block of eeprom 1101 001 0 read upper block of eeprom 1101 010 1 write upper block of eeprom 1101 010 0 downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom maxim integrated 17 ds1388 acknowledge polling since the ds1388 does not acknowledge during aneeprom write cycle, acknowledge polling can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the master issues the stop condition for a write command, the ds1388 initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition, followed by the slave address byte for a write command (r/ w = 0) to the eeprom. if the device is still busy with the writecycle, then a nack is returned. if the cycle is com- plete, then the device returns the ack and the master can then proceed with the next read or write command. the rtc registers in block 0 are accessible during an eeprom write cycle. read operation read operations are initiated in the same way as writeoperations with the exception that the r/ w bit of the slave address is set to 1. there are three basic types ofread operations: current address read, random read, and sequential read. current address read the ds1388 contains an address pointer that main-tains the last address accessed, internally increment- ed by 1. therefore, if the previous access (either a read or write operation) was to address n, the next cur- rent address read operation would access data from address n + 1. upon receipt of the slave address with the r/ w bit set to 1, the ds1388 issues an acknowl- edge and transmits the 8-bit data byte. the masterissues a nack followed by a stop condition, and the ds1388 discontinues transmission. random read random read operations allow the master to access anymemory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the ds1388 as part of a write operation. after the word address is sent, the master generates a start condi- tion following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the slave address byte again but with the r/ w bit set to 1. the ds1388 then issues an acknowledge and transmits the 8-bit databyte. the master issues a nack followed by a stop condition, and the ds1388 discontinues transmission. sequential read sequential reads are initiated in the same way as a ran-dom read except that after the ds1388 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the ds1388 to transmit the next sequentially addressed 8-bit byte. to provide sequential reads, the ds1388 contains an internal address pointer, which is incremented by one at the completion of each opera- tion. this allows the entire memory contents of the block specified in the slave address to be serially read during one operation. the master terminates the read by generating a nack followed by a stop condition. no page boundaries exist for read operations. when the address pointer reaches the end of an eeprom block (ffh), the address pointer wraps to the beginning (00h) of the same block. the ds1388 can operate in the two modes illustrated in figures 7 and 8. ... a xxxxxxxx a 1101000 s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p figure 7. data write?lave receiver mode downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom 18 maxim integrated ds1388 ... a xxxxxxxx a 1101bbb s 1 xxxxxxxx a xxxxxxxx a xxxxxxxx a p b - block select s - start a - acknowledge (ack) p - stop a - not acknowledge (nack) r/w - read/write or direction bit address data transferred (x + 1 bytes + acknowledge) note: last data byte is followed by a nack. master to slave slave to master figure 8. data read?lave transmitter mode b - block select s - start sr - repeated start a - acknowledge (ack) p - stop a - not acknowledge (nack) r/w - read/write or direction bit address a xxxxxxxx a 1101bbb 1101bbb ss r 0 a 1 data transferred (x + 1 bytes + acknowledge) note: last data byte is followed by a nack. master to slave slave to master a xxxxxxxx xxxxxxxx a xxxxxxxx a xxxxxxxx a p ... figure 9. data write/read (write pointer, then read)?lave receive and transmit chip information substrate connected to groundprocess: cmos package information for the latest package outline information and land patterns, goto www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 so s8+4 21-0041 90-0096 downloaded from: http:///
i 2 c rtc/supervisor with trickle charger and 512 bytes eeprom ds1388 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 19 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/05 initial release. removed the leaded parts from the ordering information . 1 indicated the pullup voltage for sda and scl in the pin description table. 8 added the oscillator bias circuit to the block diagram and removed the original figure 8, 10 added time and date por values in the power control section. 9 changed the last sentence of the watchdog alarm counter section (first paragraph) to when the counter is read, the current counter value is latched into a reg ister, which is output on the serial data line and the watchdog counter reloads the seed valu e. 12 added access is inhibited whenever rst is low. to the end of the power-up/down, reset, and pushbutton reset functions section (first paragraph). 12 in the control register (00ch) section, bit 7 description, added a statement that eosc is used to reduce v bat current when timekeeping is not required. 13 1 9/08 replaced the i 2 c read and write figures. 17, 18 corrected the rtc power-on default values in the power control section. 9 corrected the date register range in figure 4. 11 2 10/09 added wf flag clear to the watchdog alarm counter section. 12 in the absolute maimum ratings section, added the thermal information, lead information, and new note 1, and updated the soldering information. 2C6 in the pin description , corrected x2 pin name and bias limit on sda, scl. 8 3 8/10 added the package code and land pattern no. to the package information table. 18 4 4/13 updated absolute maimum ratings , power control and clock and calendar sections 2, 9, 11 downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1388Z-3TR

	To Download DS1388Z-3TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .