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?2015 integrated device technology, inc. october 2015 dsc-3026/12 1 high speed 3.3v 2k x 8 dual-port static ram with interrupts idt71v321s/l features high-speed access ? commercial & industrial: 25/35/55ns (max.) low-power operation ? idt71v321s ? active: 325mw (typ.) ? standby: 5mw (typ.) ? idt71v321l ? active: 325mw (typ.) ? standby: 1mw (typ.) two int flags for port-to-port communications functional block diagram notes: 1. idt71v321 (master): busy is an output 2. busy and int are totem-pole outputs. on-chip port arbitration logic (idt71v321 only) busy output flag fully asynchronous operation from either port battery backup operation?2v data retention (l only) ttl-compatible, single 3.3v power supply available in 52-pin plcc, 64-pin tqfp and stqfp packages industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information i/o control address decoder memory array arbitration and interrupt logic address decoder i/o control r/ w l ce l oe l busy l a 10l a 0l 3026 drw 01 i/o 0l - i/o 7l ce l oe l r/ w l int l busy r i/o 0r -i/o 7r a 10r a 0r int r ce r oe r (2) (1,2) (1,2) (2) r/ w r ce r oe r 11 11 r/ w r
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 2 idt71v321j j52 (4) 52-pin plcc top view (5) index i/o a a a a a a a a a i/o i/o i/o 1l 2l 3l 4l 5l 6l 7l 8l 9l 0l 1l 3l 2l oe r a a a a a a a a a a nc i/o 0r 1r 2r 3r 4r 5r 6r 7r 8r 9r 7r 4 l 5 l 6 l 7 l n c g n d i / o i / o i / o i / o i / o i / o i / o i / o i / o i / o i / o 0 r 1 r 2 r 3 r 4 r 6 r 5 r a 0 l o e l a 1 0 l i n t l b u s y l r / w l c e l v c c c e r r / w r b u s y r i n t r a 1 0 r 1 2 3 4 5 6 747 48 49 50 51 52 9 8 10 11 12 13 14 15 16 17 18 19 20 27 26 25 24 23 22 21 33 32 31 30 29 28 35 34 36 37 38 39 40 41 42 43 44 45 46 3026 drw 02 pin configurations (1,2,3) description the idt71v321 is a high-speed 2k x 8 dual-port static rams with internal interrupt logic for interprocessor communications. the idt71v321 is designed to be used as a stand-alone 8-bit dual-port ram. the device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature, controlled by ce , permits the on chip circuitry of each port to enter a very low standby power mode. fabricated using cmos high-performance technology, these de- vices typically operate on only 325mw of power. low-power (l) ver- sions offer battery backup data retention capability, with each dual-port typically consuming 200w from a 2v battery. the idt71v321 devices are packaged in a 52-pin plcc, a 64-pin tqfp (thin quad flatpack), and a 64-pin stqfp (super thin quad flatpack). index idt71v321pf or tf pp64 (4) & pn64 (4) 64-pin stqfp 64-pin tqfp top view (5) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 1 7 1 8 1 9 2 0 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 4 9 5 0 5 1 5 2 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 6 4 i/o 6r n/c a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r oe r n/c n/c i/o 2l a 0l oe l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l n/c n/c g n d 4 l i / o 5 l i / o 6 l i / o 7 l i / o i / o 0 r i / o 1 r i / o 2 r i / o 3 r i / o 4 r i / o 5 r i / o 3 l n / c n / c g n d n / c n / c a 1 0 r v c c b u s y l r / w l c e r r / w r b u s y r c e l n / c n / c a 1 0 l v c c n / c i n t r i n t l 3026 drw 03 notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. j52-1 package body is approximately .75 in x .75 in x .17 in. pp64-1 package body is approximately 10mm x 10mm x 1.4mm. pn64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 3 recommended dc operating conditions absolute maximum ratings (1) recommended operating temperature and supply voltage (1,2) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. notes: 1. v il (min.) = -1.5v for pulse width less than 20ns. 2. v term must not exceed vcc + 0.3v. notes: 1. this is the parameter t a . this is the "instant on" case temperature. 2. industrial temperature: for specific speeds, packages and powers contact your sales office. symbol rating commercial & industrial unit v te rm (2 ) te r m i n a l vo l ta g e with respect to gnd -0.5 to +4.6 v t a operating temperature 0 to +70 c t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 30 26 tbl 01 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v 3.3v + 0.3v industrial -40 o c to +85 o c0v 3.3v + 0.3v 30 26 tb l 02 symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.0 ____ v cc +0.3 (2) v v il input low voltage -0.3 (1) ____ 0.8 v 3 026 tbl 03 capacitance (1) (ta = +25c, f = 1.0mhz) tqfp only symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 3026 tbl 04 notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. dc electrical characteristics over the operating temperature and supply voltage range (v cc = 3.3v 0.3v) symbol parameter test conditions 71v321s 71v321l unit min. max. min. max. |i li | input leakage current (1) v cc = 3.6v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc v cc = 3.6v ___ 10 ___ 5a v ol output low voltage i ol = 4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 3026 tbl 05 note: 1. at v cc < 2.0v input leakages are undefined.
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 4 dc electrical characteristics over the operating temperature and supply voltage range (1,2) (v cc = 3.3v 0.3v) notes: 1. 'x' in part numbers indicates power rating (s or l). 2. v cc = 3.3v, t a = +25c, and are not production tested. i ccdc = 70ma (typ.). 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc and using "ac test conditions" of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. applies only to inputs at cmos level standby. 5. port "a" may be either left or right port. port "b" is opposite from port "a". symbol parameter test condition version 71v321x25 com'l & ind 71v321x35 com'l & ind 71v321x55 com'l & ind unit typ. max. typ. max. typ. max. i cc dynamic operating current (both ports active) ce = v il , outputs disabled sem = v ih f = f max (3) com'l s l 55 55 130 100 55 55 125 95 55 55 115 85 ma ind l 55 130 55 125 55 115 i sb1 standby current (both ports - ttl level inputs) ce r = ce l = v ih sem r = sem l = v ih f = f max (3) com'l s l 15 15 35 20 15 15 35 20 15 15 35 20 ma ind l 15 35 15 35 15 35 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (3) sem r = sem l = v ih com'l s l 25 25 75 55 25 25 70 50 25 25 60 40 ma ind l 25 75 25 70 25 60 i sb3 full standby current (both ports - all cmos level inputs) both ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) sem r = sem l > v cc - 0.2v com'l s l 1.0 0.2 5 3 1.0 0.2 5 3 1.0 0.2 5 3 ma ind l 0.2 6 1.0 5 1.0 5 i sb4 full standby current (one port - all cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) sem r = sem l > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs disabled f = f max (3) com'l s l 25 25 70 55 25 25 65 50 25 25 55 40 ma ind l 25 70 25 65 25 55 3026 tbl 06 data retention characteristics (l version only) symbol parameter test condition min. typ. (1) max. unit v dr v cc for data retention 2.0 ___ 0v i ccdr data retention current v cc = 2 v, ce > v cc - 0.2v com'l. ___ 100 500 a t cdr (3) chip deselect to data retention time v in > v cc - 0.2v or v in < 0.2v ind. ___ 100 1000 a 0 ___ ___ v t r (3) operation recovery time t rc (2) ___ ___ v 3026 tbl 07 notes: 1. v cc = 2v, t a = +25c, and is not production tested. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization but not production tested.
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 5 data retention waveform v cc ce 3.0v 3.0v data retention mode t cdr t r v ih v ih v dr v dr 2.0v 3026 drw 04 , ac test conditions 590 ? 30pf 435 ? data out 590 ? 435 ? 5pf data out 3026 drw 05 3.3v 3.3v busy int , figure 1. ac output test load figure 2. output test load (for t hz , t lz , t wz , and t ow ) * including scope and jig. input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns 1.5v 1.5v figures 1 and 2 3026 tbl 08 ac electrical characteristics over the operating temperature supply voltage range (2) 71v321x25 com'l & ind 71v321x35 com'l & ind 71v321x55 com'l & ind unit symbol parameter min. max. min. max. min. max. read cycle t rc read cycle time 25 ____ 35 ____ 55 ____ ns t aa address access time ____ 25 ____ 35 ____ 55 ns t ace chip enable access time ____ 25 ____ 35 ____ 55 ns t aoe output enable access time ____ 12 ____ 20 ____ 25 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 30 ns t pu chip enable to power up time (2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 50 ____ 50 ____ 50 ns 3026 tbl 09 notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. 'x' in part numbers indicates power rating (s or l).
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 6 ce t ace t hz t lz t pd valid data 50% oe data out current i cc i ss 50% 3026 drw 07 (4) (1) (1) (2) (2) (4) t lz t hz t aoe t pu timing waveform of read cycle no. 2, either side (3) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is de-asserted first, oe or ce . 3. r/ w = v ih and the address is valid prior to or coincidental with ce transition low. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . timing waveform of read cycle no. 1, either side (1) notes: 1. r/ w = v ih , ce = v il , and is oe = v il . address is valid prior to the coincidental with ce transition low. 2. t bdd delay is required only in the case where the opposite port is completing a write operation to the same address location. for s imultaneous read operations busy has no relationship to valid output data. 3. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . address data out t rc t oh previous data valid t aa t oh data valid 3026 drw 06 t bdd (2,3) busy out
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 7 ac electrical characteristics over the operating temperature and supply voltage range (4) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization but is not production tested. 3. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 4. 'x' in part numbers indicates power rating (s or l). symbol parameter 71v321x25 com'l & ind 71v321x35 com'l & ind 71v321x55 com'l & ind unit min. max. min. max. min. max. write cycle t wc write cycle time 25 ____ 35 ____ 55 ____ ns t ew chip enable to end-of-write 20 ____ 30 ____ 40 ____ ns t aw address valid to end-of-write 20 ____ 30 ____ 40 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 20 ____ 30 ____ 40 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 12 ____ 20 ____ 20 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 30 ns t dh data hold time (3) 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 15 ____ 15 ____ 30 ns t ow output active from end-of-write (1,2) 0 ____ 0 ____ 0 ____ ns 3026 tbl 10
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 8 timing waveform of write cycle no. 2, ( ce controlled timing) (1,5) timing waveform of write cycle no. 1, (r/ w controlled timing) (1,5,8) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of ce = v il and r/w= v il . 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the l/o pins are in the output state and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. this parameter is determined to be device characterization, but is not production tested. transition is measured 0mv from ste ady state with the output test load (figure 2). 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . t wc address oe ce r/ w data out data in t as t wr t ow t dw t dh t aw t wp (2) t hz (4) (4) t wz t hz 3026 drw 08 (6) (7) (7) (3) (7) t wc address ce r/ w data in t as t ew t wr t dw t dh t aw 3026 drw 09 (6) (2) (3)
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 9 ac electrical characteristics over the operating temperature and supply voltage range (6) notes: 1. port-to-port delay through ram cells from the writing port to the reading port, refer to ?timing waveform of write with port- to-port read and busy ." 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that a write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. 'x' in part numbers indicates power rating (s or l). 71v321x25 com'l & ind 71v321x35 com'l & ind 71v321x55 com'l & ind symbol parameter min.max.min.max.min.max.unit busy timing t baa busy access time from address ____ 20 ____ 20 ____ 30 ns t bda busy disable time from address ____ 20 ____ 20 ____ 30 ns t bac busy access time from chip enable ____ 20 ____ 20 ____ 30 ns t bdc busy disable time from chip enable ____ 20 ____ 20 ____ 30 ns t wh write hold after busy (5) 12 ____ 15 ____ 20 ____ ns t wdd write pulse to data delay (1) ____ 50 ____ 60 ____ 80 ns t ddd write data valid to read data delay (1) ____ 35 ____ 45 ____ 65 ns t aps arbitration priority set-up time (2) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 30 ____ 30 ____ 45 ns 3026 tbl 11 timing waveform of write with port-to-port read and busy (2,3,4) notes: 1. to ensure that the earlier of the two ports wins. 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for the left and right ports. port ?a? may be either the left or right port. port ?b? is opposite from port ?a?. t wc t wp t dw t dh t bdd t ddd t bda t wdd addr "b" data out"b" data in "a" addr "a" match valid match valid r/ w "a" busy "b" t aps 3026 drw 10 (1) t baa
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 10 timing waveform of busy arbitration controlled by ce timing (1) timing waveform of busy arbitration controlled by address match timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisfied, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. notes: 1. t wh must be met for busy output 71v321. 2. busy is asserted on port 'b' blocking r/ w ' b' , until busy 'b' goes high. 3. all timing is the same for the left and right ports. port "a" may be either the left or right port. port "b" is opposite from port "a". timing waveform of write with busy (3) busy "b" 3026 drw 11 r/ w "a" t wp t wh r/ w "b" (2) (1) , t aps (2) addr "a" and "b" addresses match t bac t bdc ce "b" ce "a" busy "a" 3026 drw 12 busy "b" addresses do not match addresses match t aps addr "a" addr "b" t rc or t wc 3026 drw 13 (2) t baa t bda
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 11 ac electrical characteristics over the operating temperature and supply voltage range (1) notes: 1. 'x' in part numbers indicates power rating (s or l). 71v321x25 com'l & ind 71v321x35 com'l & ind 71v321x55 com'l & ind symbol parameter min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 25 ____ 25 ____ 45 ns t inr interrupt reset time ____ 25 ____ 25 ____ 45 ns 3026 tbl 12 timing waveform of interrupt mode (1) set int clear int notes: . 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from po rt ?a?. 2. see interrupt truth table. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. t ins addr "a" int "b" interrupt address t wc t as r/ w "a" t wr 3026 drw 14 (3) (3) (2) (4) t rc interrupt clear address addr "b" oe "b" t inr int "b" 3026 drw 15 t as (3) (3) (2) ,
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 12 table iii ? address busy arbitration table i ? non-contention read/write control (4) notes: 1. pins busy l and busy r are both outputs. busy x outputs on the idt71v321 are totem- pole. 2. 'l' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'h' if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. truth tables table ii ? interrupt flag (1,4) notes: 1. a 0l ? a 10l a 0r ? a 10r . 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. 'h' = v ih , 'l' = v il , 'x' = don?t care, 'z' = high-impedance. notes : 1. assumes busy l = busy r = v ih 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. 'h' = high, 'l' = low, 'x' = don?t care left port right port function r/ w l ce l oe l a 10l -a 0l int l r/ w r ce r oe r a 10r -a 0r int r llx7ffxxxx x l (2 ) set right int r flag xxxxxxll7ffh (3) reset right int r flag xxx x l (3) llx 7fe xset left int l flag xll7feh (2) x x x x x reset left int l flag 3026 tbl 14 inputs outputs function ce l ce r a ol -a 10l a or -a 10r busy l (1 ) busy r (1) xxno match h h normal hx match h h normal xh match h h normal l l match (2) (2) write inhibit (3 ) 3026 tbl 15 left or right port (1) r/ w ce oe d 0-7 function xhx z port deselected and in power- down mode. i sb2 or i sb4 xhx z ce r = ce l = v ih, power-down mode i sb1 or i sb3 llx data in data on port written into memory (2) hl ldata out data in memory output on port (3) h l h z high-impedance outputs 3026 tb l 13
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 13 busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. depth expansion the busy arbitration, is based on the chip enable and address signals only. it ignores whether an access is a read or write. the busy outputs on the idt71v321 are totem-pole type outputs and do not require pull-up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate functional description the idt7v1321 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt71v321 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7fe (hex), where a write is defined as the ce r = r/ w r = v il per truth table ii. the left port clears the interrupt by accessing address location 7fe when ce l = oe l = v il, r/w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7ff (hex) and to clear the interrupt flag ( int r ), the right port must access the memory location 7ff. the message (8 bits) at 7fe or 7ff is user-defined, since it is an addressable sram location. if the interrupt function is not used, address locations 7fe and 7ff are not used as mail boxes, but as part of the random access memory. refer to truth table ii for the interrupt operation. 3026 drw 16 d e c o d e r busy r master dual port ram busy l busy r ce master dual port ram busy l busy r ce busy l figure 3. busy and chip enable routing for depth expansion with idt71v321.
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 14 ordering information notes: 1. contact your sales office industrial temperature range is available for selected speeds, packages and powers. 2. green parts available. for specific speeds, packages and powers contact your local sales office. a power 999 speed a package a process/ temperature range blank i (1) commercial (0c to +70c) industrial (-40c to +85c) j pf tf 52-pin plcc 64-pin tqfp 64-pin stqfp 25 35 55 xxxxx device type speed in nanoseconds 3026 drw 17 l s low power standard power 71v321 16k (2k x 8-bit) master 3.3v dual-port ram w/interrupt commercial & industrial commercial & industrial commercial & industrial blank 8 tube of tray tape and reel a g (2) green a (j52) (pn64) (pp64) datasheet document history 03/24/99: initiated da tasheet document history converted to new format cosmetic and typographical corrections page 2 added additional notes to pin configurations 06/15/99: changed drawing format 10/15/99: page 12 changed open drain to totem-pole in table iii, note 1 10/21/99: page 13 deleted 'does not' in copy from busy logic 11/12/99: replaced idt logo 01/12/01: pages 1 & 2 moved full "description" to page 2 and adjusted page layouts page 3 increased storage temperature parameters clarified t a parameter page 4 dc electrical parameters?changed wording from "open" to "disabled" changed 200mv to 0mv in notes 08/22/01: pages 4, 5, 7, industrial temp range offering removed from dc & ac electrical characteristics for 35 and 55ns 9 & 11 01/17/06: page 1 added green availability to features page 14 added green indicator to ordering information page 1 & 14 replaced old idt tm with new idt tm logo datasheet document history continued on page 15
6.42 idt71v321s/l high speed 3.3v 2k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 15 the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dua lporthelp@idt.com www.idt.com datasheet document history (con't) 08/25/06: page 11 changed int "a" to int "b" in the clear int drawing in the timing waveform of interrupt mode 10/23/08: page 14 removed "idt" from orderable part number 01/25/10: page 4 in order to correct the dc chars table for the 71v321/71v421l35 speed grade and the data retention chars table, i temp values have been added to each table respectively. in addition, all of the ac chars tables and the ordering information also now reflect this i temp correction 06/25/15: page 2 removed idt in reference to fabrication page 2 & 14 the package codes j52-1, pn64-1 & pp64-1 changed to j52, pn64 & pp64 respectively to match standard package codes page 14 added tape and reel indicator to ordering information 10/14/15: page 1 -15 removed 71v421s/l from the part number, in the pin configurations and throughout the datasheet page 1 - 15 removed all references to master/slave throughout the datasheet page 1 -15 updated the com'l and ind speeds for the 25/35/55ns offerings in features , in the dc & ac chars tables, in the ordering information and throughout the datasheet page 13 removed width expansion with busy logic master/slave arrays diagram for part numbers 71v321/71v421s/ l and updated with a depth expansion diagram for the single part number 71v321s/l updated the corresponding depth expansion descriptive text in the depth expansion section of the datasheet

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