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fn6785 rev 1.00 page 1 of 30 may 5, 2016 fn6785 rev 1.00 may 5, 2016 D2-45057, d2-45157 intelligent digital amplifier p wm controller and audio processo r datasheet the D2-45057 and d2-45157 devices are complete system-on-chip (soc) class-d digital audio amplifiers. combining high performance integrated power stages along with an optimized audio processor feature set and pwm controller, these devices offer a complete, powerful, and very cost effective audio solution for high volume and cost-critical products. this 4th generation digital audio engine (dae-4p)? device combines extensive integrated digital signal processor (dsp) audio processing with amplifier control, for a complete audio solution. its ease of integration into the existing system processor provides co mplete support for all system product and amplifier functions. the four configurable power stages operate as four separate half-bridge outputs, as two full-bridge outputs, or in combinations of half-bridge plus full-bridge, providing flexible loudspeaker drive solutions. separate pwm outputs provide additional combinations to drive headphone, or line level stereo and subwoofer outputs. related literature ? dae-4/dae-4p register api specification ? dae-4p evaluation kit guides features ? all digital class-d amplifier and controller with integrated digital signal processing (dsp) ? four integrated power stages supporting - 2 channels, bridged - 4 channels, half-bridge - 2 channels, half-bridge, plus 1 channel bridged ? output power (bridged) - 25w (8 ??? 1% thd); 30w (8 ??? 10% thd) ? fully programmable digital signal processing (dsp) - up to 5 programmable audio signal path channels - programmable equalizers, filters, mixers, limiters ? includes d2audio? soundsuite? and dts?(srs) wow/hd? audio enhancement algorithms ?i 2 s and s/pdif? digital audio inputs ? asynchronous sample rate converters; sample rates from 32khz up to 192khz ? wide 9v to 26v power stage hv supply range, plus internally-generated gate drive supply ? temperature and undervoltage monitoring and individual channel protection applications ? pc/multimedia speakers ? digital tv audio systems ? portable device docking stations ? powered speaker systems typical system implementation figure 1. system application implementing 2x full-b ridge loudspeaker outputs pl us 3 line-level outputs d2-45x57-qr dae-4p? intelligent digital power amplifier and audio processor 5 channel pwm engine 24 bit digital signal processor 2 channel sample rate converter digital audio interface s/pdif digital i/o interface soc system controller(s) i 2 s i 2 c control i 2 c s/pdif buffer s/pdif buffer optical/ coax in optical/ coax out d2audio ? soundsuite? 3 rd party enhancements (srs wow/hd ? ) d2audio ? audio canvas? processing pwm output drive output filter amplifier output 1 output filter output filter pwm output filter pwm output filter pwm stereo line out or headphone out subwoofer line out (optional) amplifier output 2 amplifier output 3 amplifier output 4 amplifier output mosfets (optional)
D2-45057, d2-45157 fn6785 rev 1.00 page 2 of 30 may 5, 2016 ordering information part number ( notes 3 , 4 ) part marking audio processing feature set support ( note 1 ) temp. range (c) tape and reel (units) package (rohs compliant) pkg. dwg. # D2-45057-qr D2-45057-qr d2audio? soundsuite? -10 to +85 - 68 ld qfn l68.10x10c D2-45057-qr-t ( note 2 ) D2-45057-qr d2audio? soundsuite? -10 to +85 3k 68 ld qfn l68.10x10c d2-45157-qr d2-45157-qr d2audio? soundsuite? dts?(srs) wow/hd? -10 to +85 - 68 ld qfn l68.10x10c d2-45157-qr-t ( note 2 ) d2-45157-qr d2audio? soundsuite? dts?(srs) wow/hd? -10 to +85 3k 68 ld qfn l68.10x10c notes: 1. the D2-45057, d2-45157 support audio processing algorithms fo r the d2audio? soundsuite?, and dts?(srs) wow/hd? audio enhancem ent features. algorithm support of these enhancem ents is device-dependent. refer to specific part number for desired feature suppor t. 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-fre e products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for D2-45057 , d2-45157 . for more information on msl please see techbrief tb363 .
D2-45057, d2-45157 fn6785 rev 1.00 page 3 of 30 may 5, 2016 table of contents typical system implementation . . . . . . . . . . . . . . . . . . . . . . . 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 recommended operating conditions . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance characteristics . . . . . . . . . . . . . . . . . .13 test considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 full-bridge typical performance curves . . . . . . . . . . . . . . . . . 13 half-bridge typical performance curves . . . . . . . . . . . . . . . . 14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 audio enhancement features . . . . . . . . . . . . . . . . . . . . . . . . . 16 serial audio digital input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 s/pdif digital audio i/o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 sample rate converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clock and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 audio outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output power stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pwm audio outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 control and operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 i 2 c 2-wire control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reading and writing control registers. . . . . . . . . . . . . . . . . . 18 control interface address spaces . . . . . . . . . . . . . . . . . . . . . . 19 storing parameters to eeprom . . . . . . . . . . . . . . . . . . . . . . . 19 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . 19 reset and device initialization. . . . . . . . . . . . . . . . . . . . . . . . . 19 boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power supply requirements. . . . . . . . . . . . . . . . . . . . . . . . . 20 high-side gate drive voltage . . . . . . . . . . . . . . . . . . . . . . . . . 20 power supply synchronization . . . . . . . . . . . . . . . . . . . . . . . . 20 power sequence requirements . . . . . . . . . . . . . . . . . . . . . . . 21 reg5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pin and control block functions . . . . . . . . . . . . . . . . . . . . . 21 i/o control pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 npdn input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 nerror[0-3] output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 iref pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 configuration assignment pin differences . . . . . . . . . . . . . . 21 ocfg0, ocfg1 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 nerror/cfg0 and pssync/cfg1 pins . . . . . . . . . . . . . . . . 22 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 error reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 short-circuit and overcurrent sensing . . . . . . . . . . . . . . . . . . 25 protection monitoring and control . . . . . . . . . . . . . . . . . . . . . 25 thermal protection and monitors . . . . . . . . . . . . . . . . . . . . . . 25 graceful overcurrent and short-circuit . . . . . . . . . . . . . . . . . 25 power supply voltage monitoring. . . . . . . . . . . . . . . . . . . . . . 26 audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 audio processing signal flow blocks. . . . . . . . . . . . . . . . . . . 26 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 about intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 disclaimer for dts?(srs) technology license required notice: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
D2-45057, d2-45157 fn6785 rev 1.00 page 4 of 30 may 5, 2016 absolute maximum ratings ( note 7 ) thermal information supply voltage hvdd[a:d], vddhv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28.0v rvdd, pwmvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4.0v cvdd, pllvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.4v input voltage any input but xtali . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to rvdd +0.3v xtali . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to pllvdd +0.3v input current, any pin but supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 68 ld qfn package ( notes 5 , 6 ) . . . . . . . . 25 1 maximum storage temperature. . . . . . . . . . . . . . . . . . . . -55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10c to +85c high voltage supply voltage, hvdd[a:d], vddhv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0v to 26.5v digital i/o supply voltage, pwmvdd . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3v core supply voltage, cvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8v analog supply voltage, pllvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8v minimum load impedance (hvdd[a:d] 24.0v), z l . . . . . . . . . . . . . . . . 4 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. absolute maximum parameters are not tested in production. electrical specifications t a = +25c, hvdd[a:d]/vddhv = 24v, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. pll at 294.912mhz, osc at 24.576mhz, core running at 147.456mhz with ty pical audio data traffic. parameter test conditions symbol min typ max unit digital input high logic level ( note 8 )v ih 2--v digital input low logic level ( note 8 )v il --0.8v high level output drive voltage (i out at -pin drive strength current) v oh rvdd - 0.4 - - v low level output drive voltage (i out at +pin drive strength current) v ol --0.4v high level input drive voltage xtali pin v ihx 0.7 - pllvdd v low level input drive voltage xtali pin v ilx --0.3v input leakage current ( note 9 )i in - - 10 a input capacitance cin - 9 - pf output capacitance all outputs except out[a:d] c out -9-pf out[a:d] - 190 - pf nreset pulse width t rst -10-ns internal pull-up resistance to pwmvdd (for nerror0-3, ocfg, npdn) --100-k digital i/o supply pin voltage, current rvdd and pwmvdd 33.33.6v active current - 10 - ma power-down current - 0.01 - ma core supply pins cvdd 1.7 1.8 1.9 v active current - 300 - ma power-down current ( note 10 ) -6-ma
D2-45057, d2-45157 fn6785 rev 1.00 page 5 of 30 may 5, 2016 analog supply pins (pll) pllvdd 1.7 1.8 1.9 v active current - 10 - ma power-down current ( note 10 ) -5-ma crystal oscillator crystal frequency (fundamental mode crystal) xo 20 24.576 25 mhz duty cycle dt 40 - 60 % start-up time (start-up time is oscillator enabled (with valid supply) to stable oscillation) t start -520ms pll vco frequency f vco 240 294.912 300 mhz pll lock time from any input change - 3 - ms 1.8v power-on reset reset enabled voltage level v en 0.95 1.1 1.3 v por minimum output pulse width t dis -5-s 1.8v brownout detection detect level 1.4 1.5 1.7 v pulse width rejection t bod1 - 100 - ns minimum output pulse width t o1 -20-ns 3.3v (pwmvdd) brownout detection detect level 2.5 2.7 2.9 v pulse width rejection t bod3 - 100 - ns minimum output pulse width t o3 -20-ns gate drive internal +5v brown-out detection gate drive supply undervoltage threshold - 4.5 - v gate drive supply undervoltage threshold hysteresis - 200 - mv gate drive supply undervoltage threshold glitch rejection - 50 - ns protection detect high voltage (+vddhv) undervoltage protection - 7 9 v overcurrent trip threshold -4-a overcurrent de-glitch -2.5-ns short-circuit current limit (peak) -8-a overcurrent response time -20-ns thermal shutdown (power stages) - 140 - c thermal shutdown hysteresis (power stages) - 30 - c notes: 8. all input pins except xtali. 9. input leakage applies to all pins except xtalo. 10. power-down is with device in reset and clocks stopped. electrical specifications t a = +25c, hvdd[a:d]/vddhv = 24v, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. pll at 294.912mhz, osc at 24.576mhz, core running at 147.456mhz with ty pical audio data traffic. (continued) parameter test conditions symbol min typ max unit
D2-45057, d2-45157 fn6785 rev 1.00 page 6 of 30 may 5, 2016 performance specifications t a = +25c, hvdd[a:d]/vddhv = 24v, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. pll at 294.912mhz, osc at 24.576mhz, core running at 147.456mhz with ty pical audio data traffic. parameter symbol min typ max unit r ds(on) (maximum, mosfets at +25c) r ds(on) - 200 - m r ds(on) mismatch -1-% pwm switching rate - 384 - khz npdn input off delay t pdnoff -1.4-ms npdn input on delay t pdnon -1.4-ms power output <1% thd, bridged, load = 8 , hvdd[a:d] = 24v p out -25-w <10% thd, bridged, load = 8 , hvdd[a:d] = 24v p out -30-w <1% thd, half-bridge, load = 8 , hvdd[a:d] = 24v p out -7-w <10% thd, half-bridge, load = 8 , hvdd[a:d] = 24v p out -9-w thd+n load = 8 , power = 25w, bridged, 1khz thd+n - 0.3 - % load = 8 , power = 1w, bridged, 1khz - 0.05 - % snr snr - 110 - db efficiency (power stage, load = 8 )-90-% serial audio interface port timing t a = +25c, hvdd[a:d]/vddhv = 24v, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. pll at 294.912mhz, osc at 24.576mhz, core running at 147.456mhz with ty pical audio data traffic. symbol description min typ max unit t c sclk sclk frequency - (sclk) - - 12.5 mhz t w sclk sclk pulse width (high and low) - (sclk) 40 - - ns t s lrclk lrckr set-up to sclk rising - (lrck) 20 - - ns t h lrclk lrckr hold from sclk rising - (lrck) 20 - - ns t s sdi sdin set-up to sclk rising - (sdin) 20 - - ns t h sdi sdin hold from sclk rising - (sdin) 20 - - ns t c sclk lrck sclk sdin t h lrclk t s lrclk t s sdi t h sdi t w sclk t w sclk figure 2. serial audio interface port timing
D2-45057, d2-45157 fn6785 rev 1.00 page 7 of 30 may 5, 2016 two-wire (i 2 c) interface port timing t a = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min max unit f scl scl frequency - 100 khz t buf bus free time between transmissions 4.7 - s t wlow sclx scl clock low 4.7 - s t whigh sclx scl clock high 4.0 - s t s sta set-up time for a (repeated) start 4.7 - s t h sta start condition hold time 4.0 - s t h sdax sda hold from scl falling ( note 11 ) 1 (typical) sys clk t s sdax sda set-up time to scl rising 250 - ns t d sdax sda output delay time from scl falling - 3.5 s t r rise time of both sda and scl ( note 12 ) - 1 s t f fall time of both sda and scl ( note 12 ) - 300 ns t s sto set-up time for a stop condition 4.7 - s notes: 11. data is clocked in as valid on next xtali rising edge after scl goes low. 12. limits established by characterization and not production tested. t wlow sclx sclx sdax (input) t s sta t h stax t r t f t s sdax t h sdax t s sto t buf sdax (output) t d sdax t whigh sclx figure 3. i 2 c interface timing
D2-45057, d2-45157 fn6785 rev 1.00 page 8 of 30 may 5, 2016 spi? master mode interface port timing t a = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min max unit t v mosi valid from clock edge - 8 ns t s miso setup to clock edge 10 - ns t h miso hold from clock edge 1 system clock + 2ns t wi nss minimum width 3 system clocks + 2ns spi? slave mode interface port timing t a = +25c, cvdd = pllvdd = 1.8v 5%, rvdd = pwmvdd = 3.3v 10%. all grounds at 0.0v. all voltages referenced to ground. symbol description min max unit t v miso valid from clock edge 3 system clocks + 2ns t s mosi set-up to clock edge 10 - ns t h mosi hold from clock edge 1 system clock + 2ns t wi nss minimum width 3 system clocks + 2ns sck(cpha = 1, cpol = 0) mosi nss sck(cpha = 0, cpol = 0) miso(cpha = 0) t v t v t h t s t wi figure 4. spi timing
D2-45057, d2-45157 fn6785 rev 1.00 page 9 of 30 may 5, 2016 pin configuration D2-45057, d2-45157 (68 ld qfn) top view 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 51 50 49 48 47 46 45 44 43 42 41 40 39 38 15 16 17 37 36 35 54 53 52 sclk sdin lrck mclk cvdd cgnd rgnd rvdd tempref/sck nmute/tio1 vol1/miso temp1/mosi pwmvdd ocfg0 pwmgnd spdifrx spdiftx test irqa irqb rgnd r vdd nerror/cfg0 pssync/cfg1 protect0 pro tect1 protect2 scl sda tempcom/tio0 nreset n r s t o u t c v d d c g n d v o l 0 / n s s p l l v d d x t a l o x t a l i p l l g n d nerror0 ner ror1 nerror2 nerror3 hvddd hgnd d o c f g 1 l i n e l l i n e r n p d n h v d d a hsbsa h g n d a outa hsbsb outb hgndb hvddb reg5v vddhv iref dnc subout hvddc hgndc outc hsbsc hsbsd outd pin description pin pin name ( note 13 )type voltage level (v) description 1 nreset i 3.3 active low reset input with hysteresis. low level acti vates system level reset, initializing all internal logic and program operations. system latches boot mode selection on the irq input pins on the rising edge. 2tempcom/ tio0 i/o 3.3 board temperature monitor common i/o pin. when op erating as output, provid es 16ma drive strength. 3 sda i/o 3.3 two-wire serial data port, open drain driver with 8ma drive strength. bidirectional signal used by both the master and slave controllers for data transport. pin floats on reset.
D2-45057, d2-45157 fn6785 rev 1.00 page 10 of 30 may 5, 2016 4 scl i/o 3.3 two-wire serial clock port, open drain driver with 8ma drive strength. bidirectional signal is used by both the master and slave controllers for clock signaling. pin floats on reset. 5sclk i 3.3i 2 s serial audio bit clock (sclk) input. input has hysteresis. 6sdin i 3.3i 2 s serial audio data (sdin) input. input has hysteresis. 7lrck i 3.3i 2 s serial audio left/right (lrck) input. input has hysteresis. 8mclk o 3.3i 2 s serial audio master clock output for external adc/ dac components, drives low on reset. output is an 8ma driver. 9 cvdd p 3.3 core power, +1.8vdc. used in the chip internal dsp, logic and interfaces. 10 cgnd gnd 3.3 core ground. 11 rgnd gnd 3.3 digital pad ring ground. internally connected to pwmgnd. 12 rvdd p 3.3 digital pad ring power, 3.3v. this 3.3v supply is used for all the digital i/o pad drivers and receivers, except for the analog pads. there are 2 of these pins and both are required to be connected. internally connected to pwmvdd. 13 tempref/ sck i/o 3.3 reference pin for temperature monitor and spi clock. at deassertion of device reset, pin operates as spi clock with 8ma drive strength. upon internal D2-45057, d2-45157 firmware execution, pin becomes temperature monitor reference. 14 nmute/ tio1 o 3.3 mute signal output. low active: mute condition drives pin low. output is a 16ma driver. initializes as input on reset, then becomes output upon internal firmware execution. 15 vol1/ miso i/o 3.3 volume control pulse input and spi master- input/slave-output data signal. at deassertion of device reset, pin operates as spi master input or slave output. (when operating as ou tput, provides 4ma drive strength.) then upon internal D2-45057, d2-45157 firmware execution, pin becomes input for monitoring up/down phase pulses from volume control. (1 of 2 volume input pins.) 16 temp1/ mosi i/o 3.3 board temperature monitor pin, and spi master-outpu t/slave-input data signal. at deassertion of device reset, pin operates as spi master output or slave input. (when operat ing as output, provides 4ma drive strength.) then upon internal D2-45057, d2-45157 firmware execution, pin becomes input for monitoring board temperature. 17 spdifrx i 3.3 s/pdif digital audio data input 18 spdiftx o 3.3 s/pdif digital audio data output this pin is the s/pdif audio output and drives a 8ma, 3.3v stereo output up to 192khz. pin floats on reset. 19 test i 3.3 hardware test mode control. for factory use only. must be tied low. 20 irqa i 3.3 interrupt request port a. one of 2 irq pins, tied to logic (3.3v) high or to ground. high/low logic status establishes boot mode selection upon deassertion of reset (nreset) cycle. 21 irqb i 3.3 interrupt request port b. one of 2 irq pins, tied to logic (3.3v) high or to ground. high/low logic status establishes boot mode selection upon deassertion of reset (nreset) cycle. 22 rgnd gnd 3.3 digital pad ring ground. internally connected to pwmgnd. 23 rvdd p 3.3 digital pad ring power, 3.3v. this 3.3v supply is used for all the digital i/o pad drivers and receivers, except for the analog pads. there are 2 of these pins and both are required to be connected. internally connected to pwmvdd. 24 nerror/ cfg0 i/o 3.3 output configuration selection input, and nerror outp ut. upon device reset, pin operates as input, using application-installed pull-up or pull-down connection to pin to specify one of 4 amplifier configurations. upon internal D2-45057, d2-45157 firmware execution, pin becomes output, providing active-low output drive when amplifier protection monitoring detects an error condition. when operating as output, provides 4ma drive strength. (note: this pin may also be referenced as ?pscurr? on some reference designs. function is identical regardless of name.) pin description (continued) pin pin name ( note 13 )type voltage level (v) description
D2-45057, d2-45157 fn6785 rev 1.00 page 11 of 30 may 5, 2016 25 pssync/ cfg1 i/o 3.3 output configuration selection input, and power supply sync output. upon device reset, pin operates as input, using application-installed pull-up or pull-down connection to pin to specify one of 4 amplifier configurations. upon internal D2-45057, d2-45157 firmware executio n, pin becomes output, providing synchronizing signal to on-board power supply circuits. when operating as ou tput, provides 4ma drive strength. note: this pin may also be referenced as ?pstemp? on some reference designs. function is identical regardless of name. 26 protect0 i/o 3.3 pwm protection input. input has hysteresis. protec tion monitoring functionality of pin is controlled by interna l D2-45057, d2-45157 firmware, and dependent on whic h of the 4 amplifier configurations is enabled. 27 protect1 i/o 3.3 pwm protection input. input has hysteresis. protec tion monitoring functionality of pin is controlled by interna l D2-45057, d2-45157 firmware, and dependent on whic h of the 4 amplifier configurations is enabled. 28 protect2 i/o 3.3 pwm protection input. input has hysteresis. protec tion monitoring functionality of pin is controlled by interna l D2-45057, d2-45157 firmware, and dependent on whic h of the 4 amplifier configurations is enabled. 29 nerror0 o 3.3 overcurrent protection output, channel a outp ut stage. open drain 16ma driver, with internal 100k (approx.) pull-up. pulls low when active from ov ercurrent detection of output stage. 30 nerror1 o 3.3 overcurrent protection ou tput, channel b output stage. open drain 16ma driver, with internal 100k (approx.) pull-up. pulls low when active from ov ercurrent detection of output stage. 31 nerror2 o 3.3 overcurrent protection output, channel c output stage. open drain 16ma driver, with internal 100k (approx.) pull-up. pulls low when active from ov ercurrent detection of output stage. 32 nerror3 o 3.3 overcurrent protection output, channel d output stage. open drain 16ma driver, with internal 100k (approx.) pull-up. pulls low when active from ov ercurrent detection of output stage. 33 hvddd p hv output stage d high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 34 hgndd gnd hv output stage d high voltage supply ground. a separate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (see note 15 ). 35 outd o hv pwm power amplifier output, channel d. 36 hsbsd i hv high-side boot strap input, output channe l d. capacitor couples to outd amplifier output. 37 hsbsc i hv high-side boot strap input, output channe l c. capacitor couples to outc amplifier output. 38 outc o hv pwm power amplifier output, channel c. 39 hgndc gnd hv output stage c high voltage supply ground. a sepa rate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (see note 15 ). 40 hvddc p hv output stage c high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 41 subout o 3.3 ?subwoofer? channel pwm output, with 16ma drive strength. connects to filter network for supplying line- level analog output to subwoofer. 42 dnc - - do not connect to this pin. 43 iref i - overcurrent reference analog input. used in setting the overcurrent error detect externally-set threshold. the pin needs to be connected to a 100k resistor to ground to set the overcurrent threshold according to the specified limits. 44 vddhv p +hv high voltage internal driver supply power. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. the internal +5v supply re gulators also operate from this vddhv input. 45 reg5v p 5 5v internal regulator filter connect. a +5v supply is internally generated from the voltage source provided at the vdd pin. reg5v is used for extern al connection of a decoupling capacitor. 46 hvddb p hv output stage b high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 47 hgndb gnd hv output stage b high voltage supply ground. a sepa rate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (see note 15 ). 48 outb o hv pwm power amplifier output, channel b. pin description (continued) pin pin name ( note 13 )type voltage level (v) description
D2-45057, d2-45157 fn6785 rev 1.00 page 12 of 30 may 5, 2016 49 hsbsb i hv high-side boot strap input, output channe l b. capacitor couples to outb amplifier output. 50 hsbsa i hv high-side boot strap input, output channe l a. capacitor couples to outa amplifier output. 51 outa o hv pwm power amplifier output, channel a. 52 hgnda gnd hv output stage a high voltage supply ground. a sepa rate ground pin connection is provided for each of the output stages. all of the hgnd[a:d] pins connect to system ?hv? power ground (see note 15 ). 53 hvdda p hv output stage a high voltage supply power. a separate power pin connection is provided for each of the output stages. all of the hvdd[a:d] pins and the vddhv pin connect to the system ?hv? power source. 54 npdn i 3.3 power-down and mute input. active low. when this input is low, all 4 outputs become inactive and their output stages float, and their output is muted. internal logi c and other references remain active during this power- down state. 55 liner o 3.3 ?right? channel pwm output, with 16ma drive stre ngth. connects to filter network for supplying line-level analog output. 56 linel o 3.3 ?left? channel pwm output, with 16ma drive stre ngth. connects to filter network for supplying line-level analog output. 57 ocfg1 i 3.3 output configuration control select. ocfg0 and oc fg1 are logic inputs to select the output configuration mode of the output stages. connects to either pw mgnd ground or pwmvdd (+3.3v) through nominal 10k resistor to select output configuration. 58 ocfg0 i 3.3 output configuration control select. ocfg0 and oc fg1 are logic inputs to select the output configuration mode of the output stages. connects to either pw mgnd ground or pwmvdd (+3.3v) through nominal 10k resistor to select output configuration. 59 pwmgnd p 3.3 pwm output pin ground . internally connected to rgnd. 60 pwmvdd p 3.3 pwm output pin power. this 3.3v supply is used for the pwm pad drivers. internally connected to rvdd. 61 pllgnd p 1.8 pll analog ground. should be tied to low volt age ground (cgnd, rgnd) through single point connection to isolate ground noise on board an d minimizing affecting of pll. 62 xtali p 1.8 crystal oscillator analog input port. 63 xtalo p 1.8 crystal oscillator analog output port. (this output drives the crystal and xtalo does not have a drive strength specification.) 64 pllvdd p 1.8 pll analog power, 1.8v. 65 vol0/ nss i/o 3.3 volume control pulse input and spi slave select. at deassertion of device reset, pin operates as spi slave select input. then upon internal D2-45057, d2-45157 firmware execution, pin becomes input for monitoring up/down phase pulses from volume co ntrol. (1 of 2 volume input pins.) 66 cgnd p 1.8 core ground 67 cvdd p 1.8 core power, +1.8vdc. used in the chip internal dsp, logic and interfaces. 68 nrstout o 3.3 active low open-drain output, with 16ma drive st rength. pin drives low from rvdd 3.3v brownout detector, pwmvdd 3.3v brownout detector, or 1.8v brownout detector going active. this output should be used to initiate a system reset to the nreset pin upon brownout event detection. notes: 13. unless otherwise specified all pin names are active high. thos e that are active low have an ?n? prefix, such as nreset. 14. all power and ground pins of same names are to be tied togeth er to all other pins of their same name. (i.e., cvdd pins to be tied together, cgnd pins to be tied together, rvdd pins to be tied together, and rgnd pins to be tied together.) also, cgnd and rgnd are to be tied toge ther on board, and rgnd and pwmgnd pins are internally connected and are to be tied together on the board. 15. thermal pad is internally connected to all 4 hgnd ground pins (hgnda, hgndb, hgndc, hgndd). any connection to the thermal pa d must be made to the common ground for these 4 ground pins. pin description (continued) pin pin name ( note 13 )type voltage level (v) description
D2-45057, d2-45157 fn6785 rev 1.00 page 13 of 30 may 5, 2016 typical performance characteristics test considerations ? typical performance measurements are made using an audio precision? 2700 series audio analyzer. ? precision power resistors are used for the 8 loudspeaker loads ? measurements are done using a +hv supply of +24.0vdc. full-bridge typical performance curves figure 5. thd vs power, full-bridge figu re 6. thd vs frequency, full-bridge figure 7. frequency response, full-bridge figure 8. noise floor, full-bridge 0.01 10.00 0.02 0.05 0.10 0.20 0.50 1.00 2.00 5.00 thd (%) 0.06 50 0.1 0.2 0.5 1 2 5 10 20 power (w) hvdd = 24.0v, 8 load, 1khz 0.001 1.000 0.002 0.005 0.010 0.020 0.050 0.100 0.200 0.500 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) p = 25w thd (%) p = 14w p = 7w p = 1w hvdd = 24.0v, 8 load, at 1w, 7w, 14w, 25w power out -6 6 -5 -4 -3 -2 -1 -0 1 2 3 4 5 dbr a 30 10k 50 100 200 500 1k 2k 5k frequency (hz) hvdd = 24.0v, 8 load, 3.5w -120 -50 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 dbr a -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs < -115db, un-weighted hvdd = 24.0v, 8 load, at 1khz, reference to 30w
D2-45057, d2-45157 fn6785 rev 1.00 page 14 of 30 may 5, 2016 half-bridge typical performance curves figure 9. thd vs power, half-bridge fig ure 10. thd vs frequency, half-bridge figure 11. frequency response, half-bridge figure 12. noise floor, half-bridge thd (%) power (w) 0.02 10.00 0.05 0.10 0.20 0.50 1.00 2.00 5.00 0.06 20 0.1 0.2 0.5 1 2 5 10 hvdd = 24.0v, 8 load, 1khz frequency (hz) thd (%) 0.001 1.000 0.002 0.005 0.010 0.020 0.050 0.100 0.200 0.500 20 20k 50 100 200 500 1k 2k 5k 10k hvdd = 24.0v, 8 load, 2.4w power out -12 12 -10 -8 -6 -4 -2 -0 2 4 6 8 10 20 20k 50 100 200 500 1k 2k 5k 10k dc response without ac response due to loudspeaker dc blocking capacitor dc blocking capacitor dbr a frequency (hz) hvdd = 24.0v, 8 load, 1w -125 -30 -120 -115 -110 -105 -100 -95 -90 -85 -45 -40 -35 -60 +0 -55-50-45-40-35-30-25-20-15-10 -5 dbfs dbr a -80 -75 -70 -65 -60 -55 -50 < -110db, un-weighted noise floor at 1khz, +24v rail, spdif input, 8 lo ad, unity dsp gain
fn6785 rev 1.00 page 15 of 30 may 5, 2016 D2-45057, d2-45157 reg5v (45) vddhv (44) ocfg0 (58) ocfg1 (57) npdn (54) iref (43) spdifrx (17) spdiftx (18) D2-45057, d2-45157 dae-4p? 24-bit fixed-point digital signal processor with 56-bit mac (signal processing and configuration blocks defined by device rom firmware) sclk (5) sdin (6) lrck (7) mclk (8) nreset (1) nrstout (68) test (19) irqa (20) irqb (21) xtali (62) xtalo (63) sda (3) scl (4) tempref/sck (13) temp1/mosi (16) vol1/miso (15) vol0/nss (65) tempcom/tio0 (2) nmute/tio1 (14) pllvdd (64) pllgnd (61) pwmvdd (60) pwmgnd (59) rvdd (12,23) rgnd (11,22) cvdd (9,67) cgnd (10,66) 2 2 2 2 protect0 (26) protect1 (27) protect2 (28) pssync/cfg1 (25) nerror/cfg0 (24) 5 channel pulse width modulator engine hvddd (33) outd (35) hgndd (34) hsbsd (36) nerror3 (32) output stage d hvddc (40) outc (38) hgndc (39) hsbsc (37) nerror2 (31) output stage c hvddb (46) outb (48) hgndb (47) hsbsb (49) nerror1 (30) output stage b hvdda (53) outa (51) hgnda (52) hsbsa (50) nerror0 (29) output stage a mixers tone controls 5-band eqs volume controls compressor/limiters loudness routers high/low-pass cross- overs 3-band eqs compressor/limiters channel attenuators speaker eqs linel (56) liner (55) subout (41) protection inputs configuration, system i/o spi interface, system i/o 2-wire (i 2 c-compatible) control, initialization s/pdif digital audio receiver, transmitter serial audio interface port (i 2 s data type receiver) sample rate converters firmware (rom) timers, i/o pll power supply amplifier configuration & control line pwm outputs linear interpolator pwm correction noise shaper quantizer pwm output drive input selection enhancement audio processing algorithms (part-number dependent) d2audio soundsuite? srs wow/hd ? figure 13. D2-45057, d2-45157 functional block diagram
D2-45057, d2-45157 fn6785 rev 1.00 page 16 of 30 may 5, 2016 functional description overview the D2-45057, d2-45157 device, shown in figure 13 on page 15 , is an integrated system-on-chip (soc) audio processor and class d digital audio amplifier. it includes digital audio input selection, signal routing, co mplete audio processing, pwm controllers, amplifier and protection control, and integrated power stages. stereo i 2 s and s/pdif digital input support, plus i 2 c and 2-wire spi control inte rfaces provide integration compatibility with existing syst em architectures and solutions. the four configurable power stages can operate as four separate half-bridge outputs, as two full-bridge outputs, or in combinations of half-bridge plus full-bridge outputs. separate pwm outputs provide additional combinations to drive headphone, or line-level stereo and subwoofer outputs. these application-dependent configurations provide for driving stereo (2.0) speaker, 2.1 speaker, and stereo (2.2) bi-amp speaker solutions, as well as providing stereo line outputs, headphone outputs, or subwoofer line outputs. audio output implementations are defined by configuration mode select pins, providing four combinations of powered and line amplifier outputs as shown in table 1 . the five independent audio processing paths feed a pwm engine, where its five pwm channels are mapped to the config uration-selected power stages and line outputs. the audio path includes a stereo sample rate converter (src), five independent audio processing channels, plus device-specific audio enhancement algorithms. programmable parameter settings for audio processing include volume control, path routing and mixing, high/low pass filtering, multi-band equalizers, comp ressors, and loudness. these parameters can be adjusted using the d2audio? audio canvas? software, or can be set by a system/amplifier microcontroller through the D2-45057, d2-45157 device?s control interface. audio enhancement features the D2-45057, d2-45157 devices include the d2audio soundsuite? or dts?(srs) wow/hd? audio enhancement algorithms. these device-specific functions are integrated within the firmware as part of the standard audio processing signal flow, and are supported per device as: ? d2audio soundsuite? (widesound?, deepbass?, audio align?, and clearvoice?) audio processing - included in the D2-45057 device ? dts?(srs) wow/hd? - included in the d2-45157 device each of these enhancements uti lizes its own algorithms, where choice of enhancement is specified by device part number. the D2-45057 includes only d2audio soundsuite? support, and the d2-45157 includes only dts?(srs) wow/hd? support. these enhancements also have their own unique set of programmable parameters to control operation. serial audio digital input the D2-45057, d2-45157 devices include one serial audio interface (sai) port accommodating two digital audio input channels. this sai port operates in slave mode only, supports the i 2 s digital audio industry standard, and can carry up to 24-bit linear pcm audio words. the digital audio input from the sai input port routes directly through the sample rate converters (src). either the i 2 s digital input, or the s/pdif digital input may be selected as the audio path source. s/pdif digital audio i/o the D2-45057, d2-45157 contains one iec60958 compliant s/pdif digital receiver inpu t and one iec60958 compatible s/pdif digital transmitter. the s/pdif digital receiver inpu t includes an input transition detector, digital pll clock recovery, and a decoder to separate the audio data. the receiver meets the jitter tolerance specified in iec60958-4. the s/pdif digital transmitter complies with the consumer applications defined in iec6095 8-3. the transmitter supports 24-bit audio data, but does not support user data and channel status. compressed digital formats ar e not decoded within the D2-45057, d2-45157 devices. but a bit-exact pass-through mode is supported from the spdifrx input to the spdiftx output, allowing for designs that require iec61937-compliant original compressed audio input bitstream be made available at the product?s s/pdif digital output. table 1. output configuration modes config mode name function 02.0 l/r 4-quadrant ? powered left and right outputs with 4-quadrant, full bridge drivers. ?no line-level outputs 12.0 l/r + l/r/sub line ? powered left and right outputs with 2-quadrant, full bridge drivers. ? stereo left + right line-level outputs. ? subwoofer line-level output 22.1 l/r/sub + l/r line ? two half bridge drivers for powered left and right outputs. ? 2-quadrant, full bridge driver for powered subwoofer output. ?two (stereo left + right) line-level outputs. ? crossover filtering included within audio path signal flow. 32.2 bi-amp ? four half bridge drivers for powered bi-amp left + right outputs. ? crossover filtering included within audio path signal flow.
D2-45057, d2-45157 fn6785 rev 1.00 page 17 of 30 may 5, 2016 sample rate converter the D2-45057, d2-45157 de vices contain a 2-channel asynchronous sample rate converter (src) within the audio input signal flow path. this src is used to convert audio data input sampled at one input sample rate, to a fixed 48khz output sample rate, aligning asynchronous input audio streams to a single rate for sy stem processing. audio data presented to the src can be from either the sai or s/pdif digital input sources, wi th an input sample rate from 16khz to 192khz. in addition to converting the input sample rate to the output sample rate, input clock jitter and sampling jitter is attenuated by the src, furt her enhancing audio quality. dsp a 24-bit fixed-point digital signal processor (dsp) controls the majority of audio processing and system control functions within the D2-45057, d2-45157 devices. audio path signal routing, programmable-parameter processing blocks, and control logic are defined within the device?s internal firmware. signal flows through the device are buffered and processed through hardware specif ic-function blocks, such as the sample rate converter. internal device registers allow full integration of dsp control with the internal rom-based firmware, as well as providing for external control of audio processing parameters. clock and pll clock is generated on-chip, using a fundamental-mode crystal connected across the xtali and xtalo pins. xtalo is an output, but is designed only to drive th e crystal, and not connect to any other circuit. xtali is an input, co nnecting to the other side of the crystal. the clock generation contains a lo w jitter pll to ensure low noise pwm output, and a precise master clock source for sample rate conversion and the audio processing data paths. the internal pll?s vco clock operates at 12x the crystal frequency (12 x 24.576mhz) and provides complete device and system timing reference. it is used throughout the device, including clock generators for brown-out detectio n, system and power-on reset, dsp, s/pdif digital transmit ter, and pwm en gine timing. clock and pll hardware functions are controlled by internal device firmware. they are not programmable and are optimized for device and system operation. timers there are two independent timers used for device and system control. one timer is used for internal references for chip-specific operations. the other is used fo r the system/board temperature sensing control algorithm. there are two i/o pins (tio0 and tio1) associated with the timers. their pin functions are defined by the device firmware. only tio0 is actually used in relationship to its timer, timer 0, and operates the timing-related i/o functions of the temperature monitoring algorithm. timer 1 is used for internal functions of the device. its pin (tio1) is not used for this timing operation and is defined by device firmware as the nmute input pin. audio outputs audio outputs are provided through four output power stages, configurable for driving loudspeakers. three additional pwm outputs are also available for dr iving line-level audio outputs. combinations of outputs and their audio processing channel assignment is defined by the device?s configuration mode settings. output power stages the devices include four independent output stages ( figure 14 ) that are each implemented using a high-side (to positive hvdd supply) and a low-side (to hv supply ground) fet pair. drivers and overcurrent monitoring are included in each of these four output stages. depending on the selected configuration mode, these four stages can be used independently as single half-bridge outputs, or as pairs for full-bridge outputs. audio processing pwm channel outp uts are routed to the inputs of the four output stages based on the ocfg0 and ocfg1, and nerror/cfg0 and pssync/cfg1 co nfiguration settings. each output stage includes its own high-side and low-side current sensing that feeds to internal monitor logic as well as providing its nerror output connection. temperature and undervoltage monitoring also provides status and input to device protection control. output options the D2-45057, d2-45157 devices provide four configuration options for the power stage outputs. the power stage configuration is selected by strapping the ocfg0 and ocfg1 pins high or low. these defined configurations include: ? 2 channels of full bridge, 4-quadrant outputs, ? 2 channels of full bridge, 2-quadrant outputs ? 4 channels of half-bridge outputs ? 2 channels half-bridge, plus 1 channel full bridge audio processing routing and cont rol supporting the output stage configurations is defined by the logical high or low strapping of the nerror/cfg0 and pssync/cfg1 pins. audio path definition, audio path output routing, and output stage configurations are automatically se t to one of the four available modes, based on these configuration settings. figure 14. output stage hsbsa high-side pwm drive low-side pwm drive nerror overcurrent hgnd (gnd) low side fet high side fet (+) hvdd out
D2-45057, d2-45157 fn6785 rev 1.00 page 18 of 30 may 5, 2016 pwm audio outputs three pwm outputs provide audio for up to three line-level outputs. audio processing cha nnel assignment is mapped to these pwm outputs, based on the device?s available configuration settings. using only a simple passive filter, the pwm outputs will drive line-level outputs at a nominal 1v rms . with addition of active filter configurations, these can al so drive headphone outputs, or 2v rms or higher line outputs. (alternately, these pwm outputs could also be used to drive powered outputs, using additional power stages on the system design.) control and operation control register summary the control interface provides access to the registers used for audio processing blocks and signal flow parameters. audio input selection (i 2 s input or s/pdif receiver input) and all programmable data elements used in the audio processing paths are controlled through these register parameters, and each parameter is defined with its specific register address. programming details, register identification, and parameter calculations are provided in the dae-4/dae-4p register api specification document. i 2 c 2-wire control interface the D2-45057, d2-45157 device includes a 2-wire i 2 c compatible interface for communicating with an external controller. this interface is usable through either an external microcontroller bus, or for communication to eeproms, or other compatible peripheral chips. the i 2 c interface supports normal and fast mode operation and is multi-master capable. in a D2-45057, d2-45157 system application, it operates as an i 2 c slave device, where the system controller operates as the i 2 c master. reading and writing control registers all reads or writes to registers (shown in figures 15 and 16 ) begin with a start condition, followed by the device address byte, three register address bytes, three data bytes and a stop condition. register writes through the i 2 c interface are initiated by setting the read/write bit that is within the device address byte. write sequence shown in figure 15 on page 19 is described in table 2 . all reads to registers, shown in figure 16 on page 19 , require two steps. first, the master must send a dummy write which consist of sending a start, followed by the device address with the write bit set, and three register addre ss bytes. then, the master must send a repeated start, following with the device address with the read/write bit set to read, and then read the next three data bytes. the master must acknowledge (ack) the first two read bytes and send a not acknowledge (nack) on the third byte received and a stop condition to complete the transaction. the device's control interface acknowledges each byte by pulling sda low on the bit immediately following each write byte. the read sequence shown in figure 16 is described in table 3 . table 2. i 2 c write sequence byte name description 0 device address device address, with r/w bit set 1 register address [23:16] upper 8 bits of address 2 register address [15:8] middle 8 bits of address 3 register address [7:0] lower 8 bits of address 4 data[23:16] upper 8 bits of write data 5 data[15:8] middle 8 bits of write data 6 data[7:0] lower 8 bits of write data table 3. i 2 c read sequence byte name description 0 device address device address, with write bit set 1 register address [23:16] upper 8 bits of address 2 register address [15:8] middle 8 bits of address 3 register address [7:0] lower 8 bits of address 4 device address device address, with read bit set 5 data[23:16] upper 8 bits of write data 6 data[15:8] middle 8 bits of write data 7 data[7:0] lower 8 bits of write data
D2-45057, d2-45157 fn6785 rev 1.00 page 19 of 30 may 5, 2016 control interface address spaces registers are accessed through the i 2 c control interface, using the i 2 c channel address of 0xb2. this establishes the device or product under control through i 2 c communication as the D2-45057, d2-45157. registers and memory spaces are defined within the D2-45057, d2-45157 for specific internal operation and control. the highest-order byte of the register address (bits 23:16) determines the internal address space used for control read or write access, and the remaining 16 bits (bits 15:0) describe the actual address with in that space. programmable settings for the audio processing blocks are internally mapped to the address space defined with the highest order bits all zero. (for exampl e, 0x00nnnn, where nnnn is the address location within this address space.) storing parameters to eeprom the D2-45057, d2-45157 device has the ability to store parameters data to an eeprom. if an eeprom is installed in the application, the programmable parameter data can be saved in this eeprom. this stored data ca n then be recalled upon reset or power-up. serial peripheral interface (spi) the serial peripheral interface (spi) is an alternate serial input port that provides an interface for loading parameter data from an optional eeprom or flash de vice during boot-up operation. the four spi interface pins are all shared functions: ? following a reset condition and while the device is initiating the boot-up process, these four spi pins (tempref/sck, temp1/mosi, vol1/miso, vol0/nss) function as an spi input port for external boot loading operation. ? as soon as the boot-up process is completed and the device begins executing its firmware prog ram, these pins are no longer used for spi functions, and are reassigned by the firmware for use as dedicated-function i/o for amplifier operation. refer to multiple-purpose pin descriptions in table 5 for more description of these pin functions. reset and device initialization the D2-45057, d2-45157 devices must be reset to initialize and begin proper operation. a system reset is initiated by applying a low level to the nreset input pin. external hardware circuitry or a controller within the amplifier sy stem design must provide this reset signal and connect to the nreset input to initiate the reset process. device initialization then begins after the nreset pin is released from its low-active state. the chip contains power rail sens ors and brownout detectors on the 3.3v rvdd and pwmvdd power supplies, and the 1.8v cvdd power supply. a loss or droop of power from these supplies will trigger their brownout detectors which will assert the nrstout output pin, driving it low. the nrstout pin should connect to the nreset input through hardware on the amplifier design, to ensure a proper reset occurs if the power supply voltages drop below their design specifications. at the deassertion of nreset, the chip will read the status of the boot mode selection pins (irqa and irqb) and begin the boot process, determined by the boot mode that is defined by these pins? logic state. these device pins are strapped either high or low on the system?s design (pcb), and it is the state of these pins that is latched into, and defines boot mode operation. figure 15. i 2 c write sequence operation ack device-addr r/w ack register [15:8] ack register [7:0] start ack ack ack ack data [7:0] data [15:8] data [23:16] stop register [23:16] register [7:0] write sequence figure 16. i 2 c read sequence operation ack device-addr r/w ack register [15:8] ack register [7:0] start ack master ack nack data [7:0] data [15:8] data [23:16] stop register [23:16] ack repeat start repeat start device-addr r/w ack master ack step 1 step 2 read sequence
D2-45057, d2-45157 fn6785 rev 1.00 page 20 of 30 may 5, 2016 boot modes the D2-45057, d2-45157 device s contain embe dded firmware to operate the part and run the amplifier system. parameter information that is used by the programmable settings can be written to the device after it is operational and running. however, parameter data can also be read at boot time, allowing saved parameter settings to be used, or allowing amplifier function to be set through a system microcontr oller interface. the device is designed to boot in one of four possible boot modes, allowing control and data to be provided through these boot sources: ?i 2 c slave (to external microcontroller) ?i 2 c eeprom ? internal device rom only ? spi slave the specific boot mode is selected based on the state of the irqb and irqa input pins at the time of reset de-assertion. boot modes and their functions are shown in table 4 . (note: ?boot mode? describes the ?mode? of device initialization with respect to the source of parameter data or start-up control settings. this is not to be confused with ?output mode? or audio processing ?configuration mode? settings that define amplifier-specific functions.) the device initializes as defined by its boot mode. but it gets its configuration and parameter data from the host device. this host device can be either an external controller, or from an eeprom. if a system uses both an external controller and an eeprom, the eeprom will load first, and during this time, the controller must remain off the i 2 c bus until after the reading sequence from eeprom has completed. power supply requirements the device requires operating power for these voltages: ? pwmvdd and rvdd: - 3.3v dc supply voltage. - rvdd operates interface and i/o logic. - pwmvdd is the same voltage, and is used for the pwm outputs and output stage drive. ? cvdd and pllvdd - 1.8v dc supply voltage - cvdd operates the internal processor and dsp core. - pllvdd also operates at th e internal processor voltage levels, but is provided through a separate connection to allow isolation and bypassing for noise and performance improvements. ? ?high voltage? (hvdd[a:d], and vddhv) - hvdda, hvddb, hvddc, and hvddd are the ?high voltage? supplies used for operating each of the four output power stages. - vddhv is used as the source for the on-chip +5v regulator that is used for the output stage drivers. - individual power (hvdd[a:d]) and their corresponding ground (hgnd[a:d]) pins are included for each of the four power stage outputs, providing channel isolation and low impedance source connections to each of the outputs. all the hvdd[a:d]/vddhv pins connect to the same voltage source. high-side gate drive voltage an on-chip bootstrap circuit provides the gate drive voltage used by each output stage. a pin is included for each output channel (hsbs[a:d]) for connection of a capacitor (nominal, 0.22f/50v) from this pin to that channel?s pwm output. drivers for high-side fets on the output stages require a voltage above the supply used for powering that fet. the charge pumping action of the driving pwm to this driver produces this ?bootstrap? voltage, and uses this capacitor to filter and hold this gate drive voltage. this enables amplifier operation without need of connection to an additional power supply voltage. power supply synchronization the the pssync/cfg1 pin provides a power supply synchronization signal for switching power supplies. firmware configures this pin to the frequency and duty cycle needed by the system switching regulator. this synchronization allows switching supplies used with the device to operate without generating in-band audio interferen ce signals that could be possible if the switching power supply is not locked to the amplifier switching. this pssync/cfg1 pin is a shared pin. (refer to multiple-purpose pin descriptions in table 5 on page 23 .) during device reset and initialization, it operates as one of two configuration input pins, where its high or low logic state is used to set the amplifier configuration mode. after completion of reset and when the device firmware begins operating, this pin becomes the pssync output. table 4. boot mode settings boot mode irqb pin irqa pin master/ slave description 000i 2 c slave operates as i 2 c slave, boot at address 0x88. an external 2-wire i 2 c master provides the boot code. 101i 2 c master operates as 2-wire master; loads boot code from rom on i 2 c port. 2 1 0 - internal rom boot/operation 3 1 1 spi slave spi slave. external spi master provides boot code.
D2-45057, d2-45157 fn6785 rev 1.00 page 21 of 30 may 5, 2016 power sequence requirements voltage sensors and brownout detectors monitor supply voltages to the device. the logic and built- in protection of this voltage monitoring prevents operation until all supply voltages are within their specified limits. however, during application of power, the cvdd and rvdd (including pwmvdd) voltages should be brought up together to avoid high current transients that could fold back a power supply regulator. during application of power to the system and while the cvdd voltage (nominal +1.8v) is below its minimum specified limit, the rvdd and pwmvdd supplies (nominal +3.3v) must not exceed the voltage that is present at cvdd. (i.e., if v cvdd < minimum-specified, then v rvdd/pwmvdd must be < v cvdd .) after cvdd has reached its minimum limit, rvdd/pwmvdd can then continue to increase to its normal design (3.3v) value. (pllvdd may be brought up separately.) best practice would be for all supplies to feed from regulators using a common power source. typically this can be achieved by using a single low-voltage supply power source and regulating the 3.3v and 1.8v supplies from that source. also, as noted in the pin specifications of this do cument, all voltages of the same names must be tied together at the board level. reg5v the output stage internal drivers require their own +5vdc supply voltage. an on-chip regulator operates from the vddhv voltage to produce this +5v voltage. the re g5v pin is used for external capacitor connection to filter this regulated voltage. a 1.0f and 0.1f capacitor should be connected to this pin, and the connection should be made as close as practical to the pin. this internal +5v is used only by the output stage drivers. no other connection is to be made to this pin. pin and control block functions i/o control pins several device pins are used as specific-function inputs and outputs to control amplifier and de vice operation. these pins are implemented within the device hardware as general purpose inputs/outputs. however, their operation is not programmable, and their specific function is totally defined by the D2-45057, d2-45157 internal firmware. functions of these pins are defined in the pin definition list, and additional detail is included within the descriptions of the function al blocks where these pins are used. some pins are multiple-purpose, where their functions are defined accordingly by the operational state (e.g., reset, initializing, booting, running) of the D2-45057, d2-45157 device. these multiple-purpose pins and their descriptions and uses are described in more detail in table 5 on page 23 . npdn input pin the npdn pin is a control input that is used to power-down the outputs. when this input is pulled low, all audio outputs turn off and become inactive, internal pwm drive to output stages is turned off, and all output stages float. internal logic and other references remain active during this power-down state. asserting npdn also causes all four nerror[0:3] outputs to pull (active) low. each of the four output stages incorporate their own latching overcurrent hardware shutdown logic, in addition to the separate protection events that occur th rough firmware control from an overcurrent condition. firmware protection control will perform other steps to clear this hardware latched shutdown, although asserting npdn will also reset the hardware-latched state. the npdn pin is active low, and inactive when at logic high level. in normal operation, it is held high with pull-up to the rvdd supply. nerror[0-3] output pins each of the four output stages includes a two-level overload and overcurrent monitor. an overcurrent or overload condition asserts the nerror output for that channel. also, an undervoltage condition for the voltages used by the output stages (hvdd[a:d]/vddhv, reg5v, pwmvdd), or assertion of npdn, will cause all four nerror outputs to assert. the nerror pins are open drain, active-low, and can be wire-or connected together. depending on the output mode configuration where more than one output stage may be used for an audio channel, nerror pins associated with that audio channel are connected together to provide monitoring status. in applications where multiple power stage outputs are defined for an audio channel, the nerror pins for these power stages would be tied together, and also tied to the protect input pin associated with that audio channel. refer to table 6 on page 24 , that shows these connections for the different configuration modes. iref pin the iref pin is used to set the overcurrent and overload monitoring threshold. th e design requires a 100k resistor to connect from this pin to ground. configuration assign ment pin differences there are two pairs of pins used for configuration assignments. both pin pairs are used for the assignment, and their settings must both match their requirements for the configuration mode. these pin pairs are: ?ocfg0, ocfg1: define the output stage topology and operation of the output configuration. ? nerror/cfg0, pssync/cfg1: de fine the audio processing and amplifier control supportin g the output configuration. ocfg0, ocfg1 input pins these two pins define the configuration of the four output stages. they are logic level input pins, and are connected to logic high (pwmvdd) or logic ground (pwmgnd) to establish which of the four output configurations is used in the design. refer to ?pin description? starting on page 9 for additional reference and definition.
D2-45057, d2-45157 fn6785 rev 1.00 page 22 of 30 may 5, 2016 nerror/cfg0 and pssync/cfg1 pins these pins define the amplifie r configuration mode that the firmware uses in operating the amplifier. in addition to the ocfg0 and ocfg1 pins that set operation of the output stages, these nerror/cfg0 and pssync/cfg1 pins also establish audio signal processing path a ssignments and set up monitoring and protection for the configurat ion mode. the configuration pin logic levels are assigned by pull-up or pull-down resistors installed on that application. the configuration defined by thes e pins is assigned when the D2-45057, d2-45157 device exits its reset state, when at that time, the logic status of these pssync/cfg1 and nerror/cfg0 pins are latched into internal device registers. these are shared-function pins, and after fi rmware begins executing, their functions are reassigned as outputs. refer to table 5 on page 23 for further description on these pins and their shared functions. temperature monitoring the tempref/sck, temp1/mosi, and tempcom/tio0 pins are used in a firmware-controlled algorithm to monitor temperature. these pins share other functions (refer to multiple-purpose pin descriptions in table 5 on page 23 ) and during firmware execution, operate as inputs an d outputs for this measurement algorithm. figure 17 shows the circuit for this temperature measurement implementation. a ntc (negative temperature coefficient) 100k resistor connects to the temp1/mosi pi n, and using the resistor?s temperature/resistance correlation, the firmware monitors temperature of the ntc resistor. the internal device timing functions associated with the ti o0 pin provide calibration that correlates to system clock. a 49.9k resistor connects to the tempref/sck pin and is used as a constant non- temperature-dependent reference for this algorithm. the firmware algorithm is internal to the D2-45057, d2-45157 device. status from this temperature monitor is used for the temperature protection functi ons of the device and its application. there are no ad justments or parameters for changing settings. figure 17. temperature monitor circuit 100k 49.9k 10 0.1f temp1/mosi tempref/sck tempcom/tio0
D2-45057, d2-45157 fn6785 rev 1.00 page 23 of 30 may 5, 2016 configuration setting the configuration mode is assigned through two pairs of pin settings. when the D2-45057, d2-45157 device exits its reset state, the logic status of th e pssync/cfg1 and nerror/cfg0 pins is latched into internal device registers. during this initialization time, these pins operate as logic inputs. after completion of the initialization and the internal firmware begins executing, these pins are re-assigned as outputs for their shared functions, and the internal latc hed logic state that defines the configuration mode remains until the device is powered down or reset again. the ocfg0 and ocfg1 pin status is not latched; those pins are to remain in their pull-up or pull-down state. selection of one of the four configuration modes is defined by strapping the configuration pins high or low: ? ocfg0 and ocfg1, to define the output power stage configuration; ? and nerror/cfg0 and pssync/cfg1 pins to define the amplifier and channel configuration these four pins are connected to either a high (+3.3v) level or low (ground = 0) level. connection should be through a 10k resistor, and not directly to supply or ground. table 6 on page 24 shows the audio processing channel assignment, audio content, and output assignments for each of the four configuration modes. ? both pairs of configuration setting pins (ocfg0, ocfg1) and (pssync/cfg1, nerror/cfg0) must be used and both must be set to the same configuration mode. in modes 2 and 3, the filtering for high and low pass crossovers is applied to the audio signal flow path, enabling the appropriate high or low pass content to be properly filtered for the pwm output channels. table 5. multi-function i/o control pin assignment and operation pin name pin state during initialization pin state during operation connection reference i/o function i/o function tempref/ sck output spi cock output. input temperature monitor reference. used for temperature monitoring algorithm. typical connection is to 49.9k resistor as temperature monitor reference. available for spi connect if spi is used in application. vol1/ miso input or output spi master input or slave output. function (master or slave) determined by nss input state. input volume control phase-b input. used for monitoring rotary- encoder volume control. typical connection to +3.3v with 10k pull-up resistors, and to 2-bit volume control encoder. temp1/ mosi output or input spi master output or slave input. function (master or slave) determined by nss input state. i/o temperature monitor reference i/o pin. used for temperature monitoring algorithm. typical connection is to 100k ntc resistor as temperature monitor reference. available for spi connect if spi is used in application. nerror/ cfg0 input (cfg0) configuration mode input select. uses pull-up or pull-down to set logic input level, to define one of 4 amplifier configurations. output active-low output amplifier protection and monitoring status indication. connects to +3.3v or to ground with 10 k resistor, to select logic high or low for setting configuration. also connects to input of monitor or indicator circuit to provide status. (referenced as ?pstemp? on some reference designs.) pssync/ cfg1 input (cfg1) configuration mode input select. uses pull-up or pull-down to set logic input level, to define one of 4 amplifier configurations. output sync output for synchronizing on- board power supply regulator. connects to +3.3v or to ground with 10k resistor, to select logic high or low for setting configuration. also connects to clock sync input of on-board switching regulator. (referenced as ?pscurr? on some reference designs.) vol0/ nss input spi slave select. input volume control phase-a input. used for monitoring rotary- encoder volume control. typical connection to +3.3v with 10k pull-up resistors, and to 2-bit volume control encoder.
D2-45057, d2-45157 fn6785 rev 1.00 page 24 of 30 may 5, 2016 table 6. configuration mode and channel assignments mode configuration description output cfg pins config mode pins audio proc channel audio content power stage outputs nerror[0:3] to protect[0:2] pwm line outputs ocfg1 ocfg0 pssync /cfg1 nerror /cfg0 outa outb outc outd linel liner sub line ?00? 2-channel 4-quad full bridge (3-level) 00 0 0 1 l spkr left full bridge nerror0 +nerror1 to prot0 2r spkr right full bridge nerror2 +nerror3 to prot1 3protect2 unused (tie high) 4 5 ?01? 2-channel 2-quad full bridge + l line + r line + sub line 01 0 1 1 l spkr left full bridge nerror0 +nerror1 to prot0 2r spkr right full bridge nerror2 +nerror3 to prot1 3l line protect2 unused (tie high) left 4r line right 5sub sub ?10? 2-channel half bridge + 1-channel full bridge for sub,+ l line, + r line 10 1 0 1 l spkr left hb nerror0 to prot0 2r spkr right hb - nerror1 to prot1 3 l line left 4r line right 5 sub ch 5 sub full bridge nerror2 +nerror3 to prot2 ?11? 4-channel half bridge 2.2 bi-amp 11 1 1 1 l hf spkr left hf (hb) nerror0 to prot0 2l lf spkr left lf (hb) nerror1 to prot1 3r hf spkr right hf (hb) nerror2 to prot2 4r lf spkr right lf (hb) nerror3 to prot2 5 note: lf = low frequency, hf = high frequency for bi-amp config; hb = half-bridge
D2-45057, d2-45157 fn6785 rev 1.00 page 25 of 30 may 5, 2016 protection the D2-45057, d2-45157 device includes multiple protection mechanisms. output overload an d overcurrent status for each output power stage provides two levels of monitoring. temperature monitoring provides two levels of temperature status. on-chip undervoltage detect ion is included for all supply voltages. several strategies are provided in the D2-45057, d2-45157 to prevent damage from the high voltages, currents, and temperatures present in class-d amplifiers. this protection is also effective against user-induced faults such as clipping, output overload, or output shorts, including both shorted outputs or short-to-ground faults. protection includes events such as: ? output overcurrent ? output short circuit ?over-temperature ? power supply brown-out ?shoot-through overcurrent certain levels of protection are managed using on-chip hardware. other protection is integrated into device firmware, and involves actions to: ? shut down the outputs for a short circuit, over-temperature, or undervoltage event. ? shut down the device if power supply sensors detect voltages dropping below their design thresholds. ? providing both indication, and device shutdown if needed for overload and overcurrent monito rs detection. dual threshold monitors provide two levels of high current conditions. ? chip temperature monitoring prov ides dual threshold status of high temperature conditions, providing both indication, and device shutdown if needed. error reporting internal monitoring of system an d device operation uses an i/o pin (nerror/cfg1) as an output to signal an external system controller of a channel shutdown er ror condition. this output may be used to turn on a simple indicator. the error output is also used to signal an external microcontroller that the i 2 c bus may be busy. when the error output is low during system initialization, the i 2 c bus is busy as a master device. this error output is active low and only becomes used as an error reporting output after the device firmware has initialized and began running. this same pin is shared as an input. (refer to table 5 on page 23 for further description on shared-function pins.) during a reset condition, this pin operates as an input, and is one of two input pins that are used to define the configuration mode. a resistor pull-up or pull-down on this pin establishes this mode input configuration state. after completion of the initialization sequence, these resistors do not affect the error output operation. short-circuit and overcurrent sensing each pwm output fet includes a dual-threshold overcurrent sensor. multiple functions occu r depending on detection of overcurrent conditions: ? the lower threshold is used to monitor fault conditions such as shorts or overloads on the loudspeaker outputs. ? the higher threshold monitors fault conditions of the pwm output pin. ? the nerror output asserts for the channel detecting the fault. ? for the lower level threshold, nerror remains asserted only through the duration of the overcurrent event. ? for the higher level threshold, the output is shut down, and its nerror output is asserted, and these remain latched until the controller acknowledges the fault event by turning off the channel?s pwm drive. (when shutdown, the pwm output pin floats.) hysteresis is built into the overcurrent detectors to suppress pwm switching transient events. protection monitoring and control these overcurrent detectors generate either a pulse or latched logic level (depending on low or high threshold) upon detection of high current. detector status is presented to the nerror[0:3] pins. the protect[0:2] pins are used as protection inputs to the firmware. firmware action based on these pins? status depends on the selected output mode configuration. the nerror[0:3] output pins and the protect[0: 2] input pins are connected together based on the particular system and output mode configuration, as shown in table 6 on page 24 . thermal protection and monitors an temperature sensing provides two thresholds of temperature monitoring. if the device reaches the lower th reshold, a warning indication is generated, and triggers one level of thermal protection management. on-chip hardware thermal protecti on shuts down the device upon a high-threshold temperature condit ion. if the device reaches the higher threshold, on-chip hardware latches and shuts down all four output stages. it also drives all four nerror0-3 outputs low (active) providing this shut-down status to the firmware through their connected protect0-2 inputs. graceful overcurrent and short-circuit hard faults from overcurrent or sh ort-circuit conditions shut down the outputs. high-threshold over-temperature also causes a shutdown. for lower-threshold event detections, graceful protection is provided for each output. specific operation depends on type and severity of the detected event, but action taken is to reduce conditions that would contribute to the event, without the severity of a complete shut-down as in a high-limit fault condition.
D2-45057, d2-45157 fn6785 rev 1.00 page 26 of 30 may 5, 2016 overcurrent monitoring status is presented to the protect0-2 inputs, from per-output detector status that drives the nerror0-3 outputs. overcurrent detection algorithms in firmware monitor these peak level detections, and upon detection of an overload condition, automatically reduce pwm gain. this automatic gain control (agc) action aids to prevent clipping of audio output, as well as avoiding related excessive-level conditions. the agc algorithm operation functions through a stepped-changing of pwm gain reduction, corresponding to characteristics and time-event dete ction of overloads. at the lower (non shut-down) high-temperature threshold, the agc function also acts to attenuate the outputs to attempt to reduce temperature. output level gain and level change effects from this agc function are similar to operation from a compressor. however, unlike a compressor where characteristics ar e determined by input levels, the pwm agc operation is controlled through detection of near-overload output levels or from high temperature detection. power supply voltage monitoring undervoltage sensors and brownout detectors monitor all supply voltages to the device. the logic and built-in protection of this voltage monitoring prevents oper ation until all supply voltages are within their specified limits. also, if any of these monitored voltages drop below their threshold, the device shuts down its outputs and asserts all four of the nerror outputs. audio processing the audio processing, signal fl ow, and system definition is defined by the D2-45057, d2-4 5157 device internal rom firmware, and executed by the dsp. this firmware defines the audio flow architecture, which includes the audio processing blocks. each of these blocks are programmable, allowing for adjustment of their audio-controlling parameters. the signal flow and audio processing blocks are shown in figure 18 . this architecture includes audi o processing functions of: ? input selection ?mixers ? input compressors and output limiters ?tone controls ? 5-band and 3-band parametric equalizers ?router ? high/low-pass crossover filters ? volume and output level controls ? loudness contour enhancement audio processing is also used. depending on which device, (D2-45057 or d2-451 57) either the d2audio soundsuite? or dts?(srs) wow/ hd? algorithms are included. audio processing signal flow blocks input selection the input select register specifies the audio inputs that are assigned to the audio processi ng input path. either the i 2 s or s/pdif digital inputs are available. mixers an input mixer provides a two-input, two-output mixing and routing path. either input can be mixed at adjustable gain into either or both of the two output s. default setting is 0db through each channel, with full cut-off for non-through channels. attenuation is continuously va riable with the programmable parameters. a stereo mixer provides a path from the two input channels. this typically is used to provide a mix of both stereo input channels for crossover processing and becoming the source for the subwoofer channel. gains for both input channels are adjustable to feed the single stereo mixer output. tone controls a tone control block is included in both of the two input channels. each of the filters (bass or treble) is implemented with a first- order (6db/octave) roll-off, using programmable corner frequency and a boost or attenuating gain. the signal flow processing automatically provides a smooth transition between tone control changes.
fn6785 rev 1.00 page 27 of 30 may 5, 2016 D2-45057, d2-45157 figure 18. D2-45057, d2-45157 audio signal flow [ 0l[hu 7rqh %dqg(4 &rpsuhvvru ',*,7$/ ,qsxw6hohfw 63',) 'ljlwdo,qsxw [ 0l[hu 6shdnhu (4 [ 5rxwhu /lfhqvhg $xglr 3urfhvvlqj $ojrulwkp * (see note) s/pdif 2 src i 2 s digital input compressor 2 tone 2 5 band eq 2 speaker eq 2 hp 1 lp 1 hp 2 lp 2 hp 3 lp 3 hp 4 lp 4 hp 5 lp 5 3 band eq 1 3 band eq 1 3 band eq 1 3 band eq 1 master volume control loudness 1 loudness 2 loudness 3 loudness 4 loudness 5 limiter 1 limiter 2 limiter 3 limiter 4 limiter 5 volume 1 volume 2 volume 3 volume 4 volume 5 crossovers 5 4 3 2 1 5 4 3 2 1 * note: device-dependent licensed audio processing algorithm sup porting d2audio soundsuite?, or srs wow/hd ? . refer to device ordering information for part number specifying each algorithm. pwm channel driver mapping output a configuration settings output b output c output d left line out right line out sub line out output stage channel assignment and amplifier topology is pr ogrammed with configuration pin settings. four output modes are available wit h combinations of 4- and 2- quadran t full bridge, a nd half bri dge operation for outputs a-d. line and subwoofer output channel assignment is also establishe d by output mode configuration settings.
D2-45057, d2-45157 fn6785 rev 1.00 page 28 of 30 may 5, 2016 compressors and limiters two individual input compressors are included in the input audio path, one for each of the two input channels. five output limiters are also included in the five output path channels. the compressor and limiter blocks operate identically, and their parameter settings allow independent control of the audio signals. typically, the input path blocks are programmed to provide a compression function, and the output path blocks are programmed to limit output si gnal levels. but each can be programmed as needed. each compressor/limiter has configurable compression ratio, threshold, attack and release time, as well as makeup gain. multi-band equalizers three sets of multi-band parametric equalizers are included in the audio signal processing path. each band of the equalizers provides for independent gain, frequency, and q-factor programming. a 5-band equalizer and a speaker equalizers (seq) are included in both of the two input channels. four 3-band equalizers are also located in the four output channels. stereo router a 4x4 stereo router is used to assign any one of the 4 input channel paths to each of the 4 output paths. the router performs path assignment only. it does not have provision for gain or signal level adjustment. high/low-pass crossover filters high-pass and low-pass filter blocks are provided for each of the 5 output channels downstream of the router and stereo mixer. these provide a flexible crossover function for all the output channels, including provision for defining the subwoofer channel?s frequency response. the high and low pass blocks operate together, and are implemented as a total of 4 cascaded elements, with 2 each of the elements allocated for high pass, and the other 2 elements allocated for low pass functionality. complete flexibility allows each element to be optionally defined for either high or low pass. each element is selectable for a slope of 6, 12, 18, or 24db, or may be or bypassed. three filter types of butterworth, bessel, or linkwitz-riley implem entations can also be chosen. master volume control a software-controlled master volume control is used to adjust the global volume for all 5 output ch annels. master volume operates a continuously adjustable attenuator, from unity gain, down to -100db and cutoff. each of the 5 output channels have their own dedicated output level adjustments, providing individual channel gain or attenuation after the output li miter stages. settings provide output level adjustment from +12db to -100db. loudness contour an individual software-controlled loudness contour is included for each of the 5 amplifier output channels. the loudness contour curve is customized to allow for dynamically and automatically enhancing the freq uency response of the audio program material relative to the master volume level setting. the loudness contour models the frequency response correction as defined by the fletcher/munson audio response curve. it provides for amplitude or volume changes to those signals to which the ear does not respond equally at very low listening levels. soundsuite? processing the d2audio soundsuite? audio processing provides a full set of enhancements to audio that greatly add to the quality and listening experience of sound in wide scopes of consumer devices. the d2audio soundsuite? algorithms use psycho-acoustic processing that create a rich-sounding environment from small speake rs, and synthesizes the sound and quality equivalent to more co mplex systems. it is especially suited to consumer products that include televisions, docking stations, and mini hi-fi stereo products. soundsuite processing includes: ? d2audio? widesound? - an advanced two-channel image field enhancement ? d2audio? deepbass? - a sophisticated bass enhancem ent using psycho-acoustics and dynamic filtering ? d2audio? audioalign? - sound positioning and alignment to the video display ?d2audio? clearvoice? - enhancement of vocal clarity the d2audio soundsuite? algorithms are completely included within the d2-41051 dae-4 devices.
fn6785 rev 1.00 page 29 of 30 may 5, 2016 D2-45057, d2-45157 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . disclaimer for dts?(srs) technology license required notice: notice of license requirement: supply of this implementation of dts technology to dts product licensees directly or through a distributor does not incur a royalty payment or convey a license, exhaust dts? rights in the implementation, or imply a right u nder any patent or any other industrial or intellectual property right of dts to use, offer for sale, sell, or import such implementatio n in any finished end-user or ready-to-use final product. a license from and royalty payment to dts is required prior to and for such us e. revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go to web to make sure you have the latest rev. date revision change may 5, 2016 fn6785.1 updated entire datash eet applying intersil?s new standards. updated the ordering information table on page 2. replaced products verbiage to about intersil verbiage. added dts disclaimer. july 29, 2010 fn6785.0 initial release
D2-45057, d2-45157 fn6785 rev 1.00 page 30 of 30 may 5, 2016 package outline drawing l68.10x10c 68 lead quad flat no-lead plastic package rev 0, 04/09 located within the zone indicated. the pin #1 indentifier may b e unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.23mm and 0.28mm from the terminal tip. dimension b applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view package outline (4x) 0.15 index area 6 pin 1 6 a b 1 68 52 51 c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 1.00 max 0.08 0.10 c 10.00 10.00 10.00 4 x 8.00 68 x 0.55 0.10 68 x 0.25 64 x 0.50 68 x 0.25 68 x 0.20 68 x 0.55 max 0.05 min 0.00 7.70 exposed pad 7.70 64 x 0.50 see detail x seating plane c c pin #1 index area

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