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november 2014 ? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving features ? excellent dimmer compatibility by active dimming control ? programmable dimming curve and input current management ? constant led current regulation in large phase angle range ? cost-effective solution without input bulk capacitor and feedback circuitry ? accurate constant-current (cc) control, independent on line voltage, output voltage, magnetizing inductance variation ? power factor correction (pfc) ? fast startup utilizing bleeding circuit ? open-led protection ? short-led protection ? sensing resistor short protection ? cycle- by -cycle current limiting ? over-temperature protection with auto restart applications ? led lighting system description the FL7734 is a highly integrated pwm controller with advanced primary-side-regulation (psr) technique to minimize components for low power led lighting solutions. using the innovative truecurrent ? technology for tight constant-current control, it enables designs with constant-current (cc) tolerance of less than 1% in the wide line voltage range to meet stringent led brightness requirements. FL7734 can operate with all types of phase cut dimmers. phase cut dimming is managed smoothly by fairchild s proprietary constant input current control and bleeding current control to achieve excellent dimmer compatibility without visible flicker. the controller can automatically detect whether there is a dimmer connection. in non dimming mode, the operating mode is set to optimize power factor and thd by enabling linear frequency control and voltage mode based on dcm. an external high-voltage bleeding circuit is utilized to implement fast startup and high system efficiency. the FL7734 also provides powerful protections, such as led open / short, sensing resistor shorted, and over- temperature for high system reliability. the FL7734 is available in 16-pin small-outline package (sop). related resources FL7734 product folder ordering information part number operating temperature range package packing method FL7734 mx - 40 c to +125c 16 -lead, small outline package (sop- 16 ) tape & reel
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 2 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving application diagram mod dim fb rbld cs pg vdd gate vin hold tcic FL7734 bld mbld vs sg bias figure 1. typical application internal block diagram 9 vin 5 dim 6 fb 2 tcic 4 hold 13 cs i tcic i hold 11 bld error amp. truecurrent ? calculation 1 vs linear frequency controller line compensation osc s r q gate driver 14 gate 10 rbld active dim control 12 bias 16 vdd 8 sg 3 mod vdd.on 10.6 v / 7.75 v short led protection open led protection vdd over-voltage protection thermal shutdown over-current protection sensing resistor short protection protections auto-recovery mode 7 mbld 15 pg v eai v eai phase angle detection biasing management figure 2. functional block diagram
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 3 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving marking information zxytt tpm 7734 figure 3. top mark pin configuration vs tcic mod hold vdd pg cs 12 3 4 gate dim fb mbld bias rbld 56 7 bld sg vin 8 14 13 11 12 10 16 9 15 figure 4. pin configuration pin definitions pin # name description 1 vs voltage sense . vs pin detects the output voltage for linear frequency control a nd discharge time for output current regulation. vs voltage detection protects led op en and short conditions. 2 tcic constant input current . tcic manages switching mode control. 3 mod modulation . min. fb is clamped by mod voltage. 4 hold holding current . external hold resistor sets the level of constant input current. 5 dim phase angle sense . dim voltage indicates the amount of phase angle. it is the referen ce voltage of the error amplifier in the feedback loop. 6 fb feedback . fb is the output of the error amplifier. 7 mbld maximum bleeding . resistor connected to mbld determines maximum bleeding current. 8 sg signal ground . 9 vin input voltage sense . vin pin detects input voltage for phase angle detection. 10 rbld bleeding control resistor . rbld current set by external resistor decides the amount of bleeding current. 11 bld bleeding control . bld flows current into rbld. 12 bias bleeding circuit bias . external bleeding switch is biased by an internal clamping circuit via bias pin . 13 cs current sense . cs pin connects a current-sense resistor to detect the mosfet current for the output current regulation. over-current protection and sensin g resistor short protection are triggered by this pin. 14 gate pwm signal output . gate driver in this pin switches power mosfet. 15 pg power ground . 16 vdd power supply . connects to a decoupling capacitor. ic operating current and mosfet driving current are supplied from this pin. f : fairchild logo z: plant code x : 1-digit year c ode y : 1-digit week c ode tt: 2-digit die run code t: package type (m=sop) p : z : pb free, y: green package m: manufacture flow code
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 4 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving absolute maximum ratings stresses exceeding the absolute maximum ratings may dama ge the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the reco mmended operating conditions may affect device reliability . the absolute maximum ratings are stress ratings only. symbol paramet er min. max. unit v vdd dc supply voltage (1,2) -0.3 30 v v dim dim pin input voltage -0.3 6.0 v v m od m od pin input voltage -0.3 6.0 v v hold hold pin input voltage -0.3 6.0 v v tcic tcic pin input voltage -0.3 6.0 v v fb fb pin input voltage -0.3 6.0 v v rbld rbld pin input voltage -0.3 6.0 v v bias bi as pin input voltage -0.3 30 .0 v v bld bld pin input voltage -0.3 30 .0 v v mbld mbld pin input voltage -0.3 6.0 v v vs vs pin input voltage -0.3 6.0 v v cs cs pin input voltage -0.3 6.0 v v gate gate pin input voltage -0.3 30 .0 v v vin vin pin input voltage -0.3 30.0 v p d power dissipation (t a 50 c) 909 mw ja thermal resistance (junction to air) 1 10 c /w t j maximum junction temperature 1 50 c t stg storage temperature range - 55 150 c t l lead temperature (soldering, 10 seconds) 260 c esd electrostatic discharge capability human body model, ansi/esda/jedec js-001-2012 5 kv charged device model, jesd22-c101 2 notes: 1. stresses beyond those listed under absolute maximum rating s may cause permanent damage to the device. 2. all voltage values, except differential voltages, are given with re spect to the gnd pin. recommended operating conditions the recommended operating conditions table defines the condi tions for actual device operation. recommended operating conditions are specified to ensure optimal perfo rmance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum rating s. symbol parameter min. max. unit t a operating ambient temperature - 40 125 c
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 5 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving electrical characteristics v dd = 20 v and t j =-40 ~ 125c unless otherwise specified. symbol parameter condition min. typ. max. unit vdd section v dd - on turn-on threshold voltage 9.1 10 .6 12.1 v v dd -off turn-off threshold voltage 6.75 7.75 8.75 v i dd - op operating current c load =1 nf 4 5 6 ma i dd - st startup current v dd =6 v - 2 10 a v dd - ov p v dd over-voltage-protection 25 27 29 v v bias-vdd-off bias clamp voltage at vdd-off v in (3) = 30 v, r bias = 20 k ? 21.3 24.4 27.5 v v bias-vdd- on bias clamp voltage at vdd- on v in (3) =30 v, r bias =20 k ? 17.6 19.5 21.4 v gate section v ol output voltage low i gate =-1 ma 1.5 v v oh output voltage high i gate =+1 ma , v dd = 10 v 5 v i source peak sourcing current (4) 60 ma i sink peak sinking current (4) 180 ma t r rising time c load =1 nf 100 150 200 ns t f falling time c load =1 nf 20 60 100 ns v gate-clamp gate clamp voltage v dd = 20 v 12 15 18 v oscillator section f d operating frequency at d.mode t j =25c 65 70 75 khz f nd -max max. frequency at nd.mode t j =25c 65 70 75 khz f nd -min min. frequency at nd.mode t j =25c 26 29.5 33 khz t on -max maximum turn-on time t j =25c 10.4 12.4 14.4 ? s t on -min minimum turn-on time (4) v fb =0 v 6 00 ns current sense section t leb leading-edge blanking time (4) 3 00 ns t pd propagation delay to gate 50 100 150 ns v cs /i vs line compensation ratio (4) 21.5 v /a voltage sense section t dis-bnk t dis blanking time at vs sampling (4) 1.5 s i vs -bnk vs current for vs blanking 67 80 93 a v vs -clamp vs clamping voltage i vs =1 ma -0.1 v i vs = 10 a 0.35 v notes : 3. v in is external voltage source and r bias is connected between v in and bias pin. 4. this parameter, although design-guaranteed, is not tested i n production.
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 6 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving electrical characteristics v dd = 20 v and t j =-40 ~ 125c unless otherwise specified. symbol parameter condition min. typ. max. unit feedback section g m transconductance 14 18 22 mho ? i fb -sink fb sink current t j =25c, v eai =2 v, v fb = 2. 5 v 14 18 22 a i fb -source fb source current v eai =0 v, v fb = 2. 5 v 14 18 22 a v fb -hgh fb high voltage (4) 4. 7 v v fb -low fb low voltage (4) 0.1 v ? start sequence section t ss1 -min minimum start sequence time 1 10.8 12.0 13.2 ms t ss3 -min minimum start sequence time 3 13.5 15.0 16.5 ms v fb -adj- ndm fb adjustment voltage in nd.mode 1.26 1.40 1.54 v protection section v cs -high- cl high current limit threshold 1.08 1.20 1.32 v v cs -low- cl low current limit threshold 0.15 0.20 0.25 v v cs -ocp over current protection voltage 1. 8 v v vs -low- cl -h low current limit h ys . voltage 'h' (4) 0.45 0.50 0.55 v v vs -low- cl -l low current limit h ys . voltage 'l' (4) 0.35 0.40 0.45 v v vs-slp- th vs threshold voltage for slp 0.35 0.40 0.45 v v vs -ovp vs threshold voltage for ovp 2.9 3.0 3.1 v t ar -delay auto restart delay time (4) 4.0 s v cs -srsp cs threshold voltage for srsp 0.05 0.10 0.15 v t otp threshold temperature for o tp (4)(5) 150 o c t otp-h ys junction temperature hysteresis (4) 10 o c dimming control section i dim dim sourcing current v dim =3 v 36 40 44 a v vin-dim dim current on/off voltage (4) 3.00 v v dim-clamp dim clamping voltage 3.25 v k hold hold conversion coefficient t j =25c, v cs =0.5 v, r hold =31.5 k ? 510 /ma i hold hold sourcing current v hold =3.5 v 36 40 44 a i tcic tcic sourcing current 13.5 15 .0 16.5 a v tcic-min-dis minimum tcic discharging voltage 0.9 1.0 1.1 v v rbld-clamp clamped rbld voltage v vin =5 v, r rbld =4 0 ? 0.45 0.50 0.55 v i mbld mbld current v mbld =3.5 v 36 40 44 a note: 5. if over-temperature protection is activated, the power system enters auto recovery mode and output is disabled. device operation above the maximum junction temperature is not guaranteed .
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 7 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving typical performance characteristics normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 figure 5. v dd - on vs. temperature figure 6. v dd -off vs. temperature normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 figure 7. i dd - op vs. temperature figure 8. v dd -o vp vs. temperature normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 figure 9. f nd -max vs. temperature figure 10. f nd -min vs. temperature
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 8 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving typical performance characteristics normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 figure 11. f d vs. temperature figure 12. v cs -high- cl vs. temperature normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 figure 13. v vs -slp- th vs. temperature figure 14. v vs -ovp vs. temperature normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 normalized to 25 oc temperature ( oc ) 0.5 0.7 0.9 1.1 1.3 1.5 - 45 - 30 - 15 0 25 50 70 90 110 130 figure 15. k hold vs. temperature figure 16. i hold vs. temperature
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 9 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving functional description FL7734 is a phase-cut dimmable pwm controller for led lighting applications. accurate led current regulation independent of input voltage, output voltage and magnetizing inductance variations is implemented by truecurrent ? technique . the controller features programmable dimming curve which ensures that the constant maximum led current can be met at the various maximum phase angle conditions of each dimmer and low led current can be set at the minimum phase angle condition with wide dimming range. fairchild s proprietary constant input current control provides excellent dimmer compatibility by maintaining input current higher than triac holding current. th e linear frequency control and dcm operation with minimized turn-on time ripple implements best power factor and thd in a single-stage topology. a variety of protections; such as short-led protection , open-led protection, sensing resistor open/short protection, over- temperature protection, and cycle- by -cycle current limitation stabilize system operation and protect external components. startup an external bleeding mosfet is utiliz ed for fast startup. once power is on, bias voltage is quickly lifted to v bias- vdd-off (24.4 v) so the bleeding mosfet can charge the vdd capacitor higher than v dd - on voltage (10.6 v). once v dd is higher than v dd - on , startup sequence (ss1) begins with maximum bleeding current to stabilize dimmer operation. ss1 ends when v in reaches the line voltage zero crossing after t ss1 -min (12 ms). 0.2 v v cs v fb v in i led time power on v dd ss1 v dd-on 1.4 v ss2 ss3 *ss = startup sequence t ss1-min t ss3-min figure 17. startup sequence during ss2 which is defined as a half line period, FL7734 determines whether phase-cut dimmer is connected in the line. from ss3, internal operation is set as either dimming mode or non-dimming mode. ss3 time is set longer than t ss3 -min which is counted except for phase-cut time and finishes synchronized with v in zero crossing. 0.2 v current-mode is activated during ss3 so that output voltage reaches a level higher than threshold for short-led protection, which is enabled after ss3. in the mean time, fb voltage is clamped to 1. 4 v at non-dimming mode or a certain level proportional to phase angle at dimming mode to set the voltage closer to steady-state level. the maximum bleeding current is disabled after ss3 and voltage mode control is enabled at non-dimming mode and constant input current control is enabled at dimming mode. constant-current regulation the output current is estimated using the peak drain current and inductor current discharge time because output current is same as the average of the diode current in steady-state. the peak value of the drain current is determined by the cs pin. the inductor discharge time (t dis ) is sensed by a t dis detector. using three sources of information; peak drain current, inductor discharging time, and operating switching period, the truecurrent ? block calculates the estimated output current. the output of the calculation is compared with an internal precise reference to generate an error voltage (v fb ). with fairchilds innovative truecurrent ? technique, constant led current can be precisely controlled. constant input current control fairchild s proprietary constant input current (cic) control generates switching duty to form input current proportional to the external resistor value at hold pin . filtered switch current is the system input current and the system input current is adjusted by the calculation of cs average voltage. input current is determined by equation (1) where k hold is coefficient of internal calculation. (1) fairchild s cic control offers superior accurate and stable current managemen t than other input current control technologies. dimming control phase angle is detected by comparing vin voltage and 3 v threshold voltage (v vin-dim ). when vin voltage is higher than 3 v, dim sourcing current (i dim ) is connected to the dim pin and the current flows into external resistors (r dim1 and r dim2 ) and capacitor (c dim ). therefore, the dim voltage filtered by c dim indicates the amount of phase angle controlled by phase-cut dimmer. (2)
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 10 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving as a function of dimming reference modulation shown in figure 18 , output current is constantly regulated with constant v ref when v dim is higher than 3 v and v ref is set lower than v eai (truecurrent ? calculation result) when v dim is lower than 2. 25 v. once v dim is less than 2. 25 v, the error amplifier always pulls down current in the output and fb voltage is clamped by mod voltage so that open loop control starts for stable led current control at low phase angle range. i dim v vin-dim (3 v) input voltage vin r vin1 r vin2 v dim-clamp (3.25 v) c dim r dim1 dim r dim2 mod fb c fb dimming reference modulation v eai error amp. v ref figure 18. dimming control high dimmer compatibility is implemented by bleeding current generated through bld to rbld and having the switching mode management by tcic. pfc and thd in a conventional boost converter, boundary conduction m ode (bcm) is generally used to keep inp ut current in phase with input voltage for power factor (pf) and total harmonic distortion (thd). however, bcm switching distorts input current in the single stage flyback / buck boost converter because power inductor current is not the same as input current. moreover, it becomes more difficult to meet pf and thd once passive bleeder (resistor and capacitor in the driver input) is added for successful firing in the single stage triac dimming system. i in i in_avg gate constant frequency figure 19. pfc control in dcm in order to optimize pf and thd in the single stage flyback topology, constant turn-on time and constant frequency in discontinuous conduction mode (dcm) are the best method to make the input current proportional to the input voltage as shown in figure 19. FL7734 basically adopts the dcm operation with constant turn-on and frequency in a half line cycle. once dimmer absence is detected during startup sequence, FL7734 selects voltage mode in which constant turn-on time is maintained by an internal error amplifier and a large external capacitor (typically >1 f) at the fb pin. constant frequency and dcm operation are managed by linear frequency control. linear frequency control dcm should be guaranteed for high power factor in flyback topology. to maintain dcm in the wide range of output voltage, frequency is linearly adjusted by output voltage in linear frequency control. output voltage is detected by auxiliary winding and resistive divider connected to the vs pin, as shown in figure 20. when output voltage decreases, secondary diode conduction time is increased and the linear frequency control lengthens switching period, which retains dcm operation in the wide output voltage range . the frequency control lowers primary rms current for better power efficiency in full-load condition. osc linear frequency controller v vs freq. v out vs t dis detector dcm bcm figure 20. linear frequency control bcm control the end of secondary diode conduction time (t dis ) can be over a switching period set by linear frequency control. in this case, FL7734 doesn t allow ccm and operation mode changes from dcm to bcm. therefore, magnetizing inductance can be largely designed to add bcm for better efficiency if pf and thd meet specification with enough margin.
? 2014 fairchild semiconductor corporation www.fairchildsemi.com FL7734 ? rev. 1.0 11 FL7734 single-stage primary-side-regulation pwm controller for pfc and phase cut dimmable led driving short-led protection in a short-led condition, the switching mosfet and secondary diode are usually stressed by the high powering current. leb cs vs v cs-high-cl (1.2 v) v vs-low-cl-h (0.5 v) / v vs-low-cl-l (0.4 v) v cs-low-cl (0.2 v) s/h gate turn-off v vs-slp-th (0.4 v) debounce count short-led protection figure 21. short led protection FL7734 changes the current-limit level in a short-led condition. when sampled vs voltage is lower than v vs - low- cl -l (0.4 v), the current-limit level is reduced to 0.2 v from 1.2 v, as shown in figure 21 so that powering is limited and external components current stress is relieved. when the sampled vs voltage is continuously lower than v vs -slp- th (0.4 v) for 3 consecutive switching cycles , short-led protection is triggered with gate shutdown. after all types of protection including short- led protection is triggered, FL7734 internally counts 4 seconds for auto restart and begins startup sequence again . open-led protection when output load is open as high impedance, the output capacitor should be protected by limiting the capacitor voltage less than its maximum rating. FL7734 can detect the output over-voltage condition by sensing both vdd and vs voltages. when vdd voltage is higher than v dd - ov p ( 27 v t yp ical) or sampled vs voltage is higher than v vs -ovp (3 v typical), protection is triggered . the protection mode is auto restart so normal operation resumes when the fault condition is removed . sensing resistor short protection during ss3, the controller operates in current-mode control and the peak cs voltage is 0.2 v during switching mode. when a sensing resistor is short circuited, cs voltage cannot reach 0.2 v and turn on time is maximized with potential damage of switching mosfet. in order to provide protection against the failure, FL7734 compares cs voltage with v cs -srsp (0.1 v) during the initial two switching operation. when vcs doesnt reach 0.1 v for the two switching, sensing resistor short protection (srsp) is triggered. in normal condition, input voltage corresponding to 1.5 v v vin is high enough to make v cs higher than 0.1 v with turn- on time shorter than maximum turn-on time. time v vin v gate 1.5 v v cs ss2 ss3 max. t on 0.1 v srsp figure 22. sensing resistor short protection under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 10.6 v and 7. 75 v, respectively. during startup, the vdd capacitor must be charged higher than 10.6 v through the external bleeding mosfet. the bleeding mosfet supplies vdd operating current until power can be delivered from the auxiliary winding of the main transformer. generally at small phase angle range, v dd supply time from auxiliary winding is short and v dd could reach to v dd -off (7. 75 v). if v dd drops below v dd -off , vdd hiccup occurs with a certain hiccup frequency determined by vdd capacitor value and vdd supply current from auxiliary winding. this hiccup mode could cause led flicker. in order to remove the unstable mode of operation, external bleeding circuit never allows v dd voltage to fall down less than v dd -off (7.75 v) once input power is supplied. over-temperature protection (otp) the built-in temperature-sensing circuit shuts down pwm output if the junction temperature exceeds 150c . after over-temperature protection (otp) is triggered, FL7734 repeats auto-restart time counting until the junction temperature is lowered less than 140c . different from short/open-led protection and srsp, startup sequence doesn t appear every 4 seconds of auto-restart delay time because the temperature is detected by monitoring internally, not by checking external pin information. normal startup sequence is started again when the junction temperature is out of the hysteresis temperature (140c ).
pin #1 front view top view ?? see detail a seating plane c gage plane [? detail a scale: 2:1 b a 6.00 8.89 4.00 3.80 10.00 9.80 (0.30) 1.27 0.250.05 1.75 max 0.250.19 0.36 0.500.25 r0.10 r0.10 0.900.50 (1.04) 0.25 c b a 0.10 c notes: a) this package conforms to jedec ms-012, variation ac, issue c. b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash and tie bar protrusions d) conforms to asme y14.5m-2009 e) landpattern standard: soic127p600x175-16am f) drawing file name: m16arev13. land pattern recommendation 1 16 8 9 0.510.31 1.501.25 3.85 7.35 1.27 0.65 1.75 8.89
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