fn4521 rev 7.00 page 1 of 9 july 2004 fn4521 rev 7.00 july 2004 HI5660 8-bit, 125/60msps, high speed d/a converter datasheet the HI5660 is an 8- bit, 125msps, high speed, low power, d/a converter whic h is implemented i n an advanced cmos process. operating from a single +3v to +5v supply, the converter provides 20ma of full scale output current and includes edge-triggered cmos input data latches. low glitch energy and excellent frequency domain performance are achieved using a se gmented current source architecture. for an equivalent performance dual version, see the hi5628. this device complements the hi5x60 family of high speed converters offered by intersil, which includes 8, 10, 12, and 14-bit devices. features ? throughput rate . . . . . . . . . . . . . . . . . . . . . . . . 125msps ? low power . . . . . . . . . . . . . . . 165mw at 5v, 27mw at 3v ? power down mode. . . . . . . . . . 23mw at 5v, 10mw at 3v ? integral linearity error . . . . . . . . . . . . . . . . . . . ? 0.25 lsb ? adjustable full scale outpu t current . . . . . 2ma to 20ma ? sfdr to nyquist at 10mhz output . . . . . . . . . . . . . 60dbc ? internal 1.2v bandgap voltage reference ? single power supply from +5v to +3v ? cmos compatible inputs ? excellent spurious free dynamic range ? pb-free available applications ? medical instrumentation ? wireless communications ? direct digital frequency synthesis ? signal reconstruction ? test instrumentation ? high resolution imaging systems ? arbitrary waveform generators pinout HI5660 (soic, tssop) top view ordering information part number temp. range (c) package pkg. dwg. # clock speed HI5660ib -40 to 85 28 ld soic m28.3 125mhz HI5660ibz (note) -40 to 85 28 ld soic (pb-free) m28.3 125mhz HI5660/6ia -40 to 85 28 ld tssop m28.173 60mhz HI5660/6ia-t 28 ld tssop tape and reel m28.173 60mhz HI5660/6iaz (note) -40 to 85 28 ld tssop (pb-free) m28.173 60mhz HI5660/6iaz-t (note) 28 ld tssop tape and reel (pb-free) m28.173 60mhz hi5760eval1 25 evaluation platform 125mhz note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-f ree soldering operations. intersil p b-free products a re msl classif ied at pb-free peak reflow temperatures that meet or exceed the pb-fre e requirements of ipc/jedec j std-020b. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) dcom dcom dcom dcom dcom dcom 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clk dcom nc av dd nc ioutb comp1 fsadj refio reflo sleep dv dd iouta acom
HI5660 fn4521 rev 7.00 page 2 of 9 july 2004 typical applications circuit functional block diagram d7 (msb) (1) d6 (2) d5 (3) d4 (4) d3 (5) d2 (6) d1 (7) d0 (lsb) (8) d7 d6 d5 d4 d3 d2 d1 d0 dcom (26) clk (28) (19) comp1 (24) av dd d/a out (22) iouta (21) ioutb 50 ? (18) fsadj (16) reflo HI5660 dv dd (27) +5v or +3v (v dd ) 0.1 ? f 50 ? 10 ? f (20) acom 50 ? (15) sleep (17) refio 0.1 ? f 1.91k ? ferrite 10 ? h 0.1 ? f (23) nc 0.1 ? f d/a out + bead r set (9-14, 25) dcom dcom acom 10 ? f + ferrite 10 ? h bead upper voltage reference (lsb) d0 d1 d2 d3 d4 (msb) d7 clk d5 d6 5-bit decoder refio latch av dd acom dv dd dcom latch cascode current source switch matrix bias generation int/ext fsadj reference int/ext select reflo 31 34 34 31 msb segments 3 lsbs + comp1 sleep iouta ioutb
HI5660 fn4521 rev 7.00 page 3 of 9 july 2004 absolute maximum ratings thermal information digital supply voltage dv dd to dcom . . . . . . . . . . . . . . . . . +5.5v analog supply voltage av dd to acom. . . . . . . . . . . . . . . . . . +5.5v grounds, acom to dcom . -0.3v to +0.3v digital input voltages (d9-d0, clk, sleep) . . . . . . . . . . . . . . . . . . . . . . . . . dv dd + 0.3v internal reference output current. . . . . . . . . . . . . . . . . . . . . ? 50 ? a reference input voltage range. . . . . . . . . . . . . . . . . . av dd + 0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ? ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 tssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ? ja is measured with the component mounted on an evaluation pc boa rd in free air. electrical specifications av dd = dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values parameter test conditions t a = -40 o c to 85 o c units min typ max system performance resolution 8- -bits integral linearity error, inl best fit straight line (note 7) - 0.5 ? 0.25 +0.5 lsb differential linearity error, dnl (note 7) -0.5 ? 0.25 +0.5 lsb offset error, i os (note 7) -0.025 +0.025 % fsr offset drift coefficient (note 7) - 0.1 - ppm fsr/ o c full scale gain error, fse with external reference (notes 2, 7) - 10 ? 2+10% fsr with internal reference (notes 2, 7) -10 ? 1+10% fsr full scale gain drift with ex ternal reference (note 7) - ? 50 - ppm fsr/ o c with internal reference (note 7) - ? 100 - ppm fsr/ o c full scale output current, i fs 2-20ma output voltage compliance range (note 3) -0.3 - 1.25 v dynamic characteristics maximum clock rate, f clk (notes 3, 9) 125 - - mhz output settling time, (t sett ) 0.8% ( ? 1 lsb, equivalent to 7 bits) (note 7) - 5 - ns 0.4% ( ? 1/2 lsb, equivalent to 8 bits) (note 7) - 15 - ns singlet glitch area (peak glitch) r l = 25 ?? (note 7) - 5 - pv?s output rise time full scale step - 1.5 - ns output fall time full scale step - 1.5 - ns output capacitance 10 pf output noise ioutfs = 20ma - 50 - pa/ ? hz ioutfs = 2ma - 30 - pa/ ? hz
HI5660 fn4521 rev 7.00 page 4 of 9 july 2004 ac characteristics HI5660ib, HI5660ia - 125mhz spurious free dynamic range, sfdr within a window f clk = 125msps, f out = 32.9mhz, 10mhz span (notes 4, 7) - 70 - dbc f clk = 100msps, f out = 5.04mhz, 4mhz span (notes 4, 7) - 73 - dbc total harmonic distortion (thd) to nyquist f clk = 100msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc spurious free dynamic range, sfdr to nyquist f clk = 125msps, f out = 32.9mhz, 62.5mhz span (notes 4, 7) - 51 - dbc f clk = 125msps, f out = 10.1mhz, 62.5mhz span (notes 4, 7) - 61 - dbc f clk = 100msps, f out = 40.4mhz, 50mhz span (notes 4, 7) - 48 - dbc f clk = 100msps, f out = 20.2mhz, 50mhz span (notes 4, 7) - 56 - dbc f clk = 100msps, f out = 5.04mhz, 50mhz span (notes 4, 7) - 68 - dbc f clk = 100msps, f out = 2.51mhz, 50mhz span (notes 4, 7) - 68 - dbc ac characteristics HI5660/6ia - 60mhz spurious free dynamic range, sfdr within a window f clk = 60msps, f out = 10.1mhz, 10mhz span (notes 4, 7) - 62 - dbc f clk = 50msps, f out = 5.02mhz, 2mhz span (notes 4, 7) - 73 - dbc f clk = 50msps, f out = 1.00mhz, 2mhz span (notes 4, 7) - 74 - dbc total harmonic distortion (thd) to nyquist f clk = 50msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc f clk = 50msps, f out = 1.00mhz (notes 4, 7) - 68 - dbc spurious free dynamic range, sfdr to nyquist f clk = 60msps, f out = 20.2mhz, 30mhz span (notes 4, 7) - 54 - dbc f clk = 60msps, f out = 10.1mhz, 30mhz span (notes 4, 7) - 60 - dbc f clk = 50msps, f out = 20.2mhz, 25mhz span (notes 4, 7) - 53 - dbc f clk = 50msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 67 - dbc f clk = 50msps, f out = 2.51mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 50msps, f out = 1.00mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 25msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 71 - dbc voltage reference internal reference voltage, v fsadj voltage at pin 18 with internal reference 1.04 1.16 1.28 v internal reference voltage drift - ? 60 - ppm / o c internal reference output current sink/source capability -0.1 - ? a reference input impedance -1 -m ? reference input multiplying bandwidth (note 7) - 1.4 - mhz digital inputs d7-d0, clk input logic high voltage with 5v supply, v ih (note 3) 3.5 5 - v input logic high voltage with 3v supply, v ih (note 3) 2.1 3 - v input logic low voltage with 5v supply, v il (note 3) - 0 1.3 v input logic low voltage with 3v supply, v il (note 3) - 0 0.9 v input logic current, i ih -10 - +10 ? a input logic current, i il -10 - +10 ? a digital input capacitance, c in -5 - pf electrical specifications av dd = dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values (continued) parameter test conditions t a = -40 o c to 85 o c units min typ max
HI5660 fn4521 rev 7.00 page 5 of 9 july 2004 timing characteristics data setup time, t su see figure 3 (note 3) 3 - - ns data hold time, t hld see figure 3 (note 3) 3 - - ns propagation delay time, t pd see figure 3 - 1 - ns clk pulse width, t pw1 , t pw2 see figure 3 (note 3) 4 - - ns power supply characteristics av dd power supply (note 8, 9) 2.7 5.0 5.5 v dv dd power supply (note 8, 9) 2.7 5.0 5.5 v analog supply current (i avdd ) 5v or 3v, ioutfs = 20ma - 23 30 ma 5v or 3v, ioutfs = 2ma - 4 - ma digital supply current (i dvdd ) 5v, ioutfs = dont care (note 5) - 3 5 ma 3v, ioutfs = dont care (note 5) - 1.5 - ma supply current (i avdd ) sleep mode 5v or 3v, ioutfs = dont care - 1.6 3 ma power dissipation 5v, ioutfs = 20ma (note 6) - 165 - mw 5v, ioutfs = 20ma (note 10) - 150 - mw 5v, ioutfs = 2ma (note 6) - 70 - mw 3.3v, ioutfs = 20ma (note 10) - 75 - mw 3v, ioutfs = 20ma (note 6) - 85 - mw 3v, ioutfs = 20ma (note 10) - 67 - mw 3v, ioutfs = 2ma (note 6) - 27 - mw power supply rejection single supply (note 7) -0.2 - +0.2 % fsr/v notes: 2. gain error measured as the error in the ratio between the ful l scale output current and the current through r set (typically 625 ? a). ideally the ratio should be 32. 3. parameter guaranteed by design or characterization and not pr oduction tested. 4. spectral measurements made wi th differential transformer coup led output and no external filtering. 5. measured with the clock at 50msps and the output frequency at 1mhz. 6. measured with the clock at 100msps and the output frequency a t 40mhz. 7. see definition of specifications. 8. it is recommended that the output current be reduced to 12ma or less to maintain optimum performance for operation below 3v. dv dd and av dd do not have to be equal. 9. for operation above 125mhz, it is recommended that the power supply be 3.3v or greater. the part is functional with the cloc k above 125msps and the power supply below 3.3v, but performance is degraded. 10. measured with the clock at 60msps and the output frequency a t 10mhz. electrical specifications av dd = dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values (continued) parameter test conditions t a = -40 o c to 85 o c units min typ max
HI5660 fn4521 rev 7.00 page 6 of 9 july 2004 timing diagrams figure 1. output settling time diagram figure 2. peak glitch area (singlet) measurement method figure 3. propagation delay, setup time, hold time and minimum p ulse width diagram clk d7-d0 i out 50% t sett 1 / 2 lsb error band t pd v t(ps) height (h) width (w) glitch area = 1 / 2 (h x w) clk i out 50% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld t sett t sett t sett d7-d0
HI5660 fn4521 rev 7.00 page 7 of 9 july 2004 definition of specifications integral linearity error, inl, is the measure of the worst case point that deviates from a best fi t straight line of data value s along the transfer curve. differential linearity error, dnl, is the measure of the step size output deviation from code to code. ideally the step size should be 1 lsb. a dnl spe cification of 1 lsb or less guarantees monotonicity. output settling time, is the time required for the output voltage to settle to within a specified error band measured fro m the beginning of the output tr ansition. in the case of the HI5660, the measurement was done by switching from code 0 to 64, or quarter scale. termination impedance was 25 ? due to the parallel resistance of the output 50 ? and the oscilloscopes 50 ? input. this also aids the abi lity to resolve the specified error band without overdriving the oscilloscope. singlet glitch area, is the switching tran sient appearing on the output during a code transition. it is measured as the area under the overshoot portion of the curve and is expressed as a volt-time specification. full scale gain error , is the error from a n ideal ratio of 32 between the output current and the full scale adjust current (through r set ). full scale gain drift, is measured by setting the data inputs to all ones and measuring the out put voltage through a known resistance as the tempera ture is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or max . the units are ppm of fsr (f ull scale range) per degree c. total harmonic distortion, thd , is the ratio of the dac output fundamental to the rms sum of the first five harmonics. spurious free dynamic range, sfdr, is the amplitude difference from the fundamental t o the largest harmonically or non-harmonically related spur within the specified window. output voltage compliance range, is the voltage limit imposed on the output. the output impedance load should be chosen such that the voltage d eveloped does not violate the compliance range. offset error, is measured by setting t he data inputs to all zeros and measuring the outp ut voltage through a known resistance. offset error is defined as the maximum deviation of the output current from a value of 0ma. offset drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from t min to max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (ful l scale range) per degree c. power supply rejection, is measured using a single power supply. its nominal +5v is varied ? 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is defined as the 3db bandwidth of the voltage r eference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the freq uency is increased un til the amplitude of the output waveform is 0 .707 of its original value. internal reference voltage drift, is defined as the maximum deviation from the value measured at room te mperature to the value measured at either t min or t max . the units are ppm per degree c. detailed description the HI5660 is an 8-bit , current out, cmos, digital to analog converter. its maximum updat e rate is 125msps and can be powered by either single or dual power supplies in the recommended range of +3v to +5 v. it consumes less than 165mw of power when using a +5v supply with the data switching at 100msps. the a rchitecture is based on a segmented current source arrang ement that reduces glitch by reducing the amount of current s witching at any one time. the five msbs are represented by 31 major current sources of equivalent current. the three lsbs are comprised of binary weighted current sources. consi der an input pattern to the converter which ramps through all the codes from 0 to 255. the three lsb current sources would begin to count up. when they reached the all high state (decimal value of 7) and needed to count to the next code, they w ould all turn off and the firs t major current source would turn on. to continue counting upward, the 3 lsbs would count up another 7 codes, and then the next major current source would turn on and the three lsbs would all turn off. the pr ocess of the sing le, equivalent, major current source turning on and the three l sbs turning off each time the conv erter reaches another 7 codes greatly reduces the glitch a t any one switching point. in previous architectures that contained all binary weighted current sources or a binary weighted r esistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. by greatly reducing the amount of current switching at c ertain major transitions, the overall glitch of the convert er is dramatically reduced, improving settling times and transient problems. digital inputs and termination the HI5660 digital inputs are guaranteed to cmos levels. however, ttl compatibility ca n be achieved by lowering the supply voltage to 3v due to the digital threshold of the input buffer being approximately ha lf of the supply voltage. the internal register is updated on the rising edge of the clock. t o minimize reflections, proper termination should be implemented. if the lines driving the clock and the digital inp uts are 50 ? lines, then 50 ? termination resistors should be placed
HI5660 fn4521 rev 7.00 page 8 of 9 july 2004 as close to the converter inputs as possible connected to the digital ground plane (if se parate grounds are used). ground plane(s) if separate digital and analog gr ound planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. the same is true for th e analog components and the analog ground plane. noise reduction to minimize power supply noise, 0.1 ? f capacitors should be placed as close as possible to the converters power supply pins, av dd and dv dd . also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on t he board is recommended. voltage reference the internal voltage reference of the device h as a nominal value of +1.2v with a ? 60 ppm/ o c drift coefficient over the full temperature range of the conver ter. it is recommended that a 0.1 ? f capacitor be placed as close as possible to the refio pin, connected to the analog ground. the reflo pin (16) selects the reference. the internal reference can be selected if pin 16 is tied low (ground) . if an external reference is desired, then pin 16 should be tied high (to the analog supply voltage) and the external reference driven into refio, pin 17. the full scale output current of t he converter is a function of the voltage reference used and the value of r set . i out should be within the 2ma to 2 0ma range, through operation below 2ma is possible, with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.16v (pin 18). if an external reference is used, v fsadj will equal the external refer ence. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set )x 32. if the full scale output current is set to 20ma by using the internal voltage reference (1.16v) and a 1.86k ? r set resistor, then the input coding to outpu t current will resemble the following: outputs iouta and ioutb are comple mentary current outputs. the sum of the two currents is always equal to the full scale outpu t current minus one lsb. if singl e ended use is desired, a load resistor can be used to convert t he output current to a voltage . it is recommended that the unus ed output be either grounded or equally terminated. the volt age developed at the output must not violate the output vol tage compliance range of -0.3v to 1.25v. r load should be chosen so t hat the desired output voltage is produced in conjunct ion with the out put full scale current, which is descr ibed above in the reference section. i f a known line impedance is to be driven, then the output load resistor should be chosen to ma tch this impedance. the output voltage equation is: v out = i out x r load . these outputs can be used in a different ial-to-single-ended arrangement to achieve better harmonic rejection. the sfdr measurements in this data sheet were performed with a 1:1 transformer on the o utput of the dac (see figure 1). with the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. it is impo rtant to note here that the negative voltage output complia nce range limit is -300mv, imposing a maximum of 600mv p-p amplitude with this configuration. the loading as s hown in figure 1 will result in a 500mv signal at the output of the transformer if the full scale output current of the dac is set to 20ma. v out = 2 x i out x r eq , where r eq is ~12.5 ? . table 1. input coding vs output current input code (d7-d0) iouta (ma) ioutb (ma) 1111 1111 20 0 1000 0000 10 10 0000 0000 0 20 pin 21 pin 22 v out = (2 x i out x r eq )v 100 ? HI5660 50 ? 50 ? 50 ? ioutb iouta figure 4.
fn4521 rev 7.00 page 9 of 9 july 2004 HI5660 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2000-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. pin descriptions pin no. pin name pin description 1-8 d7 (msb) through d0 (lsb) digital data bit 7 (most signifi cant bit) through digital data bit 0, (least significant bit). 9-14 dcom connect to digital ground. 15 sleep control pin for power-down mode. sleep mode is active hi gh; connect to ground for normal mode. sleep pin has internal 20 ? a active pulldown current. 16 reflo connect to analog ground to enable internal 1.2v referen ce or connect to av dd to disable internal reference. 17 refio reference voltage input if internal reference is disable d. reference voltage output if internal reference is enabled. use 0.1 ? f cap to ground when internal reference is enabled. 18 fsadj full scale current adjus t. use a resistor to ground to a djust full scale output cur rent. full scale output current = 32 x v fsadj /r set . 19 comp1 for use in reducing bandwidth/noise. recommended: connec t 0.1 ? f to av dd . 20 acom analog ground. 21 ioutb the complimentary current output of the device. full sca le output current is achieved when all input bits are set to binary 0. 22 iouta current output of the device. full scale output current is achieved when all input bits are set to binary 1. 23 nc internally connected to acom via a resistor. recommend leav e disconnected. adding a capacitor to acom for upward compatibility is valid. grounding to acom is va lid. (for upward compatibility to 12-bit and 14-bit devices, pin 23 needs the ability to have a 0.1 ? f capacitor to acom.) 24 av dd analog supply (+3v to +5v). 25 nc no connect (for upward compatibility to 12 and 14b, pin 25 needs to be grounded to acom). 26 dcom digital ground. 27 dv dd digital supply (+3v to +5v). 28 clk input for clock. positive edge of clock latches data.
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